Instruction obtaining method and device, processor and electronic device

Abstract

This application provides an instruction fetching method and apparatus, processor, and electronic device. The method includes: in response to detecting a function return instruction, obtaining the return address of the function; determining a target cache line from cache lines included in a first instruction cache based on the return address; wherein the target cache line includes a target instruction indicated by the return address, and the cache behavior in the first instruction cache associated with the return address triggers prefetching from a second instruction cache and storing it in the first instruction cache before the return instruction is detected, the second instruction cache being a cache applicable to multiple instruction types, and the first instruction cache being a cache applicable to return instruction types; and obtaining the target instruction from the target cache line. This application improves instruction fetching efficiency and hit rate.

Description

Technical Field

[0001] This application relates to computer technology, and more particularly to an instruction acquisition method and apparatus, a processor, and an electronic device. Background Technology

[0002] In the microarchitecture of modern superscalar processors, the instruction cache bridges the performance gap between the microprocessor and memory, reduces average memory access latency, and improves the microprocessor's instruction fetching capability. However, the performance loss caused by instruction cache misses is severe, so most high-performance processors have an instruction fetch unit to prefetch instructions that may be executed in the future into the instruction cache, thereby reducing the probability of cache access misses. Summary of the Invention

[0003] This application provides an instruction fetching method, apparatus, processor, and electronic device that can improve instruction fetching efficiency and hit rate.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides an instruction acquisition method, including:

[0006] In response to the detection of a function return instruction, the return address of the function is obtained;

[0007] Based on the return address, a target cache line is determined from the cache lines included in the first instruction cache; wherein, the target cache line includes the target instruction indicated by the return address, and the cache behavior associated with the return address in the first instruction cache triggers prefetching from the second instruction cache and storing it in the first instruction cache before the return instruction is detected, wherein the second instruction cache is a cache applicable to multiple instruction types, and the first instruction cache is a cache applicable to the return instruction type;

[0008] The target instruction is obtained from the target cache line.

[0009] This method can improve the efficiency of acquiring target instructions and increase the hit rate.

[0010] In some embodiments, the first instruction cache includes a first label for identifying a cache line;

[0011] Determining the target cache line from the cache lines included in the first instruction cache based on the return address includes:

[0012] Based on the returned address, determine the first query tag;

[0013] In the first instruction cache, a first tag matching the first query tag is determined, and the target cache line is determined based on the cache line identified by the matching first tag.

[0014] This method can improve the efficiency of querying cached rows, thereby improving the efficiency of determining target cached rows.

[0015] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line;

[0016] The process of determining the target cache line based on the cache line identified by the matched first tag includes:

[0017] In response to a cache line identified by the first matching tag, and the second tag indicating that all fields or some fields of the cache line are valid, a cache line identified by the first matching tag is determined as the target cache line;

[0018] or,

[0019] In response to the existence of multiple cache lines identified by the first matching tag, and the second tag of each cache line indicating that fields at different positions are valid, the valid fields in each cache line are merged to obtain the target cache line.

[0020] This method helps improve the accuracy of identifying target cache lines.

[0021] In some embodiments, the method further includes:

[0022] In response to detecting a function call instruction, the return address of the function is obtained;

[0023] The cache line associated with the return address is prefetched from the second instruction cache and saved to the first instruction cache.

[0024] This method can balance the prefetching of cache lines corresponding to the return addresses of various functions.

[0025] In some embodiments, the second instruction cache further includes a third tag for identifying a cache line;

[0026] The step of pre-fetching the cache line associated with the return address from the second instruction cache and saving it to the first instruction cache includes:

[0027] Based on the returned address, determine the second query tag;

[0028] Based on the second query tag, a matching third tag is determined in the second instruction cache, and the cache line corresponding to the matching third tag is prefetched and saved to the first instruction cache.

[0029] This method can improve the efficiency of prefetching cache lines, thereby helping to improve the efficiency of instruction fetching.

[0030] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line, and the method further includes:

[0031] Based on the type of the second instruction cache, determine the second label of the cache line associated with the return address;

[0032] Store the second tag in the first instruction cache and associate it with the cache line associated with the return address.

[0033] This method can improve the accuracy and comprehensiveness of the second tag information when the prefetched cache line is stored in the first instruction cache, which helps to accurately determine the target cache line and obtain the target instruction.

[0034] In some embodiments, the second instruction cache includes a first type of cache for storing undecoded instructions and / or a second type of cache for storing decoded instructions;

[0035] Determining the second tag of the cache line associated with the return address based on the type of the second instruction cache includes:

[0036] In response to the cache line associated with the return address being prefetched from the first type of cache, a second label indicating that all fields of the cache line associated with the return address is valid is determined;

[0037] In response to the prefetching of the cache line associated with the return address from the second type of cache, a second tag of the cache line associated with the return address in the first instruction cache is determined based on the fourth tag associated with the cache line associated with the return address in the second type of cache; wherein the fourth tag is used to identify the valid fields of the cache line in the second type of cache.

[0038] By distinguishing the source of prefetch cache lines and generating a second label for valid fields in the first instruction cache to identify cache lines based on the first type of cache and the second type of cache, the system exhibits high intelligence.

[0039] In some embodiments, the second type of cache includes merged cache lines, the merged cache lines including local fields associated with different return addresses;

[0040] In response to the prefetching of the cache line associated with the return address from the second type of cache, the determination of the second tag of the cache line associated with the return address in the first instruction cache based on the fourth tag associated with the cache line associated with the return address in the second type of cache includes:

[0041] In response to the cache line associated with the return address being prefetched from the second type of cache and the cache line associated with the return address belonging to a merged cache line, the second label is determined based on the fourth label of the merged cache line; wherein the second label identifies that the local field associated with the return address in the merged cache line is a valid field.

[0042] This method can improve the universality of the instruction acquisition method of this application.

[0043] In some embodiments, pre-fetching the cache line associated with the return address from the second instruction cache and saving it to the first instruction cache includes:

[0044] In response to detecting that the first instruction cache is full, the target cache space containing the cache lines in the first instruction cache that have not been accessed for a preset time is cleared, and the cache lines pre-fetched from the second instruction cache and associated with the return address are saved to the target cache space.

[0045] This method ensures that the first instruction cache always retains the instructions most likely to be reused, maximizing the actual utility of the first instruction cache.

[0046] In some embodiments, the method further includes:

[0047] In response to the detection of a return instruction of the function, a cache line not included in the first instruction cache is prefetched in the second instruction cache.

[0048] This method helps improve the fetch efficiency and hit rate of multiple instructions.

[0049] This application provides an instruction acquisition device, including:

[0050] The branch prediction module is configured to obtain the return address of the function in response to the detection of a function return instruction;

[0051] The instruction fetch module is configured to determine a target cache line from the cache lines included in the first instruction cache based on the return address; wherein the target cache line includes the target instruction indicated by the return address, and the cache behavior associated with the return address in the first instruction cache triggers prefetching from the second instruction cache and storing it in the first instruction cache before the return instruction is detected, wherein the second instruction cache is a cache applicable to multiple instruction types, and the first instruction cache is a cache applicable to the return instruction type;

[0052] The instruction fetching module is further configured to retrieve the target instruction from the target cache line.

[0053] In some embodiments, the first instruction cache includes a first label for identifying a cache line;

[0054] The instruction fetching module is further configured to determine a first query tag based on the return address; determine a first tag matching the first query tag in the first instruction cache; and determine the target cache line based on the cache line identified by the matching first tag.

[0055] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line;

[0056] The instruction fetching module is further configured to, in response to the presence of one cache line identified by the matching first tag, and the second tag indicating that all or part of the fields of the cache line are valid, determine one cache line identified by the matching first tag as the target cache line; or, in response to the presence of multiple cache lines identified by the matching first tag, and the second tag of each cache line indicating that fields at different positions are valid, merge the valid fields in each cache line to obtain the target cache line.

[0057] In some embodiments, the branch prediction module is further configured to obtain the return address of the function in response to detecting a function call instruction;

[0058] The device further includes:

[0059] The prefetch module is configured to prefetch the cache line associated with the return address from the second instruction cache and save it to the first instruction cache.

[0060] In some embodiments, the second instruction cache further includes a third tag for identifying a cache line;

[0061] The prefetch module is further configured to determine a second query tag based on the return address; determine a matching third tag in the second instruction cache based on the second query tag; and prefetch the cache line corresponding to the matching third tag and save it to the first instruction cache.

[0062] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line.

[0063] The prefetch module is further configured to determine a second tag for the cache line associated with the return address based on the type of the second instruction cache; store the second tag in the first instruction cache and associate it with the cache line associated with the return address.

[0064] In some embodiments, the second instruction cache includes a first type of cache for storing undecoded instructions and / or a second type of cache for storing decoded instructions;

[0065] The prefetch module is further configured to, in response to prefetching a cache line associated with the return address from the first type of cache, determine a second label indicating that all fields of the cache line associated with the return address are valid; and in response to prefetching a cache line associated with the return address from the second type of cache, determine a second label of the cache line associated with the return address in the first instruction cache based on a fourth label associated with the cache line associated with the return address in the second type of cache; wherein the fourth label is used to identify the valid fields of the cache line in the second type of cache.

[0066] In some embodiments, the second type of cache includes merged cache lines, the merged cache lines including local fields associated with different return addresses;

[0067] The prefetch module is further configured to, in response to a cache line associated with the return address being prefetched from the second type of cache and the cache line associated with the return address belonging to a merged cache line, determine the second label based on the fourth label of the merged cache line; wherein the second label identifies that the local field associated with the return address in the merged cache line is a valid field.

[0068] In some embodiments, the prefetch module is further configured to, in response to detecting that the first instruction cache is full, clear the target cache space containing cache lines in the first instruction cache that have not been accessed for a preset time, and save the cache lines prefetched from the second instruction cache associated with the return address to the target cache space.

[0069] In some embodiments, the prefetch module is further configured to prefetch cache lines in the second instruction cache that are not included in the first instruction cache in response to detecting a return instruction of the function.

[0070] This application provides a processor, including:

[0071] The aforementioned instruction acquisition device.

[0072] This application provides an electronic device, including:

[0073] A processor, the processor including the aforementioned instruction fetching device;

[0074] Memory including a first instruction cache and a second instruction cache;

[0075] The instruction acquisition device implements the steps of any instruction acquisition method provided in the embodiments of this application based on the first instruction cache and the second instruction cache.

[0076] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0077] In this embodiment, by triggering the prefetching of cache lines from the second instruction cache and storing them in the first instruction cache before detecting the function return instruction, the electronic device can determine the target cache line from the cache lines of the first instruction cache when detecting the function return instruction, and obtain the target instruction, including the return address, from the target cache line for subsequent execution. On the one hand, since the cache line is prefetched before the return instruction is detected, there is enough time to mask the delay of I-Cache miss, and the early prefetching ensures that the return instruction is already in place when it is actually needed, and the target cache line can be quickly determined based on the return address, thereby turning a possible cache miss into a hit, and thus improving the hit rate of the target instruction. On the other hand, since the cache line is prefetched from the general second instruction cache to the first instruction cache suitable for the return instruction type, the efficiency of querying and determining the target cache line corresponding to the return address from the smaller first instruction cache is also higher, thus improving the efficiency of obtaining the target instruction.

[0078] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0079] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0080] Figure 1 This is a schematic diagram of the architecture of the instruction acquisition system provided in the embodiments of this application.

[0081] Figure 2 This is a schematic diagram of the terminal structure provided in the embodiments of this application.

[0082] Figure 3 This is a schematic diagram of instruction prefetching technology.

[0083] Figure 4 This is a flowchart illustrating an instruction acquisition method provided in an embodiment of this application.

[0084] Figure 5 This refers to the cache line type included in the first instruction cache in the embodiments of this application.

[0085] Figure 6 This is a structural example diagram of a storage entry in the first instruction cache in an embodiment of this application.

[0086] Figure 7 This is a flowchart illustrating another instruction acquisition method provided in an embodiment of this application. Detailed Implementation

[0087] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0088] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0089] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0090] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0091] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0092] This application provides an instruction fetching method, apparatus, electronic device, computer-readable storage medium, and computer program product, which can improve the efficiency and hit rate of instruction fetching.

[0093] The following describes exemplary applications of the electronic devices provided in the embodiments of this application. These electronic devices can be implemented as various types of user terminals such as laptops, tablets, desktop computers, set-top boxes, and mobile devices (e.g., smartphones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices, and smart wearable devices), or as servers. A server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, and big data and artificial intelligence platforms.

[0094] In some embodiments, when a user terminal is reading an e-book and reaches the current page, the rendering instructions for rendering the next page can be pre-fetched in the background. When the user clicks the "Next Page" button, the rendering can be performed instantly based on the pre-fetched rendering instructions, achieving zero-latency page turning.

[0095] In some embodiments, when a player controls a character to move within a scene, the server can pre-fetch the scene rendering instructions corresponding to the next viewpoint before the player is about to perform a viewpoint change operation. When the player actually releases the joystick and triggers the viewpoint lock command, the server can directly begin rendering based on the pre-fetched instructions, thereby reducing screen latency.

[0096] The following describes an exemplary application where an electronic device is implemented as a terminal and interacts with a server. The terminal and server can be connected directly or indirectly via wired or wireless communication, and this embodiment of the invention is not limited to this.

[0097] See Figure 1 , Figure 1 This is a schematic diagram of the architecture of the instruction acquisition system 100 provided in the embodiment of this application. In order to implement the instruction acquisition method of this application, the terminal (terminal 200-1 and terminal 200-2 are shown as examples) connects to the server 400 through the network 300. The network 300 can be a wide area network or a local area network, or a combination of the two.

[0098] In some embodiments, when the camera of terminal 200-1 (such as a smart door lock) detects that someone (such as user A) is approaching and before user A rings the doorbell, it immediately prefetches local image preprocessing instructions (such as face detection and noise reduction). After user A rings the doorbell, it can process the image in real time based on the prefetched image preprocessing instructions and send the processed image data to server 400 through network 300. Server 400 performs recognition and returns the recognition result to terminal 200-1 through network 300, thereby improving the efficiency of opening the door.

[0099] In other embodiments, user B can trigger a weather query request via voice on terminal 200-2. For example, when the voice command is "What will the weather be like tomorrow? Please tell me?", terminal 200-2 can pre-fetch the local voice-to-text command after user B says the keyword "tomorrow's weather." Simultaneously, it can also initiate a weather query request to server 400 via network 300, triggering server 400 to pre-fetch the weather query command. After user B finishes speaking, terminal 200-2 can instantly obtain the converted text based on the pre-fetched voice-to-text command and send it to server 400 via network 300. Server 400, having detected the pre-fetched weather query command, directly executes the query and returns the result to terminal 200-2 via network 300, thereby improving the efficiency of weather queries.

[0100] See Figure 2 , Figure 2 This is a schematic diagram of the structure of the terminal 200 provided in the embodiments of this application. Figure 2 The terminal 200 shown includes at least one processor 210, a memory 250, at least one network interface 220, and a user interface 230. The various components in the terminal 200 are coupled together via a bus system 240. It is understood that the bus system 240 is used to implement communication between these components. In addition to a data bus, the bus system 240 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 2 The general labeled all buses as Bus System 240.

[0101] Processor 210 can be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or any conventional processor, etc.

[0102] User interface 230 includes one or more output devices 231 that enable the presentation of media content, including one or more speakers and / or one or more visual displays. User interface 230 also includes one or more input devices 232, including user interface components that facilitate user input, such as a keyboard, mouse, microphone, touch screen display, camera, other input buttons and controls.

[0103] The memory 250 may be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid-state storage, hard disk drives, optical disk drives, etc. The memory 250 may optionally include one or more storage devices physically located away from the processor 210.

[0104] The memory 250 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), and the volatile memory may be random access memory (RAM). The memory 250 described in this application embodiment is intended to include any suitable type of memory.

[0105] In some embodiments, memory 250 is capable of storing data to support various operations, examples of which include programs, modules, and data structures or subsets or supersets thereof, as illustrated below.

[0106] Operating system 251 includes system programs for handling various basic system services and performing hardware-related tasks, such as the framework layer, core library layer, driver layer, etc., for implementing various basic business functions and handling hardware-based tasks;

[0107] The network communication module 252 is used to reach other computing devices via one or more (wired or wireless) network interfaces 220, exemplary network interfaces 220 including: Bluetooth, Wi-Fi, and Universal Serial Bus (USB), etc.

[0108] Presentation module 253 is configured to enable the presentation of information (e.g., a user interface for operating peripheral devices and displaying content and information) via one or more output devices 231 associated with user interface 230 (e.g., a display screen, a speaker, etc.).

[0109] The input processing module 254 is used to detect and translate one or more user inputs or interactions from one or more input devices 232.

[0110] In some embodiments, the apparatus provided in this application can be implemented in hardware. For example, the apparatus provided in this application can be a processor in the form of a hardware decoding processor, which is programmed to execute the method provided in this application. For example, the processor in the form of a hardware decoding processor can be one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components. Figure 2 An instruction fetching apparatus 2100, which is part of processor 210, is shown, including the following hardware modules: branch prediction module 2101 and instruction fetching module 2102. The functions of each module will be described below.

[0111] In related technologies, instruction prefetching can be performed based on Fetch-Directed Prefetching (FDP) technology. The FDP prefetcher usually combines the prediction results of the Branch Prediction Unit (BPU) to perform instruction prefetching. Figure 3 This is a schematic diagram of instruction prefetching technology, such as... Figure 3As shown, after the branch prediction unit 31 generates the predicted instruction address, it sends it to the instruction fetch unit 33 to initiate the actual instruction fetch, and simultaneously sends the address to the prefetcher 35. The prefetcher 35, in conjunction with the filtering mechanism 37, filters out valuable prefetch candidates and stores them in the prefetch request queue 32; at the same time, entries that have not yet been filled in the instruction fetch queue 34 are also fed back to the prefetcher 35 as current prefetch candidates. Based on this information, the prefetcher 35 initiates prefetching to the buffer 36 or the lower-level cache, loading the instruction block into the near end in advance, thereby hiding the instruction fetch latency. If the instruction fetch unit 33 fails to fetch an instruction based on the previously received instruction address, it re-fetches the instruction through that address based on the prefetcher 35's prefetch. For example, the FDP prefetcher (i.e., the prefetcher 35) can rely on the BPU (i.e., the branch prediction unit 31) to generate the program counter (PC) address that may be needed in the next cycle, that is, the memory address of the instruction expected to be executed in the next week. The FDP prefetcher checks the L1 cache (such as the I-Cache, i.e., buffer 36) based on the memory address to determine if the corresponding cache line is already in the I-Cache. If not, it sends a fill request to the lower-level cache (such as L2), preloading the cache line containing the memory address from the lower-level cache into the I-Cache. A cache line can contain multiple instructions with consecutive memory addresses. Since programs often execute sequentially or jump within a small range, loading consecutive instruction blocks at once can increase the probability of subsequent instruction hits.

[0112] Specifically, the prefetching technique for return instructions typically triggers prefetching upon detecting a return instruction (ret). When the BPU recognizes a return instruction, it synchronously queries the Return Address Stack (RAS) to obtain the predicted return address, and then sends this address to the FDP prefetcher. The FDP prefetcher checks the I-Cache and, if the I-Cache misses, initiates a prefetch request to the lower-level cache. The working principle of RAS is as follows: during the instruction fetch phase, when executing the call instruction, the address of the next instruction (i.e., the return address) is pushed onto the stack. When the return instruction returns, the address is retrieved from the stack and used as the return address, which is also the address in memory of the next instruction to be executed.

[0113] The purpose of prefetching is to prepare instructions before they are actually executed by a processor such as a microprocessor or central processing unit, thereby avoiding pauses during execution due to cache misses. However, the mechanism of prefetching return instructions, which triggers prefetching only after a return instruction is detected, can lead to delays or failures in instruction fetching due to the need to request loading from the lower-level cache when an I-Cache miss occurs.

[0114] In response, this application provides an instruction acquisition method, which will be described below with reference to exemplary applications and implementations of the electronic device provided in the embodiments of this application.

[0115] See Figure 4 , Figure 4 This is a flowchart illustrating an instruction acquisition method provided in an embodiment of this application, which will be combined with... Figure 4 The steps shown are explained.

[0116] S41. In response to detecting a function return instruction, obtain the return address of the function;

[0117] S42. Based on the return address, determine the target cache line from the cache lines included in the first instruction cache; wherein, the target cache line includes the target instruction indicated by the return address, and the cache behavior associated with the return address in the first instruction cache triggers prefetching from the second instruction cache and storing it in the first instruction cache before the return instruction is detected, wherein the second instruction cache is a cache applicable to multiple instruction types, and the first instruction cache is a cache applicable to the return instruction type;

[0118] S43. Obtain the target instruction from the target cache line.

[0119] The instruction fetching method in this application can be applied to the aforementioned server or user terminal, collectively referred to here as an electronic device. Instruction fetching is jointly performed by modules such as a branch prediction module, an instruction fetching module, and a prefetching module within the electronic device. These modules can be integrated within the processor chip and interact closely with other parts of the processor through hardware circuitry. The branch prediction module can be... Figure 3 The branch prediction unit 31 and the instruction fetch module can be the instruction fetch unit 33, and the prefetch module can be a module including the prefetcher 35. The instruction fetching method of this embodiment will be described in detail below with respect to each module.

[0120] In step S41, in response to detecting a function return instruction, the branch prediction module obtains the function's return address. This function can be any function (code) that needs to be executed when any application within the electronic device runs, or a function that the electronic device itself needs to execute. The function return instruction is, for example, a `ret` or `return` instruction, which is used to return from the current function to the caller, and then execution continues based on the function's return address. The function's return address can be obtained from the return address stack (RAS). During the compilation and linking phases of the program in the electronic device, the compiler and linker allocate virtual addresses for each function and establish fixed associations between function instructions and these addresses.

[0121] In step S42, the instruction fetch module determines a target cache line containing the target instruction indicated by the return address from the cache line of the first instruction cache storing the return instruction type, based on the return address. Here, the return address is the address of the target instruction in memory. The target instruction can be the execution instruction of a function. In addition to the target instruction, the target cache line may also include instructions for other functions. The target cache line can be an original cache line stored in the first instruction cache, or a cache line re-determined based on an original cache line stored in the first instruction cache.

[0122] In this application, the first instruction cache includes at least a target cache line, and may also include cache lines other than the target cache line. Each cache line stores one or more instructions. Specifically, the cache line associated with the return address in the first instruction cache is prefetched from the second instruction cache and stored in the first instruction cache before the return instruction of the currently called function is detected. The second instruction cache can be the aforementioned first-level cache or a lower-level cache. The first-level cache can be an I-Cache or a Uop-Cache; this application does not impose any restrictions on this.

[0123] In some embodiments, the electronic device may initiate a prefetch request through a prefetcher before detecting the return instruction of a function, and query the cache line corresponding to the return address from the first-level cache and store it in the first instruction cache; if it is not found in the first-level cache, it queries the cache line corresponding to the return address from the lower-level cache and stores it in the first instruction cache.

[0124] In this application, the second instruction cache is a cache applicable to multiple instruction types, also known as a general instruction cache, which serves the instruction fetching needs of all instructions (such as ordinary arithmetic instructions, branch instructions, function call instructions, return instructions, etc.) and usually has a large capacity; while the first instruction cache is a cache applicable to return instruction types, that is, it stores instructions related to the return address of each function and has a relatively small capacity.

[0125] In this application, each cache line in the first instruction cache is prefetched from the second instruction cache and stored in the first instruction cache before a return instruction is detected. For example, for each cache line in the first instruction cache, it may be stored in the first instruction cache when a function call instruction associated with the cache line is detected; it may also be stored in the first instruction cache after the function call instruction associated with the cache line is detected and before the return instruction; of course, it may also be any other time before the return instruction is detected, and this application does not limit this.

[0126] It should be noted that, in this application, the electronic device may prefetch the corresponding cache line from the second instruction cache and store it in the first cache based on its own operating status before detecting a return instruction, for example, prefetching may be triggered when the processor utilization is low. Furthermore, the cache lines included in the first instruction cache may be stored once and used multiple times, instead of being stored each time a call instruction is detected; and the cache lines included in the first instruction cache may also be dynamically updated.

[0127] In step S43, the instruction fetching module retrieves the target instruction from the target cache line and can execute the instruction immediately. Taking the aforementioned application scenario as an example, the function's return instruction can be an instruction triggered when the user clicks the "next page" button, and the target instruction can be a rendering instruction that renders the content of the next page; the function's return instruction can also be an instruction triggered when the player releases the joystick to lock the view, and the target instruction can be a scene rendering instruction corresponding to the next view; the function's return instruction can be an instruction triggered when user A rings the doorbell, and the target instruction can be an image preprocessing instruction; furthermore, the function's return instruction can also be an instruction triggered when user B finishes speaking a complete sentence, and the target instruction can be a speech-to-text instruction.

[0128] It is understood that in this embodiment of the application, by triggering the prefetching of cache lines from the second instruction cache and storing them in the first instruction cache before detecting the function return instruction, the electronic device can determine the target cache line from the cache lines of the first instruction cache when it detects the function return instruction, and obtain the target instruction, including the return address, from the target cache line for subsequent execution. On the one hand, since the cache line is prefetched before the return instruction is detected, there is enough time to mask the delay of I-Cache miss, and the early prefetching ensures that the return instruction is already in place when it is really needed, and the target cache line can be quickly determined based on the return address, thereby turning the cache miss that might have occurred into a hit, and thus improving the hit rate of the target instruction. On the other hand, since the cache line is prefetched from the general second instruction cache to the first instruction cache suitable for the return instruction type, the efficiency of querying and determining the target cache line corresponding to the return address from the smaller first instruction cache is also higher, thus improving the efficiency of obtaining the target instruction.

[0129] In this application, when the instruction fetch module determines the target cache line from the cache lines included in the first instruction cache based on the return address, in some embodiments, the electronic device may maintain a mapping relationship between the return address and the cache lines in the first instruction cache. Therefore, the electronic device can directly query the associated cache line through the return address based on the mapping relationship and determine the target cache line.

[0130] In other embodiments, the first instruction cache includes a first label for identifying cache lines;

[0131] Determining the target cache line from the cache lines included in the first instruction cache based on the return address includes:

[0132] Based on the returned address, determine the first query tag;

[0133] In the first instruction cache, a first tag matching the first query tag is determined, and the target cache line is determined based on the cache line identified by the matching first tag.

[0134] In this application, the first instruction cache includes a first label for identifying cache lines. The first label uniquely identifies a cache line, and different instructions within the same cache line can correspond to the same first label. After obtaining the return address of a function, the instruction fetch module first determines a first query label. This first query label is calculated based on the return address using a predetermined algorithm. The first labels of each cache line in the first instruction cache are also calculated using the same algorithm. Therefore, the instruction fetch module can determine the matching first label in the first instruction cache based on the calculated first query label. A label match indicates that the cache line identified by the first label contains the cache line associated with the required return address. Based on this, the instruction fetch module can determine the target cache line based on the cache line identified by the matching first label.

[0135] It should be noted that in this application, the return address can be processed based on special encoding rules (algorithms) to determine a first query tag or first label that can uniquely identify a cache line. Furthermore, the first query tag or first label can also be a combination of multiple pieces of information to uniquely identify the cache line. This multiple pieces of information can come from the return address. For example, the first query tag can be determined based on the high-order and middle-order parts of the return address, thus uniquely identifying the cache line based on these two pieces of information. For example, the return address can be divided into three parts: a sub-tag, an index, and an offset within the block. The sub-tag corresponds to the high-order part of the return address, the index corresponds to the middle-order part of the return address, and the offset within the block is used to locate the specific byte within the cache line, i.e., to locate the specific instruction. The sub-tag and the index together constitute the first query tag or first label of this application, thus uniquely identifying the cache line. In this application, the corresponding cache group can be found first using the index, and then the sub-tags can be compared within the cache group. If a sub-tag matches in a certain path, it indicates a matching cache line. Of course, this application can also first match based on sub-tags and then match based on the index; this application is not limited in this regard, but the sub-tags and the index together constitute the first query tag or first tag of this application. In this application, the instruction fetching module can determine the target instruction from the target cache line based on the intra-block offset.

[0136] It should be noted that in this application, the cache lines in the first instruction cache and the second instruction cache can be controlled by the cache controller. The cache controller works closely with the prefetcher, the instruction fetch module, etc., to jointly manage the data flow of the cache lines.

[0137] It is understood that in the embodiments of this application, the first query tag is determined by returning the address and the first tag is matched in the first instruction cache to determine the matching cache line, thereby determining the target cache line. This tag matching method facilitates the query of cache lines and improves the efficiency of querying cache lines, thereby improving the efficiency of determining the target cache line.

[0138] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line;

[0139] The process of determining the target cache line based on the cache line identified by the matched first tag includes:

[0140] In response to a cache line identified by the first matching tag, and the second tag indicating that all fields or some fields of the cache line are valid, a cache line identified by the first matching tag is determined as the target cache line;

[0141] or,

[0142] In response to the existence of multiple cache lines identified by the first matching tag, and the second tag of each cache line indicating that fields at different positions are valid, the valid fields in each cache line are merged to obtain the target cache line.

[0143] In this application, the first instruction cache may include cache lines prefetched from I-Cache or cache lines prefetched from Uop-Cache. Cache lines in I-Cache are usually fully valid, while Uop-Cache supports storing micro-instruction sequences that are only partially valid. Therefore, the first instruction cache may include multiple types of cache lines and needs to include a second label to identify the valid fields in the cache line.

[0144] Figure 5 This refers to the cache line types included in the first instruction cache in the embodiments of this application, such as... Figure 5 As shown, 51 shows the cache line "cam0" with all fields valid, 52 shows the cache line "cam1" with the upper half valid, and 53 shows the cache line "cam2" with the lower half valid.

[0145] Figure 6 This is a structural example diagram of a storage entry in the first instruction cache in an embodiment of this application, as shown below. Figure 6As shown, 61 represents a cache line in the first instruction cache, 62 represents a first tag (e.g., a tag) used to identify the cache line, and 63 represents a second tag (e.g., vld) identifying the valid fields of the cache line. The second tag can distinguish whether the first half, the second half, or the entire field is valid by setting different bits of vld to 1. If vld is 2 bits, setting the high bit to 1 and the low bit to 0 indicates that the first half is valid; setting the high bit to 0 and the low bit to 1 indicates that the second half is valid; and setting the high bit to 1 and the low bit to 1 indicates that the entire field is valid.

[0146] It should be noted that invalid fields in cache lines prefetched from Uop-Cache can be assigned any value, but the valid range is explicitly defined by the second label. In contrast, cache lines stored in I-Cache are cache lines where all fields are valid. Therefore, if a cache line in the first instruction cache is prefetched from I-Cache, the second label indicates that all fields are valid.

[0147] Furthermore, since cache lines in the Uop-Cache are stored only after the processor fetches a raw instruction cache line from the I-Cache, decodes it, executes the instruction, and then stores it in the Uop-Cache, if the instruction in the raw instruction cache line is hit multiple times by accesses from different starting points (for example, the first access might start from the beginning of the line, in which case the first half of the cache line will be stored in the Uop-Cache), and a subsequent access might start from the second half of the line, in which case the second half of the cache line will be stored in the Uop-Cache. Therefore, the same return address may have two cache lines in the Uop-Cache: one with the first half of the instruction being valid and the other with the second half being valid.

[0148] Based on this, in the embodiments of this application, if the indexing module determines that there is only one cache line with the first tag identifier that matches, and the second tag indicates that the fields (all fields) of the entire cache line are valid or some fields are valid, the cache line with the first tag identifier will be determined as the target cache line. If the electronic device has multiple cache lines with the first tag identifier that match (for example, two), and the second tag of each cache line indicates that the fields at different positions are valid (such as the upper half of one tag being valid and the lower half of one tag being valid), then merging the valid fields in each cache line can yield a target cache line with all fields valid.

[0149] It is understood that, in the embodiments of this application, the target cache line is determined based on the number of cache lines identified by the first matching tag and the second tag used to identify the valid field. This can take into account the situation where cache lines are prefetched from different types of second instruction caches to the first instruction cache, such as cache lines in the first instruction cache coming from I-Cache or Uop-Cache, which helps to improve the accuracy of determining the target cache line.

[0150] In some embodiments, the method further includes:

[0151] In response to detecting a function call instruction, the return address of the function is obtained;

[0152] The cache line associated with the return address is prefetched from the second instruction cache and saved to the first instruction cache.

[0153] As previously described, the caching behavior of the return address associated in the first instruction cache is triggered by prefetching from the second instruction cache and storing it in the first instruction cache before a return instruction is detected. In this embodiment, the cache line associated with the return address is triggered by prefetching from the second instruction cache and storing it in the first instruction cache when a function call instruction is detected.

[0154] In this application, during the execution process after detecting a function call instruction, the electronic device calculates the function's return address (i.e., the address of the next instruction) and then pushes this return address into the RAS for storage, to be used by subsequent corresponding return instructions. The return address of the function obtained by the branch prediction module when the call instruction is detected can be obtained before pushing it into the RAS, or it can be obtained after pushing it into the RAS but before detecting the return instruction; this application does not impose any restrictions on this.

[0155] In this application, since the function starts running when a function call instruction is detected, and a return instruction is triggered after the function body finishes running, prefetching cache lines to the first instruction cache upon detecting a call instruction improves the efficiency and hit rate of fetching the target instruction. It also prevents cache lines associated with return addresses from occupying space due to premature prefetching to the first instruction cache, thus avoiding the inability to promptly store cache lines associated with the return addresses of other functions. It is understood that the method in this application's embodiments can balance the prefetching of cache lines corresponding to the return addresses of various functions.

[0156] It should be noted that, in this application, when prefetching the cache line associated with the return address through the prefetch module and saving it to the first instruction cache, specifically, a prefetch request is initiated by the prefetcher (such as prefetcher 35) in the prefetch module. Then, the cache controller prefetches the cache line associated with the return address in the second instruction cache based on the prefetch request and saves it to the first instruction cache. The prefetch module includes not only the prefetcher but also the cache controller. It should be noted that, when saving, the cache controller prioritizes finding free storage entries to fill; if no free storage entries are available, a storage entry can be selected for replacement based on a replacement strategy.

[0157] In some embodiments, the second instruction cache further includes a third tag for identifying a cache line;

[0158] The step of pre-fetching the cache line associated with the return address from the second instruction cache and saving it to the first instruction cache includes:

[0159] Based on the returned address, determine the second query tag;

[0160] Based on the second query tag, a matching third tag is determined in the second instruction cache, and the cache line corresponding to the matching third tag is prefetched and saved to the first instruction cache.

[0161] In this application, when the cache line associated with the return address in the second instruction cache is pre-stored into the first instruction cache by the cache controller, a tag-based query method is also used. The cache controller determines the second query tag based on the return address, and then matches the second query tag with the third tag that identifies the cache line in the second instruction cache, so as to prefetch the cache line corresponding to the matching third tag and save it into the first instruction cache. For example, the return address of the function can be carried in the prefetch request.

[0162] The method for determining the second query tag can be the same as, or different from, the method for determining the first query tag. However, the methods for determining the second query tag and the third tag must be consistent, and the methods for determining the first query tag and the first tag must be consistent. Furthermore, when saving a cache line to the first instruction cache, the aforementioned first tag can be generated synchronously based on the second query tag or the third tag, and the first tag can be associated with the cache line and stored in the first instruction cache.

[0163] It is understood that in this embodiment of the application, the second query tag is determined by the return address and the third tag is matched in the second instruction cache to prefetch the cache line to the first instruction cache. This tag matching method facilitates the prefetching of cache lines and can improve the efficiency of prefetching cache lines, thereby helping to improve the efficiency of obtaining instructions.

[0164] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line, and the method further includes:

[0165] Based on the type of the second instruction cache, determine the second label of the cache line associated with the return address;

[0166] Store the second tag in the first instruction cache and associate it with the cache line associated with the return address.

[0167] As mentioned earlier, the storage of cache lines is controlled by the cache controller. In this application, the second label used to identify the valid fields of the cache line in the first instruction cache can be generated based on the type of the first instruction cache and stored in the first instruction cache in association with the cache line associated with the return address. As mentioned earlier, the Uop-Cache may store cache lines that are valid in the first half, the second half, or all fields, while the cache lines stored in the I-Cache are valid in all fields. Therefore, the cache controller in the prefetch module needs to generate the second label of the cache line in the first instruction cache based on the type of the second instruction cache. It is understood that this method can improve the accuracy and comprehensiveness of the second label information when the prefetched cache line is stored in the first instruction cache, which helps to accurately determine the target cache line and obtain the target instruction.

[0168] In some embodiments, the second instruction cache includes a first type of cache for storing undecoded instructions and / or a second type of cache for storing decoded instructions;

[0169] Determining the second tag of the cache line associated with the return address based on the type of the second instruction cache includes:

[0170] In response to the cache line associated with the return address being prefetched from the first type of cache, a second label indicating that all fields of the cache line associated with the return address is valid is determined;

[0171] In response to the prefetching of the cache line associated with the return address from the second type of cache, a second tag of the cache line associated with the return address in the first instruction cache is determined based on the fourth tag associated with the cache line associated with the return address in the second type of cache; wherein the fourth tag is used to identify the valid fields of the cache line in the second type of cache.

[0172] In this application, the first type of cache used to store undecoded instructions can be the aforementioned I-Cache or a lower-level cache, and the second type of cache used to store decoded instructions can be the aforementioned Uop-Cache. As mentioned earlier, in the first type of cache such as the I-Cache, all fields of the cache line are valid, so the second label of the cache line associated with the return address can be determined to indicate that all fields are valid; while the second type of cache of Uop-Cache supports partially valid cache lines, so the cache controller in the prefetch module can determine the second label based on the fourth label associated with the cache line associated with the return address in the second type of cache. The fourth label is used to identify the valid fields of the cache line in the second type of cache, while the second label is used to identify the valid fields of the cache line prefetched into the first instruction cache. The representation of the fourth label and the second label can be the same or different, but the valid fields represented for the same cache line should be the same.

[0173] It is understandable that this application distinguishes the source of the prefetch cache line and generates a second label for the valid field in the first instruction cache used to identify the cache line based on the first type cache and the second type cache, which is highly intelligent.

[0174] In some embodiments, the second type of cache includes merged cache lines, the merged cache lines including local fields associated with different return addresses;

[0175] In response to the prefetching of the cache line associated with the return address from the second type of cache, the determination of the second tag of the cache line associated with the return address in the first instruction cache based on the fourth tag associated with the cache line associated with the return address in the second type of cache includes:

[0176] In response to the cache line associated with the return address being prefetched from the second type of cache and the cache line associated with the return address belonging to a merged cache line, the second label is determined based on the fourth label of the merged cache line; wherein the second label identifies that the local field associated with the return address in the merged cache line is a valid field.

[0177] In this application, the second type of cache may also include merge cache lines. A merge cache line is a cache line in which both the first half and the second half are valid. However, the instructions in these two cache lines come from two different, non-contiguous cache lines in I-cache. Therefore, the merge cache line includes local fields associated with different return addresses (two return addresses).

[0178] In this application, if the cache line associated with the return address is prefetched from the second type of cache, and the cache line belongs to the merged cache line, the cache controller in the prefetch module can modify the fourth label of the merged cache line to obtain the second label; for example, the second label only identifies the local field corresponding to the return address in the merged cache line as a valid field, while the fields other than the local field corresponding to the return address in the merged cache line are invalid fields.

[0179] It should be noted that in this application, the merged cache line in the second type of cache has corresponding identification information, which is used to indicate whether it is a merged cache line. In addition, in this application, the cache controller in the prefetch module can perform tag matching in the second type of cache based on the second query tag. The merged cache line in the second type of cache may include multiple local fields, and each local field corresponds to a third tag, such as the third tag of the first half and the third tag of the second half. The cache controller can confirm the field corresponding to the matched third tag (that is, the local field associated with the function's return address in the merged cache line) as a valid field by matching the second query tag with the third tag of the local field.

[0180] It is understandable that in this application, the prefetch module supports prefetching of merged cache lines in the second type of cache, and can adaptively adjust the second label for the prefetched merged cache lines, which is intelligent and can improve the universality of the instruction retrieval method of this application.

[0181] In some embodiments, pre-fetching the cache line associated with the return address from the second instruction cache and saving it to the first instruction cache includes:

[0182] In response to detecting that the first instruction cache is full, the target cache space containing the cache lines in the first instruction cache that have not been accessed for a preset time is cleared, and the cache lines pre-fetched from the second instruction cache and associated with the return address are saved to the target cache space.

[0183] In this application, when the cache controller in the prefetch module prefetches cache lines from the second instruction cache to the first instruction cache, since the space of the first instruction cache is limited, and to support the prefetching of more instructions, the cache lines included in the first instruction cache are allowed to be dynamically updated. Therefore, when this application detects that the first instruction cache is full and there is a new cache line storage requirement, the cache controller clears the target cache space containing cache lines in the first instruction cache that have not been accessed for a preset time, and saves the cache lines with associated return addresses prefetched from the second instruction cache to the target cache space. That is, when the first instruction cache is full, the storage is updated by replacement. The cache lines in the first instruction cache that have not been accessed for a preset time can be the cache lines that have not been accessed for the longest time. For example, replacement can be based on the replacement strategy PLRU (Pseudo-LRU).

[0184] It is understandable that this application supports dynamic updating of cache lines in the first instruction cache, and when the first instruction cache is detected to be full, it replaces the cache lines in the first instruction cache that have not been accessed for a preset period of time, so that the first instruction cache always retains the instructions most likely to be used again, maximizing the actual utility of the first instruction cache.

[0185] In some embodiments, the method further includes:

[0186] In response to the detection of a return instruction of the function, a cache line not included in the first instruction cache is prefetched in the second instruction cache.

[0187] In related technologies, upon detecting a function's return instruction, obtaining the function's return address triggers prefetching from the second instruction cache. However, this application prefetches cache lines from the second instruction cache to the first instruction cache before the return instruction. Therefore, it can prefetch cache lines from the second instruction cache that are not present in the first instruction cache. It should be noted that the prefetch module can initiate prefetch requests for cache lines not present in the first instruction cache based on the function execution order determined during the compilation and linking phases, and implement the prefetching of cache lines through the cache controller. Furthermore, these prefetched cache lines can be prefetched from lower-level caches and stored in the I-Cache.

[0188] Understandably, by prefetching cache lines of non-duplicate instructions before a return instruction is detected and then prefetching cache lines of instructions to be executed after a return instruction is detected, sufficient time can be reserved to deal with situations where I-Cache misses cause instruction fetching delays or failures, which helps to improve the fetching efficiency and hit rate of multiple instructions.

[0189] Figure 7 This is a flowchart illustrating another instruction acquisition method provided in an embodiment of this application, as shown below. Figure 7 As shown, it includes the following steps:

[0190] S701, the return address stack provides return instruction information.

[0191] In this embodiment, when the return address stack provides return instruction information, that is, when a function return instruction is detected, the RAS provides the function's return address.

[0192] S702. Has the first instruction cache been hit? If yes, proceed to step S703; otherwise, proceed to step S708.

[0193] In this embodiment, whether the first instruction cache is hit refers to whether there is a cache line in the first instruction cache corresponding to the return address of the function. As mentioned above, a first query tag can be determined based on the return address, and the first query tag can be used to match and query whether there is a cache line associated with the return address.

[0194] S703. Did all hits? If yes, proceed to step S704; if no, proceed to step S705.

[0195] In this embodiment, whether all cached lines are hit refers to whether all fields of the hit cached lines are valid.

[0196] S704, Output the entire cache line.

[0197] In this embodiment, if all fields are valid, the target cache line with all valid fields is obtained from the first instruction cache.

[0198] S705, Output the half of the valid cache line that was hit.

[0199] In this embodiment, if not all fields are valid, a cache line with half of the fields being valid is obtained from the first instruction cache. For example, if the upper half is hit, the cache line with the upper half being valid is output; if the lower half is hit, the cache line with the lower half being valid is output.

[0200] S706, Send a prefetch request.

[0201] In this embodiment, when a return instruction is detected, the prefetcher in the prefetch module will still send a prefetch request based on the return address of the function given by RAS.

[0202] S707: Retrieve the next cache line from the second instruction cache.

[0203] In this embodiment, when a return instruction is detected, cache lines in the second instruction cache that are not included in the first instruction cache can be prefetched to enable multiple prefetches at different stages, thereby improving instruction fetch efficiency and hit rate.

[0204] S708, Get the second query tag.

[0205] In this embodiment, if a cache line is not found in the first instruction cache, it indicates that the cache line was not prefetched into the first instruction cache before the function's return instruction. This could be due to a prefetching failure or an electronic device malfunction causing the prefetching not to be triggered. Therefore, this application can obtain a second query tag based on the function's return address before the next function call and before detecting the function's return instruction, or before the next function call, to prefetch the cache line from the second instruction cache into the first instruction cache.

[0206] S709. Are all fields of the matched cached row valid? If yes, proceed to step S710; if no, proceed to step S711.

[0207] In this embodiment, the cache line pre-fetched in the second instruction cache is not valid for all fields. As mentioned above, the cache line retrieved from different types of caches may have valid for some fields or valid for all fields. Based on this, different operations are performed for the valid field cases.

[0208] S710, store in the first instruction cache and mark all fields as valid.

[0209] In this embodiment, the matching cache line is stored in the first instruction cache, and if the cache line is pre-retrieved from the first type cache, the second tag indicates that all fields are valid.

[0210] S711, store in the first instruction cache and mark the corresponding field as valid.

[0211] In this embodiment, the matching cache line is stored in the first instruction cache, and if the cache line is pre-fetched from the second type cache, the upper half or the lower half can be identified as valid based on the fourth tag of the cache line in the second type cache indicating that the upper half or the lower half is valid.

[0212] The method based on the above embodiments can improve the efficiency and hit rate of finger retrieval.

[0213] The exemplary structure of the instruction acquisition device 2100 provided in the embodiments of this application will be further described below. In some embodiments, such as... Figure 2 As shown, the module stored in the instruction fetching device 2100 of the processor 210 may include:

[0214] Branch prediction module 2101 is configured to obtain the return address of the function in response to detecting a function return instruction;

[0215] The instruction fetch module 2102 is configured to determine a target cache line from the cache lines included in the first instruction cache based on the return address; wherein the target cache line includes the target instruction indicated by the return address, and the cache behavior in the first instruction cache associated with the return address triggers prefetching from the second instruction cache and storing it in the first instruction cache before the return instruction is detected, wherein the second instruction cache is a cache applicable to multiple instruction types, and the first instruction cache is a cache applicable to the return instruction type;

[0216] The instruction fetching module 2102 is further configured to retrieve the target instruction from the target cache line.

[0217] In some embodiments, the first instruction cache includes a first label for identifying a cache line;

[0218] The instruction fetching module 2102 is further configured to determine a first query tag based on the return address; determine a first tag matching the first query tag in the first instruction cache; and determine the target cache line based on the cache line identified by the matching first tag.

[0219] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line;

[0220] The instruction fetching module 2102 is further configured to, in response to the presence of one cache line identified by the matching first tag, and the second tag indicating that all or part of the fields of the cache line are valid, determine one cache line identified by the matching first tag as the target cache line; or, in response to the presence of multiple cache lines identified by the matching first tag, and the second tag of each cache line indicating that fields at different positions are valid, merge the valid fields in each cache line to obtain the target cache line.

[0221] In some embodiments, the branch prediction module 2101 is further configured to obtain the return address of the function in response to detecting a function call instruction;

[0222] The device further includes:

[0223] The prefetch module is configured to prefetch the cache line associated with the return address from the second instruction cache and save it to the first instruction cache.

[0224] In some embodiments, the second instruction cache further includes a third tag for identifying a cache line;

[0225] The prefetch module is further configured to determine a second query tag based on the return address; determine a matching third tag in the second instruction cache based on the second query tag; and prefetch the cache line corresponding to the matching third tag and save it to the first instruction cache.

[0226] In some embodiments, the first instruction cache further includes a second label for identifying valid fields in the cache line.

[0227] The prefetch module is further configured to determine a second tag for the cache line associated with the return address based on the type of the second instruction cache; store the second tag in the first instruction cache and associate it with the cache line associated with the return address.

[0228] In some embodiments, the second instruction cache includes a first type of cache for storing undecoded instructions and / or a second type of cache for storing decoded instructions;

[0229] The prefetch module is further configured to, in response to prefetching a cache line associated with the return address from the first type of cache, determine a second label indicating that all fields of the cache line associated with the return address are valid; and in response to prefetching a cache line associated with the return address from the second type of cache, determine a second label of the cache line associated with the return address in the first instruction cache based on a fourth label associated with the cache line associated with the return address in the second type of cache; wherein the fourth label is used to identify the valid fields of the cache line in the second type of cache.

[0230] In some embodiments, the second type of cache includes merged cache lines, the merged cache lines including local fields associated with different return addresses;

[0231] The prefetch module is further configured to, in response to a cache line associated with the return address being prefetched from the second type of cache and the cache line associated with the return address belonging to a merged cache line, determine the second label based on the fourth label of the merged cache line; wherein the second label identifies that the local field associated with the return address in the merged cache line is a valid field.

[0232] In some embodiments, the prefetch module is further configured to, in response to detecting that the first instruction cache is full, clear the target cache space containing cache lines in the first instruction cache that have not been accessed for a preset time, and save the cache lines prefetched from the second instruction cache associated with the return address to the target cache space.

[0233] In some embodiments, the prefetch module is further configured to prefetch cache lines in the second instruction cache that are not included in the first instruction cache in response to detecting a return instruction of the function.

[0234] This application embodiment may also provide a processor, including each module in the instruction acquisition device 2100 described above, wherein the modules may be hardware modules.

[0235] The instruction fetching method provided in this application is applied to an electronic device. The electronic device may independently include each module of the aforementioned instruction fetching device 2100, or the processor in the electronic device may include each module of the aforementioned instruction fetching device 2100. Furthermore, the electronic device may also include a memory, which includes the aforementioned first instruction cache and second instruction cache. The electronic device may implement the instruction fetching method of this application through a processor and memory, or through the instruction fetching device and memory together.

[0236] In summary, the embodiments of this application can improve the efficiency and hit rate of pointer retrieval, and have good intelligence and applicability.

[0237] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for acquiring instructions, characterized in that, The method includes: In response to the detection of a function return instruction, the return address of the function is obtained; Based on the return address, a target cache line is determined from the cache lines included in the first instruction cache; wherein, the target cache line includes the target instruction indicated by the return address, and the cache behavior associated with the return address in the first instruction cache triggers prefetching from the second instruction cache and storing it in the first instruction cache before the return instruction is detected, wherein the second instruction cache is a cache applicable to multiple instruction types, and the first instruction cache is a cache applicable to the return instruction type; The target instruction is obtained from the target cache line.

2. The method according to claim 1, characterized in that, The first instruction cache includes a first tag for identifying cache lines; Determining the target cache line from the cache lines included in the first instruction cache based on the return address includes: Based on the returned address, determine the first query tag; In the first instruction cache, a first tag matching the first query tag is determined, and the target cache line is determined based on the cache line identified by the matching first tag.

3. The method according to claim 2, characterized in that, The first instruction cache also includes a second label for identifying valid fields in the cache line; The process of determining the target cache line based on the cache line identified by the matched first tag includes: In response to a cache line identified by the first matching tag, and the second tag indicating that all fields or some fields of the cache line are valid, a cache line identified by the first matching tag is determined as the target cache line; or, In response to the existence of multiple cache lines identified by the first matching tag, and the second tag of each cache line indicating that fields at different positions are valid, the valid fields in each cache line are merged to obtain the target cache line.

4. The method according to claim 1, characterized in that, The method further includes: In response to detecting a function call instruction, the return address of the function is obtained; The cache line associated with the return address is prefetched from the second instruction cache and saved to the first instruction cache.

5. The method according to claim 4, characterized in that, The second instruction cache also includes a third tag for identifying cache lines; The step of pre-fetching the cache line associated with the return address from the second instruction cache and saving it to the first instruction cache includes: Based on the returned address, determine the second query tag; Based on the second query tag, a matching third tag is determined in the second instruction cache, and the cache line corresponding to the matching third tag is prefetched and saved to the first instruction cache.

6. The method according to claim 4, characterized in that, The first instruction cache also includes a second label for identifying valid fields in the cache line, and the method further includes: Based on the type of the second instruction cache, determine the second label of the cache line associated with the return address; Store the second tag in the first instruction cache and associate it with the cache line associated with the return address.

7. The method according to claim 6, characterized in that, The second instruction cache includes a first type of cache for storing undecoded instructions and / or a second type of cache for storing decoded instructions; Determining the second tag of the cache line associated with the return address based on the type of the second instruction cache includes: In response to the cache line associated with the return address being prefetched from the first type of cache, a second label indicating that all fields of the cache line associated with the return address is valid is determined; In response to the prefetching of the cache line associated with the return address from the second type of cache, a second tag of the cache line associated with the return address in the first instruction cache is determined based on the fourth tag associated with the cache line associated with the return address in the second type of cache; wherein the fourth tag is used to identify the valid fields of the cache line in the second type of cache.

8. The method according to claim 7, characterized in that, The second type of cache includes merged cache lines, which include local fields associated with different return addresses; In response to the prefetching of the cache line associated with the return address from the second type of cache, the determination of the second tag of the cache line associated with the return address in the first instruction cache based on the fourth tag associated with the cache line associated with the return address in the second type of cache includes: In response to the cache line associated with the return address being prefetched from the second type of cache and the cache line associated with the return address belonging to a merged cache line, the second label is determined based on the fourth label of the merged cache line; wherein the second label identifies that the local field associated with the return address in the merged cache line is a valid field.

9. The method according to claim 4, characterized in that, The step of pre-fetching the cache line associated with the return address from the second instruction cache and saving it to the first instruction cache includes: In response to detecting that the first instruction cache is full, the target cache space containing the cache lines in the first instruction cache that have not been accessed for a preset time is cleared, and the cache lines pre-fetched from the second instruction cache and associated with the return address are saved to the target cache space.

10. The method according to claim 1, characterized in that, The method further includes: In response to the detection of a return instruction of the function, a cache line not included in the first instruction cache is prefetched in the second instruction cache.

11. An instruction acquisition device, characterized in that, The device includes: The branch prediction module is configured to obtain the return address of the function in response to the detection of a function return instruction; The instruction fetch module is configured to determine a target cache line from the cache lines included in the first instruction cache based on the return address; wherein the target cache line includes the target instruction indicated by the return address, and the cache behavior associated with the return address in the first instruction cache triggers prefetching from the second instruction cache and storing it in the first instruction cache before the return instruction is detected, wherein the second instruction cache is a cache applicable to multiple instruction types, and the first instruction cache is a cache applicable to the return instruction type; The instruction fetching module is further configured to retrieve the target instruction from the target cache line.

12. A processor, characterized in that, include: The instruction acquisition device of claim 11.

13. An electronic device, characterized in that, include: The processor includes the instruction fetching device of claim 11; Memory including a first instruction cache and a second instruction cache; The instruction acquisition device implements the steps of the instruction acquisition method according to any one of claims 1 to 10 based on the first instruction cache and the second instruction cache.

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