Instruction processing method, processor, chip and electronic device

Abstract

The instruction processing method, processor, chip, and electronic device provided in this disclosure specifically include: acquiring an input instruction and reading its content; when the instruction is a first instruction, during the decoding stage, writing the first instruction directly into the reorder buffer (ROB) without using the issue queue; when the first instruction is the oldest microinstruction in the ROB, waking up the first instruction to read the general-purpose register status value; after the first instruction preempts the fixed-point pipeline, writing the general-purpose register status value into the first physical register P11. This eliminates the need to add additional comparison logic to the issue queue and avoids consuming issue queue resources. Furthermore, by preempting the write port of the execution pipeline, no additional write port is required, achieving pre-order execution at a low cost.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, specifically to an instruction processing method, processor, chip, and electronic device. Background Technology

[0002] The Intel APX instruction set APXGetS T0 is designed to accelerate the XSAVE instruction's save operation on R16-R31 and the XRSTOR instruction's restore operation on R16-R31. If all R16-R31 are in their initial state (i.e., their value is 1), XSAVE can skip saving R16-R31, and XRSTOR can skip restoring R16-R31.

[0003] Because the state value of the architecture register T0 cannot be speculatively updated (i.e., it cannot be updated during out-of-order execution), it must be updated upon instruction commit. APXGetS therefore needs to wait for all older microinstructions to complete before it can execute, as older microinstructions might update the state value of any one of R16-R31; this is called bottom execution. However, existing bottom execution schemes require adding APXGetS T0 to the issue queue, consuming issue queue resources; the issue queue needs additional comparison logic to compare the issue queue RID and RetPtr sizes every cycle, which incurs significant power consumption; furthermore, each entry in the issue queue requires a comparator, resulting in additional area overhead. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide an instruction processing method, processor, chip, and electronic device. A new scheme is proposed for the characteristics of the APXGetS T0 instruction, which eliminates the need to enter the issue queue, eliminates the need to compare the issue queue RID and RetPtr every cycle, reduces power consumption, and avoids the problem of adding extra physical register write ports.

[0005] To achieve the above objectives, the present disclosure provides the following technical solutions.

[0006] In a first aspect, this disclosure provides an instruction processing method, characterized by comprising the following steps: Obtain the input command and read the command content; When the instruction is the first instruction, the first instruction is written directly into the reorder buffer (ROB) without going through the instruction issue queue; When the first instruction is the oldest microinstruction in the reorder buffer (ROB), the first instruction is woken up to read the first data; After preempting the fixed-point pipeline, the first data read by the first instruction is written into the first physical register (P11).

[0007] In a second aspect, this disclosure provides a processor, characterized in that it includes: The instruction fetch unit is used to fetch input instructions; Decoding unit, used to decode the instruction content; The renaming unit is used to determine that the instruction is the first instruction and write the first instruction directly into the reorder buffer (ROB) without going through the instruction issue queue. The reorder buffer (ROB) is used for out-of-order execution and sequential submission of instructions; The micro-operation unit is used to wake up the first instruction to read the first data when the first instruction is the oldest micro-instruction in the reorder buffer (ROB); after preempting the fixed-point pipeline, it writes the first data read by the first instruction into the first physical register (P11).

[0008] Thirdly, this disclosure provides an APXGetS T0 instruction processing method, characterized by including the following steps: During the decoding stage, the instructions are decoded; During the renaming phase, if the instruction is APXGetS T0, the APXGetS T0 instruction is written directly to the reorder buffer (ROB), and the temporary architecture register (T0) is mapped to the first physical register (P11). When the APXGetS T0 instruction is the oldest microinstruction in the reorder buffer (ROB), the APXGetS T0 instruction is woken up to read the general-purpose register status value; Preempt the fixed-point pipeline and write the status value of the general-purpose register into the first physical register (P11).

[0009] Fourthly, this disclosure provides a processor, characterized in that it includes: The decoding unit is used to decode instructions; The renaming unit is used to write the APXGetS T0 instruction directly into the reorder buffer (ROB) if the instruction is an APXGetS T0 instruction, and to map the temporary architecture register (T0) to the first physical register (P11). The micro-operation unit is used to wake up the APXGetS T0 instruction to read the general-purpose register status value when the APXGetS T0 instruction is the oldest micro-instruction in the reorder buffer (ROB); preempt the fixed-point pipeline and write the general-purpose register status value into the first physical register (P11).

[0010] Fifthly, this disclosure provides a chip including the processor described in the embodiments of this disclosure.

[0011] Sixthly, this disclosure provides an electronic device including the chip described in the embodiments of this disclosure.

[0012] The instruction processing method, processor, chip, and electronic device provided in this disclosure acquire input instructions and read instruction content. When the instruction is a first instruction, during the decoding stage, the first instruction is directly written into the reorder buffer (ROB) without going through the issue queue. When the first instruction is the oldest microinstruction in the reorder buffer (ROB), the first instruction is woken up to read the general-purpose register status value. After the first instruction preempts the fixed-point pipeline, the general-purpose register status value is written into the first physical register (P11). This eliminates the need to add additional comparison logic to the issue queue and avoids consuming issue queue resources. Furthermore, by preempting the write port of the execution pipeline, no additional write port is required, achieving ordered execution at a low cost. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0014] Figure 1 A schematic diagram of a processor architecture provided for an embodiment of this disclosure; Figure 2 This is a schematic diagram of the execution flow of the APXGetS T0 instruction provided in an embodiment of this disclosure; Figure 3a This is a schematic diagram of a storage node waiting to execute a ROB, provided in an embodiment of this disclosure. Figure 3b This is a schematic diagram of the storage structure for waking up and executing the ROB provided in an embodiment of the present disclosure; Figure 3c A schematic diagram of the storage structure of the submission instruction ROB provided in this embodiment of the disclosure; Figure 4 A schematic diagram of the EGPR (R16–R31) state vector data structure provided in this embodiment of the disclosure; Figure 5 This is a schematic diagram of the architecture of a processor provided in one embodiment of the present disclosure. Detailed Implementation

[0015] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0016] The Central Processing Unit (CPU) is the core of a computer architecture, responsible for computation and control. Examples include various Complex Instruction Set Computing (CISC) processors, Reduced Instruction Set Computing (RISC) processors, and Very Long Instruction Word (VLIW) processors. Processors are typically configured for pipelined operations, including fetch, decode, rename, execute, and commit phases. The CPU consists of multiple subsystems and modules that work together to achieve efficient data processing and instruction execution.

[0017] ROB, or Reorder Buffer, is used for out-of-order execution and sequential commit in superscalar processors. After instruction decoding, it is written to the ROB in instruction order, containing basic instruction information such as instruction type, instruction architecture registers, and corresponding physical registers. The ROB assigns a microinstruction index (RID) to each instruction. The RID is the ROB index and can also indicate the age of instructions. Instructions are decoded sequentially, renamed, written to the ROB, and issued to the execution unit. The execution unit executes them out of order, and when certain conditions are met, they are committed sequentially and the system state is updated. The ROB maintains a Retptr (instruction commit pointer, pointing to the oldest entry in the ROB), which points to the oldest ROB entry. Only after the corresponding microinstruction is completed and committed can younger microinstructions be committed sequentially. The ROB also maintains a DispPtr (instruction issue pointer, pointing to the youngest entry in the ROB), which points to the youngest position, i.e., the position where the next decoded microinstruction will be written.

[0018] Appendix Figure 1 A detailed description of a typical CPU framework diagram, such as Figure 1 As shown in the diagram, this framework diagram illustrates the main components inside the CPU and the interactions between them.

[0019] The decoding unit 101 is the front-end of the CPU, responsible for translating machine instructions fetched from memory into micro-operations (micro-instructions). These micro-operations are the smallest units of operation that the CPU can execute; they can be arithmetic operations, logical operations, data transfers, etc. The decoding unit breaks down instructions into micro-operations and issues them to the renaming unit. Figure 1 In the middle, the decoding unit supports 6 transmits, that is, 6 micro-operations can be transmitted to the renaming unit in each cycle.

[0020] The primary function of the renaming unit 102 is to reduce register conflicts during instruction execution and improve instruction-level parallelism. It maps architectural registers (logical registers) to physical registers by querying the renaming mapping table DispMap 103. This process, called register renaming, allows multiple instructions to use the same logical registers simultaneously without conflict, as each instruction has its own physical register. The renaming unit then sends the renamed micro-operations to the fixed-point instruction issue queue and the memory access instruction issue queue, respectively.

[0021] The issue queue is a structure in the CPU used to temporarily store micro-operations to be executed. Figure 1 There are two types of issue queues: fixed-point instruction issue queue 104 and memory access instruction issue queue 105. Fixed-point instruction issue queue 104 corresponds to the fixed-point arithmetic unit ALU 106, while memory access instruction issue queue 105 corresponds to the address generation unit AGU 107. These queues ensure that micro-operations are issued to the execution unit in the correct order.

[0022] The fixed-point arithmetic unit (ALU106) is the part of the CPU that performs arithmetic and logical operations. Figure 1 There are four ALU106s in the array, which can execute micro-operations in parallel. When all source registers for a micro-operation in an ALU106 are ready, the micro-operation can be issued to the corresponding ALU106 for execution. After the ALU106 completes its execution, the result is written back to the physical register queue PRFARRAY109.

[0023] The address generation unit AGU107 is responsible for generating the addresses for memory access. Figure 1 There are three AGU107 units, which can generate addresses in parallel. When all source registers for a micro-operation in an AGU107 unit are ready, the micro-operation can be issued to the corresponding AGU107 for execution. The address generated by the AGU107 is then sent to the memory access unit LSDC108 for memory access.

[0024] The memory access unit LSDC108 is the part of the CPU responsible for memory access. It receives the address from the AGU, accesses memory, and writes the acquired data (LoadData) back to the physical register queue PRFARRAY109. The memory access unit can handle multiple memory access requests simultaneously, improving memory access efficiency.

[0025] The physical register queue PRFARRAY109 is a set of physical registers used to store the execution results of ALU106 and AGU107. The flag register queue FLAGARRAY110 is used to store condition flags, such as the carry flag (CF) and the zero flag (ZF), which are crucial for operations such as conditional branching and data comparison.

[0026] The decoding unit breaks down instructions into micro-operations and maps logical registers to physical registers through a renaming unit and a renaming mapping table to reduce register conflicts. Fixed-point instruction issue queues and memory access instruction issue queues temporarily store the micro-operations to be executed and issue them to the ALU and AGU for execution, respectively. The ALU performs arithmetic and logical operations, while the AGU generates memory access addresses. The LSDC (Low-Speed ​​Memory Address Coordination Unit) handles memory access and writes data back to the physical register queue. Throughout this process, the physical register queue and flag register queue play crucial roles in storing and transferring data. This CPU design improves instruction-level parallelism and processor performance through register renaming, instruction issue queues, and parallel execution units. It allows multiple instructions to execute simultaneously without interference, thereby improving program execution efficiency. Furthermore, by breaking instructions down into micro-operations, the CPU can more flexibly schedule instruction execution order, optimize resource utilization, reduce latency, and further enhance performance. This design is the cornerstone of modern high-performance processors, providing higher execution efficiency and better scalability while maintaining instruction set architecture compatibility.

[0027] The APX instruction set extension increased the number of registers from 16 to 32 through the GPR register. The extended general-purpose registers are called EGPR, with extension bits R16 to R31. Unlike GPR, each architecture register in EGPR maintains a status bit indicating whether the value is initial. When the status bits of the EGPR extended general-purpose registers R16–R31 are initial, the XSAVE instruction (saving system state) does not need to save the corresponding register; the XRSTOR instruction (restoring system state) does not need to restore the corresponding register. Status bit updates are performed by microinstructions such as ADD R16, R7, and R8; the target architecture register is R16. When the instruction execution results in all zeros, the zero flag is recorded in the corresponding RTQ entry. When the instruction is committed, if the result is all zeros, the INIT bit of register R16 is set to 1; if the result is not all zeros, the INIT bit of register R16 is set to 0. The status bits of the EGPR architecture registers are only updated upon instruction commit, not during out-of-order execution, because the status bits of the architecture registers themselves cannot be speculatively updated.

[0028] The APXGetS T0 instruction is designed to accelerate the XSAVE instruction's save operation on R16-R31 and the XRSTOR instruction's restore operation on R16-R31. If all R16-R31 are in their initial state (i.e., their value is 1), XSAVE can skip saving R16-R31 and XRSTOR can skip restoring R16-R31.

[0029] Combined with appendix Figure 2The first embodiment of this disclosure proposes a new execution method based on the characteristics of the APXGetS T0 instruction. It does not require the APXGetS T0 instruction to be entered into the issue queue, does not require comparing the issue queue RID and RetPtr every cycle, is power-friendly, and does not require additional physical register write ports.

[0030] Step S201: The decoding unit acquires the input instruction and decodes the instruction to identify the instruction type.

[0031] In this step, the decoding unit completes instruction recognition, source / destination register index extraction, immediate value expansion, load / store width and alignment attribute calculation, and generates corresponding control flow signals (branch type, prediction direction, exception type, etc.) to provide operation descriptors for subsequent out-of-order execution.

[0032] The determination of the APXGetS T0 instruction is completed by the instruction decoding and opcode mapping logic in the decoding unit. Based on the combination of the instruction prefix, main opcode and ModR / M field, it is matched with the microcode ROM or hard-wired table. Once the encoding of the APXGetS T0 instruction is matched, the APXGetS T0 instruction type flag is output and the target register field is locked as T0. At the same time, the corresponding bottom execution control signals are generated, and the subsequent pipeline enters the dedicated data path of the APXGetS T0 instruction according to this.

[0033] Step S202: When the instruction is the first instruction, during the renaming stage, the first instruction is written directly into the reordering buffer ROB without going through the launch queue.

[0034] After the decoding unit completes the recognition of the APXGetS T0 instruction, during the renaming stage, it first extracts the T0 field from the instruction and regards it as the target architecture register. Then, it selects an available item (such as P11) from the free physical register pool and establishes a new mapping in the RAT to bind the logical register T0 to the physical register P11. From then on, all subsequent read and write operations on T0 will be completed by P11.

[0035] The APXGetS T0 instruction does not need to enter the ALU or AGU pipeline. It actively shields the request for ALQS / AGSQ slots, only retains the request for the reorder cache ROB item, and at the same time pulls the lifetime tracking bit of the physical register P11 high to ensure that it will not be erroneously reclaimed before commit.

[0036] During the same cycle, the renaming unit can write the Bottom-Exec flag in the corresponding ROB entry, indicating that the microinstruction must wait until the commit pointer RetPtr points to itself to be woken up; in addition, the type encoding of the APXGetS T0 instruction is recorded in the ROB so that the control logic can directly select the EGPR-init status read path after waking up, without going through the conventional wake-up process of the issue queue. Set the completion flag DONE of the APXGetS T0 instruction to zero.

[0037] For non-APXGetS T0 instructions, the renaming module implements register alias elimination and dynamic resource allocation functions. It uses the renaming mapping table RAT to map the architectural register number ARF index in the micro-operation µOP to the free physical register file PRF entry in real time, and at the same time allocates reorder buffer ROB and issue queue slots.

[0038] Step S203, when the first instruction is the oldest microinstruction in the reorder buffer ROB, wake up the first instruction to read the general register status value.

[0039] The APXGetS T0 instruction is not the oldest micro-operation in the ROB and waits to be executed; it needs to wait until the previous instruction has been executed before it can be executed. Specifically, every cycle Retirement broadcasts the global commit pointer RetPtr to the entire ROB, and each row uses a combined comparator to calculate older = (RID < RetPtr); the APXGetS T0 instruction entry synchronously sends out the Bottom-Exec flag, and as long as older is 0 (RID ≥ RetPtr), apx_wake is pulled low, the EGPR-init read port and the WB preemption multiplexer remain disabled, and the APXGetS T0 instruction is suspended with zero power consumption. The previous instruction is normally written back and DONE = 1 is set, and RetPtr is incremented accordingly; when RetPtr is equal to the RID of the APXGetS T0 instruction, the comparison result flips, and the internal single-pulse wake-up signal apx_wake is instantly established, and the waiting ends and it immediately enters execution.

[0040] The APXGetS T0 instruction is the oldest micro-operation in the ROB. RetPtr points to the APXGetS T0 instruction, but the completion flag DONE=0, preventing commit. At this point, the ROB prepares to execute the APXGetS T0 instruction to retrieve the instruction type and target physical register P11 from the ROB. Specifically, when the APXGetS T0 instruction has become the oldest entry in the ROB (RetPtr == RID) and DONE=0, the Retirement phase immediately issues a bottom wake-up pulse; in the same ROB cycle, the uOP_TYPE_APXGetS (micro-instruction is APXGetS) and DestPRF (physical register number) fields statically stored for this entry are read, and the target physical register number P11 is latched into the apx_dest register.

[0041] The specific implementation of the wake-up instruction for reading the general-purpose register status value is as follows: When RetPtr equals RID and Bottom-Exec is 1, ROB reads uOP_TYPE_APXGetS and DestPRF (P11) written during the renaming phase in the first half of the next clock cycle. At the same time, the apx_wake pulse opens the EGPR-init read-only array and reads the 17th to 32nd bits of the general-purpose register EGPR (R16-R31) of the architecture status bits INIT to obtain the status vector EGPR (R16-R31); 48 bits of 0 data are filled before the status vector to form the status data ({48'b0,State[15:0]}). The 64-bit status data ({48'b0,State[15:0]}) is latched into the apx_dest register at P11.

[0042] Step S204: After preempting the fixed-point pipeline, write the general-purpose register status value read by the first instruction into the first physical register P11.

[0043] Once the bottom wake-up signal apx_wake goes high, the control register / enable signal apx_grab is immediately set to 1, instantly shutting down the strobe signals of the four ALU write ports and opening the 5th channel of the WB multiplexer (Write-Back Multiplexer). The 16-bit INIT state read from the EGPR-init array in the same clock cycle is zero-extended to 64 bits {48′b0, INIT[15:0]}, and sent to the APX channel along with the DestPRF (P11) given by ROB. On the next rising edge of the clock, the multiplexer directly writes this 64-bit data back to P11 of the physical register file PRF. After the write is completed, it sends DONE=1 back to ROB. Then apx_grab is automatically pulled low, and the ALU write ports are reopened. The entire preemptive write port process ends precisely within one WB cycle.

[0044] The preemptive multiplexer directly sends the 64-bit {48′b0, INIT[15:0]} to the PRF write port. The address is selected by P11 given by ROB. The PRF completes the writing on the rising edge of the clock and immediately outputs the wb_done pulse. In the same pulse, the corresponding item DONE of ROB is set to 1. Since RetPtr already points to this item, the next cycle RetPtr increments to release the ROB item and update the architecture state. APXGetS then completes the sequential commit and retirement.

[0045] In this embodiment, after the decoding unit identifies APXGetS T0, it directly outputs the bottom execution flag and locks the target register T0. Subsequent pipelines then enter a dedicated bypass channel, bypassing the transmit queue. During the renaming phase, T0 is mapped to P11, skipping ALQS / AGSQ reservations, occupying only the ROB entry and setting DONE=0, while simultaneously writing the Bottom-Exec flag to ensure the instruction is only woken up at the oldest position. APXGetS T0 bypasses ALQS / AGSQ and directly registers the ROB, saving transmit slots and comparator area.

[0046] When RetPtr equals RID and Bottom-Exec is active, the combinational logic instantaneously pulls apx_wake high, opens the EGPR-init array, reads the INIT bits of R16-R31 and concatenates them into a 64-bit {48′b0,State[15:0]}, preparing for write-back. Bottom wake-up uses only the RetPtr==RID combinational logic, eliminating row-by-row RID-vs-RetPtr toggling, significantly reducing dynamic power consumption.

[0047] `apx_grab` is set to 1 to mask the ALU write port for 1 cycle. WB-MUX selects the APX channel, writes the 64-bit status value to P11, and `wb_done` is set to DONE=1 in the same cycle. In the next cycle, `RetPtr` is incremented, and instructions are committed and retired sequentially upon completion. WB-MUX completes the 64-bit write-back using 1T of the ALU write port, without adding any new ports, and the IPC impact is approximately 0. XSAVE / XRSTOR skips the all-zero register with a 64-bit mask, reducing storage bandwidth by 30–60% and shortening VM / process switching by tens of nanoseconds.

[0048] The following is combined Figure 3a and Figure 3c The execution of the APXGetS T0 instruction is explained in detail.

[0049] During the decoding stage, the decoding unit completes instruction recognition, source / destination register index extraction, immediate value expansion, load / store width and alignment attribute calculation, and generates corresponding control flow signals (branch type, prediction direction, exception type, etc.). Specifically, the determination of the APXGetS T0 instruction is completed by the instruction decoding and opcode mapping logic within the decoding unit. Based on the combination of the instruction prefix, main opcode, and ModR / M field, it matches with the microcode ROM or hardwired table. Once the encoding of the APXGetS T0 instruction is matched, the APXGetS T0 instruction type flag is output and the target register field is locked as T0. At the same time, the corresponding bottom execution control signals are generated, and the subsequent pipeline enters the dedicated data path of the APXGetS T0 instruction accordingly.

[0050] After the decoding unit completes the recognition of the APXGetS T0 instruction, during the renaming phase, it first extracts the T0 field from the instruction and treats it as the target architecture register. Then, it selects an available item (e.g., P11) from the free physical register pool and establishes a new mapping in the RAT, binding the logical register T0 to the physical register P11. From then on, all subsequent read and write operations on T0 are redirected to P11. For the APXGetS T0 instruction, the hardware does not generate ALU / AGSQ requests, does not occupy the issue queue, and does not occupy the ALU / AGU pipeline.

[0051] The APXGetS T0 instruction does not need to enter the ALU or AGU pipeline. The renaming unit records the type code of APXGetS in the ROB, indicating that this microinstruction must wait until the commit pointer RetPtr points to itself before it can be awakened. The completion flag DONE of the APXGetST0 instruction is set to zero. At this time, the storage structure of the ROB is as follows: Figure 3a . Figure 3a This is a schematic diagram of the storage structure for a ROB awaiting execution. The first column, RID, is the index value of the microinstruction in the ROB; the index value of the microinstruction ADD is 0X26. The second column, TYPE, indicates the microinstruction type; for example, index value 0X26 is ADD, and index value 0X27 is APXGetS. The third column, ARF, lists the target architecture registers (such as R8 and R9). The fourth column, PRF, lists the renamed physical register numbers (P10, P11, P12), used for internal data temporary storage. The fifth column, DONE, is a flag used to indicate the completion status: 0 for not executed and 1 for executed.

[0052] The instruction commit pointer RetPtr is used to point to the oldest position in the ROB. Figure 3a The fact that RetPtr points to RID=0X26 indicates that only this line can be committed; APXGetS (RID=0X27) is not the oldest micro-operation, and APXGetS is still in the waiting execution phase.

[0053] Figure 3b This diagram illustrates the memory structure for waking up the execution ROB. At 0x26, ADD is written back and DONE=1 is set, RetPtr moves down to RID=0x27, at which point APXGetS becomes the oldest microinstruction. However, because the completion flag DONE=0, APXGetS cannot be committed. At this point, preparation is made to execute APXGetS. A bottom wake-up pulse is immediately issued during the Retirement phase; in the same pulse, the ROB reads the statically stored uOP_TYPE_APXGetS (microinstruction is APXGetS) and DestPRF (physical register number) fields, and latches the target physical register number P11 into the apx_dest register. Simultaneously, the apx_wake pulse opens the EGPR-init read-only array, reads bits 17 to 32 (R16-R31) of the general-purpose register EGPR (the architecture status bits INIT), and obtains the state vector EGPR (R16-R31). The state vector is padded with 48 bits of 0 data to form the state data ({48'b0,State[15:0]}). The 64-bit state data ({48'b0,State[15:0]}) is latched into physical register P11 to update the PRF.

[0054] Figure 3cThis is a schematic diagram of the storage structure for the submit instruction ROB. Because the write port of the fixed-point physical register is bound to the emit queue execution pipeline, APXGetS does not enter the emit queue and therefore has no corresponding write port. Therefore, when APXGetS executes, it needs to block the emit queue pipeline for one cycle to preempt the corresponding write port and write the acquired status data into the target physical register P11. Once the bottom wake-up signal apx_wake goes high, the control register / enable signal apx_grab is immediately set to 1, instantly shutting down the strobe signals of the four ALU write ports and opening the 5th channel of the WB multiplexer (Write-Back Multiplexer); in the same clock cycle, the status data ({48'b0,State[15:0]}) along with the DestPRF (P11) provided by ROB is sent to the APX channel. On the next rising edge of the clock, the multiplexer directly writes this 64-bit data back to P11 of the physical register file PRF. After the write is completed, DONE=1 is fed back to ROB. Then apx_grab is automatically pulled low, and the ALU write ports are reopened. The entire preemptive write port process ends precisely within one WB cycle.

[0055] The preemptive multiplexer directly sends the 64-bit {48′b0, INIT[15:0]} to the PRF write port. The address is selected by P11 given by ROB. The PRF completes the writing on the rising edge of the clock and immediately outputs the wb_done pulse. In the same pulse, the corresponding item DONE of ROB is set to 1. Since RetPtr already points to this item, the next cycle RetPtr increments to release the ROB item and update the architecture state. APXGetS then completes the sequential commit and retirement.

[0056] Figure 4 This is a schematic diagram of the EGPR (R16–R31) state vector data structure provided in this embodiment. The left column lists the 16 extended architecture register numbers, and the right column corresponds to a 1-bit INIT flag: 1 indicates that the register is currently still in its initial all-zero value, and 0 indicates that non-zero data has been written to it. The 16 INIT bits are concatenated side by side to form a 16-bit state vector State[15:0], which serves as the source data directly read by the APXGetS instruction and is used for the subsequent generation of the 64-bit state mask.

[0057] Figure 5 This is a schematic diagram of the architecture of a processor provided in an embodiment of the present disclosure. The processor includes: an instruction fetch unit 501, a decoding unit 502, a renaming unit 503, a micro-operation unit 504, and the reordering buffer 505.

[0058] The instruction fetch unit 501 is used to fetch input instructions.

[0059] Decoding unit 502 is used to decode the instruction content.

[0060] The renaming unit 503 is used to immediately allocate a ROB entry to the first instruction APXGetS T0 after it is identified, and to forcibly clear the completion flag DONE to zero, while skipping the ALQS / AGSQ launch queue reservation.

[0061] The micro-operation unit 504 is used to wake up the first instruction to read the general-purpose register status value when the first instruction is the oldest micro-instruction in the reordering buffer 505; preempt the fixed-point pipeline and write the general-purpose register status value into the first physical register P11.

[0062] The reorder buffer 505 is used for out-of-order execution and sequential commit of the superscalar processor. After instruction decoding, it is written into the ROB in instruction order, containing basic instruction information such as instruction type, instruction architecture registers, and corresponding physical registers. The ROB assigns a microinstruction index value (RID) to each instruction. The RID is the ROB index and can also be used to indicate the age of instructions. Instructions are decoded sequentially, renamed, written into the ROB, and issued to the execution unit. The execution unit executes them out of order, and when certain conditions are met, they are committed sequentially and the system state is updated. The ROB maintains a Retptr (instruction commit pointer, pointing to the oldest position in the ROB), pointing to the oldest ROB entry. Only after the corresponding microinstruction is completed and committed can younger microinstructions be committed sequentially. The ROB also maintains a DispPtr (instruction issue pointer, pointing to the youngest position in the ROB), pointing to the youngest position, which is the position where the next decoded microinstruction will be written.

[0063] The renaming unit 503 is also used to map the temporary architecture register T0 of the first instruction to the first physical register P11 and update the remapping table.

[0064] Micro-operation unit 504 is further configured to set the completion flag DONE of the first instruction to zero; when the retirement pointer RetPtr of the reordering buffer ROB points to the first instruction, the first instruction is the oldest micro-instruction in the reordering buffer ROB; when the retirement pointer RetPtr does not point to the first instruction, the first instruction remains in a pending execution state; read the architecture status bits of the general-purpose register EGPR according to the first instruction to obtain status vector data; read bits 17 to 32 of the general-purpose register EGPR according to the first instruction (… The state vector (EGPR(R16-R31)) is obtained by the INIT state bit of the R16-R31 architecture; 48 bits of 0 data are filled before the state vector to form the state data ({48'b0,State[15:0]}); when the first instruction is executed, the fixed-point pipeline of the fixed-point instruction issue queue is blocked for one cycle, and the corresponding write port is preempted; after the general-purpose register state value is written to the first physical register P11, the completion flag bit DONE of the first instruction in the reordering buffer ROB is set to 1; the retirement pointer RetPtr is incremented by 1, and the first instruction is released in the reordering buffer ROB.

[0065] It should be noted that, Figure 5 The instruction fetch unit 501, decoding unit 502, renaming unit 503, micro-operation unit 504, and reordering buffer 505 shown can be logic circuit units in a processor. Furthermore, it is understood that... Figure 5 The processor is only shown as an example of some optional structures. The processor may also include other possible devices, such as other circuit devices that are not essential for understanding the contents of this disclosure. Since other circuit devices are not essential for understanding the contents of this disclosure, they will not be described in detail here.

[0066] In the specific embodiment disclosed herein, after the first instruction APXGetS T0 is identified during the decoding stage, an ROB entry is immediately allocated to it and the completion flag DONE is forcibly cleared. At the same time, the ALQS / AGSQ launch queue reservation is skipped, and only the "bottom execution" and "EGPR read" attributes are written to the reorder buffer 505. At this time, the retirement pointer RetPtr has not yet pointed to this entry, and the instruction enters a pure waiting state, without occupying any execution bandwidth or updating the architecture state, ensuring that the INIT bit remains up-to-date before subsequent wake-ups.

[0067] When RetPtr advances and equals the RID of the ROB row, the bottom wake-up logic immediately issues an apx_wake pulse: within the same clock cycle, the micro-operation unit 504 reads the 16-bit INIT flags of R16 to R31 from the EGPR zero-state array at once, forming a 16-bit vector State[15:0], and fills its high 48 bits with constant 0, concatenating them into 64-bit state data {48′b0, State[15:0]}; at the same time, the control state machine pulls the apx_grab signal high, reserving the WB write port for the next cycle, preparing for preemption of the fixed-point pipeline, while the ALU write port will be temporarily shielded in the following clock cycle to ensure no data path conflict.

[0068] On the next rising edge of the clock, the WB multiplexer selects the APX channel and writes the 64-bit status value to the first physical register P11 provided by ROB. The PRF immediately returns the wb_done pulse. On the same clock cycle, the corresponding DONE value of the ROB is set to 1, the retirement pointer RetPtr is incremented by 1, the current item is released and the architecture mapping is updated. The first instruction APXGetS T0 completes the sequential commit, and subsequent XSAVE / XRSTOR can directly read P11 to obtain the EGPR zero-state mask, thus saving bandwidth during context switching.

[0069] As another optional implementation of the content disclosed in this disclosure, this disclosure provides a chip that includes the processor provided in any embodiment of this disclosure.

[0070] As another optional implementation of the content disclosed in this disclosure, this disclosure provides an electronic device that includes the chip provided in any embodiment of this disclosure. This electronic device can be a terminal device or a cloud server device.

[0071] The foregoing describes multiple embodiment schemes provided by the present disclosure. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and made public by the present disclosure.

[0072] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

[0073] Various changes, substitutions, and modifications can be made to the technology herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.

[0074] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0075] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. An instruction processing method, characterized in that, Includes the following steps: Obtain the input command and read the command content; When the instruction is the first instruction, the first instruction is written directly into the reorder buffer (ROB) without going through the instruction issue queue; When the first instruction is the oldest microinstruction in the reorder buffer (ROB), the first instruction is woken up to read the first data; After preempting the fixed-point pipeline, the first data read by the first instruction is written into the first physical register (P11).

2. The instruction processing method according to claim 1, characterized in that, The first instruction is the APXGetS T0 instruction, and the first data is the general-purpose register status value.

3. The instruction processing method according to claim 1 or 2, characterized in that, The step of writing the first instruction directly into the reorder buffer (ROB) without going through the instruction issue queue includes: After decoding the first instruction, the temporary architecture register (T0) is mapped to the first physical register (P11) during the renaming phase, and the remapping table is updated. The APXGetS T0 instruction is not written to the instruction issue queue, but directly written to the reorder buffer (ROB), and the completion flag (DONE) of the APXGetS T0 instruction is set to zero.

4. The instruction processing method according to claim 1 or 2, characterized in that, The condition that the first instruction is the oldest microinstruction in the reorder buffer (ROB) includes: When the retirement pointer (RetPtr) of the reorder buffer (ROB) points to the first instruction, the first instruction is the oldest microinstruction in the reorder buffer (ROB). When the retirement pointer (RetPtr) does not point to the first instruction, the first instruction remains in a pending execution state.

5. The instruction processing method according to claim 1 or 2, characterized in that, The step of waking up the first instruction to read the first data includes: The first instruction reads the architecture status bits of the general-purpose register (EGPR) to obtain the status vector data.

6. The instruction processing method according to claim 5, characterized in that, The first instruction reads the architecture status bits of the general-purpose register (EGPR) to obtain state vector data, including: The first instruction reads the architecture status bits (INIT) from bits 17 to 32 (R16 to R31) of the general-purpose register (EGPR) to obtain the status vector (EGPR(R16-R31)). The state vector is padded with 48 bits of 0 data to form the state data ({48'b0,State[15:0]}).

7. The instruction processing method according to claim 1 or 2, characterized in that, The designated acquisition assembly line includes: When the first instruction is executed, the fixed-point pipeline of the instruction issuance queue is blocked for one cycle, and the corresponding write port is preempted.

8. The instruction processing method according to claim 2, characterized in that: After the general-purpose register status value is written to the first physical register (P11), the completion flag (DONE) of the first instruction in the reorder buffer (ROB) is set to 1; Increment the retirement pointer (RetPtr) by 1 and release the first instruction in the reorder buffer (ROB).

9. A processor, characterized in that, include: The instruction fetch unit is used to fetch input instructions; Decoding unit, used to decode the instruction content; The renaming unit is used to determine that the instruction is the first instruction and write the first instruction directly into the reorder buffer (ROB) without going through the instruction issue queue. The reorder buffer (ROB) is used for out-of-order execution and sequential submission of instructions; The micro-operation unit is used to wake up the first instruction to read the first data when the first instruction is the oldest micro-instruction in the reorder buffer (ROB); after preempting the fixed-point pipeline, it writes the first data read by the first instruction into the first physical register (P11).

10. The processor according to claim 9, characterized in that, The first instruction is the APXGetS T0 instruction, and the first data is the general-purpose register status value.

11. The processor according to claim 9 or 10, characterized in that, The renaming unit is used to map the temporary architecture register (T0) of the first instruction to the first physical register (P11) and update the remapping table.

12. The processor according to claim 11, characterized in that, The micro-operation unit is used for: Set the completion flag (DONE) of the first instruction to zero.

13. The processor according to claim 9 or 10, characterized in that, The micro-operation unit is used for: When the retirement pointer (RetPtr) of the reorder buffer (ROB) points to the first instruction, the first instruction is the oldest microinstruction in the reorder buffer (ROB). When the retirement pointer (RetPtr) does not point to the first instruction, the first instruction remains in a pending execution state.

14. The processor according to claim 9 or 10, characterized in that, The micro-operation unit is used for: The first instruction reads the architecture status bits of the general-purpose register (EGPR) to obtain the status vector data.

15. The processor according to claim 14, characterized in that, The micro-operation unit is used for: The first instruction reads the architecture status bits (INIT) of the general-purpose register (EGPR) from bits 17 to 32 (R16 to R31) to obtain the status vector (EGPR(R16-R31)). The state vector is padded with 48 bits of 0 data to form the state data ({48'b0,State[15:0]}).

16. The processor according to claim 9 or 10, characterized in that, The micro-operation unit is used for: When the first instruction is executed, the fixed-point pipeline of the instruction issuance queue is blocked for one cycle, and the corresponding write port is preempted.

17. The processor according to claim 9 or 10, characterized in that, The micro-operation unit is used for: After the general-purpose register status value is written to the first physical register (P11), the completion flag (DONE) of the first instruction in the reorder buffer (ROB) is set to 1; Increment the retirement pointer (RetPtr) by 1 and release the first instruction in the reorder buffer (ROB).

18. A method for processing the APXGetS T0 instruction, characterized in that, Includes the following steps: During the decoding stage, the instructions are decoded; During the renaming phase, if the instruction is APXGetS T0, the APXGetS T0 instruction is written directly to the reorder buffer (ROB), and the temporary architecture register (T0) is mapped to the first physical register (P11). When the APXGetS T0 instruction is the oldest microinstruction in the reorder buffer (ROB), the APXGetST0 instruction is woken up to read the general-purpose register status value; Preempt the fixed-point pipeline and write the status value of the general-purpose register into the first physical register (P11).

19. The APXGetS T0 instruction processing method according to claim 18, characterized in that: After the APXGetS T0 instruction is directly written to the reorder buffer (ROB), the completion flag (DONE) of the APXGetS T0 instruction is set to zero; After the general-purpose register status value is written to the first physical register (P11), the completion flag (DONE) of the first instruction in the reorder buffer (ROB) is set to 1.

20. A processor, characterized in that, include: The decoding unit is used to decode instructions; The renaming unit is used to write the APXGetS T0 instruction directly into the reorder buffer (ROB) if the instruction is an APXGetS T0 instruction, and to map the temporary architecture register (T0) to the first physical register (P11). The micro-operation unit is used to wake up the APXGetS T0 instruction to read the general-purpose register status value when the APXGetS T0 instruction is the oldest micro-instruction in the reorder buffer (ROB); preempt the fixed-point pipeline and write the general-purpose register status value into the first physical register (P11).

21. The processor according to claim 20, characterized in that, The micro-operation unit is also used to set the completion flag (DONE) of the APXGetS T0 instruction to zero when the APXGetS T0 instruction is directly written into the reorder buffer (ROB). After the general-purpose register status value is written to the first physical register (P11), the completion flag (DONE) of the first instruction in the reorder buffer (ROB) is set to 1.

22. A chip, characterized in that, Includes the processor described in any one of claims 9 to 17, 20 and 21.

23. An electronic device, characterized in that, Includes the chip described in claim 22.

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