A package model and method for a switched filter

By employing a combination structure of beryllium oxide substrate, GaAs chip, and electromagnetically shielded copper alloy package cover in the switching filter, the problems of electromagnetic interference, insertion loss, and insufficient reliability in traditional packaging are solved, achieving low-loss, high-shield packaging effect and improving integration.

CN122174773APending Publication Date: 2026-06-09NANJING UNIV OF POSTS & TELECOMM

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
NANJING UNIV OF POSTS & TELECOMM
Filing Date
2026-03-05
Publication Date
2026-06-09

AI Technical Summary

Technical Problem

Traditional switching filter packaging suffers from severe electromagnetic interference, high insertion loss, insufficient reliability, and low integration, making it difficult to meet the performance requirements of high-frequency communication.

Method used

A combination structure consisting of a beryllium oxide substrate, a GaAs semiconductor chip, an electromagnetically shielded copper alloy encapsulation cap, and an epoxy resin sealing layer, combined with gold wire bonding and laser welding technologies, is used to form a low-loss, high-shield encapsulation model.

Benefits of technology

It improves electromagnetic compatibility, reduces insertion loss, enhances device reliability and integration, and meets the performance requirements of high-frequency communication.

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Abstract

This invention proposes a packaging model and method for a switching filter, relating to the field of electronic component packaging technology. The packaging model includes a fabricated packaging substrate, a switching chip and a filter chip disposed on the substrate, and a packaging cover covering the packaging shell. The substrate integrates matching circuits and interconnect structures, and the packaging cover is made of electromagnetic shielding material. The packaging method includes steps such as substrate pretreatment, chip mounting, wire bonding, packaging cover soldering, and performance testing. This invention, through optimized packaging structure design, effectively reduces the insertion loss and electromagnetic interference of the switching filter, improves its high-frequency performance and reliability, and is suitable for signal processing systems in fields such as communications and radar.
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Description

Technical Field

[0001] This invention relates to the field of electronic component packaging technology, specifically to a packaging model and method for a switching filter. Background Technology

[0002] Switched filters, as core components of radio frequency (RF) front-ends, are widely used in wireless communication, radar detection, satellite navigation, and other fields. With the development of communication technologies towards higher frequency bands (such as millimeter waves and terahertz), the performance requirements for switched filters are increasing, including low insertion loss, high isolation, fast switching speed, and good electromagnetic compatibility. However, traditional packaging methods have the following problems:

[0003] 1. Severe electromagnetic interference: High-frequency signals are prone to crosstalk through packaging gaps or substrate coupling, resulting in signal distortion.

[0004] 2. High insertion loss: Package parasitic parameters such as lead inductance and substrate capacitance increase signal transmission loss and affect system sensitivity.

[0005] 3. Insufficient reliability: Environmental factors such as high temperature and humidity can easily cause the packaging material to age, reducing the life of the device.

[0006] 4. Low integration: The packaging methods of discrete components are difficult to meet the requirements of miniaturization and high-density integration. Summary of the Invention

[0007] This invention proposes a packaging model and method for a switched filter, aiming to solve the problems of high electromagnetic interference, high insertion loss, low reliability, and insufficient integration in existing switched filter packaging. The technical solution provided by this invention is as follows:

[0008] Firstly, a packaging model for a switched filter includes:

[0009] The substrate has an inner layer made of beryllium oxide and an embedded slotted structure to position the chip placement. The outer layer integrates microstrip line matching circuits and metallized vias.

[0010] The switch chip is made of GaAs semiconductor material. Its surface has an input port RFC, an output port RF1-RF4, a power control VDD, and switch control pins IN1-IN3. It is fixed to the substrate by conductive adhesive and connected by gold wire bonding.

[0011] Four filter chips, made of GaAs semiconductor material, have an input port RFIN and an output port RFOUT on their surface. They are fixed to a predetermined position on the substrate with conductive adhesive and connected by gold wire bonding.

[0012] The encapsulation cover is made of copper alloy, an electromagnetic shielding material, with an electroplated passivation layer on the surface and a coating containing wave-absorbing material sprayed on the inside. It is then laser-welded onto the chip.

[0013] The sealing layer is located at the connection between the encapsulation cover and the substrate, and is formed by curing epoxy resin sealant.

[0014] Preferably, the outer surface of the substrate is covered with copper for circuit traces and large-area ground plane, with a copper thickness of 30μm and a 0.1μm gold layer deposited on the surface.

[0015] Preferably, the size of the switch chip is 2×1.8×0.1mm, and the size of the filter chip is 1.7×0.9×0.1mm.

[0016] Preferably, the size of the encapsulation cap is 4.76×7.26×0.1mm.

[0017] Secondly, a method for packaging a switched filter includes the following steps:

[0018] Substrate fabrication: A beryllium oxide ceramic substrate was selected. Copper was used as the circuit trace and ground plane on the outside of the substrate. The copper thickness was 30 μm. The copper thickness of the microstrip trace was 0.3 mm. A 0.1 μm gold layer was deposited on the surface and a 50Ω microstrip matching circuit and metallized vias were fabricated by photolithography.

[0019] Chip mounting: Fix the switch chip to the center of the substrate, and fix four filter chips around the switch chip. Use conductive adhesive to fix them and cure at 150°C for 1 hour.

[0020] Gold wire bonding: Using 25μm diameter gold wires to bond the chip pins to the substrate interconnect structure at 200℃, with a bonding strength ≥5g;

[0021] Packaging cover preparation: Copper alloy is selected, and a passivation layer is formed on the surface of the copper cover using an electroplating process. A coating containing microwave absorbing material is sprayed on the part of the copper cover that does not contact the tube shell.

[0022] Sealing process: With the microwave-absorbing coating facing down, apply epoxy resin sealant and cure at 100°C for 45 minutes;

[0023] Encapsulation cap welding: The encapsulation cap is fixed to the substrate by laser welding with a welding power of 50W and a time of 10ms.

[0024] Compared with the prior art, the beneficial effects achieved by the present invention are:

[0025] (a) Improved electromagnetic compatibility: The shielding structure and absorbing material of the encapsulation cover effectively reduce electromagnetic radiation and external interference.

[0026] (ii) Reduced insertion loss: Low-loss substrates and optimized interconnect structures reduce signal transmission loss.

[0027] (iii) Enhanced reliability: The sealing layer and thermal matching design improve the device's moisture resistance and thermal stability.

[0028] (iv) Increased integration: Matching circuits are integrated on the substrate, reducing the use of discrete components. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0030] Figure 1 A schematic diagram of the main process of the packaging method for the switching filter provided by the present invention;

[0031] Figure 2 This is a schematic diagram of the overall 3D structure of the encapsulation model of the present invention;

[0032] Figure 3 This is a 3D structural diagram of the substrate after slotting according to the present invention;

[0033] Figure 4 A schematic diagram of the 3D structure of the substrate after copper plating and gold immersion in the present invention.

[0034] Figure 5 This is a schematic diagram of the 3D structure of the filter of the present invention;

[0035] Figure 6 This is a 3D structural diagram of the switch of the present invention;

[0036] Figure 7 This is a 3D structural diagram of the cover plate of the present invention;

[0037] Figure 8 This is a schematic diagram of the top surface of the substrate after copper plating and gold plating of the present invention;

[0038] Figure 9 This is a schematic diagram of the chip's interconnect layout in this invention.

[0039] Figure 10 This is a simulation result of the insertion loss at the port of this invention.

[0040] Figure 11 This is a simulation diagram of the input return loss at the port of this invention. Detailed Implementation

[0041] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] To make the above-mentioned objectives, features and effects of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] Example 1: Reference Figures 2 to 7 A packaging model for a switching filter, comprising:

[0044] The substrate has an inner layer made of beryllium oxide with an embedded slotted structure to position the chip. The outer layer integrates microstrip line matching circuits and metallized vias to achieve signal matching and electrical connection between the chip and external circuits. The outer part of the substrate uses copper plating for circuit traces and a large area ground plane, with a copper thickness of 30μm and a 0.1μm gold layer deposited on the surface.

[0045] The switch chip is made of GaAs semiconductor material and has an input port RFC, an output port RF1-RF4, a power control VDD, and switch control pins IN1-IN3 on its surface. The back of the chip is fixed to the substrate by conductive adhesive mounting and the circuit is connected by gold wire bonding. The preferred size of the switch chip is 2×1.8×0.1mm.

[0046] Four filter chips, made of GaAs semiconductor material, have an input port RFIN and an output port RFOUT on their surface. The control function is realized by a switch chip. They are fixed to predetermined positions on the substrate by conductive adhesive and connected by gold wire bonding. The preferred size of the filter chip is 1.7×0.9×0.1mm.

[0047] The encapsulation cover is made of copper alloy, an electromagnetic shielding material, with an electroplated passivation layer on the surface and a coating containing microwave absorbing material sprayed on the inside. It is then laser-welded over the chip to form a closed shielding cavity to suppress electromagnetic radiation and external interference. The preferred dimensions of the encapsulation cover are 4.76 × 7.26 × 0.1 mm.

[0048] The sealing layer, located at the connection between the encapsulation cover and the substrate, is formed by curing epoxy resin sealant to ensure the airtightness and moisture resistance of the encapsulation.

[0049] This embodiment provides a simulation model test result, such as Figure 10 and Figure 11As shown, the single-port S-parameter loss S21 is less than 0.1dB, and the return loss S11 is less than -20dB within 20GHz.

[0050] Example 2: A packaging method for a switching filter, such as... Figure 1 As shown, it includes the following steps:

[0051] Substrate fabrication: A beryllium oxide ceramic substrate was selected. Copper was used as the circuit trace and ground plane on the outside of the substrate. The copper thickness was 30 μm. The copper thickness of the microstrip trace was 0.3 mm. A 0.1 μm gold layer was deposited on the surface and a 50Ω microstrip matching circuit and metallized vias were fabricated by photolithography.

[0052] Chip mounting: Fix the switch chip at center A of the substrate, and fix the four filter chips at points B, C, D and E of the substrate respectively. Use conductive adhesive to fix them and cure at 150°C for 1 hour.

[0053] Gold wire bonding: Using 25μm diameter gold wires at 200℃ to bond the chip pins to the substrate interconnect structure, with a bonding strength ≥5g. Figure 9 This is a schematic diagram of the overall chip supply chain.

[0054] Packaging cover preparation: Copper alloy is selected to enhance the chip's heat dissipation capacity. Electroplating is used to form a passivation layer on the surface of the copper cover to prevent oxidation. On the part of the copper cover that does not contact the casing, a coating containing microwave absorbing material is sprayed to solve the problems of electromagnetic interference and signal integrity within the chip package.

[0055] Sealing process: With the microwave-absorbing coating facing down, apply epoxy resin sealant and cure at 100°C for 45 minutes;

[0056] Encapsulation cap welding: The encapsulation cap is fixed to the substrate by laser welding with a welding power of 50W and a time of 10ms.

[0057] The specific steps for substrate fabrication are as follows:

[0058] (a) Cleaning the substrate aims to thoroughly remove contaminants (such as particles, organic matter, metal ions, static electricity, etc.) without damaging the substrate surface. The steps include:

[0059] Pre-cleaning and deep decontamination remove most organic and inorganic contaminants generated during the packaging process, such as flux residue, solder paste, grease, particles, and metal ions. The substrate is immersed in a bath containing a specialized semi-aqueous cleaning agent or a weakly alkaline aqueous cleaning agent (pH 9-11). Ultrasonic cleaning (40kHz) is then initiated to physically remove contaminants using cavitation. The temperature is typically controlled at 50-65°C, and the time is approximately 3-10 minutes.

[0060] Multi-stage countercurrent rinsing thoroughly removes residual chemical cleaning agents and stripped contaminants from the first step, preventing secondary contamination and water stains. The substrate is sequentially transferred into 2-3 rinsing tanks connected in series. The rinsing medium is 18.2 MΩcm ultrapure deionized water (DI water). The countercurrent design ensures the cleanest DI water is injected from the last rinsing tank and replenished progressively with overflow from the next tank, guaranteeing the substrate begins rinsing in the dirtiest water and ends in the cleanest. Megasonic waves (0.8-1 MHz) can be used throughout the process to gently remove submicron particles. The water temperature in the final rinsing tank can be raised to 70-80°C to reduce surface tension and facilitate drying.

[0061] (II) Efficient drying and surface activation aim to completely remove moisture and provide an ultra-clean, highly active surface for subsequent bonding, molding, and other processes. The steps include:

[0062] Efficient drying: Immediately place the rinsed substrate into a centrifugal dryer or hot nitrogen drying equipment. Quickly remove moisture from surfaces and crevices to prevent water stains, which is crucial for reliability.

[0063] Plasma surface activation: The dried substrate is placed in a vacuum plasma cleaner. A mixture of oxygen and argon is introduced. The oxygen plasma completely decomposes residual trace organic matter, while argon ions physically bombard and remove extremely fine particles. This step significantly improves the surface energy of the substrate, greatly enhancing the reliability of subsequent conductive adhesive bonding.

[0064] (iii) Substrate Grooving: The goal of this step is to precisely machine the required grooves and through holes on the alumina ceramic substrate. The steps include:

[0065] Laser cutting: Using ultraviolet or ultrafast lasers, the groove structure is precisely ablated on the substrate according to the design pattern.

[0066] Cleaning process: Ultrasonic cleaning to remove residual ceramic dust and slag from the tank.

[0067] (iv) Metallization treatment, the objective of which is to form a strong, continuous conductive metal layer on the non-conductive ceramic tank walls and bottom, the steps of which include:

[0068] Surface activation: Plasma cleaning or chemical roughening of the inner wall of the tank to improve adhesion.

[0069] Seed layer deposition: A thin copper composite metal layer is uniformly deposited in the tank by magnetron sputtering, with the copper thickness precisely controlled at 30um, and vias are filled using via plugging technology.

[0070] (v) Electroplating gold, the goal of which is to form a pure gold surface with excellent solderability, conductivity and oxidation resistance. The steps include:

[0071] Nickel Plating Preparation and Pretreatment: Thoroughly clean the substrate after patterned electroplating. First, chemically degrease with an alkaline solution, then activate the copper surface with dilute acid to remove the oxide layer. After thorough rinsing with water, immediately immerse in a nickel sulfamate plating solution. Electroplat a dense nickel layer of 3-8µm at 50-60℃, specific pH, and current density. This layer acts as a critical barrier, preventing gold-copper interdiffusion and providing a reliable solder substrate. After plating, thoroughly rinse with water and activate with 5-10% dilute sulfuric acid.

[0072] Electroplating a pure gold layer: The activated substrate is rapidly transferred into an acidic (e.g., citrate system) gold plating bath. Under precisely controlled temperature (40-55℃), current density, and stirring conditions, a 0.05-1.0µm pure gold layer (purity ≥99.99%) is deposited on the nickel layer through electrolysis. This process requires strict parameter control to obtain a fine-grained, low-porosity gold surface, providing an ideal surface for subsequent wire bonding, soldering, or contact.

[0073] Post-treatment and final drying: Immediately after gold plating, a multi-stage countercurrent ultrapure water rinse is performed to thoroughly remove any plating solution residue. This is followed by rapid drying with hot air (or hot nitrogen), or by using a centrifugal dryer to remove surface and crevices moisture. This step ensures the substrate surface is free of water stains, discoloration, and other defects, ultimately yielding a clean, bright product with excellent solderability. The entire process must be carried out in a clean environment, with strict control over the purity of water and chemical reagents.

[0074] (vi) Fabricating matching circuits and interconnect structures using photolithography to realize circuit functions and ensure low loss, the steps of which include:

[0075] Photoresist coating and exposure: Photoresist is spin-coated onto the surface, and ultraviolet exposure is performed through a mask. After development, a circuit pattern window is formed.

[0076] Pattern plating: Electroplating (such as copper plating) is performed using the exposed area as the cathode to thicken circuit lines and vias to the target thickness.

[0077] Photoresist removal and etching: Remove residual photoresist and use chemical etching solution to remove the protected thin seed layer, completing the isolated forming of circuit patterns and vias.

[0078] The specific steps for chip mounting are as follows:

[0079] (a) Substrate and chip pretreatment to ensure that the surfaces of the substrate and chip are free of impurities. The steps include:

[0080] Plasma cleaning: The mounting area of ​​the beryllium oxide substrate and the back of the chip are cleaned with oxygen / argon plasma to thoroughly remove organic contaminants and activate the surface, greatly improving wettability and adhesion.

[0081] Preheating: Preheat the substrate to 80-120°C (depending on the type of adhesive) on a heating table or conveyor belt to reduce the viscosity of the adhesive and promote curing.

[0082] (ii) Dispensing and placement: Confirm the chip position and apply adhesive to ensure chip reliability and heat dissipation. The steps include:

[0083] Precise dispensing: Using a screw valve or jet valve, precisely apply one or several drops of conductive adhesive (silver paste is most common) to the center of the substrate pads. The amount of adhesive must be strictly controlled, ideally covering more than 80% of the back area after the chip is pressed down without overflowing.

[0084] Chip Pickup and Placement: Reference Figure 8 For placement, the chip is picked up by the nozzle of a high-precision pick-and-place machine, aligned with the aid of a vision system, and accurately placed on the dispensing position. Appropriate pressure of 0.5-3N is applied. The switching chip is fixed at the center A of the substrate, and the filter chip is fixed at the center B, C, D, and E of the substrate.

[0085] (iii) Curing: Ensure the chip is completely bonded and attached to the package. The steps include:

[0086] Stepped curing: Transfer the mounted components to a curing oven and cure according to the curing profile provided by the adhesive supplier. A typical profile is: first hold at 100-150℃ for 10-30 minutes to evaporate the solvent, then increase the temperature to 150-250℃ and hold for 60-120 minutes to complete polymerization. Curing must be carried out in a clean, well-ventilated environment.

[0087] Process monitoring: After curing, shear force testing and electrical / thermal conductivity checks are required to ensure the mechanical and electrical reliability of the bond.

[0088] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A packaging model for a switching filter, characterized in that, include: The substrate has an inner layer made of beryllium oxide and an embedded slotted structure to position the chip placement. The outer layer integrates microstrip line matching circuits and metallized vias. The switch chip is made of GaAs semiconductor material. Its surface has an input port RFC, an output port RF1-RF4, a power control VDD, and switch control pins IN1-IN3. It is fixed to the substrate by conductive adhesive and connected by gold wire bonding. Four filter chips, made of GaAs semiconductor material, have an input port RFIN and an output port RFOUT on their surface. They are fixed to a predetermined position on the substrate with conductive adhesive and connected by gold wire bonding. The encapsulation cover is made of copper alloy, an electromagnetic shielding material, with an electroplated passivation layer on the surface and a coating containing wave-absorbing material sprayed on the inside. It is then laser-welded onto the chip. The sealing layer is located at the connection between the encapsulation cover and the substrate, and is formed by curing epoxy resin sealant.

2. The packaging model of a switching filter according to claim 1, characterized in that, The outer side of the substrate is covered with copper for circuit traces and large-area ground plane, with a copper thickness of 30μm and a 0.1μm gold layer deposited on the surface.

3. The packaging model of a switching filter according to claim 1, characterized in that, The size of the switch chip is 2×1.8×0.1mm, and the size of the filter chip is 1.7×0.9×0.1mm.

4. The packaging model of a switching filter according to claim 1, characterized in that, The package cover measures 4.76 × 7.26 × 0.1 mm.

5. A packaging method for a switched filter, characterized in that, Includes the following steps: Substrate fabrication: A beryllium oxide ceramic substrate was selected. Copper was used as the circuit trace and ground plane on the outside of the substrate. The copper thickness was 30 μm. The copper thickness of the microstrip trace was 0.3 mm. A 0.1 μm gold layer was deposited on the surface and a 50Ω microstrip matching circuit and metallized vias were fabricated by photolithography. Chip mounting: Fix the switch chip to the center of the substrate, and fix four filter chips around the switch chip. Use conductive adhesive to fix them and cure at 150°C for 1 hour. Gold wire bonding: Using 25μm diameter gold wires to bond the chip pins to the substrate interconnect structure at 200℃, with a bonding strength ≥5g; Packaging cover preparation: Copper alloy is selected, and a passivation layer is formed on the surface of the copper cover using an electroplating process. A coating containing microwave absorbing material is sprayed on the part of the copper cover that does not contact the tube shell. Sealing process: With the microwave-absorbing coating facing down, apply epoxy resin sealant and cure at 100°C for 45 minutes; Encapsulation cap welding: The encapsulation cap is fixed to the substrate by laser welding with a welding power of 50W and a time of 10ms.