A multi-level interconnection planning method for signal-power-thermal integrity in 2.5d-3d integrated corelets

Abstract

This invention belongs to the field of integrated circuit layout and design technology, specifically relating to a multi-level interconnect planning method for signal-power-thermal integrity in 2.5D-3D integrated chips. It aims to solve the problems of low planning efficiency and design convergence difficulties caused by differences in design rules between silicon interposers and packaging substrates. This invention takes chip placement, chip pin layout, and available wiring resources as inputs. Based on a hierarchical variable scheduling strategy, it divides interconnect design variables into three subsets: interposer design variables, substrate design variables, and bridging variables. A three-stage Bayesian optimization algorithm is used to optimize sequentially: Stage 1 optimizes interposer and bridging variables, generates candidate designs and interconnect layouts, and updates the surrogate model until convergence; Stage 2 optimizes bridging and substrate variables, initializes with the optimal solution from Stage 1, and executes the same process; Stage 3 jointly optimizes all variables, executes the evaluation and update process until convergence; the algorithm finally outputs the optimal set of interconnect design variables.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout design, and provides a multi-level interconnect planning method for signal-power-thermal integrity in 2.5D-3D integrated chips. Background Technology

[0002] As the advantage of Moore's Law diminishes[1], traditional monolithic chips face inherent limitations in terms of performance scaling and cost efficiency[2][3]. To overcome these obstacles, the industry is increasingly turning to chiplet-based designs supported by 2.5D and 3D integration technologies[4][5]. In 2.5D packaging, multiple chips are placed side-by-side on a silicon interposer and interconnected by microbumps, which in turn are connected to the substrate via C4 bumps. Electrical connections are achieved through redistribution layers (RDLs) and through-silicon vias (TSVs) in the interposer, as well as substrate RDLs and planes that connect the C4 bumps to the ball grid array (BGA) solder balls. In contrast, 3D integration vertically stacks chips, with the bottom chip functioning similarly to the interposer, while the overall interconnect scheme remains similar.

[0003] In 2.5D / 3D ICs, interconnects are divided into vertical interconnects (VICs), such as bumps (μbumps, C4 bumps and solder balls) and vias (TSVs, package vias (TPVs) and RDL vias), and planar interconnects (PICs), including interposer conductors and metal planes. These VICs and PICs together determine the overall performance of the system, defining its signal, power, and thermal integrity (SI / PI / TI). SI is primarily determined by PICs, where the trade-off between crosstalk and shielding versus routing capability is a critical issue [6][7]. PI depends on resistive losses in the power supply network (PDN) based on VICs and PICs [8]. TI is dominated by VICs, which provide efficient metal heat conduction paths [9].

[0004] Recognizing the importance of interconnects, existing work has been optimizing them for power and thermal purposes [9]

[10] . However, these studies have only explored narrow design spaces with limited physical constraints. Different design rules between the core and the interposer / substrate complicate the planning of VICs and PICs in 2.5D / 3D ICs. Although the VICs of the interposer and the substrate share some commonalities, their PICs differ significantly due to different manufacturing techniques. In particular, interposer RDLs carry wiring conductors, while substrate RDLs are primarily implemented through planes. Consequently, the design rules for layer stacking and via insertion also differ, leading to different effects on physical design metrics such as PI. Although previous work has planned the interposer

[11] and the substrate

[12] separately, their methods are not scalable to support multi-level co-optimization because they are highly dependent on the characteristics within each level. To address this challenge, this invention proposes a hierarchical variable scheduling strategy that divides design variables into three optimization stages based on physical properties. This is the first study of unified co-optimization of the interposer and the substrate under multiphysics constraints.

[0005] Furthermore, the increased system integration density of 2.5D / 3D systems exacerbates multiphysics coupling, making design convergence more difficult to achieve. Previous works have only addressed a portion of single or multiphysics effects, thus failing to meet design constraints. For example, references

[13]

[14] introduced thermal vias to improve TI, while reference

[15] further incorporated PI into via allocation; however, SI and routing capabilities were not considered. In reference [9], the authors introduced VIC planning for power and signal connections, but they only considered routing capabilities and did not provide any quantitative assessment of SI or PI. In this work, we propose a multi-stage Bayesian optimization algorithm to quantitatively assess multiphysics coupling to overcome the aforementioned challenges. A simplified SI / PI / TI model was developed for rapid evaluation, while hybrid expert (MoE) scoring candidate selection and elite sampling were used to ensure convergence.

[0006] Due to the vast design space defined by the aforementioned competitive metrics, comprehensive design space exploration (DSE) is extremely difficult. Current research reduces the design space by ignoring some design constraints. Floorplet

[16] optimizes chip performance by limiting its scope to chip placement without addressing physical implementation. SYSgen[9] proposes a VIC planning framework that ignores PICs. Furthermore, it only focuses on a finite set of variables in the interposer and fails to explore a broader design space. Therefore, an interconnect planning method is needed that can simultaneously consider the interposer and substrate, comprehensively optimize VICs and PICs, and achieve a balance between signal, power, and thermal integrity. Summary of the Invention

[0007] The purpose of this invention is to solve the problems of low interconnect planning efficiency, difficult design convergence, and high manufacturing cost in 2.5D / 3D integrated chip-level interconnects caused by the tight coupling of multiple physical fields for signal integrity, power integrity, and thermal integrity, as well as the different design rules of the interposer and the substrate.

[0008] To achieve the above objectives, the present invention employs the following technical means:

[0009] This invention provides a multi-level interconnect planning method for signal-power-thermal integrity in 2.5D-3D integrated chips, the method comprising:

[0010] Step 1: Obtain input data, which includes chip placement information, pin mapping information, package type, and wiring resources;

[0011] Step 2: Based on the hierarchical variable scheduling strategy, the interconnect design variables are divided into three subsets: the first subset contains interposer design variables, the second subset contains substrate design variables, and the third subset contains bridging variables, wherein the bridging variables are C4 bump-related parameters;

[0012] Step 3: Optimize sequentially using a three-stage Bayesian optimization algorithm:

[0013] Phase 1: Optimize the first and third subsets, generate candidate design variables, generate interconnect layout, evaluate multiphysics performance and manufacturing cost, update the surrogate model, and use the optimal solution as the initial value for Phase 2 after convergence.

[0014] Phase 2: Optimize the second and third subsets, initialize with the optimal solution from Phase 1, perform the same evaluation and update process as in Phase 1, and use the optimal solution as the initial value for Phase 3 after convergence.

[0015] Phase 3: Jointly optimize the first, second, and third subsets, perform the evaluation and update process, and terminate the optimization after convergence;

[0016] Step 4: Output the final optimized set of optimal interconnect design variables, which are used to guide the physical implementation of vertical and planar interconnects in 2.5D / 3D integration.

[0017] In the above scheme, step 1 includes the following steps:

[0018] Step 1.1: Obtain chip placement information, which includes the physical position, size parameters, and stacking relationship of each chip in the package;

[0019] Step 1.2: Obtain pin mapping information, which includes the pin coordinates of each chip and a list of networks connecting the pins;

[0020] Step 1.3: Obtain the packaging type information, which is used to identify the 2.5D packaging or 3D packaging type;

[0021] Step 1.4: Obtain wiring resource information, which includes the number of interlayer redistribution layers and the interlayer height, the number of interlayer redistribution layers and the interlayer height, and the available wiring area of ​​each layer;

[0022] Step 1.5: Obtain chip power distribution information, which includes power values ​​for each voltage region or spatial power distribution data generated by the architecture simulator.

[0023] In the above scheme, step 2 includes the following steps:

[0024] Step 2.1: Determine the complete set of interconnect design variables The interconnect design variables include the geometric and density parameters of vertical interconnects and the geometric parameters of planar interconnects; wherein, the vertical interconnects include microbumps, C4 bumps, solder balls, through-silicon vias, package vias, and redistribution layer vias; the planar interconnects include the interposer conductor segment parameters and the substrate power plane parameters;

[0025] Step 2.2: Based on physical hierarchy, the interconnection design variables are divided into three categories:

[0026] Intermediate layer dominant variables: Design variables that have a major impact on signal integrity, power integrity, and thermal integrity in the intermediate layer domain;

[0027] Substrate-dominant variables: Design variables that have a major impact on the power integrity and thermal integrity of the substrate domain;

[0028] Bridging variables: C4 bump related parameters, whose physical function is to bridge the power transmission path and heat conduction path between the interposer domain and the substrate domain;

[0029] Step 2.3: Assign the dominant variables of the intermediary layer to the first subset. The dominant variables of the substrate are assigned to the second subset. The bridging variables are then assigned to the third subset;

[0030] Step 2.4: Set the scheduling strategy for the optimization phase: First phase optimization At that time, The variables in the second stage are fixed at preset initial values; At that time, The variables in the third stage are fixed as the optimal solution obtained in the first stage; joint optimization is performed in the third stage. ;

[0031] Where “⧵” is the standard symbol for set difference. This indicates that in the complete set of interconnect design variables X, the first child variable is removed. The set consisting of all variables remaining after the set;

[0032] This indicates that the second child variable is removed from the complete set X of interconnect design variables. The set consisting of all the variables remaining after the set.

[0033] In the above scheme, in step 3, each optimization stage performs the following steps:

[0034] Step 3.1: Generate a set of candidate design variables corresponding to the current subset to be optimized;

[0035] Step 3.2: Input the candidate design variables into the layout generator to generate an initial interconnect layout that satisfies the routing capability constraints. The layout generator prioritizes inter-die signal network routing and reserves minimum routing resources for the power transmission network.

[0036] Step 3.3: Perform multiphysics evaluation on the initial interconnect layout: use the signal integrity model to extract the S-parameters of the transmission lines between the chips, use the power integrity model to calculate the voltage drop of each voltage domain pin, use the electrothermal coupling model to calculate the maximum temperature of each chip, and verify whether the routing resources meet the routing requirements of all networks; at the same time, calculate the manufacturing cost of the current layout based on the interconnect cost model.

[0037] Step 3.4: Feed the evaluation results back to the Bayesian optimization model:

[0038] (a) Update the Gaussian process surrogate model with respect to the objective function and all constraints;

[0039] (b) Cumulative number of feasible solutions If the current evaluation point simultaneously meets all constraints related to signal integrity, power integrity, thermal integrity, and cabling capability, then... Increase by 1;

[0040] (c) Determine whether the current stage has converged according to the preset convergence condition; if it has converged, use the optimal solution of the current stage as the initial value of the next stage and enter the next stage; if all stages have converged, terminate the optimization and output the global optimal solution.

[0041] Among them, the This is a cumulative value that is dynamically maintained during the optimization process. The initial value is the number of feasible solutions generated by the Sobol sequence during the initial trial phase.

[0042] In the above scheme, step 3.1, generating a set of candidate design variables includes: scoring and filtering candidate points in the search space, wherein the scoring includes development score, exploration score and boundary learning score;

[0043] The development score Calculated using the following formula:

[0044]

[0045] in, Let be the posterior mean of the objective function (manufacturing cost). For feasibility probability, Candidate design variables;

[0046] The probability of feasibility Calculated using the following formula:

[0047]

[0048] in, and The first The posterior mean and standard deviation of each constraint. The cumulative distribution function of the standard normal distribution. These are the indices corresponding to signal integrity constraints, power integrity constraints, and thermal integrity constraints, respectively.

[0049] The exploration score Calculated using the following formula:

[0050]

[0051] in, Let be the posterior standard deviation of the objective function. Preset exploration weight coefficients.

[0052] The boundary learning score Calculated using the following formula:

[0053]

[0054] in, These are constraint indices, corresponding to signal integrity, power integrity, and thermal integrity constraints, respectively.

[0055] In the above scheme, in the third optimization stage, step 3.1 further includes an elite sampling step:

[0056] Building an elite group The elite group Contains the most A historically feasible point, The first, representing the concentration of elites One elite point;

[0057] For any candidate point in the search space Calculate its value to the elite set minimum normalized distance :

[0058]

[0059] in, This represents the current candidate design variable vector. The first, representing the concentration of elites One elite point, Represents Euclidean distance. and Each dimension component is normalized to the [1,0] interval according to the corresponding variable range;

[0060] Based on the minimum normalized distance Calculate sampling probability The sampling probability Calculated using the following formula:

[0061]

[0062] in, To uniformly explore the weighting coefficients and , For temperature parameters and , For the current search space The total number of candidate points;

[0063] Based on the sampling probability Probabilistic sampling is performed on candidate points to generate a downsampled candidate set for subsequent Bayesian optimization iterations, in order to achieve a balance between the neighborhood of historical good solutions and the global search space.

[0064] In the above scheme, in step 3.1, after generating the downsampling candidate set, a learned function is used to select the design variable to be evaluated from the candidate set; when When this is the case, the logarithmic feasibility probability is used as the learning function:

[0065]

[0066] in: This represents the probability of feasibility. and The first Posterior mean and standard deviation of a constrained Gaussian process; The cumulative distribution function of the standard normal distribution; These correspond to signal integrity, power integrity, and thermal integrity constraints, respectively.

[0067] when At that time, the logarithmic expectation is used to improve LogEI as the learned function:

[0068]

[0069]

[0070] in: This represents the probability of feasibility. and The first Posterior mean and standard deviation of a constrained Gaussian process; The cumulative distribution function of the standard normal distribution; These correspond to signal integrity, power integrity, and thermal integrity constraints, respectively.

[0071] In the above scheme, step 3.2, generating the interconnection layout includes:

[0072] Vertical interconnect layout: Microbumps and chip leads are arranged one-to-one; C4 bumps and solder balls are arranged in a checkerboard array; Through-Silicon Vias are vertically aligned with C4 bumps, and a single C4 bump fans out to one or more through-silicon vias; Package vias are vertically aligned with solder balls.

[0073] Planar interconnect layout: The signal routing of the interposer layer adopts the G–nS–G scheme. The power supply network is alternately routed in the x–y–x direction between the redistribution layers and vias are set at the intersections. The power supply network of the substrate generates a connection skeleton through the A* algorithm and expands it into a power plane through the k nearest neighbor algorithm.

[0074] In the above scheme, the multiphysics evaluation in step 3.3 includes:

[0075] Signal integrity assessment: A parasitic parameter extraction method based on lookup tables is adopted. The pre-constructed parasitic parameter mapping table is queried according to the interconnect geometry, the equivalent circuit is assembled, and the S-parameters are obtained through SPICE simulation.

[0076] Power integrity assessment: The parasitic extraction method used in the interposer redistribution layer is used to obtain the resistance of segments and vias in the interposer redistribution layer. The power plane of the substrate is discretized into a grid and the unit resistance is calculated. After assembling the equivalent circuit, the voltage drop is calculated by SPICE simulation.

[0077] Thermal integrity assessment: Using a stackable thermal model and combining the regional power distribution output by the architecture simulator, the maximum temperature of each core particle is calculated;

[0078] Cabling capacity verification: Based on the available cabling area, wire width, wire spacing and shielding group size, directly calculate the minimum cabling resources required for each network;

[0079] The signal integrity constraints require inter-grain network insertion loss satisfy: ,in The target threshold is (e.g., -10 dB); the power integrity constraint requires a voltage range. Pin voltage The thermal integrity constraints require core particles highest temperature The cabling capability constraints require the network to... Available cabling resources Each constraint threshold is preset based on the packaging process and circuit requirements.

[0080] In the above scheme, the manufacturing cost calculation adopts the following model:

[0081] Cost of through-hole vertical interconnects:

[0082]

[0083] Cost of convex vertical interconnects:

[0084]

[0085] Cost of planar interconnection on substrate:

[0086]

[0087] Cost of planar interconnection on substrate:

[0088]

[0089] The total manufacturing cost of interconnecting all components is:

[0090]

[0091] in For photolithography costs, This is the process coefficient. For height, For diameter, For density proxy parameters, , For quantity, For width, For length, For copper thickness, The area is the copper area.

[0092] In the above scheme, step 3.4, updating the Bayesian optimization model, includes:

[0093] In this model, adjusting the hardness or softness of the constraints in the Bayesian optimization model as follows helps to accelerate model convergence:

[0094] In this Bayesian optimization model, the learned function considers the influence of constraint hardness and softness in the following product manner:

[0095]

[0096] in These are the LogPoF and LogEI functions mentioned earlier.

[0097] Constraint strictness parameter The stiffness or softness of the constraint can be adjusted: The larger the value, the softer the constraint, which encourages exploration and helps to escape local optima, but the lower the feasibility of the solution. The smaller the value, the stricter the constraint, and the more it encourages development, meaning that the more feasible the solution is, the better it is to explore within known favorable areas.

[0098] This Bayesian optimization model is based on the constraint of the median posterior standard deviation. And recently Feasibility rate of this experiment Dynamically adjust constraint strictness parameters :

[0099]

[0100] in, , , For the most recent The proportion of feasible results in this experiment;

[0101] The convergence condition is: continuity If the optimization objective does not improve within the next iteration, the current stage is considered converged, and the previous stages are considered converged. The next iteration is a warm-up period and is not included in the convergence count.

[0102] Because the present invention employs the above-mentioned technical means, it has the following beneficial effects:

[0103] 1. This invention solves the problem of excessively large search space and difficulty in convergence caused by considering all variables in traditional optimization methods by adopting a hierarchical variable scheduling strategy (step 2) to divide interconnection design variables into three subsets.

[0104] In traditional integrated circuit design optimization, the search space is exceptionally large due to the need to simultaneously consider multiple design parameters, including those related to the interposer, substrate, and bridging variables. This makes the optimization process time-consuming and difficult to converge. The hierarchical variable scheduling strategy proposed in this invention first optimizes the design variables affecting the interposer, then the substrate-related variables, and finally jointly optimizes all variables. This effectively reduces the search space at each stage, improving optimization efficiency and convergence speed.

[0105] This invention achieves comprehensive consideration and optimization of signal integrity, power integrity and thermal integrity through a three-stage Bayesian optimization algorithm (step 3), overcoming the problem of previous studies that only focused on single or multiple physical field effects.

[0106] In existing technologies, optimization of signal integrity, power integrity, and thermal integrity is often performed individually or only one aspect is considered. This makes it difficult for the design to meet comprehensive design requirements in practical applications. The three-stage Bayesian optimization algorithm proposed in this invention evaluates the aforementioned multiphysics performance at each optimization stage and comprehensively considers manufacturing costs, ensuring that the final design can achieve the lowest manufacturing cost while meeting multiphysics constraints.

[0107] This invention solves the problem of local optimal solutions in high-dimensional design space by introducing an elite sampling step (step 3.1) in the third optimization stage, thereby establishing a balance between the neighborhood of historical feasible points and the global search space.

[0108] In high-dimensional design spaces, it is easy to get trapped in local optima, especially in the later stages of optimization, where exploring new regions becomes more difficult. This invention introduces an elite sampling step in the third optimization stage, which performs centralized sampling based on the neighborhood of historical good solutions while retaining a certain proportion of random exploration. This ensures in-depth exploration of the vicinity of known good solutions while avoiding premature convergence to suboptimal solutions, thereby increasing the probability of finding the global optimum.

[0109] This invention combines a hierarchical variable scheduling strategy with a three-stage Bayesian optimization algorithm, resulting in a significant synergistic effect and solving the problems of tight multi-physics coupling and difficult design convergence in complex integrated circuit design.

[0110] While using a hierarchical variable scheduling strategy alone can effectively reduce the search space at each stage, it cannot guarantee consistently high convergence throughout the optimization process. Conversely, relying solely on the Bayesian optimization algorithm may lead to low optimization efficiency due to insufficient initial exploration. This invention combines the two, utilizing a hierarchical variable scheduling strategy to provide an ordered variable partitioning basis for Bayesian optimization, while leveraging the powerful search capabilities of Bayesian optimization. This not only accelerates the entire optimization process but also improves the quality of the final solution, ensuring efficient convergence and high-quality completion of the design. Attached Figure Description

[0111] Figure 1 : A simplified flowchart of the invention;

[0112] Figure 2 Examples of the impact on the following aspects: (a) Signal integrity (SI): Insertion loss increases with increasing shield size; (b) Power integrity (PI): IR drop increases with increasing interposer via pitch; (c) Thermal integrity (TI): Through silicon vias (TSVs) conduct heat and form hot spots.

[0113] Figure 3 Overview of the MIP-SPT framework. "Acq." represents the learned function; "Mfg." represents the manufactured function.

[0114] Figure 4 : Variables are scheduled at different stages using a hierarchical variable scheduling (HVS) strategy;

[0115] Figure 5 Ablation study of downsampling and elite sampling on the execution time decomposition of each stage of MPBO. "Can." represents candidate selection; "Acq." represents the learned function.

[0116] Figure 6 Layout examples. (a) Signal routing on a single redistribution layer (RDL) when n=2; (b) Dual-network power supply network (PDN) on layers M1 and M2; (c) Dual-network board power supply network (PDN) on layer M0.

[0117] Figure 7 Convergence comparison of MIP-SPT and baseline SPBO in Case 1 (first row) and Case 3 (second row). Detailed Implementation

[0118] The embodiments of the present invention will be described in detail below. Although the present invention will be described and illustrated in conjunction with some specific embodiments, it should be noted that the present invention is not limited to these embodiments. On the contrary, any modifications or equivalent substitutions made to the present invention should be covered within the scope of the claims of the present invention.

[0119] Furthermore, to better illustrate the present invention, numerous specific details are set forth in the following detailed embodiments. Those skilled in the art will understand that the present invention can be practiced without these specific details.

[0120] To facilitate a better understanding of the technical concept of this invention by those skilled in the art, the relevant technologies involved in this invention will be further described in detail:

[0121] 1. Interconnection cost model

[0122] In MIP-SPT, manufacturing cost is defined as the primary optimization objective. This section details the corresponding cost model.

[0123] For interconnects with similar process flows, we apply a unified model with interconnect-specific parameters.

[0124] According to previous research

[17] , the cost of vias (including through silicon vias (TSVs), package vias (TPVs), and RDL vias) is expressed in the following equation:

[0125]

[0126] in It is the number of through holes. and Indicates the height and diameter of the through hole. It is a density proxy (e.g., for a spacing of...). Through-hole array, ). It is the cost of photolithography, which is considered an approximate constant. Depth-dependent etching costs were captured. Insulating and barrier layer depositions were combined into a sidewall area component. Volume term Modeling with metal fill, and The density effect of chemical mechanical polishing (CMP) is explained.

[0127] Similarly, the cost modeling for bumps (including μbumps, C4 bumps, and solder balls) is as follows:

[0128]

[0129] in It is the number of bumps. It is the diameter. It is the effective height. It's a density proxy. Cost item. , and These correspond to under-bump metallization (UBM) / pad metallization, solder formation, and CMP penalty, respectively

[18] .

[0130] A key observation is that the cost of VICs depends primarily on their diameter, height, and density. We optimize these design variables in our planning algorithm.

[0131] The cost of PIC is primarily determined by its area; therefore, the relevant variables were optimized in MIP-SPT. The middle segment of the intermediary layer (width is...) The copper thickness is , length is Density proxy is The cost modeling for ) is as follows:

[0132]

[0133] in Coverage-driven steps (patterning and barrier / seed deposition). Proportional to trench etching and copper filling, This corresponds to the CMP penalty.

[0134] The cost of the substrate plane is then modeled as follows:

[0135]

[0136] in It is the copper area. It is a density proxy. Etching covering the metal retention / lamination and the clearing areas, while The CMP penalty is explained.

[0137] The total manufacturing cost of interconnecting all components is:

[0138]

[0139]

[0140] 2. Main Concept

[0141] The input to MIP-SPT is a set of chips and their pin locations, a net list of connecting pins, package type, and routing resources. Our algorithm then outputs interconnect design variables, such as bump pitch, via density, and wire width. The objective is to minimize the total manufacturing cost of the interconnect, which is primarily influenced by the number of VICs and the PIC area. Therefore, the objective function for optimization is defined as follows:

[0142]

[0143] in It is a collection of all VICs, including μbumps, C4 bumps, BGAs, TSVs, TPVs, and RDL vias. It is the collection of all PICs, including segments in the interposer and planes in the substrate.

[0144] In addition to process constraints, we consider four additional constraints in the optimization.

[0145] Cabling Capacity. We selected design variables to ensure sufficient cabling resources and congestion-free cabling across all networks. Special attention was paid to inter-die connections, which are particularly vulnerable to cabling issues due to the high density of transmission lines. During planning, MIP-SPT estimated cabling requirements based on conductor width and spacing constraints and provided capacity accordingly to avoid congestion.

[0146] Signal integrity. We quantify the signal integrity of inter-die connections using the insertion loss derived from S21. The primary source of insertion loss is coupling between adjacent and parallel transmission lines. Grounding shields can mitigate this coupling, but they consume routing traces and stitching via resources, increasing routing utilization and congestion risk. A trade-off must be struck between signal integrity and routing capability.

[0147] Power integrity. Power integrity characterizes the quality of the supply voltage and is a critical issue in PDN. In this work, we focus on voltage drop (IR drop), which is strongly influenced by VIC array density and geometry, conductor width and length, and power plane area—parameters that affect resistance in a PDN. These coupling dependencies expand the design space and complicate planning.

[0148] Thermal integrity. Thermal integrity issues commonly arise in 3D packaging, where vertically stacked cores impede effective heat dissipation from the underlying layers. In such cases, VICs form metal heat conduction paths with strong heat removal capabilities. Therefore, adding VICs not only enhances power distribution but also improves heat transfer. Our algorithm leverages this property to effectively improve both power and thermal integrity.

[0149] Based on the above constraints, the entire problem can be defined as follows:

[0150]

[0151]

[0152] The symbols are shown below: :network Available cabling resources :network Minimum cabling resources required :network Insertion loss, Target insertion loss Voltage region The Middle Voltage of each pin Voltage region Target voltage of the middle pin Core The highest temperature on the surface, Core The target temperature.

[0153] 3. MIP-SPT Framework

[0154] This section introduces our MIP-SPT framework for interconnect planning. We first summarize its components and describe the end-to-end workflow. Then, we describe in detail the proposed Multi-Stage Bayesian Optimization (MPBO). Next, we introduce our layout generation strategy to clarify our assumptions in physical design. Finally, we briefly introduce our models for SI, PI, TI, and architecture simulation.

[0155] 3.1 Overview of MIP-SPT

[0156] An overview of the MIP-SPT framework is as follows: Figure 3 As shown. Given the core placement and pin mapping, MPBO generates a set of high-potential design variables and passes them to the layout generator, which generates initial layouts for VICs and PICs only if routing capability constraints are met. Then, we evaluate multiphysics aspects: the architecture and thermal simulator work together to perform electrothermal simulations and estimate the power and temperature distribution for each core. Voltage drop analysis is performed based on the power in each voltage domain. Simultaneously, the SI module extracts S-parameters based on the transmission line geometry and operating frequency. The resulting SI, PI, and TI metrics are fed back to MPBO to select the next candidate. This loop continues until MPBO converges.

[0157] 3.2 Hierarchical Variable Scheduling Strategy

[0158] Design variables from the interposer and substrate result in a 15-dimensional design space. While not every dimension offers high flexibility for adjustment, the total combinatorial space is... The sheer size of the search space makes convergence extremely challenging, and multiphysics constraints further exacerbate the problem. In principle, physical parameters should monotonically change with some variables (e.g., voltage drop typically decreases with increasing TSV density). However, in practice, physical effects in real-world designs introduce local non-monotonic fluctuations. This behavior makes optimization prone to getting trapped in local optima, especially when the search space is too large for dense sampling, necessitating dimensionality reduction.

[0159] To address this issue, a Hierarchical Variable Scheduling (HVS) strategy is proposed. We will design variable partitioning and optimize it in three stages. In the first stage, subsets... The optimization is performed, while the remaining variables remain fixed. In the second phase, another subset... Adjustments were made. In the third phase, all variables were released, and the entire set was jointly optimized. Each stage begins with a warm-up phase following the previous one.

[0160] The most crucial issue is to determine and Inspired by fundamental physics, we group variables based on the domain in which they primarily have an impact (i.e., the interposer or substrate). Therefore, we attempt to categorize physical parameters into interposer and substrate components. For SI, inter-die signal connections are routed on the interposer, independent of the substrate. For PI, the package PDN can be decomposed into interposer-side and substrate-side sub-networks. The interposer PDN contains μbumps, interposer RDLs, and C4 bumps, while the substrate PDN contains C4 bumps, substrate RDLs, and solder balls. Specifically, C4 bumps are part of both sub-networks because they bridge the two domains. For TI, at the package scale, the overall thermal resistance can be approximated as a series combination of the interposer and substrate conduction paths. C4 bumps are still included on both sides because they are at the domain boundaries.

[0161] Based on this decomposition, we model the multiphysics contributions as approximately separable between domains, where variables in one domain have limited influence on another. This makes staged optimization possible: interposer variables are adjusted in the first stage, substrate / BGA variables in the second stage, and C4-related variables are considered in both stages to capture their bridging effect. and The final partition is in Figure 4 Summary.

[0162] One concern with hierarchical parameter scheduling is the risk of getting trapped in local optima due to parameter freezing in the first and second stages. This problem is carefully addressed in our algorithm. First, we reduce cross-stage coupling through physics-based partitioning, thus mitigating premature convergence. Second, we carefully select initialization points to ensure sufficient search space is reserved for both the first and second stages (Section 4.3.2). Third, we introduce a third stage to jointly optimize all variables as a safety measure to escape suboptimal basins. Based on the experiments in Section 4, our algorithm achieves near-optimal solutions without getting trapped in local optima.

[0163] 3.3 Multi-stage Bayesian optimization

[0164] In the preceding sections, we introduced the design variables in integrated cores. Such a large design space presents challenges for optimization algorithms. Furthermore, due to the time-consuming SI, PI, and TI simulations, the algorithm should converge within an acceptable number of iterations. Bayesian optimization (BO) offers a promising solution to this "black box" problem when we cannot find an analytical expression between the design variables and the multiphysics simulation results. The following subsections introduce the techniques we use to improve MPBO convergence, performance, and runtime.

[0165] 3.3.1 Goal, Constraint, and Proxy Model

[0166] Our goal is to minimize total manufacturing cost. The constraints are SI, PI, TI, and routing capability. The format is written to match the BO convention. We use a Gaussian process (GP) agent and fit independent models for SI, PI, and TI constraints, while routing capabilities are calculated directly based on available routing area, conductor width, conductor spacing, and shield group size.

[0167] 3.3.2 Initialization

[0168] This section introduces the startup strategy and the initialization of the first and second phases. BO typically begins with a small number of startup trials to fit the agent and establish a baseline optimum, ensuring that the improved acquisition works correctly. We use the Sobol sequence to generate these startup trials, which produces a set of quasi-uniform points covering the search domain

[19] . In the first phase, we will... Fixed at a single point, the multiphysics-constrained substrate assembly will not exhaust the available budget, thus enabling optimization. Leave room. In the second phase, we simply... Set to the optimal value found in the first stage. No initialization is needed in the third stage because all variables have been optimized.

[0169] 3.3.3 Candidate Selection

[0170] We refer to the candidates as points selected from the general set for evaluation. Since evaluation acquisition in a large search space is very expensive, we first perform lightweight downsampling.

[0171] set up Let be the set of all points in the search space, with size . For each candidate point We evaluate the Gaussian posterior of the BO agent to obtain the target posterior. and constrained posterior , ,in These correspond to SI, PI, and TI constraints, respectively. We directly calculate routing capabilities and remove candidate points that cause violations. Then, we employ a hybrid expert (MoE) scoring strategy with random backoff, and the scoring is defined as follows:

[0172] (i) Prioritize development scores for feasible areas with high target values:

[0173]

[0174] in

[0175]

[0176] in It is the cumulative distribution function (CDF) of the standard normal distribution.

[0177] (ii) Scoring for exploration of uncertain but promising areas:

[0178]

[0179] (iii) Three-boundary learning scoring to accelerate the identification of feasibility boundaries:

[0180]

[0181] We select the top K candidates based on each score, where K is set as the proportion of N, typically for... For 0.03N, For each 0.02N The value is 0.01N. Furthermore, we randomly sample 0.005N points to mitigate bias in the early stages. By selecting the union of the sets, we obtain a downsampling candidate set that strikes a balance between exploitation, exploration, and feasibility learning. The heuristic downsampling method is applied across all stages, achieving an average speedup of 38x, such as... Figure 5 Summarize.

[0182] Specifically, to address the extremely large search space in the third stage and avoid getting trapped in local optima, we insert an elite mixed sampling step before candidate downsampling in the third stage. We construct a proposal clustered around historically good feasible points (elites) while preserving uniform global exploration. We select the most... Individual elites, forming an elite group For any candidate point The distance to the elite group is:

[0183]

[0184] in and All are normalized by dimension (e.g., to) ).

[0185] Then, we define the sampling probability as a mixture of the softmax and uniform components over the elite distance:

[0186]

[0187] in Control the amount of exploration uniformly. It's about adjusting the temperature around the elites to increase their concentration. yes The size. In the MPBO implementation, we set... and This is to ensure sufficient random sampling to escape local optima.

[0188] This elite sampling simultaneously searches near historical optima and in the global domain, striking a balance between exploitation and exploration. Specifically, it mitigates the tendency for overexploration in the third stage, which can prevent convergence to the optimum. Combined with heuristic downsampling, it significantly reduces the computational workload of the third stage. Runtime results in ablation studies show that candidate selection and acquisition in the third stage achieve a further 7.88x speedup, such as... Figure 5 As shown.

[0189] 3.3.4 Obtaining

[0190] We primarily use Log-Expected Improvement (LogEI) as the learning function. At the start of MPBO, if the number of feasible points is below a preset threshold (…), ), baseline Possibly unstable, LogEI This might bias towards points with high expected improvement but very low feasibility, thus wasting evaluation time. Since we've already included a pilot test, this typically occurs when constraints are tight. In this case, we switch to the log-feasibility probability (LogPoF) as a fallback:

[0191]

[0192] in and It is the first The posterior mean and standard deviation of each constraint. It is the CDF of the standard normal distribution.

[0193] 3.3.5 Adjusting the strictness of constraints

[0194] In our MPBO, constraints are treated as multiplicative weights in the learned function:

[0195]

[0196] hyperparameters Control the "strictness" of constraints. Smaller... This produces a steeper feasibility curve, making the optimizer more conservative, while a larger... Softening the threshold allows for more aggressive exploration near the feasibility boundary.

[0197] We adjusted based on the recent feasibility rate. .set up Indicates recent The proportion of feasible results in this experiment Indicated in these The median of the constrained posterior standard deviations calculated in this trial. Settings:

[0198]

[0199] in Deviation term This adaptive approach tightens when feasible solutions are scarce. Relax when feasible solutions are plentiful This helps to maintain a balance between caution and exploration.

[0200] 3.3.6 Stage Switching and Termination Criteria

[0201] The criteria for phase switching and termination are straightforward. First, we impose a cap on the total number of MPBO trials. Second, we apply an early termination rule: each phase... After a series of consecutive trials showing no improvement, the process stops, and the counter is reset before starting a new phase. Each phase begins with... This test is considered a warm-up and is not included in this count.

[0202] 3.4 Layout Assumptions

[0203] Before delving into the details of our MPBO algorithm, we first introduce the principles and assumptions adopted by our layout generator. Specifically, we first address inter-die signal networks because they have higher requirements for routing resources; simultaneously, we explicitly reserve a minimum amount of routing traces and associated vias for the PDN to ensure that power delivery is not limited by signal routing. We must note that, since our algorithm is designed for early-stage planning, reasonable simplifications have been made to accelerate the iteration process.

[0204] Bumps, TSVs, and TPVs. Bumps in 2.5D / 3D ICs include μbumps, C4 bumps, and solder balls. We assume a one-to-one correspondence between μbumps and chip pins, following common design practices, while C4 bumps and solder balls are arranged in a checkerboard pattern with a specified spacing. TSVs and TPVs are vertically aligned to C4 bumps and solder balls, respectively. A single C4 bump may fan out to one or more TSVs, while a BGA ball is typically connected to a TPV

[21] . Bump spacing, TSV and TPV diameters, and the mapping between TSVs and C4 bumps are design variables for MPBO optimization.

[0205] Signal routing. Signal routing strategies differ across packaging technologies. In 3D packages, signal pins are typically vertically aligned and directly connected via TSVs, while in 2.5D packages, they are interconnected via transmission lines on an interposer. To limit additional insertion loss caused by resistive discontinuities at via-segment connections, we allow segments in the x and y directions within the same RDL

[22] . We employ a G–nS–G (ground–n×signal–ground) scheme

[23] to strike a balance between crosstalk mitigation and limited routing resources. Figure 6 (a) shows an example of a transmission line on a single RDL.

[0206] Intermediate PDN. Following common practice, we route segments in a single direction within each RDL layer to avoid crossings and simplify routing. The intermediate PDN is constructed as follows: on the top RDL, we connect μbumps belonging to the same network, and apply the same strategy to C4 bumps on the bottom RDL. On the inner RDLs, we alternate segment directions in an x–y–x pattern and place vias at each crossing

[24] to form a multi-layered mesh. Figure 6 Figure (b) illustrates a dual-network PDN example on metal layers M1 and M2.

[0207] Substrate PDN. Compared to interposers, substrate PDN offers greater design freedom, where PICs are no longer limited to line segments and can be implemented as arbitrary polygons. To simplify the design while adhering to conventions, we construct the substrate through a skeleton extension process. First, via arrays are placed on RDLs in a checkerboard pattern. Treating C4 bumps, RDL vias, and solder balls as graph nodes, we use the A* algorithm

[25] to generate a skeleton for each network. Then, the skeleton is extended to the plane on all RDLs using the k-nearest neighbor (KNN) algorithm

[26] . Figure 6 (c) shows the first metal layer (M0) of a representative dual-network substrate.

[0208] 3.5 Multiphysics Model

[0209] In this section, we present our SI, PI, and TI models. Chip power can be specified by the user; otherwise, the architecture simulator (ArchSim) performs power analysis and enables electrothermal simulation. For completeness, we also briefly describe ArchSim in Section 4.5.3.

[0210] 3.5.1 SI Model

[0211] We employ a parasitic extraction method based on lookup tables (LUTs) for rapid S-parameter analysis. We pre-compute the mapping from interconnect geometry to its parasitic parameters. The self-capacitance and mutual capacitance, conductance and inductance of the transmission lines are derived from the Partial Component Equivalent Circuit (PEEC) model

[27] . Given the layout, we query the LUT and assemble the equivalent circuit, and then simulate it in SPICE to obtain the S-parameters.

[0212] 4.5.2 PI Model

[0213] We apply the same method as in Section 4.5.1 to extract the resistance of the mid-segment of the interposer RDLs and the vias. For the substrate, we discretize the power plane into a basic cell mesh and calculate the resistance of each cell based on its geometry and material conductivity. The cells are then assembled into an equivalent circuit for SPICE simulation, with voltage regulation modules (VRMs) positioned at the center of the voltage domain.

[0214] 3.5.3 TI Model and ArchSim

[0215] The stackable model proposed in reference

[28] provides an effective and efficient method for TI evaluation. Since the original model was developed for interposers, we extend the same approach to substrates and BGAs. ArchSim is built on top of SYSgen [9] and adds support for 3D integration. ArchSim generates temperature-dependent power analysis, reporting the spatial power distribution over the region. Combined with the TI model, electrothermal simulation is enabled.

[0216] 4. Experiment

[0217] In this section, we evaluate the proposed interconnect planning framework for 2.5D and 3D integration. We first evaluate the convergence and effectiveness of the proposed MPBO relative to the baseline single-stage BO (SPBO). Then, we compare the resulting total interconnect cost with two previous methods in real-world cases. Signal, power, and thermal integrity results are also reported.

[0218] 4.1 Experimental Setup

[0219] We evaluated MIP-SPT on three scaled versions of the MCore-OPU architecture

[29]

[30] . The MCore-OPU consists of a single ASIC chip containing two logic cores and two JESD235B high-bandwidth memory (HBM) stacks, designed to accelerate converter-based workloads. The average power density of the logic cores is approximately 0.2 W / mm², while detailed power trajectories were obtained from our architecture simulator. For the 2.5D package, we used TSMC CoWoS-S

[31] , where the HBM stacks are placed next to the ASIC chip. The layout was generated using Floorplet

[16] . For the 3D package, we used TSMC InFO-PoP

[32] , where the HBM stacks are placed vertically on top of the ASIC chip. The structural parameters for the 2.5D and 3D cases are summarized in Table 1.

[0220] In the physical design of integrated cores, certain parameters are technology-dependent and remain fixed, such as the thickness of the RDL layer. These parameters are treated as user-defined constants during the optimization process. Table 1 summarizes the values ​​of the fixed parameters in three cases, which are derived from previous research papers

[11]

[33]

[34] and industry data.

[0221] Next, we specify the constraints used in the evaluation. For SI, we adopt the insertion loss criterion. dB (i.e.) dB) was used for inter-die transmission lines; under this condition, insertion loss was negligible

[23] . The frequency was set to 5 GHz, taking into account harmonic content. For PI, voltage drop limits varied between circuit regions. For example, logic cores tolerated voltage drops up to 10%, while high-speed I / Os were limited to 5%. Therefore, we evaluated four voltage drop thresholds: 3%, 5%, 8%, and 10%. For TI, the maximum temperatures for the different cases were 343 K and 348 K, respectively.

[0222] Table 1: Fixed structural parameters for 2.5D / 3D cases

[0223]

[0224] The substrate chip in 3D integration has the same parameters as the interposer in 2.5D integration.

[0225] ASIC is 200μm, HBM is 720μm.

[0226] 4.2 BO Convergence and Performance

[0227] In this experiment, we examined the convergence behavior and final performance of MPBO and compared it with the baseline SPBO, where all variables are optimized within one stage. The constraints, candidate selection, and quantification techniques remained the same as for MPBO. For fairness, both methods used the same evaluation budget (i.e., the number of BO trials) on the same cases, although the budgets may differ between cases. For each case, we ran 10 independent replicates and reported the mean and standard deviation. We considered two input cases, each under four different constraint settings (a total of 8 experimental settings).

[0228] Figure 7 The optimal score (solid line) and its variability (shaded band; ± one standard deviation) are plotted as a function of BO iterations. The first line reports Case 1 (2.5D), while the second line reports Case 3 (3D). Constraints are indicated in the subplot headers, while SI constraints are fixed in... dB. In all eight settings, MPBO consistently outperformed the baseline in terms of final convergence and standard deviation. On average, MPBO achieved a 22.4% reduction in manufacturing costs across these cases. Furthermore, the narrower standard deviation band indicates more stable convergence. These results demonstrate the effectiveness and robustness of our proposed MPBO.

[0229] Table 2: Mean and standard deviation of the best scores for MPBO and baseline SPBO in eight experimental settings

[0230]

[0231] Improvement (%) represents the ratio of cost reduction to standard deviation.

[0232] 4.3 Comparison with previous work

[0233] In this section, we compare MIP-SPT with two previous planners [9] and

[15] . Since both works ignore the substrate, for fairness we restrict the optimization to only the interposer and C4 bumps, involving a total of seven decision variables. Furthermore, we disable SI and routing capability constraints, which are not supported by existing work. PI and TI are enforced using the same thresholds across all methods: the voltage drop across the interposer is limited to below 3%, and the maximum temperature is limited to [missing value]. K. All methods were evaluated in the same three cases listed in Table 1.

[0234] Table 3: Comparison of our VIC plan with previous work

[0235] Table 3 reports the manufacturing cost reductions, as well as the RDL via and TSV counts (other VIC counts are omitted for brevity). Compared to the baseline, MIP-SPT consistently reduced both the VIC count and total cost. On average, we reduced manufacturing costs by 23.1% and 18.1%, respectively. The advantages stem from the effective exploration of the design space and careful handling of physical constraints.

[0236] 5. Conclusion

[0237] This invention proposes MIP-SPT, an interconnect planning framework under SI, PI, TI, and routing capability constraints. We propose a hierarchical variable scheduling strategy to decouple interposer and substrate design variables and optimize them at different stages. To improve the convergence and efficiency of MPBO, we employ score-based downsampling and elite sampling. Under the same inter-die S-parameters, voltage drop, and maximum temperature constraints, our MPBO achieves a 22.4% lower manufacturing cost than the baseline SPBO. Compared to previous work, MIP-SPT reduces interconnect costs by 23.1% and 18.1%, respectively.

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Claims

1. A multi-level interconnect planning method for signal-power-thermal integrity in 2.5D-3D integrated chips, characterized in that, The method includes: Step 1: Obtain input data, which includes chip placement information, pin mapping information, package type, and wiring resources; Step 2: Based on the hierarchical variable scheduling strategy, the interconnect design variables are divided into three subsets: the first subset contains interposer design variables, the second subset contains substrate design variables, and the third subset contains bridging variables, wherein the bridging variables are C4 bump-related parameters; Step 3: Optimize sequentially using a three-stage Bayesian optimization algorithm: Phase 1: Optimize the first and third subsets, generate candidate design variables, generate interconnect layout, evaluate multiphysics performance and manufacturing cost, update the surrogate model, and use the optimal solution as the initial value for Phase 2 after convergence. Phase 2: Optimize the second and third subsets, initialize with the optimal solution from Phase 1, perform the same evaluation and update process as in Phase 1, and use the optimal solution as the initial value for Phase 3 after convergence. Phase 3: Jointly optimize the first, second, and third subsets, perform the evaluation and update process, and terminate the optimization after convergence; Step 4: Output the final optimized set of optimal interconnect design variables, which are used to guide the physical implementation of vertical and planar interconnects in 2.5D / 3D integration.

2. The method according to claim 1, characterized in that, Step 1 includes the following steps: Step 1.1: Obtain chip placement information, which includes the physical position, size parameters, and stacking relationship of each chip in the package; Step 1.2: Obtain pin mapping information, which includes the pin coordinates of each chip and a list of networks connecting the pins; Step 1.3: Obtain the packaging type information, which is used to identify the 2.5D packaging or 3D packaging type; Step 1.4: Obtain wiring resource information, which includes the number of interlayer redistribution layers and the interlayer height, the number of interlayer redistribution layers and the interlayer height, and the available wiring area of ​​each layer; Step 1.5: Obtain chip power distribution information, which includes power values ​​for each voltage region or spatial power distribution data generated by the architecture simulator.

3. The method according to claim 1, characterized in that, Step 2 includes the following steps: Step 2.1: Determine the complete set of interconnect design variables The interconnect design variables include the geometric and density parameters of vertical interconnects and the geometric parameters of planar interconnects; wherein, the vertical interconnects include microbumps, C4 bumps, solder balls, through-silicon vias, package vias, and redistribution layer vias; the planar interconnects include the interposer conductor segment parameters and the substrate power plane parameters; Step 2.2: Based on physical hierarchy, the interconnection design variables are divided into three categories: Intermediate layer dominant variables: Design variables that have a major impact on signal integrity, power integrity, and thermal integrity in the intermediate layer domain; Substrate-dominant variables: Design variables that have a major impact on the power integrity and thermal integrity of the substrate domain; Bridging variables: C4 bump related parameters, whose physical function is to bridge the power transmission path and heat conduction path between the interposer domain and the substrate domain; Step 2.3: Assign the dominant variables of the intermediary layer to the first subset. The dominant variables of the substrate are assigned to the second subset. The bridging variables are then assigned to the third subset; Step 2.4: Set the scheduling strategy for the optimization phase: First phase optimization At that time, The variables in the second stage are fixed at preset initial values; At that time, The variables in the third stage are fixed as the optimal solution obtained in the first stage; joint optimization is performed in the third stage. ; Where "⧵" is the standard symbol for set difference. This indicates that in the complete set of interconnect design variables X, the first child variable is removed. The set consisting of all variables remaining after the set; This indicates that in the complete set of interconnect design variables X, the second child is removed. The set consisting of all the variables remaining after the set.

4. The method according to claim 1, characterized in that, In step 3, each optimization stage performs the following steps: Step 3.1: Generate a set of candidate design variables corresponding to the current subset to be optimized; Step 3.2: Input the candidate design variables into the layout generator to generate an initial interconnect layout that satisfies the routing capability constraints. The layout generator prioritizes inter-die signal network routing and reserves minimum routing resources for the power transmission network. Step 3.3: Perform multiphysics evaluation on the initial interconnect layout: use the signal integrity model to extract the S-parameters of the transmission lines between the chips, use the power integrity model to calculate the voltage drop of each voltage domain pin, use the electrothermal coupling model to calculate the maximum temperature of each chip, and verify whether the routing resources meet the routing requirements of all networks; at the same time, calculate the manufacturing cost of the current layout based on the interconnect cost model. Step 3.4: Feed the evaluation results back to the Bayesian optimization model: (a) Update the Gaussian process surrogate model with respect to the objective function and all constraints; (b) Cumulative number of feasible solutions If the current evaluation point simultaneously meets all constraints related to signal integrity, power integrity, thermal integrity, and cabling capability, then... Increase by 1; (c) Determine whether the current stage has converged according to the preset convergence condition; if it has converged, use the optimal solution of the current stage as the initial value of the next stage and enter the next stage; if all stages have converged, terminate the optimization and output the global optimal solution. Among them, the This is a cumulative value that is dynamically maintained during the optimization process. The initial value is the number of feasible solutions generated by the Sobol sequence during the initial trial phase.

5. The method according to claim 4, characterized in that, In step 3.1, generating a set of candidate design variables includes: scoring and filtering candidate points in the search space, wherein the scoring includes development score, exploration score and boundary learning score; The development score Calculated using the following formula: in, Let be the posterior mean of the objective function. For feasibility probability, Candidate design variables; The probability of feasibility Calculated using the following formula: in, and The first The posterior mean and standard deviation of each constraint. The cumulative distribution function of the standard normal distribution. These are the indices corresponding to signal integrity constraints, power integrity constraints, and thermal integrity constraints, respectively. The exploration score Calculated using the following formula: in, Let be the posterior standard deviation of the objective function. Preset exploration weight coefficients; The boundary learning score Calculated using the following formula: in, These are constraint indices, corresponding to signal integrity, power integrity, and thermal integrity constraints, respectively. and The first Posterior mean and standard deviation of a constrained Gaussian process.

6. The method according to claim 5, characterized in that, In the third optimization stage, step 3.1 also includes an elite sampling step: Building an elite group The elite group Contains the most A historically feasible point, The first, representing the concentration of elites One elite point; For any candidate point in the search space Calculate its value to the elite set minimum normalized distance : in, This represents the current candidate design variable vector. The first, representing the concentration of elites One elite point, Represents Euclidean distance. and Each dimension component is normalized to the [1,0] interval according to the corresponding variable range; Based on the minimum normalized distance Calculate sampling probability The sampling probability Calculated using the following formula: in, To uniformly explore the weighting coefficients and , For temperature parameters and , For the current search space The total number of candidate points; Based on the sampling probability Probabilistic sampling is performed on candidate points to generate a downsampled candidate set for subsequent Bayesian optimization iterations, in order to achieve a balance between the neighborhood of historical good solutions and the global search space.

7. The method according to claim 5, characterized in that, In step 3.1, after generating the downsampling candidate set, a learned function is used to select the design variable to be evaluated from the candidate set; when When this is the case, the logarithmic feasibility probability is used as the learning function: This represents the probability of feasibility. and The first Posterior mean and standard deviation of a constrained Gaussian process; The cumulative distribution function of the standard normal distribution; These correspond to signal integrity, power integrity, and thermal integrity constraints, respectively. when At that time, the logarithmic expectation is used to improve LogEI as the learned function: in: and This represents the posterior mean and standard deviation of a Gaussian process. The cumulative distribution function of the standard normal distribution. It is a minimum value, taking the value 1e-12.

8. The method according to claim 4, characterized in that, In step 3.2, generating the interconnect layout includes: Vertical interconnect layout: Microbumps and chip leads are arranged one-to-one; C4 bumps and solder balls are arranged in a checkerboard array; Through-Silicon Vias are vertically aligned with C4 bumps, and a single C4 bump fans out to one or more through-silicon vias; Package vias are vertically aligned with solder balls. Planar interconnect layout: The interposer signal routing adopts the G–nS–G scheme, and the power supply network is alternately routed in the x–y–x direction between redistribution layers with vias at the intersections; the substrate power supply network is connected via A. * The algorithm generates a connection skeleton and expands it into a power plane using the k-nearest neighbor algorithm.

9. The method according to claim 4, characterized in that, The multiphysics evaluation in step 3.3 includes: Signal integrity assessment: A parasitic parameter extraction method based on lookup tables is adopted. The pre-constructed parasitic parameter mapping table is queried according to the interconnect geometry, the equivalent circuit is assembled, and the S-parameters are obtained through SPICE simulation. Power integrity assessment: The parasitic extraction method used in the interposer redistribution layer is used to obtain the resistance of segments and vias in the interposer redistribution layer. The power plane of the substrate is discretized into a grid and the unit resistance is calculated. After assembling the equivalent circuit, the voltage drop is calculated by SPICE simulation. Thermal integrity assessment: Using a stackable thermal model and combining the regional power distribution output by the architecture simulator, the maximum temperature of each core particle is calculated; Cabling capacity verification: Based on the available cabling area, wire width, wire spacing and shielding group size, directly calculate the minimum cabling resources required for each network; The signal integrity constraints require inter-grain network insertion loss satisfy: ,in The target threshold is defined as the power integrity constraint requirement for the voltage region. Pin voltage The thermal integrity constraints require core particles highest temperature The cabling capability constraints require the network to... Available cabling resources Each constraint threshold is preset based on the packaging process and circuit requirements.

10. The method according to claim 4, characterized in that, The manufacturing cost calculation uses the following model: Cost of through-hole vertical interconnects: Cost of convex vertical interconnects: Cost of planar interconnection on substrate: Cost of planar interconnection on substrate: The total manufacturing cost of interconnecting all components is: in For photolithography costs, This is the process coefficient. For height, For diameter, For density proxy parameters, , For quantity, For width, For length, For copper thickness, For copper area; In step 3.4, adjusting the hardness or softness of the constraints in the Bayesian optimization model as follows helps to accelerate model convergence: In this Bayesian optimization model, the learned function considers the influence of constraint hardness and softness in the following product manner: in These are the LogPoF and LogEI functions mentioned earlier; Constraint strictness parameter The stiffness of the constraint can be adjusted: The larger the value, the softer the constraint, the more it encourages exploration and helps to escape local optima, but the lower the feasibility of the solution. The smaller the value, the stricter the constraint, and the more it encourages development, meaning that the more feasible the solution is, the better it is to explore within known favorable areas. This Bayesian optimization model is based on the constraint of the median posterior standard deviation. And recently Feasibility rate of this experiment Dynamically adjust constraint strictness parameters : in, , , For the most recent The proportion of feasible results in this experiment; The convergence condition is: continuity If the optimization objective does not improve within the next iteration, the current stage is considered converged, and the previous stages are considered converged. The next iteration is a warm-up period and is not included in the convergence count.

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