Silicon-based hybrid integrated laser and chip
By incorporating a heat dissipation structure into a silicon-based hybrid integrated laser, the problem of rapid heat dissipation in silicon photonic chips is solved, thereby improving the chip's heat dissipation and communication performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUAWEI TECH CO LTD
- Filing Date
- 2024-12-06
- Publication Date
- 2026-06-09
AI Technical Summary
The buried oxide layer in silicon photonics chips prevents the heat generated by the laser from being dissipated quickly, which may cause the chip to burn out and affect communication performance.
A silicon-based hybrid integrated laser is designed to achieve rapid heat dissipation by setting a heat dissipation structure between the silicon substrate and the metal electrode. The heat dissipation structure includes a heat dissipation structure that is thermally connected along a first direction and is housed within an oxide buried layer and a dielectric layer. Multiple heat dissipation structures are arranged around or around a III-V semiconductor waveguide to improve heat dissipation.
It effectively improves the heat dissipation and communication performance of silicon-based hybrid integrated lasers, avoiding chip burnout problems caused by poor thermal conductivity.
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Figure CN122178183A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of laser technology, and more particularly to a silicon-based hybrid integrated laser and chip. Background Technology
[0002] In silicon photonics (SiP) technology, silicon waveguides (SiWG / Si) are an excellent light transmission medium due to their low insertion loss. However, silicon itself cannot emit light, making the light source a primary problem that needs to be solved in silicon photonics technology.
[0003] Lasers fabricated by molecularly bonding III-V compound semiconductor materials to SOI wafers offer higher alignment accuracy and lower coupling insertion loss compared to off-chip light sources. However, the presence of the buried oxide layer in the silicon photonics chip prevents the rapid dissipation of heat generated by the laser, potentially leading to chip burnout and impacting its communication performance. Summary of the Invention
[0004] This application provides a silicon-based hybrid integrated laser and chip that can improve the chip's communication performance.
[0005] In a first aspect, a silicon-based hybrid integrated laser is provided, comprising: a silicon substrate, a buried oxide layer, a silicon optical waveguide, a dielectric layer, a III-V semiconductor waveguide, a plurality of metal electrodes, and one or more heat dissipation structures; the silicon substrate, the buried oxide layer, the silicon optical waveguide, the dielectric layer, and the III-V semiconductor waveguide are stacked along a first direction; the III-V semiconductor waveguide includes an N-type semiconductor, a multi-quantum-well active layer, and a P-type semiconductor stacked along the first direction, wherein the N-type semiconductor is electrically connected to the metal electrodes; the heat dissipation structure is housed within the buried oxide layer and the dielectric layer, one end of the heat dissipation structure along the first direction is thermally connected to the metal electrodes, and the other end of the heat dissipation structure along the first direction is thermally connected to the silicon substrate.
[0006] For example, a multi-quantum-well active layer is used to generate a pump source. The pump source is used to excite a III-V semiconductor waveguide to generate laser light.
[0007] Based on the solution provided in the embodiments of this application, by setting a heat dissipation structure that thermally connects the silicon substrate and the metal electrode along the first direction, the heat generated by the laser can be directly and quickly heat-sinked through the silicon substrate, avoiding poor heat dissipation of the chip due to the poor thermal conductivity of the buried oxide layer, thereby improving the heat dissipation and communication performance of the chip where the silicon-based hybrid integrated laser is located.
[0008] In some possible implementations, multiple heat dissipation structures are arranged around the III-V semiconductor waveguide.
[0009] For example, multiple heat dissipation structures are arranged around a III-V semiconductor waveguide.
[0010] In some possible implementations, multiple heat dissipation structures are arranged on both sides of the III-V semiconductor waveguide.
[0011] For example, multiple heat dissipation structures are two heat dissipation structures, which are disposed on both sides of the III-V semiconductor waveguide.
[0012] In some possible implementations, along the second direction, at least two of the multiple heat dissipation structures are at different distances from the N-type semiconductor at one end, and this end is thermally connected to a metal electrode, with the second direction perpendicular to the first direction; or, along the second direction, at least two of the multiple heat dissipation structures are at different distances from the N-type semiconductor at one end, and this end is thermally connected to a silicon substrate, with the second direction perpendicular to the first direction.
[0013] In some possible implementations, along the second direction, one end of a plurality of heat dissipation structures is at the same distance from the N-type semiconductor, and this end is thermally connected to a metal electrode, with the second direction perpendicular to the first direction; or, along the second direction, one end of a plurality of heat dissipation structures is at the same distance from the N-type semiconductor, and this end is thermally connected to a silicon substrate, with the second direction perpendicular to the first direction.
[0014] For example, along the second direction, the distances between the two heat dissipation structures and the N-type semiconductor can be the same or different.
[0015] For example, along the second direction, the two heat dissipation structures are at the same distance from the N-type semiconductor, and the two heat dissipation structures are symmetrically arranged on both sides of the III-V semiconductor waveguide.
[0016] Along the second direction, if multiple or two heat dissipation structures are at the same distance from the N-type semiconductor, the silicon-based hybrid integrated laser has high symmetry, which facilitates the fabrication of silicon-based hybrid integrated lasers.
[0017] In some possible implementations, the heat dissipation structure satisfies axisymmetry, and the axis of symmetry of the heat dissipation structure is parallel to the first direction.
[0018] For example, when a heat dissipation structure is formed by etching and deposition, the etched space can be axisymmetric. Therefore, the heat dissipation structure obtained by depositing metal can also be axisymmetric.
[0019] In this embodiment, the axial symmetry of the heat dissipation structure can also be understood as the portion of the heat dissipation structure that does not extend beyond the bottom surface of the N-type semiconductor along the first direction satisfying axial symmetry. The portion of the heat dissipation structure that extends beyond the bottom surface of the N-type semiconductor along the first direction can be designed according to the shape of the metal electrode that is thermally connected to it. No limitation is imposed in this regard.
[0020] Based on the solution provided in the embodiments of this application, by setting a heat dissipation structure that satisfies axisymmetry, it is convenient for industrial production.
[0021] In some possible implementations, the projection of the P-type semiconductor onto the upper surface of the multi-quantum-well active layer is located inside the projection of the multi-quantum-well active layer onto the upper surface of the multi-quantum-well active layer.
[0022] For example, the projection of the P-type semiconductor onto the upper surface of the multi-quantum-well active layer is covered by the projection of the multi-quantum-well active layer onto the upper surface of the multi-quantum-well active layer.
[0023] For example, along the second direction and the opposite direction of the second direction, the upper surface of the multi-quantum-well active layer covers the lower surface of the P-type semiconductor, and the multi-quantum-well active layer extends to both sides and beyond the P-type semiconductor.
[0024] The lower surface can be understood as a surface that is perpendicular to and away from the first direction, and the upper surface can be understood as a surface that is perpendicular to and close to the first direction.
[0025] Based on the solution provided in the embodiments of this application, the pumping efficiency of the multi-quantum-well active layer can be improved by designing a multi-quantum-well active layer and a P-type semiconductor.
[0026] In some possible implementations, the projection of the silicon optical waveguide onto the silicon substrate is formed as a first stripe; the projection of the III-V semiconductor waveguide onto the silicon substrate is formed as a second stripe.
[0027] In some possible implementations, the end of the first strip covers the end of the second strip; or, the end of the second strip covers the end of the first strip.
[0028] For example, the width of the end of the first strip along the second direction is greater than or equal to the width of the end of the second strip along the second direction.
[0029] In some possible implementations, the cross-section of the P-type semiconductor is tapered along the first direction.
[0030] In some possible implementations, the cross-section of the P-type semiconductor is rectangular along the first direction.
[0031] In some possible implementations, the bottom surface of the cone is electrically connected to the upper surface of the multi-quantum-well active layer; or, the top surface of the cone is electrically connected to the upper surface of the multi-quantum-well active layer.
[0032] For example, a P-type semiconductor is a tapered structure that gradually narrows along a first direction or the opposite direction. Alternatively, a tapered structure that gradually narrows along the first direction can be called a tapered structure; a tapered structure that gradually narrows along the opposite direction can be called an inverse tapered structure. The surface area of the top surface of the tapered structure is smaller than the surface area of the bottom surface of the tapered structure.
[0033] In some possible implementations, the first stripe covers the second stripe.
[0034] For example, the width of the first strip along the second direction is greater than or equal to the width of the second strip along the second direction.
[0035] In some possible implementations, the projection of the silicon optical waveguide onto the silicon substrate is formed as a first strip; the projection of the III-V semiconductor waveguide onto the silicon substrate is formed as a second strip; and the end of the second strip covers the end of the first strip.
[0036] For example, the width of the end of the first strip along the second direction is smaller than the width of the end of the second strip along the second direction.
[0037] In some possible implementations, the second stripe covers the first stripe.
[0038] For example, the width of the first strip along the second direction is smaller than the width of the second strip along the second direction.
[0039] In some possible implementations, the silicon optical waveguide is a silicon waveguide, a silicon nitride waveguide, or a lithium niobate waveguide.
[0040] For example, when the silicon waveguide is a silicon waveguide, the buried oxide layer and the dielectric layer can be fabricated using silicon-on-insulator (SOI) technology, that is, by depositing an insulating layer on a silicon substrate. This allows for one-step patterning, saving process steps and processing costs.
[0041] In a second aspect, a III-V semiconductor waveguide is provided, the III-V semiconductor waveguide comprising an N-type semiconductor, a multi-quantum-well active layer and a P-type semiconductor stacked along a first direction; the projection of the P-type semiconductor onto the upper surface of the multi-quantum-well active layer is located inside the projection of the multi-quantum-well active layer onto the upper surface of the multi-quantum-well active layer.
[0042] The specific implementation of the second aspect of the solution can be found in the detailed description of the first aspect, and will not be repeated here for the sake of brevity.
[0043] The beneficial effects of the second aspect of the solution can be found in the detailed description of the first aspect, and will not be repeated here for the sake of brevity.
[0044] Thirdly, a chip is provided, the chip including a laser, the laser being a silicon-based hybrid integrated laser as described in the first aspect or any possible implementation of the first aspect.
[0045] The beneficial effects of the third aspect of the solution can be found in the detailed description of the first aspect, and will not be repeated here for the sake of brevity.
[0046] Fourthly, an optical communication device is provided, the optical communication device including the chip described in the third aspect above.
[0047] In conjunction with the fourth aspect, in some implementations of the fourth aspect, the optical communication device includes any one of an optical module, an optical switch, and an optical modem.
[0048] Fifthly, an optical module is provided, the optical module including the chip described in the third aspect above.
[0049] A sixth aspect provides a communication device, comprising: a receiver including the chip in the third aspect; and / or a transmitter including the chip in the third aspect.
[0050] In a seventh aspect, a communication device is provided, comprising: a transceiver for receiving or transmitting signals, the transceiver including the chip in the third aspect, the chip being used to modulate or demodulate the signals; and a processor for processing the signals. Attached Figure Description
[0051] Figure 1 This is a schematic diagram of an exemplary SOI wafer applicable to embodiments of this application.
[0052] Figure 2 This is a schematic diagram of an exemplary SOI waveguide applicable to embodiments of this application.
[0053] Figure 3 This is a schematic diagram of the structure of a laser applicable to an embodiment of this application.
[0054] Figure 4 This is a schematic diagram of a waveguide structure applicable to an embodiment of this application.
[0055] Figure 5 This is a cross-sectional schematic diagram of various waveguides applicable to embodiments of this application.
[0056] Figure 6 This is a cross-sectional schematic diagram of various lasers applicable to embodiments of this application.
[0057] Figure 7These are top and cross-sectional schematic diagrams of various III-V compound semiconductor lasers applicable to embodiments of this application.
[0058] Figure 8 This is a cross-sectional schematic diagram of a chip applicable to an embodiment of this application.
[0059] Figure 9 This is a schematic diagram of the layout of various lasers applicable to embodiments of this application.
[0060] Figure 10 This is a schematic diagram of a hybrid bonding process applicable to embodiments of this application.
[0061] Figure 11 This is an exemplary schematic diagram of an optical communication device provided in an embodiment of this application.
[0062] Figure 12 This is an exemplary schematic diagram of another optical communication device provided in the embodiments of this application.
[0063] Figure 13 This is an exemplary schematic diagram of another optical communication device provided in the embodiments of this application. Detailed Implementation
[0064] The technical solutions of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.
[0065] Before introducing the embodiments of this application, the following points should be made first.
[0066] In this application, the terms "exemplary," "for example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.
[0067] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0068] References such as "in some possible implementations" as used in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in some possible implementations" appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless otherwise specifically emphasized.
[0069] In this application, "at least one" or "at least one item" refers to one or more items, and "more than one" refers to two or more items. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.
[0070] In this application, "#1", "#2", etc., are used merely for descriptive convenience to distinguish objects and are not intended to limit the scope of the embodiments of this application. They are not used to describe the order or sequence of features. It should be understood that such described objects can be interchanged where appropriate to describe solutions other than those in the embodiments of this application.
[0071] In 1969, Miller SE of Bell Labs first proposed the concept of "integrated optics," heralding the arrival of the integrated device era for the fiber optic communication industry. Optical paths using integrated circuit technology to manufacture waveguide chips integrate the various functions of conventional discrete optical components onto the same optical substrate surface. This enables the optical information processing capabilities of a large optical system composed of multiple discrete optical components, realizing functions such as optical signal generation and detection, optical power distribution, optical switching, and optical filtering. With the rapid development of fiber optic communication technology, this technology has also developed rapidly, gradually forming its own unique characteristics. Since most functional structures are on the same optical substrate, and the main structure is the optical waveguide channel, this technology is called planar lightwave circuit (PLC).
[0072] Planar waveguide technology, developed based on integrated circuit technology, has its unique features. The basic components of integrated circuits are resistors, capacitors, inductors, and transistors (diodes, triodes). Integrated circuit technology fabricates these basic components on silicon substrates through processes such as thin-film deposition, diffusion, epitaxy, photolithography, etching, and annealing, and interconnects them with wires. The basic components of planar waveguides are lasers, waveguides, and detectors. The substrate materials used vary, including III-V compound semiconductors (InP and GaAs), silicon dioxide (SiO2), lithium niobate (LiNbO3), silicon-on-insulator (SOI), silicon nitride (SiN), polymers, and glass. This variety of materials leads to a variety of fabrication processes.
[0073] Planar optical waveguide devices are manufactured using planar optical waveguide technology and are categorized into passive devices, active devices, and hybrid active / passive devices. Passive devices can be understood as devices that do not require a power source and can be used to achieve functions such as optical signal transmission, demultiplexing, multiplexing, and filtering. Passive devices mainly include planar optical waveguide splitters, arrayed waveguide gratings (AWGs), and optical filters.
[0074] In silicon photonics (SiP) technology applications, silicon waveguides (SiWG / Si) are an excellent light transmission medium due to their low insertion loss. However, silicon itself cannot emit light, making the light source a primary problem that needs to be solved in silicon photonics technology. Traditional methods include using an off-chip laser source via spatial optics and coupling it to a grating coupler through a prism; or using flip-chip (FC) technology, where a pre-fabricated laser chip is flipped onto the surface of a silicon photonic chip, and the optical signal is coupled into the silicon photonic chip via end-face or evanescent wave coupling to provide a light source. Compared with traditional off-chip light sources, this method has lower coupling insertion loss and smaller package size, but the alignment between the laser and the silicon photonic chip is difficult, resulting in poor alignment accuracy and hindering mass production. Alternatively, III-V compound semiconductor materials can be bonded to SOI wafers via die-to-wafer hybrid bonding, and then the laser can be formed by etching the III-V compound semiconductor material.
[0075] Planar optical waveguide devices fabricated based on SOI wafers can be called SOI waveguides (WG) or silicon waveguides. A cross-sectional view of an SOI wafer is shown below. Figure 1 As shown, Figure 1 A schematic diagram of an exemplary SOI wafer is shown. Figure 1 As shown, the SOI wafer includes a substrate layer 101a, a buried oxide layer 102a, and a single-crystal silicon layer 103a, which are respectively a silicon (Si) substrate layer, a silicon dioxide (SiO2) layer, and a Si layer. Generally, the thickness of the Si substrate layer is 500μm to 725μm, the thickness of the SiO2 layer is 2μm or 3μm, and the thickness of the Si layer is 200nm to 300nm. The buried oxide layer can also be called a buried oxide (BOX) layer.
[0076] SOI waveguides are fabricated on SOI substrates. A 3D diagram of an SOI waveguide is shown below. Figure 2 As shown. Figure 2 A schematic diagram of an exemplary SOI waveguide structure is shown. (As shown...) Figure 2 As shown, the SOI waveguide includes a bottom layer 101b, a lower cladding layer 102b, a core layer 103b, and an upper cladding layer 104b, which are respectively a Si substrate layer, a SiO2 layer, a Si layer, and air. It should be understood that SOI waveguides can have various structures, such as slab waveguide structures or... Figure 2 The ridge waveguide structure shown.
[0077] Figure 2The dimensions of the SOI waveguide shown are only one possible example, and the dimensions of the SOI waveguide are not limited to this. For example, in an SOI waveguide, the thickness of the Si epitaxial layer of the core 103b is not limited to 70 nm.
[0078] Lasers fabricated by molecularly bonding III-V compound semiconductor materials to SOI wafers offer higher alignment accuracy and lower coupling insertion loss compared to off-chip light sources. However, the presence of the buried oxide layer in the silicon photonics chip prevents the heat generated by the laser from being dissipated quickly, potentially causing the silicon photonics chip to burn out.
[0079] This application provides a silicon-based hybrid integrated laser, optical waveguide, and chip that can improve the communication performance of the chip.
[0080] Figure 3 A schematic diagram of the structure of a laser 300 applicable to an embodiment of this application is shown.
[0081] Laser 300 is a silicon-based hybrid integrated laser. Laser 300 includes: a substrate, a buried oxide layer, a silicon optical waveguide, a dielectric layer, a III-V semiconductor waveguide, multiple metal electrodes, and one or more heat dissipation structures. Along a first direction, the substrate, buried oxide layer, silicon optical waveguide, dielectric layer, and III-V semiconductor waveguide are stacked. The III-V semiconductor waveguide includes an N-type semiconductor, a multiple quantum well (MQW) active layer, and a P-type semiconductor stacked along the first direction. The N-type semiconductor is electrically connected to the metal electrodes. The heat dissipation structure is housed within the buried oxide layer and the dielectric layer. One end of the heat dissipation structure along the first direction is thermally connected to the metal electrodes, and the other end of the heat dissipation structure along the first direction is thermally connected to the silicon substrate.
[0082] Figure 3 In the diagram, polygons filled with small black dots represent P-type semiconductors, rectangles filled with intersecting horizontal and vertical lines represent MQW active layers, rectangles filled with diagonal lines represent N-type semiconductors, rectangles filled with thick horizontal lines represent metal electrodes, rectangles filled with thin horizontal lines represent substrates, polygons filled with large black dots represent heat dissipation structures, black-filled areas represent silicon optical waveguides, and gray-filled areas represent buried oxide layers or dielectric layers. III-V semiconductor waveguides include N-type semiconductors, MQW active layers, and P-type semiconductors.
[0083] In some possible implementations, multiple heat dissipation structures are arranged around the III-V semiconductor waveguide.
[0084] For example, multiple heat dissipation structures are arranged around a III-V semiconductor waveguide.
[0085] In some possible implementations, multiple heat dissipation structures are arranged on both sides of the III-V semiconductor waveguide.
[0086] For example, multiple heat dissipation structures are two heat dissipation structures, which are disposed on both sides of the III-V semiconductor waveguide.
[0087] In some possible implementations, along the second direction, at least two of the multiple heat dissipation structures are at different distances from the N-type semiconductor at one end, and this end is thermally connected to a metal electrode, with the second direction perpendicular to the first direction; or, along the second direction, at least two of the multiple heat dissipation structures are at different distances from the N-type semiconductor at one end, and this end is thermally connected to a silicon substrate, with the second direction perpendicular to the first direction.
[0088] In some possible implementations, along the second direction, one end of a plurality of heat dissipation structures is at the same distance from the N-type semiconductor, and this end is thermally connected to a metal electrode, with the second direction perpendicular to the first direction; or, along the second direction, one end of a plurality of heat dissipation structures is at the same distance from the N-type semiconductor, and this end is thermally connected to a silicon substrate, with the second direction perpendicular to the first direction.
[0089] For example, along the second direction, the distances between the two heat dissipation structures and the N-type semiconductor can be the same or different.
[0090] For example, the substrate of laser 300 may be a silicon substrate.
[0091] For example, a multi-quantum-well active layer is used to generate a pump source. The pump source is used to excite a III-V semiconductor waveguide to generate laser light.
[0092] Figure 4 A schematic diagram of a waveguide 400 applicable to an embodiment of this application is shown. Waveguide 400 is a possible implementation of a III-V semiconductor waveguide in laser 300.
[0093] Figure 4 In the diagram, polygons filled with small black dots represent P-type semiconductors, rectangles filled with intersecting horizontal and vertical lines represent the MQW active layer, and rectangles filled with diagonal lines represent N-type semiconductors. Waveguide 400 includes N-type semiconductors, the MQW active layer, and P-type semiconductors.
[0094] Waveguide 400 includes an N-type semiconductor, a multi-quantum-well active layer, and a P-type semiconductor stacked along a first direction; the P-type semiconductor is tapered along the first direction.
[0095] In some possible implementations, the bottom surface of the cone is electrically connected to the upper surface of the multi-quantum-well active layer; or, the top surface of the cone is electrically connected to the upper surface of the multi-quantum-well active layer.
[0096] For example, a P-type semiconductor is a tapered structure that gradually narrows along a first direction or the opposite direction. Alternatively, a tapered structure that gradually narrows along the first direction can be called a tapered structure; a tapered structure that gradually narrows along the opposite direction can be called an inverse tapered structure. The surface area of the top surface of the tapered structure is smaller than the surface area of the bottom surface of the tapered structure.
[0097] Alternatively, waveguide 400 includes an N-type semiconductor, a multi-quantum-well active layer, and a P-type semiconductor stacked along a first direction; the projection of the P-type semiconductor onto the upper surface of the multi-quantum-well active layer is located inside the projection of the multi-quantum-well active layer onto the upper surface of the multi-quantum-well active layer.
[0098] For example, the projection of the P-type semiconductor onto the upper surface of the multi-quantum-well active layer is covered by the projection of the multi-quantum-well active layer onto the upper surface of the multi-quantum-well active layer.
[0099] For example, along the second direction and the opposite direction of the second direction, the upper surface of the multi-quantum-well active layer covers the lower surface of the P-type semiconductor, and the multi-quantum-well active layer extends to both sides and beyond the P-type semiconductor.
[0100] In the embodiments of this application, the lower surface can be understood as a surface that is perpendicular to the first direction and away from the first direction, and the upper surface can be understood as a surface that is perpendicular to the first direction and close to the first direction.
[0101] In the embodiments of this application, the first direction and the second direction are perpendicular, the first direction is perpendicular to the third direction, and the second direction is perpendicular to the third direction.
[0102] Combined with the following text Figures 5 to 8 Describe in detail several possible implementations of the laser 300 or waveguide 400.
[0103] like Figure 5 As shown, Figure 5 Cross-sectional schematic diagrams of various waveguides applicable to embodiments of this application are shown. Figure 5 Any of the 12 waveguides shown is a possible implementation of the III-V semiconductor waveguide or waveguide 400 in laser 300.
[0104] Figure 5Any of the waveguides shown can be a laser waveguide formed by bonding a III-V compound semiconductor material to a silicon photonic wafer and then etching it. Along the first direction, an N-type semiconductor, a multi-quantum-well active layer, and a P-type semiconductor are sequentially stacked to form the waveguide. Along the first direction, a buffer layer and / or a contact layer can also be disposed on the P-type semiconductor. The contact layer can be made of metals such as aluminum, copper, titanium, platinum, and gold, or other materials; the buffer layer can be made of InP, GaAs, or other III-V compound semiconductor materials. The P-type or N-type semiconductor can be a III-V compound semiconductor material; for example, the P-type semiconductor can be a P-InP waveguide made of P-type III-V compound semiconductor material, and the N-type semiconductor can be an N-InP waveguide made of N-type III-V compound semiconductor material. Figure 5 Any one of the waveguides shown can also be called a III-V compound semiconductor waveguide.
[0105] Figure 5 In the diagram, polygons filled with small black dots represent P-type semiconductors, rectangles filled with intersecting horizontal and vertical lines represent MQW active layers, rectangles filled with right diagonal lines represent N-type semiconductors, portions filled with left diagonal lines represent passivation layers, rectangles filled with thick horizontal lines represent metal electrodes, rectangles filled with vertical lines represent buffer layers, and rectangles filled with intersecting diagonal lines represent contact layers.
[0106] For example, the cross-section of a P-InP waveguide can be as follows: Figure 5 This is one of several conical shapes shown. The cross-section of the P-InP waveguide can also be a rectangle with its sides perpendicular to the MQW active layer.
[0107] For example, along the second direction, the lower surface of the P-InP waveguide can be completely covered by the upper surface of the MQW active layer.
[0108] For example, the area of the lower surface of the P-InP waveguide is smaller than the area of the upper surface of the MQW active layer (which can also be understood as the MQW active layer extending beyond the P-InP waveguide along the second direction and in the opposite direction to the second direction in a plane perpendicular to the first direction). Compared to the lower surface of the P-InP waveguide having an area equal to the upper surface of the MQW active layer, the MQW active layer extending beyond the P-InP waveguide along the second direction and in the opposite direction to the second direction can improve pumping efficiency.
[0109] For example, in a plane perpendicular to the first direction, the N-InP waveguide can extend in the second direction and in the opposite direction to the second direction and be electrically connected to a metal electrode.
[0110] For example, the materials of N-type semiconductors, MQW active layers, or P-type semiconductors can be III-V compound semiconductor materials with different types and / or contents of doped elements.
[0111] For example, the outer surface of the structure consisting of the MQW active layer, P-type semiconductor, buffer layer and contact layer can be provided with a SiN layer or SiO2 layer as a passivation layer.
[0112] like Figure 6 As shown, Figure 6 A cross-sectional schematic diagram of various lasers applicable to embodiments of this application is shown.
[0113] Figure 6 Any one of the four lasers shown is one possible implementation of laser 300. Figure 6 The III-V compound semiconductor waveguide in any of the lasers shown is a waveguide 400 or... Figure 5 This illustrates one possible implementation of any one of the various waveguides shown.
[0114] Figure 6 In the diagram, polygons filled with dense small black dots represent P-type semiconductors; rectangles filled with intersecting horizontal and vertical lines represent MQW active layers; rectangles filled with right-hand diagonal lines represent N-type semiconductors; portions filled with left-hand diagonal lines represent passivation layers; rectangles filled with vertical lines represent buffer layers; rectangles filled with intersecting diagonal lines represent contact layers; rectangles filled with thick horizontal lines represent metal electrodes; rectangles filled with thin horizontal lines represent substrates; polygons filled with large black dots represent heat dissipation structures; black-filled portions represent silicon optical waveguides; sparsely filled rectangles with small black dots represent silicon nitride waveguides; and gray-filled portions represent buried oxide layers or dielectric layers. III-V semiconductor waveguides include N-type semiconductors, MQW active layers, and P-type semiconductors.
[0115] In some possible implementations, the silicon optical waveguide is a silicon waveguide, a silicon nitride waveguide, or a lithium niobate waveguide.
[0116] For example, a waveguide made of silicon material can be called a silicon waveguide; a waveguide made of silicon nitride material can be called a silicon nitride waveguide; and a waveguide made of lithium niobate material can be called a lithium niobate waveguide.
[0117] Figure 6 For a specific implementation of the III-V compound semiconductor waveguide in any of the various lasers shown, please refer to [reference needed]. Figure 5 The relevant parts will not be elaborated upon here.
[0118] For example, along the first direction, a silicon substrate, a BOX, an SOI waveguide layer, and a dielectric layer or a III-V compound semiconductor waveguide are sequentially stacked; or, along the first direction, a silicon substrate, a BOX, a silicon nitride waveguide (SiN WG / SiN) layer, and a dielectric layer or a III-V compound semiconductor waveguide are sequentially stacked. The BOX has low thermal conductivity and poor heat dissipation performance.
[0119] Figure 6 Each of the various lasers shown includes one or more heat dissipation structures (also referred to as T-VIA layers). Along a first direction, both ends of the heat dissipation structure are connected to a metal electrode or a silicon substrate, respectively. The heat dissipation structure rapidly conducts heat generated by the laser to the silicon substrate via the metal electrode, forming a heat sink on the silicon substrate and preventing heat conduction through the BOX to the silicon substrate. This heat dissipation structure effectively prevents burnout or failure of the laser due to overheating.
[0120] Multiple heat dissipation structures can be arranged around the III-V compound semiconductor waveguide. For example, two heat dissipation structures can be arranged on both sides of the III-V compound semiconductor waveguide; multiple heat dissipation structures can be arranged around the III-V compound semiconductor waveguide.
[0121] The distance between different heat dissipation structures and the N-type semiconductor of the III-V compound semiconductor waveguide along the second direction can be the same or different. This application does not impose such limitations on the embodiments.
[0122] Different heat dissipation structures are equidistant from the III-V compound semiconductor waveguide along the second direction (which can also be understood as different heat dissipation structures being symmetrically arranged with the III-V compound semiconductor waveguide as the center). This results in high symmetry of the laser and facilitates its fabrication.
[0123] For example, the material of the heat dissipation structure can be metals such as aluminum, copper, titanium, platinum, and gold, or other materials.
[0124] The materials used in different heat dissipation structures can be the same or different. This application does not impose any limitations on this.
[0125] For example, the materials of the two heat dissipation structures located on both sides of the III-V compound semiconductor waveguide can be aluminum or copper, respectively.
[0126] Any structure that can connect to the laser's electrodes or the silicon substrate at both ends along the first direction can serve as a heat dissipation structure. This application does not impose any limitations on this.
[0127] For example, the structure of the heat dissipation structure can be linear, sheet-like, or bulk.
[0128] Different heat dissipation structures can have the same or different structures. This application does not impose any limitations on this.
[0129] For example, the two heat dissipation structures located on both sides of a III-V compound semiconductor waveguide can be linear or bulk, respectively.
[0130] Along the first direction, above the linear heat dissipation structure are a BOX and a dielectric layer (e.g., the linear heat dissipation structure is as follows). Figure 6 (as shown in the V-shape).
[0131] The linear heat dissipation structure can be a uniform line with a constant diameter or a non-uniform line with a varying diameter. This application does not impose any limitations on this.
[0132] Along the first direction, the plate-shaped heat dissipation structure is topped with a dielectric layer; along the direction perpendicular to the first direction, the plate-shaped heat dissipation structure is flanked by BOX and dielectric layers on both sides.
[0133] The sheet-like heat dissipation structure can be perpendicular to a third direction, or it can be non-perpendicular to a third direction. This application does not impose any limitations on this.
[0134] Along the first direction, the bulk heat dissipation structure is surrounded by a dielectric layer; along the direction perpendicular to the first direction, the bulk heat dissipation structure is surrounded by a BOX and a dielectric layer.
[0135] The side of the volumetric heat dissipation structure can be perpendicular to the second direction, or it can be non-perpendicular to the second direction (for example, the volumetric heat dissipation structure is as follows). Figure 6 (The inverted cone shape shown). This application does not limit this aspect.
[0136] For example, the heat dissipation structure can be prepared by etching a dielectric layer, an SOI waveguide layer / silicon nitride waveguide layer, and a BOX layer in the opposite direction of the first direction to the silicon substrate, and then depositing metal or other materials in the etched portion to form a heat dissipation structure.
[0137] Figure 5 or Figure 6 The III-V compound semiconductor material shown is integrated with silicon photonics to form a laser. When energized, it can provide a light source. The light propagates in the form of an evanescent wave to the silicon photonic waveguide in the silicon photonic chip and propagates within the silicon photonic waveguide.
[0138] like Figure 7 As shown, Figure 7 Top and cross-sectional schematic diagrams of various III-V compound semiconductor lasers applicable to embodiments of this application are shown. Figure 7Either of the two III-V compound semiconductor lasers shown is one possible implementation of laser 300.
[0139] It should be understood that Figure 7 In any of the various III-V compound semiconductor lasers shown, the InP waveguide is only an example of a III-V compound semiconductor waveguide. The III-V compound semiconductor waveguide can also be made of other III-V compound semiconductor materials, and the embodiments of this application do not limit this.
[0140] In some possible implementations, the projection of the silicon optical waveguide onto the silicon substrate is formed as a first stripe; the projection of the III-V semiconductor waveguide onto the silicon substrate is formed as a second stripe.
[0141] In some possible implementations, the end of the first strip covers the end of the second strip.
[0142] For example, the width of the end of the first strip along the second direction is greater than or equal to the width of the end of the second strip along the second direction.
[0143] In some possible implementations, the first stripe covers the second stripe.
[0144] For example, the width of the first strip along the second direction is greater than or equal to the width of the second strip along the second direction.
[0145] In some possible implementations, the end of the second strip covers the end of the first strip.
[0146] For example, the width of the end of the first strip along the second direction is smaller than the width of the end of the second strip along the second direction.
[0147] In some possible implementations, the second stripe covers the first stripe.
[0148] For example, the width of the first strip along the second direction is smaller than the width of the second strip along the second direction.
[0149] For example, as shown in the cross-sectional view, silicon optical waveguides (SOI waveguides / silicon nitride waveguides) can be formed into ridge or T-shaped structures, with the silicon optical waveguide overlapping the InP waveguide along the first direction. The portion shown in the cross-sectional view corresponds to the portion indicated by the dashed line in the top view.
[0150] For example, as shown in the top view, either end of the InP waveguide along a third direction may contain or be contained within a silicon optical waveguide.
[0151] In the cross-sectional view, the InP waveguide and the silicon optical waveguide are separated by a dielectric layer. Figure 7 (Not shown in the image).
[0152] like Figure 8 As shown, Figure 8 A cross-sectional schematic diagram of a chip applicable to an embodiment of this application is shown. Figure 3 , Figure 4 , Figure 5 , Figure 6 or Figure 7 The structure shown can be applied to chips.
[0153] Figure 8 In the diagram, polygons filled with dense small black dots represent P-type semiconductors; rectangles filled with intersecting horizontal and vertical lines represent MQW active layers; rectangles filled with right-hand diagonal lines represent N-type semiconductors; portions filled with left-hand diagonal lines represent passivation layers; rectangles filled with vertical lines represent buffer layers; rectangles filled with intersecting diagonal lines represent metals; rectangles filled with thick horizontal lines represent metal electrodes; rectangles filled with thin horizontal lines represent substrates; polygons filled with large black dots represent heat dissipation structures; black-filled portions represent silicon optical waveguides; sparsely filled rectangles with small black dots represent silicon nitride waveguides; gray-filled portions represent buried oxide layers or dielectric layers; white-filled portions represent SOI layers; and hexagons filled with left-hand diagonal lines represent IV:GE (silicon-based germanium photodetectors). III-V semiconductor waveguides include N-type semiconductors, MQW active layers, and P-type semiconductors.
[0154] In this embodiment, along the first direction, the P-type semiconductor of the III-V compound semiconductor waveguide is connected to one end of a metal wire through a buffer layer and a metal contact layer, and the other end of the metal wire is connected to a metal pad. The modulator and / or detector are connected to one end of the metal wire through the metal pad, and the other end of the metal wire is connected to another metal pad. The number of metal pad layers can be one or more; the metal wires connect the leads, and the number of metal pad layers can also be one or more. The III-V compound semiconductor waveguide is placed within the dielectric layer of the silicon photonic chip, forming a highly integrated silicon photonic chip.
[0155] For example, after fabricating a passive silicon optical waveguide, modulator (e.g., Mach-Zehnder modulator, MZM), and photodiode detection (PD) on a silicon optical wafer, a III-V compound semiconductor material is bonded to the silicon optical wafer via molecular bonding. A III-V compound semiconductor waveguide layer is formed by etching the III-V compound semiconductor. Metallization is performed on the NPN junction surface of the III-V compound semiconductor waveguide to form metal electrodes. Windows are created in the silicon substrate around the III-V compound semiconductor waveguide by etching, and metal is deposited. The deposited metal is connected to the metal electrodes, and the metal electrodes are connected to the III-V compound semiconductor waveguide. The deposited metal serves as a heat dissipation structure for the laser. The electrodes of the modulator, detector, and laser are led out through a metal interconnect process to form a highly integrated silicon optical hybrid laser chip.
[0156] For example, after the heat dissipation structure is deposited, a BOX or dielectric layer material can be filled on top of the heat dissipation structure. For instance, the deposited heat dissipation structure is as follows: Figure 6 The V-shaped structure shown has a BOX and a dielectric layer on top of it.
[0157] In some possible implementations, the heat dissipation structure satisfies axisymmetry, and the axis of symmetry of the heat dissipation structure is parallel to the first direction.
[0158] For example, when a heat dissipation structure is formed by etching and deposition, the etched space can be axisymmetric. Thus, the heat dissipation structure obtained by depositing metal can be an axisymmetric structure such as a V-shape or an inverted cone shape.
[0159] The photodetector can be IV:GE (silicon-based germanium photodetector), which refers to a photodetector made of germanium (Ge) material integrated on a silicon-based platform.
[0160] like Figure 8 The chip shown can avoid the problem of poor alignment accuracy in flip chip solutions, and can also improve the heat dissipation performance of the laser (or the chip in which the laser is located).
[0161] like Figure 9 As shown, Figure 9 A schematic diagram of the layout of various lasers applicable to embodiments of this application is shown. Figure 3 , Figure 4 , Figure 5 , Figure 6 or Figure 7 The structure shown can be applied to hybrid lasers in chips.
[0162] exist Figure 9 In the chip shown, the transmitter silicon photonics chip is used... Figure 9 Either of the two layouts shown and the bonding method can be used to integrate multiple III-V compound semiconductor lasers. Integrating multiple lasers can realize a multi-channel light source array.
[0163] For example, light emitted from n hybrid lasers (n being an integer greater than 1) is sent to their respective MZMs, and the n MZMs send modulated light to their respective PDs. Or,
[0164] The light emitted by n hybrid lasers (n is an integer greater than 1) is sent to the corresponding MZM. The n MZMs send the modulated light to a multiplexer (MUX). The MUX sends the modulated light to the demultiplexer (DEMUX) of the receiver. The DEMUX sends the demultiplexed light to the n PDs.
[0165] like Figure 10 As shown, Figure 10 A schematic diagram of a hybrid bonding process applicable to embodiments of this application is shown. Figure 10 The process shown can be applied to silicon photonic wafers, lasers, or waveguides in any of the above possible implementations.
[0166] For example, the process first involves temporary bonding between the laser (InP dies) and the carrier (SiP wafer), followed by bonding and debonding of the carrier and the silicon photonics wafer as a whole, resulting in a hybrid laser (III-V patternmetal). Compared to the traditional FC method for mounting laser chips on silicon photonics chips, this process offers higher bonding efficiency, is suitable for multi-channel light source integration solutions, and simultaneously meets the requirements for small-size, highly integrated silicon photonics chips.
[0167] In some implementations, the aforementioned bonding can specifically refer to direct bonding, that is, connecting two surfaces together through physical contact, or it can be understood as the two surfaces being bonded by van der Waals forces. In the case of direct bonding, the double cantilever beam (DCB) method can be used for measurement. Alternatively, bonding can also specifically refer to bonding using adhesives, such as polymer adhesives, epoxy resins, polyurethane, etc. In this case, an adhesive layer is also provided on the two bonded surfaces. This type of bonding can be called die-to-die bonding or die-to-wafer bonding. Specific implementations of temporary bonding, bonding, or debonding can be found in relevant technologies and will not be elaborated upon here.
[0168] In this embodiment, along the first direction, a III-V compound semiconductor waveguide layer is bonded to an SOI waveguide layer or a dielectric layer of a silicon photonics wafer; the SOI waveguide includes an SOI layer and a Si epitaxial layer (the Si epitaxial layer is...). Figure 6 The raised portion of the silicon waveguide shown along the first direction can have its dielectric layer thickness changed between the SOI waveguide and the III-V compound semiconductor waveguide along the first direction by adjusting the thickness of the Si epitaxial layer.
[0169] Compared to purchasing or directly fabricating silicon wafers that meet thickness requirements, growing Si epitaxial layers allows for adjustment of the thickness of SOI waveguides, increasing the thickness of necessary portions as needed, and placing lower demands on silicon wafer raw materials.
[0170] Figure 11 This is an exemplary schematic diagram of an optical communication device 1100 provided in an embodiment of this application. For example... Figure 11 As shown, the optical communication device 1100 includes an optical module 1110. Optionally, the optical module 1110 includes components satisfying the above... Figures 3 to 9 The chip with the structure shown above, or using the above-mentioned Figure 10 The chip is fabricated using the process shown. Optionally, the optical communication device 1100 may also include one or more other optical modules, such as optical module 1120.
[0171] In one possible implementation, optical module 1110 is used to process signals received in optical communication device 1100, while optical module 1120 is used to process signals transmitted in optical communication device 1100.
[0172] Figure 12 This is an exemplary schematic diagram of another optical communication device 1200 provided in an embodiment of this application. For example... Figure 12 As shown, the optical communication device 1200 includes an optical switch 1210. Optionally, the optical switch 1210 includes components that satisfy the above... Figures 3 to 9 The chip with the structure shown above, or using the above-mentioned Figure 10 The chip is fabricated using the process shown. Optionally, the optical communication device 1200 may also include one or more other optical switches, such as optical switch 1220.
[0173] In one possible implementation, optical switch 1210 is used to process signals received in optical communication device 1200, while optical switch 1220 is used to process signals transmitted in optical communication device 1200.
[0174] Figure 13 This is an exemplary schematic diagram of another optical communication device 1300 provided in an embodiment of this application. For example... Figure 13 As shown, the optical communication device 1300 includes an optical modem 1310. Optionally, the optical modem 1310 includes components satisfying the above... Figures 3 to 9 The chip with the structure shown above, or using the above-mentioned Figure 10 The chip is fabricated using the process shown. Optionally, the optical communication device 1300 may also include one or more other optical modems, such as optical modem 1320.
[0175] In one possible implementation, optical modem 1310 is used to process signals received in optical communication device 1300, while optical modem 1320 is used to process signals transmitted in optical communication device 1300.
[0176] This application also provides an optical module, which includes the above-described chip.
[0177] This application also provides a communication device, including: a receiver including the above-described chip; and / or a transmitter including the above-described chip.
[0178] This application embodiment also provides a communication device, including: a transceiver for receiving or transmitting signals, the transceiver including the aforementioned chip, the chip being used to modulate or demodulate the signals; and a processor for processing the signals.
[0179] Skilled professionals may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0180] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0181] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0182] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0183] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0184] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.
[0185] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A silicon-based hybrid integrated laser, characterized in that, include: Silicon substrate, buried oxide layer, silicon optical waveguide, dielectric layer, III-V semiconductor waveguide, multiple metal electrodes, one or more heat dissipation structures. Along the first direction, the silicon substrate, the buried oxide layer, the silicon optical waveguide, the dielectric layer, and the III-V semiconductor waveguide are stacked. The III-V semiconductor waveguide includes an N-type semiconductor, a multi-quantum-well active layer, and a P-type semiconductor stacked along the first direction, wherein the N-type semiconductor is electrically connected to the metal electrode; The heat dissipation structure is housed within the buried oxide layer and the dielectric layer. One end of the heat dissipation structure along the first direction is thermally connected to the metal electrode, and the other end of the heat dissipation structure along the first direction is thermally connected to the silicon substrate.
2. The silicon-based hybrid integrated laser according to claim 1, characterized in that, The plurality of heat dissipation structures are disposed around the III-V semiconductor waveguide.
3. The silicon-based hybrid integrated laser according to claim 1 or 2, characterized in that, The plurality of heat dissipation structures are disposed on both sides of the III-V semiconductor waveguide.
4. The silicon-based hybrid integrated laser according to any one of claims 1 to 3, characterized in that, Along the second direction, at least two of the plurality of heat dissipation structures are at different distances from one end or the other end to the N-type semiconductor, and the second direction is perpendicular to the first direction; or, Along the second direction, one end or the other end of the plurality of heat dissipation structures is at the same distance from the N-type semiconductor, and the second direction is perpendicular to the first direction.
5. The silicon-based hybrid integrated laser according to any one of claims 1 to 4, characterized in that, The heat dissipation structure is axially symmetric, and the axis of symmetry of the heat dissipation structure is parallel to the first direction.
6. The silicon-based hybrid integrated laser according to any one of claims 1 to 5, characterized in that, The projection of the P-type semiconductor onto the upper surface of the multi-quantum-well active layer is located inside the projection of the multi-quantum-well active layer onto the upper surface of the multi-quantum-well active layer.
7. The silicon-based hybrid integrated laser according to any one of claims 1 to 6, characterized in that, The projection of the silicon optical waveguide onto the silicon substrate is formed as a first strip; The projection of the III-V semiconductor waveguide onto the silicon substrate is formed as a second stripe.
8. The silicon-based hybrid integrated laser according to claim 7, characterized in that, The end of the first strip covers the end of the second strip; or, The end of the second strip covers the end of the first strip.
9. The silicon-based hybrid integrated laser according to any one of claims 1 to 7, characterized in that, The silicon optical waveguide is a silicon waveguide, a silicon nitride waveguide, or a lithium niobate waveguide.
10. The silicon-based hybrid integrated laser according to claim 9, characterized in that, The cross-section of the P-type semiconductor is tapered along the first direction; or, The cross-section of the P-type semiconductor is rectangular along the first direction.
11. The silicon-based hybrid integrated laser according to claim 10, characterized in that, The bottom surface of the cone is electrically connected to the upper surface of the multi-quantum-well active layer; or, The top surface of the cone is electrically connected to the upper surface of the multi-quantum-well active layer.
12. A chip, characterized in that, The chip includes a silicon-based hybrid integrated laser, wherein the silicon-based hybrid integrated laser is the silicon-based hybrid integrated laser according to any one of claims 1 to 11.
13. An optical communication device, characterized in that, The optical communication device includes the chip described in claim 12.
14. The optical communication device according to claim 13, characterized in that, The optical communication equipment includes any one of an optical module, an optical switch, and an optical modem.