A high speed mode switching control system for wide input multi-mode ZVS-buck converter

Abstract

The application discloses a high-speed mode switching control system for a wide-input multi-mode ZVS-Buck converter, and belongs to the technical field of high-power-density power converters and power management, comprising a control circuit and a driving circuit, wherein the control circuit comprises a logic control circuit and a mode control circuit, wherein the logic control circuit comprises an inductor current sampling module, an output voltage sampling module, a compensation network module, two comparison modules, two timers, three dead-time modules and a flip-flop; the mode control circuit comprises two conduction time detection modules, a switching frequency detection module, two flip-flops and a logic AND gate. The application effectively adopts CrCM mode, DCM mode and COT mode, improves the efficiency under full load conditions, and significantly improves the dynamic response performance based on the mode switching method of conduction time or switching frequency detection. The application realizes fast mode switching when the load changes by detecting the conduction time or the switching frequency.

Description

Technical Field

[0001] This invention belongs to the field of high power density power converter and power management technology, specifically relating to a high-speed mode switching control system for a wide-input multimode ZVS-Buck converter. Background Technology

[0002] With the rapid advancements in technologies such as electric vehicles, big data, and artificial intelligence, voltage regulator modules (VRMs) have been widely adopted in several key areas. For example, in computer motherboards, VRMs provide precise power to the central processing unit (CPU), ensuring its efficient and stable operation; in server systems, VRMs provide reliable power support for various core computing and storage units, thereby ensuring the safety and stability of data processing and storage tasks. In recent years, as electronic devices have continued to evolve towards miniaturization and high performance, higher demands have been placed on the power density of VRMs, prompting power converters to continuously evolve towards higher power density. Increasing power density not only helps enhance the overall performance of electronic devices but also effectively reduces device size and weight, better meeting the dual demands of modern electronic devices for portability and high efficiency.

[0003] To improve power density, the frequency of power switches is constantly being increased. Increasing the switching frequency allows for a significant reduction in the size of magnetic components in the converter, such as inductors, playing a crucial role in improving power density. By increasing the switching frequency, more electrical energy can be processed per unit time, resulting in a faster transient response. In fields such as avionics and industrial control, 28V power systems are typically used, requiring high-voltage point-of-load (POL) power supplies. Due to their hard-switching operation, traditional Buck converters exhibit significant efficiency degradation under wide input voltage and high switching frequency conditions. To address these issues, research has been conducted on zero-voltage switching Buck converters (ZVS-Buck), which effectively solve the problems faced by traditional hard-switching Buck converters. By achieving zero-voltage turn-on of the high-side switch, switching losses can be effectively reduced, the switching frequency and conversion efficiency of the converter can be improved, and electromagnetic interference can be reduced.

[0004] Current research on ZVS-Buck converters faces several challenges: First, fixed-frequency control results in insufficient inductor current for charging and discharging the junction capacitance of the switching transistors under light loads, leading to the loss of ZVS conditions and the entry into a more lossy hard-switching state, thus reducing efficiency. Second, the input voltage range is insufficient, limiting application scenarios. Third, the switching frequency is relatively low; higher frequencies significantly increase core and drive losses, further reducing efficiency and hindering power density improvements. Therefore, existing designs generally employ low switching frequencies. Thus, a new control method needs to be explored to address these issues in ZVS-Buck converters. Summary of the Invention

[0005] This invention addresses the problems existing in the prior art by providing a high-speed mode switching control system for wide-input multimode ZVS-Buck converters. This system effectively solves the challenges currently faced by ZVS-Buck converters, enabling the converter to operate in COT, DCM, and CrCM modes under light, medium, and heavy load conditions, respectively. It achieves efficiency optimization across the ZVS and full load range. Furthermore, the mode switching method based on conduction time or switching frequency detection significantly improves dynamic response performance, effectively reducing the converter output voltage recovery time under load changes and minimizing electromagnetic interference. This provides a practical solution to meet the requirements of VRM in high-power-density, high-frequency applications.

[0006] To address the above technical problems, this invention provides the following technical solution: a high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter, comprising: a ZVS-Buck converter, a switch drive circuit, and a control circuit; the switch drive circuit is connected to the ZVS-Buck converter, the control circuit is connected to the switch drive circuit, and the ZVS-Buck converter is connected to the control circuit; wherein, the control circuit includes a mode control circuit and a logic control circuit, the mode control circuit generates a mode control signal by detecting the switch on-time and switching frequency of the ZVS-Buck converter, and the logic control circuit generates a switch control signal by detecting the mode control signal and the switch state of the ZVS-Buck converter; the switch drive circuit generates a switch drive signal using the switch control signal; the ZVS-Buck converter uses the switch drive signal to control the switch to be on or off, thereby realizing high-speed mode switching of the ZVS-Buck converter under load changes.

[0007] Furthermore, the aforementioned driving circuit includes: a clamping switch driving circuit, a low-side switch driving circuit, and a high-side switch driving circuit; the first input terminal of the ZVS-Buck converter is connected to the input voltage ZVS_V. IN The second input terminal is connected to the clamp switch drive signal S. 33The third input terminal is connected to the low-side switch drive signal S. 22 The fourth input terminal is connected to the high-side switch drive signal S. 11 The first output terminal of the ZVS-Buck converter is connected to the output voltage ZVS_V. OUT The second output terminal is connected to the inductor current I. L .

[0008] Furthermore, the aforementioned logic control circuit includes an inductor current sampling module, an output voltage sampling module, a compensation network module, a comparison module 1, a timer T1_Timer, a dead time module 1, a comparison module 2, an RS flip-flop RS1, a dead time module 2, an RS flip-flop RS2, a dead time module 3, and a timer T... S The circuit includes a timer and an RS flip-flop RS3; the mode control circuit includes a high-side switch conduction time detection circuit T1_Detector and a converter switching frequency detection circuit f. SW _Detector, clamp switch conduction time detection circuit T3_Detector, RS flip-flop RS4, RS flip-flop RS5 and logic AND gate AND1;

[0009] The input to the inductor current sampling module is the inductor current I. L The output is the inductor current sampling signal I. SMP The input to the output voltage sampling module is the output voltage ZVS_V. OUT The output is the output voltage feedback signal V. FB The input to the compensation network module is the output voltage feedback signal V. FB and reference voltage V ref1 The output is a control signal V. err The input to comparison module 1 is the inductor current sampling signal I. SMP With control signals The output is a control signal S. 1_OFF The inputs to timer T1_Timer are control signal S1 and control signal S. 1_OFF And the mode control signal COT, the output of which is the reset signal RESET1; timer T S The inputs to the _Timer are the modal control signal COT, modal control signal DCM, modal control signal CrCM, and control signal V. err Reference voltage V ref2 Reference voltage V ref3 Control signal S 1B and control signal S 2B The output is a control signal T. S _SET.

[0010] The input to dead time module 1 is the control signal T.S The RS flip-flop RS1 outputs the set signal SET1; the set terminal of RS1 is connected to the set signal SET1, and the reset terminal is connected to the reset signal RESET1; the output of RS1 is the control signal S1 and S... 1B The input to the high-side switch drive circuit is the control signal S1, and the output is the high-side switch drive signal S. 11 .

[0011] The input to dead time module 2 is the control signal S. 1B The output is the set signal SET2; the output of the comparator module 2 is the inductor current sampling signal I. SMP With reference voltage V ref4 The output is a reset signal RESET2; the set terminal of RS2 flip-flop is connected to the set signal SET2, and the reset terminal is connected to the reset signal RESET2; the output of RS2 flip-flop is the control signal S2 and S... 2B The input to the low-side switch drive circuit is the control signal S2, and the output is the low-side switch drive signal S. 22 .

[0012] The input to dead time module 3 is the control signal S. 2B The output is the set signal SET3; the reset terminal of the RS flip-flop RS3 is connected to the control signal T. S _SET, the set terminal is connected to the set signal SET3; the output of RS flip-flop RS3 is the control signal S3 and S 3B The input to the clamp switch drive circuit is the control signal S3, and the output is the clamp switch drive signal S. 33 ;

[0013] The input to the high-side switch conduction time detection circuit T1_Detector is the control signal S. 1B With fixed charging current I charge1 The output is the mode enable signal COT_EN; the converter switching frequency detection circuit f SW The input to the _Detector is the control signal S1 and the fixed charging current I. charge3 The output is the mode enable signal DCM_EN; the input of the clamp switch conduction time detection circuit T3_Detector is the control signal S. 3B and fixed charging current I charge2The output is the modal enable signal CrCM_EN; the set terminal of RS4 flip-flop is connected to the modal enable signal COT_EN, and the reset terminal is connected to the modal enable signal DCM_EN; the Q terminal of RS4 flip-flop is connected to the modal control signal COT; the set terminal of RS5 flip-flop is connected to the modal enable signal CrCM_EN, and the reset terminal is connected to the modal enable signal DCM_EN; the Q terminal of RS5 flip-flop is connected to the modal control signal CrCM; the outputs of the QN terminals of RS4 and RS5 flip-flops are input to the AND gate; the output of the AND gate AND1 is the modal control signal DCM.

[0014] Furthermore, the aforementioned timer T S The timer includes: a proportional amplifier K, transistor Q2, transistor Q3, a voltage-controlled current source VCCS, and a capacitor C. T1 Transistor Q1, comparator COMP_a, AND gate AND2, and OR gate OR.

[0015] The inputs to the proportional amplifier K are the amplification factor K and the control signal V. err The output is connected to the drain of transistor Q2; the gate input of transistor Q2 is the mode control signal SAMP_COT; the source of transistor Q2 is connected to the input of the voltage control current source VCCS; the drain input of transistor Q3 is the reference voltage SAMP_V. ref2 The gate input of transistor Q3 is the mode control signal SAMP_DCM; the source of transistor Q3 is connected to the input of the voltage-controlled current source VCCS; the output of the voltage-controlled current source VCCS is connected to capacitor C. T1 The upper end of the capacitor is connected to the drain of transistor Q1 and the non-inverting input of comparator COMP_a; capacitor C T1 The lower end is connected to ground; control signal S 1B The voltage is connected to the gate of transistor Q1 after passing through inverter INV; the source of transistor Q1 is connected to ground; the inverting input of comparator COMP_a is connected to the reference voltage SAMP_V. ref3 The input to the AND gate AND2 is the control signal SAMP_S. 2B The modal control signal SAMP_CrCM; the output of comparator COMP_a and the output of AND gate AND2 are input to the OR gate; the output of the OR gate is the control signal SAMP_T. S _SET.

[0016] Furthermore, the aforementioned modal control circuit includes: a high-side switch on-time detection circuit SAMP_T1_Detector, a clamp switch on-time detection circuit SAMP_T3_Detector, and a converter switching frequency detection circuit SAMP_fSW _Detector, RS flip-flop SAMP_RS4, RS flip-flop SAMP_RS5, and logic AND gate SAMP_AND1.

[0017] The input to the high-side switch conduction time detection circuit SAMP_T1_Detector is the control signal SAMP_S. 1B With fixed charging current SAMP_I charge1 The output is the mode enable signal SAMP_COT_EN; the converter switching frequency detection circuit SAMP_f SW The input to _Detector is the control signals SAMP_S1 and SAMP_I. charge3 The output is the mode enable signal SAMP_DCM_EN; the input of the clamp switch on-time detection circuit SAMP_T3_Detector is the control signal SAMP_S. 3B and SAMP_I charge2 The output is the mode enable signal SAMP_CrCM_EN; the set terminal of RS flip-flop SAMP_RS4 is connected to the mode enable signal SAMP_COT_EN, and the reset terminal is connected to the mode enable signal SAMP_DCM_EN; the Q terminal of RS flip-flop SAMP_RS4 is connected to the mode control signal SAMP_COT; the set terminal of RS flip-flop SAMP_RS5 is connected to the mode enable signal SAMP_CrCM_EN, and the reset terminal is connected to the mode enable signal SAMP_DCM_EN; the Q terminal of RS flip-flop SAMP_RS5 is connected to the mode control signal SAMP_CrCM; the output of the SAMP_QN terminal of RS flip-flop SAMP_RS4 and the output of the QN terminal of RS flip-flop SAMP_RS5 are input to the logic AND gate; the output of the logic AND gate SAMP_AND1 is the mode control signal SAMP_DCM.

[0018] Furthermore, the aforementioned high-side switch on-time detection circuit SAMP_T1_Detector includes transistor Q4 and capacitor C. T2 Capacitor C T3 Transmission gate TRANS1, OneShot module 1, Delay module 1, Inverter chain INV_CHAIN1, High-side switch minimum on-time generator SAMP_T 1_MIN_GEN And the comparator COMP_b.

[0019] The drain of transistor Q4 is connected to the fixed charging current I. charge1 Connected, gate and control signal S 1B_delay Connected, source and ground are connected; capacitor C T2 The upper end is connected to the fixed charging current I charge1Connected to the ground at the bottom; the input of the transmission gate TRANS1 is connected to the fixed charging current I. charge1 Connected, the control input is the control signal S 1B_Shot The output is the high-side switch conduction time SAMP_T1; capacitor C T3 The upper end is connected to the output of the transmission gate TRANS1, and the lower end is connected to ground; the input of OneShot module 1 is the control signal SAMP_S 1B The output is a control signal S. 1B_Shot The input to the inverter chain INV_CHAIN1 is the control signal S. 1B_Shot The output is the pulse signal CLK1; the input of delay module 1 is the control signal SAMP_S. 1B The output is a control signal S. 1B_delay High-side switch minimum on-time generator SAMP_T 1_MIN_GEN The input is the control signal SAMP_S 1B The output is the minimum on-time of the high-side switch, SAMP_T. 1_MIN The inverting input of comparator COMP_b is the high-side switch on-time SAMP_T1, and the non-inverting input is the high-side switch minimum on-time SAMP_T. 1_MIN The clock pulse control terminal takes a pulse signal CLK1 as input and outputs a mode enable signal SAMP_COT_EN as output.

[0020] Furthermore, the aforementioned clamping switch on-time detection circuit SAMP_T3_Detector includes transistor Q5 and capacitor C. T4 Capacitor C T5 Transmission gate TRANS2, OneShot module 2, Delay module 2, Inverter chain INV_CHAIN2, Clamp switch minimum on-time generator SAMP_T 3_MIN_GEN And the comparator COMP_c.

[0021] The drain of transistor Q5 is connected to the fixed charging current I. charge2 Connected, gate and control signal S 3B_delay Connected, source and ground are connected; capacitor C T4 The upper end is connected to the fixed charging current I charge2 Connected to the ground at the bottom; the input of the transmission gate TRANS2 is connected to the fixed charging current I. charge2 Connected, the control input is the control signal S 3B_Shot The output is the high-side switch conduction time SAMP_T3; capacitor C T5 The upper end is connected to the output of the transmission gate TRANS2, and the lower end is connected to ground; the input of OneShot module 2 is the control signal SAMP_S 3B The output is a control signal S.3B_Shot The input to the inverter chain INV_CHAIN2 is the control signal S. 3B_Shot The output is the pulse signal CLK2; the input of delay module 2 is the control signal SAMP_S. 3B The output is a control signal S. 3B_delay Minimum On-Time Generator for Clamp Switches (SAMP_T) 3_MIN_GEN The input is the control signal SAMP_S 3B The output is the minimum on-time of the high-side switch, SAMP_T. 3_MIN The inverting input of comparator COMP_c is the high-side switch on-time SAMP_T3, and the non-inverting input is the high-side switch minimum on-time SAMP_T. 1_MIN The clock pulse control terminal takes a pulse signal CLK2 as input and outputs a mode enable signal SAMP_CrCM_EN as output.

[0022] Furthermore, the aforementioned converter switching frequency detection circuit SAMP_f SW The detector includes transistor Q6 and capacitor C. T6 Capacitor C T7 Transmission gate TRANS3, OneShot module 3, OneShot module 4, Delay module 3, Inverter chain INV_CHAIN3, Converter switch maximum frequency generator SAMP_f sw_MAX_GEN And the comparator COMP_d.

[0023] The drain of transistor Q6 is connected to the fixed charging current I. charge3 Connected, gate and control signal S 1_Shot2 Connected, source and ground are connected; capacitor C T6 The upper end is connected to the fixed charging current I charge3 Connected to the ground at the bottom; the input of the transmission gate TRANS3 is connected to the fixed charging current I. charge3 Connected, the control input is the control signal S 1_Shot1 The output is the converter switching frequency SAMP_f SW Capacitor C T7 The upper end is connected to the output of the transmission gate TRANS3, and the lower end is connected to ground; the input of OneShot module 3 is the control signal SAMP_S1, and the output is the control signal S. 1_Shot1 The input to the inverter chain INV_CHAIN3 is the control signal S. 1_Shot1 The output is the pulse signal CLK3; the input of delay module 3 is the control signal SAMP_S1, and the output is the control signal S. 1_delay The input to OneShot module 4 is the control signal S. 1_delay The output is S 1_Shot2; Converter switching maximum frequency generator SAMP_f sw_MAX_GEN The input is the control signal SAMP_S1, and the output is the maximum switching frequency of the converter, SAMP_f. SW_MAX The inverting input of comparator COMP_d is the converter switching frequency SAMP_f. SW The non-inverting input is the maximum switching frequency of the converter, SAMP_f. SW_MAX The clock pulse control terminal takes a pulse signal CLK3 as input and outputs a mode enable signal SAMP_DCM_EN.

[0024] Compared with the prior art, the beneficial technical effects of the present invention using the above technical solution are as follows:

[0025] This invention proposes a high-speed mode-switching control system for wide-input multimode ZVS-Buck converters, based on current ZVS-Buck converters. The core of the proposed control system lies in achieving rapid mode switching during load changes by detecting conduction time or switching frequency. Current ZVS-Buck converters, on the one hand, can only achieve fixed-frequency control, which easily leads to the switch losing ZVS conditions under light load conditions, switching to a high-loss hard-switching state and resulting in decreased efficiency. On the other hand, traditional multimode control can cause a deterioration in dynamic response speed, resulting in voltage overshoot and undershoot during load changes.

[0026] This invention addresses the high switching losses of traditional hard-switching Buck converters by proposing a novel control method. This method effectively employs CrCM, DCM, and COT modes to improve efficiency under full load conditions and significantly enhances dynamic response performance through mode switching based on conduction time or switching frequency detection. Figure 2 As shown, the solid line represents the efficiency of the proposed control method under different input voltages and loads, while the dashed line represents the efficiency of the traditional ZVS-Buck converter under different input voltages and loads. The proposed high-speed mode switching control system for wide-input multimode ZVS-Buck converters can significantly improve efficiency under different input voltages and loads. Attached Figure Description

[0027] Figure 1 This is a functional block diagram of the control method of the present invention.

[0028] Figure 2 This is a comparison chart of the efficiency of existing ZVS-Buck converters and the proposed ZVS-Buck converter and its control method.

[0029] Figure 3(a) shows the multimode ZVS-Buck converter and switch drive circuit diagram.

[0030] Figure 3(b) is the logic control circuit diagram.

[0031] Figure 3(c) shows timer T. S Timer circuit diagram,

[0032] Figure 3(d) is the modal control circuit diagram.

[0033] Figure 3(e) is the circuit diagram of the high-side switch on-time detection circuit SAMP_T1_Detector.

[0034] Figure 3(f) is the circuit diagram of the clamp switch on-time detection circuit SAMP_T3_Detector.

[0035] Figure 3(g) shows the converter switching frequency detection circuit SAMP_f SW Detector circuit diagram. Detailed Implementation

[0036] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.

[0037] In this invention, various aspects of the invention are described with reference to the accompanying drawings, in which numerous illustrative embodiments are shown. Embodiments of the invention are not limited to those depicted in the drawings. It should be understood that the invention is implemented through any of the various concepts and embodiments described above, as well as the concepts and embodiments described in detail below, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.

[0038] like Figure 1 As shown, this invention proposes a high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter. It includes: a ZVS-Buck converter, a switch drive circuit, and a control circuit; the switch drive circuit is connected to the ZVS-Buck converter, the control circuit is connected to the switch drive circuit, and the ZVS-Buck converter is connected to the control circuit.

[0039] The drive circuit includes: a clamping switch drive circuit, a low-side switch drive circuit, and a high-side switch drive circuit.

[0040] The control circuit includes a logic control circuit and a modal control circuit. The logic control circuit includes an inductor current sampling module, an output voltage sampling module, a compensation network module, a comparator module 1, a timer T1_Timer, a dead-time module 1, a comparator module 2, an RS flip-flop RS1, a dead-time module 2, an RS flip-flop RS2, a dead-time module 3, and a timer T... SThe circuit includes a timer and an RS flip-flop RS3; the mode control circuit includes a high-side switch conduction time detection circuit T1_Detector and a converter switching frequency detection circuit f. SW The circuit includes a detector, a clamp switch conduction time detection circuit T3, an RS flip-flop RS4, an RS flip-flop RS5, and an AND gate AND1.

[0041] The first input terminal of the ZVS-Buck converter is connected to the input voltage ZVS_V. IN The second input terminal is connected to the clamping switch drive signal S. 33 The third input terminal is connected to the low-side switch drive signal S. 22 The fourth input terminal is connected to the high-side switch drive signal S. 11 The first output terminal of the ZVS-Buck converter is connected to the output voltage ZVS_V. OUT The second output terminal is connected to the inductor current I. L .

[0042] The input to the inductor current sampling module is the inductor current I. L The output is the inductor current sampling signal I. SMP The input to the output voltage sampling module is the output voltage ZVS_V. OUT The output is the output voltage feedback signal V. FB The input to the compensation network module is the output voltage feedback signal V. FB and reference voltage V ref1 The output is a control signal V. err The input to comparison module 1 is the inductor current sampling signal I. SMP With control signals The output is a control signal S. 1_OFF The inputs to timer T1_Timer are control signal S1 and control signal S. 1_OFF And the mode control signal COT, the output of which is the reset signal RESET1; timer T S The inputs to the _Timer are the modal control signal COT, modal control signal DCM, modal control signal CrCM, and control signal V. err Reference voltage V ref2 Reference voltage V ref3 Control signal S 1B and control signal S 2B The output is a control signal T. S _SET.

[0043] The input to dead time module 1 is the control signal T. SThe RS flip-flop RS1 outputs the set signal SET1; the set terminal of RS1 is connected to the set signal SET1, and the reset terminal is connected to the reset signal RESET1; the output of RS1 is the control signal S1 and S... 1B The input to the high-side switch drive circuit is the control signal S1, and the output is the high-side switch drive signal S. 11 .

[0044] The input to dead time module 2 is the control signal S. 1B The output is the set signal SET2; the output of the comparator module 2 is the inductor current sampling signal I. SMP With reference voltage V ref4 The output is a reset signal RESET2; the set terminal of RS2 flip-flop is connected to the set signal SET2, and the reset terminal is connected to the reset signal RESET2; the output of RS2 flip-flop is the control signal S2 and S... 2B The input to the low-side switch drive circuit is the control signal S2, and the output is the low-side switch drive signal S. 22 .

[0045] The input to dead time module 3 is the control signal S. 2B The output is the set signal SET3; the reset terminal of the RS flip-flop RS3 is connected to the control signal T. S _SET, the set terminal is connected to the set signal SET3; the output of RS flip-flop RS3 is the control signal S3 and S 3B The input to the clamp switch drive circuit is the control signal S3, and the output is the clamp switch drive signal S. 33 .

[0046] The input to the high-side switch conduction time detection circuit T1_Detector is the control signal S. 1B Minimum on-time T of the high-side switch 1_MIN The output is the mode enable signal COT_EN; the converter switching frequency detection circuit f SW The input to the _Detector is the control signal S1 and the highest switching frequency f of the converter. SW_MAX The output is the mode enable signal DCM_EN; the input of the clamp switch conduction time detection circuit T3_Detector is the control signal S. 3B Minimum on-time T of clamping switch 3_MINThe output is the modal enable signal CrCM_EN; the set terminal of RS4 flip-flop is connected to the modal enable signal COT_EN, and the reset terminal is connected to the modal enable signal DCM_EN; the Q terminal of RS4 flip-flop is connected to the modal control signal COT; the set terminal of RS5 flip-flop is connected to the modal enable signal CrCM_EN, and the reset terminal is connected to the modal enable signal DCM_EN; the Q terminal of RS5 flip-flop is connected to the modal control signal CrCM; the outputs of the QN terminals of RS4 and RS5 flip-flop are input to the AND gate; the output of the AND gate AND1 is the modal control signal DCM.

[0047] The working principle of the logic control system is as follows: After the ZVS-Buck converter starts working, the inductor current sampling module and the output voltage sampling module sample and generate the inductor current sampling signal I. SMP With output voltage feedback signal V FB Output voltage feedback signal V FB With reference voltage V ref1 After frequency compensation by the compensation network module, a control signal V is generated. err Inductor current sampling signal I SMP With control signal V err After entering comparison module 1, a control signal S is generated. 1_OFF Modal control signal COT, control signal S1, and control signal S 1_OFF A timer T1_Timer is connected, and the timer T1_Timer generates a reset signal RESET1, which is connected to the reset terminal of the RS flip-flop RS1. When the reset signal RESET1 is low, the timer T1_Timer... S The control signal T output by _Timer S _SET accesses dead time module 1, when T S When _SET is high, after time T delay1 The generated signal SET1 is then transmitted to the set pin of RS1, T delay1 The dead time is generated by dead time module 1; the control signal S1 changes from low level to high level and is transmitted to the high-side switch drive circuit, and then the high-side switch drive circuit generates the high-side switch control signal S. 11 The signal changes from low to high, turning on the high-side switch ZVS_SW1; when the inductor current sampling signal I... SMP Compared to the control signal V err When high, control signal S 1_OFF The signal changes from low to high; control signal S1, control signal S 1_OFF Together with the modal control signal COT, the reset signal RESET1 is determined when the control signal S... 1_OFFWhen the signal is high and the mode control signal COT is low, the reset signal RESET1 changes from low to high; when the mode control signal COT is high, the control signal S1 changes from low to high after the minimum on-time T of the high-side switch. 1_MIN Afterwards, the reset signal RESET1 changes from low to high; when the reset signal RESET1 is high, the control signal S1 changes from high to low. 1B The signal changes from low to high; control signal S1 is transmitted to the high-side switch drive circuit, and then the high-side switch drive circuit generates a high-side switch control signal S. 11 The high-level signal changes to a low-level signal, turning off the high-side switch ZVS_SW1; control signal S 1B Entering dead time module 2, after time T delay2 The generated signal SET2 is then transmitted to the set terminal of RS flip-flop RS2, T delay2 The dead time is generated by dead time module 2; control signal S2 changes from low level to high level, S 2B The signal changes from high to low; the control signal S2 is transmitted to the low-side switch drive circuit, and then the low-side switch drive circuit generates the low-side switch control signal S. 22 The signal changes from low to high, turning on the low-side switch ZVS_SW2; when the inductor current sampling signal I... SMP Compared to the reference voltage V ref4 When the signal is low, the reset signal RESET2 output by comparator module 2 changes from low to high and is transmitted to the RS2 reset terminal; the control signal S2 changes from high to low, S... 2B The signal changes from low to high; the control signal S2 is transmitted to the low-side switch drive circuit, and then the low-side switch drive circuit generates the low-side switch control signal S. 22 The signal changes from high to low, turning off the low-side switch ZVS_SW2; control signal S 2B Entering dead time module 3, after time T delay3 The generated signal SET3 is then transmitted to the RS3 set pin, T delay3 The dead time is generated by dead time module 3; control signal S3 changes from low level to high level, S 3B The signal changes from high to low; control signal S3 is transmitted to the clamp switch drive circuit, and then the clamp switch drive circuit generates clamp switch control signal S. 33 The change from low to high level activates the clamping switch ZVS_SW3; timer T S The control signal T output by _Timer S _SET is connected to the RS3 reset terminal. When the control signal T S When _SET is high, S 3BThe signal changes from low to high; control signal S3 is transmitted to the clamp switch drive circuit, and then the clamp switch drive circuit generates clamp switch control signal S. 33 The change from high level to low level turns off the clamping switch ZVS_SW3.

[0048] The working principle of the modal control system is as follows: The input of the high-side switch conduction time detection circuit T1_Detector is the control signal S. 1B Minimum on-time T of the high-side switch 1_MIN The output is the mode enable signal COT_EN; the mode enable signal COT_EN is connected to the set terminal of RS flip-flop RS4. When the mode enable signal COT_EN is high, the mode control signal COT is high, and the circuit is in COT mode; the input of the clamp switch conduction time detection circuit T3_Detector is the control signal S. 3B Minimum on-time T of clamping switch 3_MIN The output is a mode enable signal CrCM_EN; the mode enable signal CrCM_EN is connected to the set terminal of RS flip-flop RS5. When the mode enable signal CrCM_EN is high, the mode control signal CrCM is high, and the circuit is in CrCM mode; the converter switching frequency detection circuit f SW The input to the _Detector is the control signal S1 and the highest switching frequency f of the converter. SW_MAX The output is the mode enable signal DCM_EN. The mode enable signal DCM_EN converter is connected to the reset terminals of RS flip-flops RS4 and RS5. When the mode enable signal DCM_EN is high, the mode control signal DCM is high, and the circuit is in DCM mode.

[0049] Specific embodiments of the present invention are shown in Figures 3(a) to (g). Figure 3(a) is a circuit diagram of a multimodal ZVS-Buck converter and a switch drive circuit, showing the number and names of the ports. Figure 1 The ZVS-Buck converter remains consistent with the control circuit in Figure 3(a). The inductor current sampling module and output current sampling module belong to the control circuit section. The ZVS-Buck converter has a high-side switch M1, a low-side switch M2, and clamping switches M3 and M4. The input of the ZVS-Buck converter and the switch drive circuit is SAMP_V. IN The control signals SAMP_S1 (high-side switch drive circuit), SAMP_S2 (low-side switch drive circuit), and SAMP_S3 (clamp switch drive circuit) output SAMP_V. OUT Output voltage feedback signal SAMP_V FB and inductor current sampling signal SAMP_I SMP SAMP_V INAfter passing through capacitor SAMP_C IN After filtering, the energy storage element outputs through the high-side switch M1, the low-side switch M2, and the energy storage element output inductor SAMP_L. OUT With output capacitor SAMP_C OUT The voltage is stepped down. The zero-voltage switch Buck (ZVS-Buck), high-side switch drive circuit, low-side switch drive circuit, and clamping switch drive circuit mentioned above are existing technologies and will not be described in detail here.

[0050] The logic control circuit is shown in Figure 3(b). The inputs of the logic control circuit are the mode control signal SAMP_COT, the mode control signal SAMP_DCM, the mode control signal SAMP_CrCM, and the output voltage feedback signal SAMP_V. FB、 Inductor current sampling signal SAMP_I SMP Reference voltage SAMP_V ref1 Reference voltage SAMP_V ref2 Reference voltage SAMP_V ref3 and reference voltage SAMP_V ref4 The mode enable signal comes from the mode control circuit; the output of the logic control circuit is the control signals SAMP_S1 and SAMP_S. 1B Control signals SAMP_S2 and SAMP_S 2B and control signals SAMP_S3 and SAMP_S 3B Output voltage feedback signal SAMP_V FB With reference voltage SAMP_V ref1 After frequency compensation by the compensation network module, the control signal SAMP_V is generated. err Inductor current sampling signal SAMP_I SMP With control signal SAMP_V err After entering comparator COMP_e, the control signal SAMP_S is generated. 1_OFF Modal control signal SAMP_COT, control signal SAMP_S1, and control signal SAMP_S 1_OFF A timer T1_Timer is connected, and the timer T1_Timer generates a reset signal SAMP_RESET1, which is connected to the reset terminal of the RS flip-flop SAMP_RS1. When the reset signal SAMP_RESET1 is low, the timer T1_Timer... S The control signal SAMP_T output by _Timer S _SET accesses dead time module 1, when SAMP_T S When _SET is high, time SAMP_T elapses. delay1 The generated signal SAMP_SET1 is then transmitted to the set pin of SAMP_RS1, SAMP_Tdelay1 The dead time is generated by dead time module 1; the control signal SAMP_S1 changes from low to high and is transmitted to the high-side switch drive circuit; when the inductor current sampling signal SAMP_I... SMP Comparison of control signal SAMP_V err When high, the control signal SAMP_S 1_OFF The signal changes from low to high; control signal SAMP_S1, control signal SAMP_S 1_OFF Together with the modal control signal SAMP_COT, the reset signal SAMP_RESET1 is determined. When the control signal SAMP_S... 1_OFF When the mode control signal SAMP_COT is high and the mode control signal SAMP_COT is low, the reset signal SAMP_RESET1 changes from low to high; when the mode control signal SAMP_COT is high, the control signal SAMP_S1 changes from low to high after the minimum on-time SAMP_T of the high-side switch. 1_MIN Afterwards, the reset signal SAMP_RESET1 changes from low to high; when the reset signal SAMP_RESET1 is high, the control signal SAMP_S1 changes from high to low, and SAMP_S 1B When the signal changes from low to high, the control signal SAMP_S1 is transmitted to the high-side switch driver circuit; the control signal SAMP_S 1B Entering dead time module 2, time SAMP_T has elapsed. delay2 The generated signal SAMP_SET2 is then transmitted to the set pin of the RS flip-flop SAMP_RS2, SAMP_T delay2 The dead time generated by dead time module 2; the control signal SAMP_S2 changes from low to high, SAMP_S 2B The signal changes from high to low; the control signal SAMP_S2 is transmitted to the low-side switch drive circuit; when the inductor current sampling signal SAMP_I... SMP Comparison with reference voltage SAMP_V ref4 When the signal is low, the reset signal SAMP_RESET2 output by comparator COMP_f changes from low to high and is transmitted to the reset terminal of SAMP_RS2; the control signal SAMP_S2 changes from high to low, and SAMP_S... 2B When the signal changes from low to high, the control signal SAMP_S2 is transmitted to the low-side switch driver circuit; the control signal SAMP_S 2B Entering dead time module 3, time SAMP_T has elapsed. delay3 The generated signal SAMP_SET3 is then transmitted to the set pin of SAMP_RS3, SAMP_T delay3The dead time generated by dead time module 3; the control signal SAMP_S3 changes from low to high, SAMP_S 3B The signal changes from high to low; the control signal SAMP_S3 is transmitted to the clamp switch driver circuit; timer T... S The control signal SAMP_T output by _Timer S _SET is connected to the SAMP_RS3 reset pin, when the control signal SAMP_T S When _SET is high, SAMP_S 3B When the signal changes from low to high, the control signal SAMP_S3 is transmitted to the clamp switch drive circuit.

[0051] As shown in Figure 3(c), timer T s The timer includes: a proportional amplifier K, transistors Q1, Q2, and Q3, an inverter INV, a voltage-controlled current source VCCS, and a capacitor C. T1 Transistor Q1, comparator COMP_a, AND gate AND2, and OR gate OR.

[0052] The inputs to the proportional amplifier K are the amplification factor K and the control signal V. err The output is connected to the drain of transistor Q2; the gate input of transistor Q2 is the mode control signal SAMP_COT; the source of transistor Q2 is connected to the input of the voltage control current source VCCS; the drain input of transistor Q3 is the reference voltage SAMP_V. ref2 The gate input of transistor Q3 is the mode control signal SAMP_DCM; the source of transistor Q3 is connected to the input of the voltage-controlled current source VCCS; the output of the voltage-controlled current source VCCS is connected to capacitor C. T1 The upper end of the capacitor is connected to the drain of transistor Q1 and the non-inverting input of comparator COMP_a; capacitor C T1 The lower end is connected to ground; control signal S 1B The voltage is connected to the gate of transistor Q1 after passing through inverter INV; the source of transistor Q1 is connected to ground; the inverting input of comparator COMP_a is the reference voltage SAMP_V. ref3 The input to the AND gate AND2 is the control signal SAMP_S. 2B The modal control signal SAMP_CrCM; the output of comparator COMP_a and the output of AND gate AND2 are input to the OR gate; the output of the OR gate is the control signal SAMP_T. S _SET.

[0053] The timer T sThe inputs to _Timer are the modal control signals SAMP_COT, SAMP_DCM, SAMP_CrCM, and SAMP_V. err Reference voltage SAMP_V ref2 Reference voltage SAMP_V ref3 Control signal SAMP_S 1B and control signal SAMP_S 2B The output is the control signal SAMP_T S _SET. Assume the control signal SAMP_S 1B When the SAMP_COT signal is high, transistor Q1 is off. When the mode control signal SAMP_COT is high, transistor Q2 is on and transistor Q3 is off. The control signal SAMP_V... err After being multiplied by the amplification factor K of the proportional amplifier K, the current is supplied to capacitor C through the voltage-controlled current source VCCS. T1 Charging; when the mode control signal SAMP_DCM is high, transistor Q3 is turned on, transistor Q2 is turned off, and the reference voltage SAMP_V is charged. ref2 The voltage-controlled current source VCCS supplies power to capacitor C. T1 Charging; Capacitor C T1 The voltage across the terminals and the reference voltage SAMP_V ref3 The input comparator COMP_a performs a comparison, and when the capacitor C... T1 The voltage across the terminals is greater than the reference voltage SAMP_V ref3 When the comparator COMP_a outputs a high level, this high-level signal is ORed by a logic gate, causing the control signal SAMP_T to... S The _SET signal changes from low to high, controlling the SAMP_T signal. S _SET is transmitted to the reset terminal of RS flip-flop SAMP_RS3 and dead time module 1; when the control signal SAMP_S 1B When the voltage level changes from high to low, transistor Q1 turns on, and capacitor C... T1 Discharge to ground causes capacitor C to... T1 The voltage across the terminals is less than the reference voltage SAMP_V ref3 When the comparator COMP_a outputs a low level, this low-level signal is ORed by a logic gate, causing the control signal SAMP_T to... S The _SET signal changes from high to low, controlling the SAMP_T signal. S _SET is transmitted to the reset terminal of RS flip-flop SAMP_RS3 and dead-time module 1, thus ending one timing cycle. When the mode control signal SAMP_CrCM is high, when the control signal SAMP_S 2BWhen the signal is high, the output of the AND gate AND2 is high. This high-level signal is then passed through the OR gate OR to control the SAMP_T signal. S The _SET signal changes from low to high, controlling the SAMP_T signal. S _SET is transmitted to the reset terminal of RS flip-flop SAMP_RS3 and dead time module 1; when the mode control signal SAMP_CrCM is high, when the control signal SAMP_S 2B When the signal is low, the output of the AND gate AND2 is low. This low-level signal is then passed through the OR gate OR to control the SAMP_T signal. S The _SET signal changes from high to low, controlling the SAMP_T signal. S The _SET signal is transmitted to the reset pin of the RS flip-flop SAMP_RS3 and the dead-time module 1, thus completing one timing cycle. The above is the control signal SAMP_T. S The _SET generation mechanism involves the control signal being input to the logic control circuit and then passing through the high-side switch drive circuit and the clamp switch drive circuit. This controls the shutdown of clamp switches M3 and M4 and the activation of the high-side switch M1, thereby generating the ZVS-Buck's operating cycle time T. S .

[0054] As shown in Figure 3(d), the mode control circuit includes: a high-side switch on-time detection circuit SAMP_T1_Detector, a clamp switch on-time detection circuit SAMP_T3_Detector, and a converter switching frequency detection circuit SAMP_f SW _Detector, RS flip-flop SAMP_RS4, RS flip-flop SAMP_RS5, and logic AND gate SAMP_AND1.

[0055] The input to the high-side switch on-time detection circuit SAMP_T1_Detector is the control signal SAMP_S. 1B Minimum On-Time SAMP_T of High-Side Switch 1_MIN The output is the mode enable signal SAMP_COT_EN; the converter switching frequency detection circuit SAMP_f SW The input to _Detector is the control signal SAMP_S 1B With the highest switching frequency of the converter, SAMP_f SW_MAX The output is the mode enable signal SAMP_DCM_EN; the input of the clamp switch on-time detection circuit SAMP_T3_Detector is the control signal SAMP_S. 3B and the minimum on-time of the clamping switch, SAMP_T 3_MINThe output is the mode enable signal SAMP_CrCM_EN; the set terminal of RS flip-flop SAMP_RS4 is connected to the mode enable signal SAMP_COT_EN, and the reset terminal is connected to the mode enable signal SAMP_DCM_EN; the Q terminal of RS flip-flop SAMP_RS4 is connected to the mode control signal SAMP_COT; the set terminal of RS flip-flop SAMP_RS5 is connected to the mode enable signal SAMP_CrCM_EN, and the reset terminal is connected to the mode enable signal SAMP_DCM_EN; the Q terminal of RS flip-flop SAMP_RS5 is connected to the mode control signal SAMP_CrCM; the output of the SAMP_QN terminal of RS flip-flop SAMP_RS4 and the output of the QN terminal of RS flip-flop SAMP_RS5 are input to the logic AND gate SAMP_AND1, and the output is the mode control signal SAMP_DCM.

[0056] The inputs to the modal control circuit are control signal SAMP_S1 and control signal SAMP_S. 1B Control signal SAMP_S 3B Minimum on-time of high-side switch SAMP_T 1_MIN The highest switching frequency of the converter, SAMP_f SW_MAX and the minimum on-time of the clamping switch, SAMP_T 3_MIN The outputs are mode control signals SAMP_COT, SAMP_CrCM, and SAMP_DCM. The input to the high-side switch on-time detection circuit SAMP_T1_Detector is the control signal SAMP_S. 1B Minimum On-Time SAMP_T of High-Side Switch 1_MIN The output is the mode enable signal SAMP_COT_EN; the mode enable signal COT_EN is connected to the set terminal of the RS flip-flop SAMP_RS4. When the mode enable signal COT_EN is high, the mode control signal SAMP_COT is high, and the circuit is in COT mode; the input of the clamp switch conduction time detection circuit SAMP_T3_Detector is the control signal SAMP_S 3B and the minimum on-time of the clamping switch, SAMP_T 3_MIN The output is the mode enable signal SAMP_CrCM_EN; the mode enable signal SAMP_CrCM_EN is connected to the set terminal of RS flip-flop RS5. When the mode enable signal SAMP_CrCM_EN is high, the mode control signal SAMP_CrCM is high, and the circuit is in CrCM mode; the converter switching frequency detection circuit SAMP_f SW The input to _Detector is the control signal SAMP_S1 and the highest switching frequency of the converter SAMP_f. SW_MAXThe output is the mode enable signal SAMP_DCM_EN. The mode enable signal SAMP_DCM_EN converter is connected to the reset terminal of RS flip-flops SAMP_RS4 and SAMP_RS5. When the mode enable signal SAMP_DCM_EN is high, the mode control signal SAMP_DCM is high, and the circuit is in DCM mode.

[0057] As shown in Figure 3(e), the high-side switch conduction time detection circuit SAMP_T1_Detector includes: transistor Q4, capacitor C T2 Capacitor C T3 Transmission gate TRANS1, OneShot module 1, Delay module 1, Inverter chain INV_CHAIN1, High-side switch minimum on-time generator SAMP_T 1_MIN_GEN And the comparator COMP_b.

[0058] The drain of transistor Q4 is connected to the fixed charging current I. charge1 Connected, gate and control signal S 1B_delay Connected, source and ground; capacitor C T2 The upper end is connected to the fixed charging current I charge1 Connected to the ground at the bottom; the input of the transmission gate TRANS1 is connected to the fixed charging current I. charge1 Connected, the control input is the control signal S 1B_Shot The output is the high-side switch conduction time SAMP_T1; capacitor C T3 The upper end is connected to the output of the transmission gate TRANS1, and the lower end is connected to ground; the input of OneShot module 1 is the control signal SAMP_S 1B The output is a control signal S. 1B_Shot The input to the inverter chain INV_CHAIN1 is the control signal S. 1B_Shot The output is the pulse signal CLK1; the input of delay module 1 is the control signal SAMP_S. 1B The output is a control signal S. 1B_delay High-side switch minimum on-time generator SAMP_T 1_MIN_GEN The input is the control signal SAMP_S 1B The output is the minimum on-time of the high-side switch, SAMP_T. 1_MIN The inverting input of comparator COMP_b is the high-side switch on-time SAMP_T1, and the non-inverting input is the high-side switch minimum on-time SAMP_T. 1_MIN The clock pulse control terminal takes a pulse signal CLK1 as input and outputs a mode enable signal SAMP_COT_EN as output.

[0059] The input to the high-side switch conduction time detection circuit SAMP_T1_Detector is a fixed charging current I. charge1 and control signal SAMP_S 1B The output is the mode enable signal SAMP_COT_EN. The control signal SAMP_S... 1B SAMP_T, the minimum on-time generator for the high-side switch. 1_MIN_GEN The minimum on-time SAMP_T of the high-side switch is then generated. 1_MIN And input the positive input of comparator COMP_b; control signal SAMP_S 1B The comparison time T is generated after OneShot module 1. COMP1 and output control signal S 1B_Shot Control signal SAMP_S 1B After passing through delay module 1, a delay time T is generated. delay4 and output control signal S 1B_delay The delay time T delay4 Less than the comparison time T COMP1 Comparison time T COMP1 Less than the cycle time T of ZVS-Buck S When the control signal SAMP_S 1B When the signal is low, the high-side switch of the converter is turned on, and the control signal S... 1B_delay When the signal is low, transistor Q4 is turned off, and control signal S... 1B_Shot When the signal is low, the transmission gate TRANS1 is turned on, and the charging current I is fixed. charge1 For capacitor C T2 and capacitor C T3 Charging; when the control signal SAMP_S 1B When the signal changes from low to high, the high-side switch of the converter is turned off, and the control signal S... 1B_Shot The transition from low to high level generates a comparison time T. COMP1 When the transmission gate TRANS1 is turned off, the high-side switch conduction time SAMP_T1 is generated and input to the inverting input of the comparator COMP_b; control signal S 1B_delay After the delay time T delay4 When the voltage level changes from low to high, transistor Q4 turns on, and capacitor C... T2 Discharge to ground; control signal S 1B_Shot After passing through the inverter chain INV_CHAIN1, a clock signal CLK1 is generated. This signal is then input to the clock pulse control terminal of the comparator COMP_b for comparison. The signal is determined when the high-side switch on-time SAMP_T1 is less than the high-side switch minimum on-time SAMP_T. 1_MINWhen the comparison time T is 10, the comparator COMP_b outputs the mode enable signal SAMP_COT_EN at a high level; conversely, when the comparison time T is 10, the mode enable signal SAMP_COT_EN is at a low level. COMP1 After completion, the transmission gate TRANS1 is turned on, and capacitor C... T3 Discharge to ground; when the control signal SAMP_S 1B When the signal changes from high to low again, the high-side switch conduction time detection circuit SAMP_T1_Detector enters the next cycle; the above is the generation mechanism of the mode enable signal SAMP_COT_EN.

[0060] As shown in Figure 3(f), the clamp switch conduction time detection circuit SAMP_T3_Detector includes: transistor Q5, capacitor C T4 Capacitor C T5 Transmission gate TRANS2, OneShot module 2, Delay module 2, Inverter chain INV_CHAIN2, Clamp switch minimum on-time generator SAMP_T 3_MIN_GEN And the comparator COMP_c.

[0061] The drain of transistor Q5 is connected to the fixed charging current I. charge2 Connected, gate and control signal S 3B_delay Connected, source and ground are connected; capacitor C T4 The upper end is connected to the fixed charging current I charge2 Connected to the ground at the bottom; the input of the transmission gate TRANS2 is connected to the fixed charging current I. charge2 Connected, the control input is the control signal S 3B_Shot The output is the high-side switch conduction time SAMP_T3; capacitor C T5 The upper end is connected to the output of the transmission gate TRANS2, and the lower end is connected to ground; the input of OneShot module 2 is the control signal SAMP_S 3B The output is a control signal S. 3B_Shot The input to the inverter chain INV_CHAIN2 is the control signal S. 3B_Shot The output is the pulse signal CLK2; the input of delay module 2 is the control signal SAMP_S. 3B The output is a control signal S. 3B_delay Minimum On-Time Generator for Clamp Switches (SAMP_T) 3_MIN_GEN The input is the control signal SAMP_S 3B The output is the minimum on-time of the high-side switch, SAMP_T. 3_MIN The inverting input of comparator COMP_c is the high-side switch on-time SAMP_T3, and the non-inverting input is the high-side switch minimum on-time SAMP_T. 1_MINThe clock pulse control terminal takes a pulse signal CLK2 as input and outputs a mode enable signal SAMP_CrCM_EN as output.

[0062] The input to the clamp switch on-time detection circuit SAMP_T3_Detector is a fixed charging current I. charge2 and control signal SAMP_S 3B The output is the mode enable signal SAMP_CrCM_EN. The control signal is SAMP_S. 1B Minimum on-time generator SAMP_T after clamping switch 3_MIN_GEN The minimum on-time SAMP_T of the clamping switch is then generated. 3_MIN And input the positive input of comparator COMP_c; control signal SAMP_S 3B The comparison time T is generated after OneShot module 2. COMP2 and output control signal S 3B_Shot Control signal SAMP_S 3B After delay module 2, a delay time T is generated. delay5 and output control signal S 3B_delay The delay time T delay5 Less than the comparison time T COMP2 Comparison time T COMP2 Less than the cycle time T of ZVS-Buck S When the control signal SAMP_S 3B When the signal is low, the converter clamp switch is turned on, and the control signal S... 3B_delay When the signal is low, transistor Q5 is turned off, and control signal S... 3B_Shot When the signal is low, the transmission gate TRANS2 is turned on, and the charging current I is fixed. charge2 For capacitor C T4 and capacitor C T5 Charging; when the control signal SAMP_S 3B When the signal changes from low to high, the converter clamp switch turns off, and the control signal S... 3B_Shot The transition from low to high level generates a comparison time T. COMP2 When the transmission gate TRANS2 is turned off, the clamp switch conduction time SAMP_T3 is generated and input to the inverting input of the comparator COMP_c; control signal S 3B_delay After the delay time T delay5 When the voltage level changes from low to high, transistor Q5 turns on, and capacitor C... T4 Discharge to ground; control signal S 3B_ShotAfter passing through the inverter chain INV_CHAIN2, a clock signal CLK2 is generated. This signal is then input to the clock pulse control terminal of the comparator COMP_c for comparison. The clamping switch's on-time SAMP_T3 is compared to the minimum on-time SAMP_T3 of the clamping switch. 3_MIN When the comparison time T is 10, the comparator COMP_c outputs the mode enable signal SAMP_CrCM_EN at a high level; conversely, when the comparison time T is 10, the mode enable signal SAMP_CrCM_EN is at a low level. COMP2 After completion, the transmission gate TRANS2 is turned on, and capacitor C... T5 Discharge to ground; when the control signal SAMP_S 3B When the signal changes from high to low again, the clamp switch conduction time detection circuit SAMP_T3_Detector enters the next cycle; the above is the generation mechanism of the mode enable signal SAMP_CrCM_EN.

[0063] As shown in Figure 3(g), the converter switching frequency detection circuit SAMP_f SW The detector includes: transistor Q6 and capacitor C. T6 Capacitor C T7 Transmission gate TRANS3, OneShot module 3, OneShot module 4, Delay module 3, Inverter chain INV_CHAIN3, Converter switch maximum frequency generator SAMP_f sw_MAX_GEN And the comparator COMP_d.

[0064] The drain of transistor Q6 is connected to the fixed charging current I. charge3 Connected, gate and control signal S 1_Shot2 Connected, source and ground are connected; capacitor C T6 The upper end is connected to the fixed charging current I charge3 Connected to the ground at the bottom; the input of the transmission gate TRANS3 is connected to the fixed charging current I. charge3 Connected, the control input is the control signal S 1_Shot1 The output is the converter switching frequency SAMP_f SW Capacitor C T7 The upper end is connected to the output of the transmission gate TRANS3, and the lower end is connected to ground; the input of OneShot module 3 is the control signal SAMP_S1, and the output is the control signal S. 1_Shot1 The input to the inverter chain INV_CHAIN3 is the control signal S. 1_Shot1 The output is the pulse signal CLK3; the input of delay module 3 is the control signal SAMP_S1, and the output is the control signal S. 1_delay The input to OneShot module 4 is the control signal S. 1_delay The output is S 1_Shot2; Converter switching maximum frequency generator SAMP_f sw_MAX_GEN The input is the control signal SAMP_S1, and the output is the maximum switching frequency of the converter, SAMP_f. SW_MAX The inverting input of comparator COMP_d is the converter switching frequency SAMP_f. SW The non-inverting input is the maximum switching frequency of the converter, SAMP_f. SW_MAX The clock pulse control terminal takes a pulse signal CLK3 as input and outputs a mode enable signal SAMP_DCM_EN.

[0065] The converter switching frequency detection circuit SAMP_f SW The input to the _Detector is a fixed charging current I. charge3 The control signal SAMP_S1 outputs a mode enable signal SAMP_DCM_EN. The control signal SAMP_S1 then passes through the clamp switch minimum on-time generator SAMP_f. sw_MAX_GEN The maximum switching frequency SAMP_f of the converter is then generated. SW_MAX The input is then fed into the positive input of the comparator COMP_d; the control signal SAMP_S1 generates the comparison time T after passing through the OneShot module 3. COMP3 and output control signal S 1_Shot1 The control signal SAMP_S1 generates a delay time T after passing through delay module 3. delay6 and output control signal S 1_delay Control signal S 1_delay The discharge time T is generated after passing through OneShot module 4. discharge and output control signal S 1_Shot2 Among them, the delay time T delay6 and discharge time T discharge All are less than the comparison time T COMP3 When the control signal S 1_Shot2 and control signal S 1_Shot1 When both are at low levels, transistor Q6 is off, transmission gate TRANS3 is on, and the fixed charging current I... charge3 For capacitor C T6 and capacitor C T7 Charging; when the control signal SAMP_S1 changes from low to high, the high-side switch of the converter is turned off, and the control signal S... 1_Shot1 The transition from low to high level generates a comparison time T. COMP3 The transmission gate TRANS3 is turned off, generating the converter switching frequency SAMP_f. SW And input the inverting input of comparator COMP_d; control signal S 1_delay After the delay time T delay6The signal changes from low to high level, and the discharge time T is generated after inputting to OneShot module 4. discharge and make the control signal S 1_Shot2 When the voltage level changes from low to high, transistor Q6 turns on, and capacitor C... T6 Discharge to ground; control signal S 1_Shot1 After passing through the inverter chain INV_CHAIN3, a clock signal CLK3 is generated. This signal is then input to the comparator COMP_d clock pulse control terminal for comparison. The converter switching frequency SAMP_f is then used to determine the clock signal. SW Less than the maximum switching frequency of the converter, SAMP_f SW_MAX When the comparison time T is 10, the comparator COMP_d outputs the mode enable signal SAMP_DCM_EN at a high level; conversely, when the comparison time T is 10, the mode enable signal SAMP_DCM_EN is at a low level. COMP3 After completion, transmission gate TRANS3 is turned on, and capacitor C... T7 Discharge to ground; when the discharge time T discharge After completion, control signal S 1_Shot2 When the voltage level changes from high to low, transistor Q6 is turned off, and capacitor C... T6 and capacitor C T7 Entering the next charging cycle, the converter switching frequency detection circuit SAMP_f sw The _Detector enters the next cycle; the above is the generation mechanism of the mode enable signal SAMP_DCM_EN.

[0066] This invention includes a ZVS-Buck converter, an inductor current sampling module, an output voltage sampling module, a compensation network module, a comparator module 1, a comparator module 2, a timer T1_Timer, a dead-time module 1, an RS flip-flop SAMP_RS1, a dead-time module 2, an RS flip-flop SAMP_RS2, a dead-time module 3, an RS flip-flop SAMP_RS3, an OR gate, an AND gate AND2, an inverter INV, a comparator COMP_a, a voltage-controlled current source VCCS, a proportional amplifier K, an AND gate AND1, an RS flip-flop SAMP_RS4, an RS flip-flop SAMP_RS5, a transmission gate TRANS1, an inverter chain INV_CHAIN1, a comparator COMP_b, a OneShot module 1, a delay module 1, and a high-side switch minimum on-time generator SAMP_T. 1_MIN_GEN Transmission gate TRANS2, inverter chain INV_CHAIN2, comparator COMP_c, OneShot module 2, delay module 2, clamp switch minimum on-time generator SAMP_T 3_MIN_GENThe following components are included: TRANS gate 3, INV_CHAIN ​​chain 3, comparator COMP_d, OneShot module 3, delay module 3, OneShot module 4, and converter switch maximum frequency generator SAMP_f. SW_MAX_GEN This is existing technology and will not be elaborated further here.

[0067] This invention proposes a high-speed mode-switching control system for wide-input multimode ZVS-Buck converters, based on current ZVS-Buck converters. The core of the proposed control system lies in achieving rapid mode switching during load changes by detecting conduction time or switching frequency. Current ZVS-Buck converters, on the one hand, can only achieve fixed-frequency control, which easily leads to the switch losing ZVS conditions under light load conditions, switching to a high-loss hard-switching state and resulting in decreased efficiency. On the other hand, traditional multimode control can cause a deterioration in dynamic response speed, resulting in voltage overshoot and undershoot during load changes.

[0068] This invention addresses the high switching losses of traditional hard-switching Buck converters by proposing a novel control method. This method effectively employs CrCM, DCM, and COT modes to improve efficiency under full load conditions and significantly enhances dynamic response performance through mode switching based on conduction time or switching frequency detection. Figure 2 As shown, the solid line represents the efficiency of the proposed control method under different input voltages and loads, while the dashed line represents the efficiency of the traditional ZVS-Buck converter under different input voltages and loads. The proposed high-speed mode switching control system for wide-input multimode ZVS-Buck converters can significantly improve efficiency under different input voltages and loads.

[0069] While the present invention has been described above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter, characterized in that, include: The ZVS-Buck converter comprises a switch driver circuit and a control circuit. The switch driver circuit is connected to the ZVS-Buck converter, and the control circuit is connected to the switch driver circuit. The ZVS-Buck converter is also connected to the control circuit. The control circuit includes a mode control circuit and a logic control circuit. The mode control circuit generates a mode control signal by detecting the switch on-time and switching frequency of the ZVS-Buck converter. The logic control circuit generates a switch control signal by detecting the mode control signal and the switch state of the ZVS-Buck converter. The switch driver circuit generates a switch drive signal using the switch control signal. The ZVS-Buck converter uses the switch drive signal to control the switch to turn on or off, realizing high-speed mode switching of the ZVS-Buck converter under load changes.

2. The high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter according to claim 1, characterized in that, The driving circuit includes: a clamping switch driving circuit, a low-side switch driving circuit, and a high-side switch driving circuit; the first input terminal of the ZVS-Buck converter is connected to the input voltage ZVS_V. IN The second input terminal is connected to the clamping switch drive signal S. 33 The third input terminal is connected to the low-side switch drive signal S. 22 The fourth input terminal is connected to the high-side switch drive signal S. 11 The first output terminal of the ZVS-Buck converter is connected to the output voltage ZVS_V. OUT The second output terminal is connected to the inductor current I. L .

3. The high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter according to claim 1, characterized in that, The logic control circuit includes an inductor current sampling module, an output voltage sampling module, a compensation network module, a comparator module 1, a timer T1_Timer, a dead time module 1, a comparator module 2, an RS flip-flop RS1, a dead time module 2, an RS flip-flop RS2, a dead time module 3, and a timer T1_Timer. S The circuit includes a timer and an RS flip-flop RS3; the mode control circuit includes a high-side switch conduction time detection circuit T1_Detector and a converter switching frequency detection circuit f. SW _Detector, clamp switch conduction time detection circuit T3_Detector, RS flip-flop RS4, RS flip-flop RS5 and logic AND gate AND1; The input to the inductor current sampling module is the inductor current I. L The output is the inductor current sampling signal I. SMP The input to the output voltage sampling module is the output voltage ZVS_V. OUT The output is the output voltage feedback signal V. FB The input to the compensation network module is the output voltage feedback signal V. FB and reference voltage V ref1 The output is a control signal V. err The input to comparison module 1 is the inductor current sampling signal I. SMP With control signals The output is a control signal S. 1_OFF The inputs to timer T1_Timer are control signal S1 and control signal S. 1_OFF And the mode control signal COT, the output of which is the reset signal RESET1; timer T S The inputs to the _Timer are the modal control signal COT, modal control signal DCM, modal control signal CrCM, and control signal V. err Reference voltage V ref2 Reference voltage V ref3 Control signal S 1B and control signal S 2B The output is a control signal T. S _SET; The input to dead time module 1 is the control signal T. S The RS flip-flop RS1 outputs the set signal SET1; the set terminal of RS1 is connected to the set signal SET1, and the reset terminal is connected to the reset signal RESET1; the output of RS1 is the control signal S1 and S... 1B The input to the high-side switch drive circuit is the control signal S1, and the output is the high-side switch drive signal S. 11； The input to dead time module 2 is the control signal S. 1B The output is the set signal SET2; the output of the comparator module 2 is the inductor current sampling signal I. SMP With reference voltage V ref4 The output is a reset signal RESET2; the set terminal of RS2 flip-flop is connected to the set signal SET2, and the reset terminal is connected to the reset signal RESET2; the output of RS2 flip-flop is the control signal S2 and S... 2B The input to the low-side switch drive circuit is the control signal S2, and the output is the low-side switch drive signal S. 22； The input to dead time module 3 is the control signal S. 2B The output is the set signal SET3; the reset terminal of the RS flip-flop RS3 is connected to the control signal T. S _SET, the set terminal is connected to the set signal SET3; the output of RS flip-flop RS3 is the control signal S3 and S 3B The input to the clamp switch drive circuit is the control signal S3, and the output is the clamp switch drive signal S. 33 ; The input to the high-side switch conduction time detection circuit T1_Detector is the control signal S. 1B With fixed charging current I charge1 The output is the mode enable signal COT_EN; the converter switching frequency detection circuit f SW The input to the _Detector is the control signal S1 and the fixed charging current I. charge3 The output is the mode enable signal DCM_EN; the input of the clamp switch conduction time detection circuit T3_Detector is the control signal S. 3B and fixed charging current I charge2 The output is the modal enable signal CrCM_EN; the set terminal of RS4 flip-flop is connected to the modal enable signal COT_EN, and the reset terminal is connected to the modal enable signal DCM_EN; the Q terminal of RS4 flip-flop is connected to the modal control signal COT; the set terminal of RS5 flip-flop is connected to the modal enable signal CrCM_EN, and the reset terminal is connected to the modal enable signal DCM_EN; the Q terminal of RS5 flip-flop is connected to the modal control signal CrCM; the outputs of the QN terminals of RS4 and RS5 flip-flops are input to the AND gate; the output of the AND gate AND1 is the modal control signal DCM.

4. The high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter according to claim 3, characterized in that, Timer T S The timer includes: a proportional amplifier K, transistor Q2, transistor Q3, a voltage-controlled current source VCCS, and a capacitor C. T1 Transistor Q1, comparator COMP_a, AND gate AND2, and OR gate OR; The inputs to the proportional amplifier K are the amplification factor K and the control signal V. err The output is connected to the drain of transistor Q2; the gate input of transistor Q2 is the mode control signal SAMP_COT; the source of transistor Q2 is connected to the input of the voltage control current source VCCS; the drain input of transistor Q3 is the reference voltage SAMP_V. ref2 The gate input of transistor Q3 is the mode control signal SAMP_DCM; the source of transistor Q3 is connected to the input of the voltage-controlled current source VCCS; the output of the voltage-controlled current source VCCS is connected to capacitor C. T1 The upper end of the capacitor is connected to the drain of transistor Q1 and the non-inverting input of comparator COMP_a; capacitor C T1 The lower end is connected to ground; control signal S 1B The voltage is connected to the gate of transistor Q1 after passing through inverter INV; the source of transistor Q1 is connected to ground; the inverting input of comparator COMP_a is connected to the reference voltage SAMP_V. ref3 The input to the AND gate AND2 is the control signal SAMP_S. 2B The modal control signal SAMP_CrCM; the output of comparator COMP_a and the output of AND gate AND2 are input to the OR gate; the output of the OR gate is the control signal SAMP_T. S _SET.

5. The high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter according to claim 3, characterized in that, The modal control circuit includes: a high-side switch on-time detection circuit SAMP_T1_Detector, a clamp switch on-time detection circuit SAMP_T3_Detector, and a converter switching frequency detection circuit SAMP_f. SW _Detector, RS flip-flop SAMP_RS4, RS flip-flop SAMP_RS5, and logic AND gate SAMP_AND 1； The input to the high-side switch on-time detection circuit SAMP_T1_Detector is the control signal SAMP_S. 1B With fixed charging current SAMP_I charge1 The output is the mode enable signal SAMP_COT_EN; the converter switching frequency detection circuit SAMP_f SW The input to _Detector is the control signals SAMP_S1 and SAMP_I. charge3 The output is the mode enable signal SAMP_DCM_EN; the input of the clamp switch on-time detection circuit SAMP_T3_Detector is the control signal SAMP_S. 3B and SAMP_I charge2 The output is the mode enable signal SAMP_CrCM_EN; the set terminal of RS flip-flop SAMP_RS4 is connected to the mode enable signal SAMP_COT_EN, and the reset terminal is connected to the mode enable signal SAMP_DCM_EN; the Q terminal of RS flip-flop SAMP_RS4 is connected to the mode control signal SAMP_COT; the set terminal of RS flip-flop SAMP_RS5 is connected to the mode enable signal SAMP_CrCM_EN, and the reset terminal is connected to the mode enable signal SAMP_DCM_EN; the Q terminal of RS flip-flop SAMP_RS5 is connected to the mode control signal SAMP_CrCM; the output of the SAMP_QN terminal of RS flip-flop SAMP_RS4 and the output of the QN terminal of RS flip-flop SAMP_RS5 are input to the logic AND gate; the output of the logic AND gate SAMP_AND1 is the mode control signal SAMP_DCM.

6. The high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter according to claim 3, characterized in that, The high-side switch conduction time detection circuit SAMP_T1_Detector includes transistor Q4 and capacitor C. T2 Capacitor C T3 Transmission gate TRANS1, OneShot module 1, Delay module 1, Inverter chain INV_CHAIN1, High-side switch minimum on-time generator SAMP_T 1_MIN_GEN And the comparator COMP_b; The drain of transistor Q4 is connected to the fixed charging current I. charge1 Connected, gate and control signal S 1B_delay Connected, source and ground are connected; capacitor C T2 The upper end is connected to the fixed charging current I charge1 Connected to the ground at the bottom; the input of the transmission gate TRANS1 is connected to the fixed charging current I. charge1 Connected, the control input is the control signal S 1B_Shot The output is the high-side switch conduction time SAMP_T1; capacitor C T3 The upper end is connected to the output of the transmission gate TRANS1, and the lower end is connected to ground; the input of OneShot module 1 is the control signal SAMP_S 1B The output is a control signal S. 1B_Shot The input to the inverter chain INV_CHAIN1 is the control signal S. 1B_Shot The output is the pulse signal CLK1; the input of delay module 1 is the control signal SAMP_S. 1B The output is a control signal S. 1B_delay High-side switch minimum on-time generator SAMP_T 1_MIN_GEN The input is the control signal SAMP_S 1B The output is the minimum on-time of the high-side switch, SAMP_T. 1_MIN The inverting input of comparator COMP_b is the high-side switch on-time SAMP_T1, and the non-inverting input is the high-side switch minimum on-time SAMP_T. 1_MIN The clock pulse control terminal takes a pulse signal CLK1 as input and outputs a mode enable signal SAMP_COT_EN as output.

7. The high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter according to claim 3, characterized in that, The clamp switch on-time detection circuit SAMP_T3_Detector includes transistor Q5 and capacitor C. T4 Capacitor C T5 Transmission gate TRANS2, OneShot module 2, Delay module 2, Inverter chain INV_CHAIN2, Clamp switch minimum on-time generator SAMP_T 3_MIN_GEN And the comparator COMP_c; The drain of transistor Q5 is connected to the fixed charging current I. charge2 Connected, gate and control signal S 3B_delay Connected, source and ground are connected; capacitor C T4 The upper end is connected to the fixed charging current I charge2 Connected to the ground at the bottom; the input of the transmission gate TRANS2 is connected to the fixed charging current I. charge2 Connected, the control input is the control signal S 3B_Shot The output is the high-side switch conduction time SAMP_T3; capacitor C T5 The upper end is connected to the output of the transmission gate TRANS2, and the lower end is connected to ground; the input of OneShot module 2 is the control signal SAMP_S 3B The output is a control signal S. 3B_Shot The input to the inverter chain INV_CHAIN2 is the control signal S. 3B_Shot The output is the pulse signal CLK2; the input of delay module 2 is the control signal SAMP_S. 3B The output is a control signal S. 3B_delay Minimum On-Time Generator for Clamp Switches (SAMP_T) 3_MIN_GEN The input is the control signal SAMP_S 3B The output is the minimum on-time of the high-side switch, SAMP_T. 3_MIN The inverting input of comparator COMP_c is the high-side switch on-time SAMP_T3, and the non-inverting input is the high-side switch minimum on-time SAMP_T. 1_MIN The clock pulse control terminal takes a pulse signal CLK2 as input and outputs a mode enable signal SAMP_CrCM_EN as output.

8. The high-speed mode switching control system for a wide-input multimodal ZVS-Buck converter according to claim 3, characterized in that, Converter switching frequency detection circuit SAMP_f SW The detector includes transistor Q6 and capacitor C. T6 Capacitor C T7 Transmission gate TRANS3, OneShot module 3, OneShot module 4, Delay module 3, Inverter chain INV_CHAIN3, Converter switch maximum frequency generator SAMP_f sw_MAX_GEN And the comparator COMP_d; The drain of transistor Q6 is connected to the fixed charging current I. charge3 Connected, gate and control signal S 1_Shot2 Connected, source and ground are connected; capacitor C T6 The upper end is connected to the fixed charging current I charge3 Connected to the ground at the bottom; the input of the transmission gate TRANS3 is connected to the fixed charging current I. charge3 Connected, the control input is the control signal S 1_Shot1 The output is the converter switching frequency SAMP_f SW Capacitor C T7 The upper end is connected to the output of the transmission gate TRANS3, and the lower end is connected to ground; the input of OneShot module 3 is the control signal SAMP_S1, and the output is the control signal S. 1_Shot1 The input to the inverter chain INV_CHAIN3 is the control signal S. 1_Shot1 The output is the pulse signal CLK3; the input of delay module 3 is the control signal SAMP_S1, and the output is the control signal S. 1_delay The input to OneShot module 4 is the control signal S. 1_delay The output is S 1_Shot2 ; Converter switching maximum frequency generator SAMP_f sw_MAX_GEN The input is the control signal SAMP_S1, and the output is the maximum switching frequency of the converter, SAMP_f. SW_MAX The inverting input of comparator COMP_d is the converter switching frequency SAMP_f. SW The non-inverting input is the maximum switching frequency of the converter, SAMP_f. SW_MAX The clock pulse control terminal takes a pulse signal CLK3 as input and outputs a mode enable signal SAMP_DCM_EN.

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