ANPC type three-level power module and electronic device

Abstract

This application discloses an ANPC-type three-level power module and electronic device, relating to the field of power module technology. The ANPC-type three-level power module includes: a heat sink; a first AMB board, a second AMB board, and a third AMB board located on the heat sink; a patterned textured surface area located on the upper surface of each AMB board; multiple silicon carbide MOSFET chips fixed to and electrically connected to the corresponding patterned textured surface areas; busbar assemblies and signal pin assemblies arranged on the AMB boards and electrically connected to the patterned textured surface areas; wherein the first AMB board, the second AMB board, and the third AMB board are electrically interconnected via connecting lines; the silicon carbide MOSFET chips, the busbar assembly, and the patterned textured surface areas together constitute an ANPC-type three-level topology. The solution of this application has advantages such as compact structure, high power density, low parasitic inductance, excellent current sharing performance, and strong heat dissipation capability.

Description

Technical Field

[0001] This application relates to the field of power module technology, and more specifically, to an ANPC type three-level power module and electronic device. Background Technology

[0002] With the transformation and upgrading of the energy structure and the rapid development of power electronics technology, high-efficiency, high-power-density power conversion devices are increasingly widely used in new energy power generation, electric vehicles, rail transportation, industrial frequency conversion, and other fields. In these application scenarios, the power module, as the core component for realizing the energy conversion between DC and AC, directly determines the efficiency, size, reliability, and cost of the entire system.

[0003] Traditional two-level power converters, due to their large output voltage fluctuations and high harmonic content, typically require bulky filters to improve power quality, thus limiting the improvement of the overall system power density. To address this, multi-level topologies have emerged. Among them, the three-level topology has become the mainstream choice for medium- and high-voltage, high-power applications because it can reduce the voltage stress on switching devices to half that of the DC bus voltage while significantly improving the output voltage waveform quality.

[0004] Among numerous three-level topologies, the Active Neutral Oit Clamed (ANPC) topology has attracted widespread attention due to its combination of high efficiency, good control flexibility, and effective suppression of neutral point potential fluctuations. The ANPC topology, by introducing a clamping bridge arm composed of a pair of auxiliary switches, can flexibly switch between different operating modes to achieve three-level output, effectively reducing voltage stress and switching losses on the main switch.

[0005] However, as the requirements for system efficiency and power density continue to increase, traditional silicon-based IGBT-based power modules have gradually revealed their limitations: due to material properties, silicon devices have low operating frequencies and large conduction and switching losses, making it difficult for the system to be further miniaturized and made more efficient.

[0006] In recent years, the rise of wide bandgap semiconductor materials such as silicon carbide (SiC) has made it possible to overcome the aforementioned bottlenecks. SiC MOSFETs have higher breakdown electric field strength, higher thermal conductivity, and faster switching speed, supporting higher frequency, higher temperature, and higher efficiency operating states, making them an ideal choice for realizing next-generation high power density power modules.

[0007] However, while the high-frequency characteristics of silicon carbide devices improve performance, they also bring new challenges: on the one hand, the switching process is more sensitive to circuit parasitic parameters, resulting in greater electrical stress on the devices; on the other hand, the asymmetry of the commutation circuit in the three-level topology will cause an imbalance of electrothermal stress between the switching transistors. Summary of the Invention

[0008] The purpose of this application is to provide an ANPC-type three-level power module and electronic device to solve the problems of large electrical stress on the power module and the easy occurrence of electrothermal stress imbalance between the switching transistors in the prior art.

[0009] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: On one hand, embodiments of this application provide an ANPC-type three-level power module, including: Heat sink; The heat sink has a first AMB plate, a second AMB plate, and a third AMB plate. The first AMB plate and the third AMB plate are symmetrically arranged in the upper half of the heat sink, and the second AMB plate is arranged in the middle area of ​​the lower half of the heat sink. The first AMB plate and the third AMB plate are arranged vertically, and the second AMB plate is arranged horizontally. The patterned textured surface area located on the upper surface of each of the AMB boards is composed of a conductive metal layer and is used to realize electrical connections in the circuit topology. Multiple silicon carbide MOSFET chips are fixed on the corresponding patterned surface area and electrically connected. Busbar assembly, the busbar assembly being disposed on the AMB plate and electrically connected to the patterned surface area; A signal pin assembly, the signal pin assembly comprising pin components respectively connected to the gate, source and drain of each of the silicon carbide MOSFET chips; The first AMB board, the second AMB board, and the third AMB board are electrically interconnected through connecting wires. The silicon carbide MOSFET chip, together with the busbar assembly and the patterned textured surface area, constitutes an ANPC-type three-level topology.

[0010] On the other hand, embodiments of this application also provide an electronic device, which includes the above-described ANPC type three-level power module.

[0011] Compared with the prior art, this application has the following advantages: This application provides an ANPC-type three-level power module and electronic device. The ANPC-type three-level power module includes: a heat sink; a first AMB board, a second AMB board, and a third AMB board located on the heat sink, with the first and third AMB boards symmetrically arranged in the upper half of the heat sink, and the second AMB board located in the middle region of the lower half of the heat sink; the first and third AMB boards are vertically arranged, and the second AMB board is horizontally arranged; a patterned textured surface area located on the upper surface of each AMB board, the patterned textured surface area being composed of a conductive metal layer and used to realize the electrical circuit topology. Connections; multiple silicon carbide MOSFET chips, which are fixed on corresponding patterned surface areas and electrically connected; busbar assembly, which is arranged on the AMB board and electrically connected to the patterned surface areas; signal pin assembly, which includes pin components connected to the gate, source, and drain of each silicon carbide MOSFET chip respectively; wherein, the first AMB board, the second AMB board, and the third AMB board are electrically interconnected through connecting lines; the silicon carbide MOSFET chips, the busbar assembly, and the patterned surface areas together constitute an ANPC-type three-level topology.

[0012] In the ANPC-type three-level power module provided in this application, a finely patterned conductive metal layer is constructed on the surface of the AMB board as a textured surface area, which is directly used for chip interconnection and main circuit routing. Compared with traditional bonding wires or long leads, this significantly shortens the high-frequency current path. Furthermore, the first, second, and third AMB boards each carry different functional units and are connected to each other via connecting lines. This partitioned centralized wiring strategy avoids the accumulation of distributed inductance caused by long-distance traces, while also facilitating symmetrical design and controlling differential-mode and common-mode noise. Simultaneously, the symmetrical arrangement of the first and third AMB boards achieves current sharing, thereby achieving overall compact structure, high power density, low parasitic inductance, excellent current sharing performance, and strong heat dissipation.

[0013] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1This is a schematic diagram of the overall structure of the ANPC-type three-level power module provided in the embodiments of this application.

[0016] Figure 2 This is a top view of the ANPC-type three-level power module provided in an embodiment of this application.

[0017] Figure 3 This is a schematic diagram of the structure of the heat sink provided in an embodiment of this application.

[0018] Figure 4 This is a schematic diagram of the structure of the DC positive busbar provided in an embodiment of this application.

[0019] Figure 5 This is a schematic diagram of the structure of the midpoint potential clamping busbar provided in an embodiment of this application.

[0020] Figure 6 A schematic diagram of the stacked structure of the DC positive busbar and the midpoint potential clamping busbar is provided for the embodiments of this application.

[0021] Figure 7 The left view of the ANPC type three-level power module provided in the embodiment of this application.

[0022] Figure 8 This is a schematic diagram of the circuit topology of the ANPC type three-level power module provided in the embodiments of this application.

[0023] Figure 9 This is a schematic diagram of the layout of a silicon carbide chip provided in an embodiment of this application.

[0024] Figure 10 This is a schematic diagram of the textured area on the AMB board provided in an embodiment of this application.

[0025] Figure 11 Provided for the embodiments of this application Figure 10 A magnified view of a portion of point A in the middle.

[0026] Figure 12 Provided for the embodiments of this application Figure 10 A magnified view of a portion of point C in the middle.

[0027] Figure 13 Provided for the embodiments of this application Figure 10 A magnified view of a portion of point B in the middle.

[0028] In the picture: 10-First AMB board; 20-Second AMB board; 30-Third AMB board; 40-Heat sink; 41-Pin fin structure; 50-DC positive busbar; 60-DC negative busbar; 70-First midpoint potential clamping busbar; 80-Second midpoint potential clamping busbar; 90-Binding wire; 100-AC busbar; 110-First connecting area; 111-Rough area of ​​the right terminal of the DC positive busbar; 112-Rough area of ​​the right half of the first silicon carbide chip; 113-Rough area of ​​the drain of the first silicon carbide chip; 120-Second connecting area; 121-Rough area of ​​the left terminal of the DC positive busbar; 122-Rough area of ​​the left half of the first silicon carbide chip; 130-Third connecting area; 131-First bonding wire The text describes the textured areas of various silicon carbide (SiC) chips, including: 132 - Source area of ​​the right half of the first SiC chip; 133 - Source area of ​​the left half of the first SiC chip; 134 - Right solder joint of the center island bonding line; 135 - Left solder joint of the center island bonding line; 136 - Right solder joint of the fifth SiC chip; 137 - Left solder joint of the fifth SiC chip; 138 - Drain area of ​​the fifth SiC chip; 140 - Fourth connecting region; 141 - Textured area of ​​the first midpoint potential clamping busbar; 142 - Source area of ​​the right half of the fifth SiC chip; 143 - Source area of ​​the left half of the fifth SiC chip; 151 - Textured area of ​​the source of the first SiC chip. 152 - Textured area of ​​the gate of the first silicon carbide chip; 153 - Textured area of ​​the first intermediate island; 154 - Textured area of ​​the source of the fifth silicon carbide chip; 155 - Textured area of ​​the gate of the fifth silicon carbide chip; 310 - Fifth connecting region; 311 - Textured area of ​​the right terminal of the second midpoint potential clamping busbar; 312 - Textured area of ​​the right half of the sixth silicon carbide chip; 313 - Textured area of ​​the drain of the sixth silicon carbide chip; 320 - Sixth connecting region; 321 - Textured area of ​​the left terminal of the second midpoint potential clamping busbar; 322 - Textured area of ​​the left half of the sixth silicon carbide chip; 330 - Seventh connecting region; 331 - Textured area of ​​the solder pads on the second bonding line; 332 - Textured area of ​​the right half of the sixth silicon carbide chip. 333 - Source region of the sixth silicon carbide chip (left half); 334 - Source region of the right solder pad of the center island bonding line; 335 - Source region of the left solder pad of the center island bonding line; 336 - Source region of the fourth silicon carbide chip (right half); 337 - Source region of the fourth silicon carbide chip (left half); 338 - Source region of the fourth silicon carbide chip (drain); 340 - Eighth connecting region; 341 - Source region of the DC negative busbar; 342 - Source region of the fourth silicon carbide chip (right half); 343 - Source region of the fourth silicon carbide chip (left half); 351 - Source region of the sixth silicon carbide chip; 352 - Source region of the sixth silicon carbide chip (gate).353 - Textured area of ​​the second intermediate island; 354 ​​- Textured area of ​​the source electrode of the fourth silicon carbide chip; 355 - Textured area of ​​the gate electrode of the fourth silicon carbide chip; 210 - Ninth connecting region; 211 - Textured area of ​​the solder pads under the first bonding line; 212 - Textured area of ​​the right half of the second silicon carbide chip; 213 - Textured area of ​​the left half of the second silicon carbide chip; 214 - Textured area of ​​the drain electrode of the second silicon carbide chip; 220 - Tenth connecting region; 221 - Textured area of ​​the source electrode of the right half of the second silicon carbide chip; 222 - Textured area of ​​the source electrode of the left half of the second silicon carbide chip; 223 - Textured area of ​​the AC busbar; 224 - Textured area of ​​the right half of the third silicon carbide chip; 225 - Textured area of ​​the left half of the third silicon carbide chip; 226 - Third silicon carbide chip 230 - Drain ripple region; 231 - Ribbed region of the solder pad under the second bonding line; 232 - Ribbed region of the right half of the source electrode of the third silicon carbide chip; 233 - Ribbed region of the left half of the source electrode of the third silicon carbide chip; 251 - First rippled region of the gate electrode of the second silicon carbide chip; 252 - First rippled region of the source electrode of the second silicon carbide chip; 253 - First rippled region of the source electrode of the third silicon carbide chip; 254 - First rippled region of the gate electrode of the third silicon carbide chip; 255 - Second rippled region of the gate electrode of the second silicon carbide chip; 256 - Second rippled region of the source electrode of the second silicon carbide chip; 257 - Second rippled region of the gate electrode of the third silicon carbide chip; 258 - Second rippled region of the source electrode of the third silicon carbide chip; 259 - Ribbed region of the marker point; 261 - The textured area of ​​the top electrode of the NTC; the textured area of ​​the bottom electrode of the 262-NTC; Q1 - first silicon carbide chip; Q2 - second silicon carbide chip; Q3 - third silicon carbide chip; Q4 - fourth silicon carbide chip; Q5 - fifth silicon carbide chip; Q6 - sixth silicon carbide chip. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0031] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0032] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0033] In the description of this application, it should be noted that the terms "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0034] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0035] As described in the background section, the high-frequency characteristics of SiC devices also bring new technical challenges. On the one hand, the rapid rate of change of current (di / dt) makes the parasitic inductance in the circuit particularly sensitive, easily causing severe voltage overshoot and oscillation, threatening device safety. On the other hand, the ANPC three-level topology itself has multiple commutation loops. If the arrangement design is not reasonable, it will lead to uneven current distribution among the parallel chips (i.e., poor current sharing), resulting in local overheating and decreased reliability.

[0036] Furthermore, in the context of high power density integration, the concentrated arrangement of multiple heat-generating SiC chips places higher demands on the heat dissipation system. Traditional planar substrates and simple air-cooling structures are no longer sufficient to meet heat dissipation requirements, necessitating the combination of efficient heat dissipation structures and low thermal resistance packaging processes to achieve rapid heat removal.

[0037] In the existing technology, although some three-level power modules have adopted SiC devices and optimized some electrical connection methods, there are still shortcomings in busbar structure, AMB (Active Metal Brazing) ceramic substrate wiring, chip layout symmetry and overall thermal-electrical synergistic design, which have not fully released the potential of SiC devices. In particular, there is still much room for improvement in reducing parasitic inductance of the main circuit, improving the current sharing of multiple chips in parallel and enhancing thermal management capabilities.

[0038] Therefore, this application provides an ANPC-type three-level power module to achieve compact structure, low parasitic parameters, excellent current sharing performance, and strong heat dissipation. As one implementation method, please refer to... Figure 1 and Figure 2 The ANPC type three-level power module includes: A heat sink 40; a first AMB plate 10, a second AMB plate 20, and a third AMB plate 30 are located on the heat sink 40. The first AMB plate 10 and the third AMB plate 30 are symmetrically arranged in the upper half of the heat sink 40, and the second AMB plate 20 is located in the middle area of ​​the lower half of the heat sink 40. The first AMB plate 10 and the third AMB plate 30 are vertically arranged, and the second AMB plate 20 is horizontally arranged. For example, the first AMB plate 10 is arranged on the right side of the upper half of the heat sink 40, and the third AMB plate 30 is arranged on the left side of the upper half of the heat sink 40. The third AMB plate 30 is located in the middle position of the lower half of the heat sink 40. The first AMB plate 10, the second AMB plate 20, and the third AMB plate 30 have the same size. The circuit includes a patterned surface area on the upper surface of each AMB board, which is composed of a conductive metal layer and is used to realize electrical connections in the circuit topology; multiple silicon carbide MOSFET chips, which are fixed on the corresponding patterned surface areas and electrically connected; a busbar assembly, which is arranged on the AMB board and electrically connected to the patterned surface areas; and a signal pin assembly, which includes pin components connected to the gate, source, and drain of each silicon carbide MOSFET chip respectively; wherein, the first AMB board 10, the second AMB board 20, and the third AMB board 30 are electrically interconnected through connecting lines; for example, the patterned surface area of ​​the first AMB board 10 and the patterned surface area of ​​the second AMB board 20 are electrically connected through a bonding line 90 or a copper strip, and the patterned surface area of ​​the second AMB board 20 and the patterned surface area of ​​the third AMB board 30 are electrically connected through a bonding line 90 or a copper strip; the silicon carbide MOSFET chips, the busbar assembly, and the patterned surface areas together constitute an ANPC-type three-level topology.

[0039] Understandably, this application employs silicon carbide semiconductor chips and advanced interconnect technology, enabling the power module to adapt to higher operating voltages, switching frequencies, and ambient temperatures, significantly improving overall performance. Simultaneously, the improved output waveform quality effectively reduces the size of the passive filter, laying the foundation for achieving high power density.

[0040] Furthermore, in one implementation, please refer to [link / reference]. Figure 3 The heat sink 40 can have a pin fin structure 41, which is arranged in an array to increase heat dissipation, reduce thermal resistance, and improve the overall heat dissipation capacity of the power module.

[0041] Furthermore, this embodiment achieves the technical effects of compact structure, low parasitic parameters, excellent current sharing performance, and strong heat dissipation capacity by partitioning, layering, connecting, and symmetrically designing the key electrical and heat dissipation components of the power module.

[0042] In this arrangement, the first AMB board 10 and the third AMB board 30 are symmetrically positioned on the upper half of the heat sink 40, while the second AMB board 20 is located in the middle area of ​​the lower half of the heat sink 40. This arrangement creates a vertically divided, centrally concentrated spatial pattern for the entire module, which facilitates the rational allocation of heat-generating units and prevents heat accumulation. Combined with the heat sink 40 with its pin-fin structure 41, this greatly enhances the module's heat dissipation capacity and provides a clear spatial path for subsequent wiring and connections.

[0043] Specifically, the first AMB board 10 and the third AMB board 30 are vertically arranged, with their long sides extending vertically; while the second AMB board 20 is horizontally arranged, with its long side extending horizontally. This differentiated orientation can accommodate the wiring requirements of different functional units: the two vertically placed AMB boards at the top are more suitable for arranging components that require vertical wiring, such as the upper tubes of the main bridge arm and clamping switches, while the horizontally arranged AMB boards at the bottom are more conducive to the lateral expansion of AC output terminals and related structures at the midpoint, thereby improving space utilization and making the overall structure more compact.

[0044] In this process, each AMB board has a patterned textured surface area on its upper surface. These areas are composed of conductive metal layers, such as pre-etched copper lines, used to achieve electrical connections between internal circuits. By setting the textured surface area, complex jumpers can be completed without relying on a large number of bonding wires. Instead, the required connection paths can be formed directly on the substrate, significantly reducing the use of additional wiring. This not only saves space but also reduces parasitic inductance caused by excessively long leads.

[0045] Furthermore, multiple silicon carbide MOSFET chips are fixed on corresponding patterned surface areas and electrically connected through methods such as welding or sintering. Because silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) have high-frequency, high-voltage, and high-temperature operating capabilities, they are particularly suitable for high-efficiency power conversion applications, but they are also more sensitive to parasitic parameters in the circuit. Therefore, this embodiment precisely arranges each silicon carbide MOSFET chip on the textured surface of its respective AMB board, making its current input and output paths as short and symmetrical as possible, thereby effectively controlling voltage oscillations and electromagnetic interference during the switching process.

[0046] In one implementation, the busbar assembly includes a DC positive busbar, a DC negative busbar 60, a first midpoint potential clamping busbar 70, a second midpoint potential clamping busbar 80, and an AC busbar 100. These busbars are all arranged on the AMB board and electrically connected to the patterned textured surface area. Please refer to [link / reference]. Figure 4 and Figure 5 The DC positive busbar and the second midpoint potential clamping busbar 80 are bent metal busbars with the same structure, and the DC negative busbar 60 and the first midpoint potential clamping busbar 70 are bent metal busbars with the same structure. The DC positive busbar is arranged on both sides above the textured surface area of ​​the first AMB plate 10, the first midpoint potential clamping busbar 70 is arranged in the middle above the textured surface area of ​​the first AMB plate 10, the DC negative busbar 60 is arranged in the middle above the textured surface area of ​​the third AMB plate 30, the second midpoint potential clamping busbar 80 is arranged on both sides above the textured surface area of ​​the third AMB plate 30, and the AC busbar 100 is arranged in the middle below the textured surface area of ​​the second AMB plate 20.

[0047] The function of the busbar is to carry high current and introduce / exit it from external power supply or load into / out of the module. Because asymmetrical high-current paths or excessively large loops can generate significant parasitic inductance, affecting device safety, please refer to [the relevant documentation]. Figure 6 and Figure 7 In this application, the DC positive busbar and the first midpoint potential clamping busbar 70 are arranged in a stacked configuration, and the DC positive busbar and the first midpoint potential clamping busbar 70 are not in contact; the DC negative busbar 60 and the second midpoint potential clamping busbar 80 are also arranged in a stacked configuration, and the DC negative busbar 60 and the second midpoint potential clamping busbar 80 are not in contact. By designing the busbars as a stacked structure and a bent structure, for example, the DC positive busbar and the first midpoint potential clamping busbar 70 form one stack, and the DC negative busbar 60 and the second midpoint potential clamping busbar 80 form another stack, the forward and reverse current paths can be tightly attached together, canceling each other's magnetic fields and significantly reducing the overall circuit inductance.

[0048] In addition, signal pin assemblies are used to transmit control signals, including pin components connected to the gate, source, and drain of each silicon carbide MOSFET chip. Although these pin components do not carry the main power current, their layout directly affects the consistency of the drive signals. If the gate trace of a chip is too long or its impedance is too high, it may cause a lag in its turn-on and turn-off timing, leading to uneven current distribution among parallel chips. Therefore, in this embodiment, each group of pin components is arranged as close as possible to the corresponding chip, and the arrangement order is uniform to ensure that the drive conditions of all parallel branches are as consistent as possible.

[0049] Specifically, the signal pin assembly includes pin components that are respectively connected to the gate, source, and drain of each silicon carbide MOSFET chip. The silicon carbide MOSFET chip provided in this application includes a total of 6 groups of multi-parallel connected chips, namely the first silicon carbide chip Q1, the second silicon carbide chip Q2, the third silicon carbide chip Q3, the fourth silicon carbide chip Q4, the fifth silicon carbide chip Q5, and the sixth silicon carbide chip Q6. Each chip has corresponding signal connection requirements. For this purpose, a first signal pin assembly, a second signal pin assembly, a third signal pin assembly, a fourth signal pin assembly, a fifth signal pin assembly, and a sixth signal pin assembly are provided, each dedicated to the silicon carbide MOSFET chip corresponding to its name.

[0050] Each pin assembly contains three specific signal pins: a drain (D) pin, a gate (G) pin, and a source (S) pin. The drain (D) pin connects to the drain terminal of the corresponding silicon carbide MOSFET chip and is primarily used to detect the voltage state of the branch containing that chip. The gate (G) pin connects to the gate terminal of the chip and receives turn-on and turn-off commands from the drive circuit. The source (S) pin connects to the source terminal of the chip, serving as a reference point or return path for the drive loop. This one-to-one, full-function design allows each silicon carbide MOSFET chip to have an independent control and detection channel, avoiding interference or voltage drop accumulation problems caused by shared pins.

[0051] In addition, a negative temperature coefficient thermistor (NTC) can be integrated within the power module for real-time monitoring of critical temperature zones within the module. To achieve electrical connection to this NTC, a dedicated NTC signal pin assembly is provided, consisting of two pins: T1 and T2. The T1 pin is connected to the top electrode of the NTC, and the T2 pin is connected to the bottom electrode, forming a complete bidirectional measurement path. By applying a small current to these two pins through external circuitry and reading the voltage change across them, the current temperature value can be calculated, thereby determining whether the module is within its safe operating range.

[0052] It is important to note that although these signal pins do not carry large currents, their placement and connection paths can still affect the electromagnetic compatibility and signal integrity of the entire module. Therefore, in actual installation, these signal pins are usually placed in easily accessible locations around the perimeter of the AMB board, and the trace length from the pin to the chip is minimized to reduce the risk of parasitic inductance and noise coupling.

[0053] As can be seen, by equipping each silicon carbide MOSFET chip with complete gate, source, and drain signal connections and setting up dedicated NTC signal pins, this signal pin assembly can not only support precise dynamic drive control, but also realize real-time acquisition of key temperature parameters, thereby improving the overall controllability and safety of the module.

[0054] Furthermore, the first AMB board 10, the second AMB board 20, and the third AMB board 30 do not operate independently; instead, they are electrically interconnected via connecting wires (such as bonding wires or copper strips). Therefore, each of the three AMB boards undertakes a portion of the circuit functionality, and they are then connected together via short-distance connecting wires to form a complete ANPC three-level topology. Please refer to [link / reference]. Figure 8 , Figure 8 The circuit topology diagram of the power module is shown. Port "P" and port "N" are the positive and negative electrodes of the DC bus, respectively, corresponding to... Figure 1 The DC positive busbar 50 and DC negative busbar 60 are connected in the circuit. Port "U" is mainly used for outputting AC current, corresponding to... Figure 1 In the AC busbar 100, port "O" corresponds to Figure 1 The circuit consists of a first midpoint potential clamping busbar 70 and a second midpoint potential clamping busbar 80. The main bridge arm, composed of the first silicon carbide chip Q1, the second silicon carbide chip Q2, the third silicon carbide chip Q3, and the fourth silicon carbide chip Q4, is connected in series. The clamping bridge arm, composed of the fifth silicon carbide chip and the sixth silicon carbide chip Q6, is also connected in series. The drain of the fifth silicon carbide chip is connected to the source of the first silicon carbide chip Q1 and the drain of the second silicon carbide chip Q2. The source of the sixth silicon carbide chip Q6 is connected to the source of the third silicon carbide chip Q3 and the drain of the fourth silicon carbide chip Q4.

[0055] It is pieced together by short connecting lines. Figure 8 The circuit topology shown achieves both functional decoupling and electrical continuity, making it particularly suitable for high-density integration scenarios. For example, the upper part of the main bridge arm may be located on the first AMB board 10, the lower part on the third AMB board 30, and the intermediate commutation node on the second AMB board 20. A complete path can be formed by connecting the two boards, avoiding the problems of trace crossing or detours on a single substrate.

[0056] Specifically, the DC positive busbar, the first midpoint potential clamping busbar 70, the first silicon carbide chip Q1, and the fifth silicon carbide chip Q5 are arranged on the textured surface of the first AMB board 10; the AC busbar 100, the second silicon carbide chip Q2, and the third silicon carbide chip Q3 are arranged on the textured surface of the second AMB board 20; and the DC negative busbar 60, the second midpoint potential clamping busbar 80, the fourth silicon carbide chip Q4, and the sixth silicon carbide chip Q6 are arranged on the textured surface of the third AMB board 30. A DC positive busbar is arranged on both sides above the surface of the first AMB. A small island is provided in the center of the first AMB. The left side, the small island, and the right side of the first AMB surface are electrically connected by a bonding wire 90. The DC positive busbar is arranged in the middle above the surface of the first AMB. The first silicon carbide chip Q1 is symmetrically arranged in the lower half of the surface of the first AMB, separated by the gate and source of the first silicon carbide chip Q1. The fifth silicon carbide chip Q5 is symmetrically arranged in the upper half of the surface of the first AMB, separated by the gate and source of the fifth silicon carbide chip Q5. The surface area corresponding to the source of the first silicon carbide chip Q1 and the surface area corresponding to the drain of the fifth silicon carbide chip Q5 are a single connected area. The first signal pin assembly is arranged below the first AMB, from left to right: gate signal pin G1, source signal pin S1, and drain signal pin D1. The fifth signal pin assembly is arranged above the first AMB, from left to right: gate signal pin G5, source signal pin S1, and drain signal pin D1. S5 and drain signal pin D5; The AC busbar 100 is arranged in the middle below the tread surface of the second AMB. The second silicon carbide chip Q2 is symmetrically arranged in the right half of the tread surface of the second AMB, separated by the source and gate of the second silicon carbide chip Q2. The tread area corresponding to the drain of the second silicon carbide chip Q2 and the tread area corresponding to the source of the first silicon carbide chip Q1 (or the drain of the fifth silicon carbide chip Q5) are electrically connected by bonding wire 90 or copper strip. The third silicon carbide chip Q3 is symmetrically arranged in the left half of the tread surface of the second AMB, separated by the source and gate of the third silicon carbide chip Q3. The tread area corresponding to the source of the third silicon carbide chip Q3 and the tread area corresponding to the drain of the fourth silicon carbide chip Q4 (or the source of the sixth silicon carbide chip Q6) are electrically connected by bonding wire 90 or copper strip. The second signal pin assembly is arranged below the right half of the second AMB, and from left to right, they are: drain signal pin D2, source signal pin S2, and gate signal pin. G2; The third signal pin assembly is located at the lower left half of the second AMB, and from left to right are: source signal pin S3, gate signal pin G3 and drain signal pin D3; The NTC signal pin assembly is located at the middle of the upper part of the second AMB, and from left to right are: T1 signal pin and T2 signal pin. DC negative busbar 60 is arranged on both sides above the surface of the third AMB. A small island is provided in the center area of ​​the third AMB. The left side, the small island and the right side of the surface of the third AMB are electrically connected by bonding wire 90. The second midpoint potential clamping busbar 80 is arranged in the middle above the surface of the third AMB. The fourth silicon carbide chip Q4 is symmetrically arranged in the upper half of the surface of the third AMB, separated by the gate and source of the fourth silicon carbide chip Q4. The sixth silicon carbide chip Q6 is symmetrically arranged in the lower half of the surface of the third AMB, separated by the gate and source of the sixth silicon carbide chip Q6. The surface area corresponding to the source of the sixth silicon carbide chip Q6 and the surface area corresponding to the drain of the fourth silicon carbide chip Q4 are a single connected area. The sixth signal pin assembly is arranged below the third AMB, from left to right: gate signal pin G6, source signal pin S6 and drain signal pin. D6; The fourth signal pin assembly is located above the third AMB, and from left to right are: gate signal pin G4, source signal pin S4, and drain signal pin D4.

[0057] Ultimately, the silicon carbide MOSFET chip, busbar assembly, and patterned surface area together constitute the ANPC-type three-level topology. This topology can output three voltage levels (positive, zero, and negative), which, compared to the traditional two-level topology, can effectively reduce the output voltage jump amplitude, reduce the filter size, and improve system efficiency. Furthermore, in this embodiment, due to the optimized layout and low-inductance design of each key component, the ANPC topology remains stable under high-frequency operation, and is less prone to voltage overshoot or oscillation.

[0058] As can be seen, through the spatial arrangement of the AMB board, the meticulous design of the textured surface area, the low-inductance structure of the busbar, the symmetrical installation of the chips, and the rational use of the inter-board connection lines, this power module achieves high integration and a very compact structure within a limited space. At the same time, the main power circuit path is short and symmetrical, and the parasitic inductance is reduced to a low level. The electrical lengths of the parallel branches of the multiple chips are nearly consistent, which helps to achieve good static and dynamic current sharing. In addition, the heat source is evenly distributed throughout, and with the heat sink 40 at the bottom for efficient heat conduction, the module as a whole has excellent heat dissipation capabilities.

[0059] The specific layout of the patterned pavement area provided in this application is described in detail below: In one possible implementation, please refer to Figures 9-11The fourth silicon carbide chip Q4 and the sixth silicon carbide chip Q6 are arranged on the third AMB board 30, and the second silicon carbide chip Q2 and the third silicon carbide chip Q3 are arranged on the second AMB board. The first silicon carbide chip Q1 includes a first silicon carbide left half chip and a first silicon carbide right half chip arranged in parallel. The fifth silicon carbide chip includes a fifth silicon carbide left half chip and a first silicon carbide right half chip arranged in parallel. The patterned surface area on the first AMB board 10 includes: The first connected area 110 is located on the right side of the first AMB board 10. The first connected area 110 has a textured area 111 for the right terminal of the DC positive busbar, a textured area 112 for the right half of the first silicon carbide chip, and a textured area 113 for the drain of the first silicon carbide chip. The second connected region 120 is located on the left side of the first AMB board 10. The second connected region 120 is provided with the textured region 121 of the left terminal of the DC positive busbar and the textured region 122 of the left half of the first silicon carbide chip. The first connected region 110 and the second connected region 120 are symmetrical about the vertical direction. A third connected region 130 is located between the first connected region 110 and the second connected region 120 and is symmetrically arranged about the vertical direction. The third connected region 130 is provided with the following texture areas: 131 for the solder feet on the first bonding line, 132 for the source electrode of the right half of the first silicon carbide chip, 133 for the source electrode of the left half of the first silicon carbide chip, 134 for the right solder foot of the bonding line on the center island, 135 for the left solder foot of the bonding line on the center island, 136 for the right half of the fifth silicon carbide chip, 137 for the left half of the fifth silicon carbide chip, and 138 for the drain electrode of the fifth silicon carbide chip. Regarding the vertically symmetrically arranged fourth connected region 140, the fourth connected region 140 is arranged with the textured region 141 of the first midpoint potential clamping busbar, the textured region 142 of the source electrode of the right half of the fifth silicon carbide chip, and the textured region 143 of the source electrode of the left half of the fifth silicon carbide chip; the first connected region 110, the second connected region 120, the third connected region 130, and the fourth connected region 140 are isolated from each other; the textured region 151 of the source electrode of the first silicon carbide chip; the textured region 152 of the gate electrode of the first silicon carbide chip; the textured region 153 of the first intermediate island; the textured region 154 of the source electrode of the fifth silicon carbide chip; and the textured region 155 of the gate electrode of the fifth silicon carbide chip.

[0060] Among them, the upper half of the third communication area 130 is in a "U" shape. The left half chip of the fifth silicon carbide and the right half chip of the fifth silicon carbide are respectively arranged on both sides of the upper half of the third communication area 130 and are symmetrically arranged about the vertical direction. The left half chip of the first silicon carbide and the right half chip of the first silicon carbide are respectively arranged in the lower half of the first communication area 110 and the second communication area 120 and are symmetrically arranged about the vertical direction.

[0061] It can be understood that in this embodiment, by setting a plurality of independent conductive areas with symmetrical distribution on the first AMB board 10 and reasonably arranging the connection paths of the chips and the busbars, the balanced distribution of current and the reduction of parasitic parameters are achieved.

[0062] Specifically, the first silicon carbide chip Q1 includes a left half chip of the first silicon carbide and a right half chip of the first silicon carbide arranged in parallel. These two parts are respectively arranged in the second communication area 120 and the first communication area 110 on the left and right sides of the first AMB board 10. Inside each area, the DC positive busbar terminal and the drain of the corresponding side chip are directly connected on the same conductive surface, so that the current is input from both sides at the same time, avoiding the current skew caused by single-sided power supply.

[0063] During this process, the third communication area 130 is located between the left and right and is symmetric about the vertical direction. The source of the first silicon carbide chip Q1, two parallel parts of the fifth silicon carbide chip, and the pattern areas of its drain and source are arranged thereon, forming a concentrated conductive channel, making the connection of the common nodes of the upper and lower bridge arms more compact. The fourth communication area 140 is specifically used for the connection of the midpoint potential clamping busbar and the source of the fifth silicon carbide chip, and is isolated from other areas to prevent short circuits.

[0064] It should be noted that the upper half of the third communication area 130 is in a "U" shape, and the left half chip of the fifth silicon carbide and the right half chip of the fifth silicon carbide are symmetrically arranged on both sides, which is beneficial to current sharing and heat dissipation balance. The pattern area 153 of the first intermediate island is located in the center and connects the left and right solder feet through the bonding wire 90, further enhancing the electrical symmetry.

[0065] Thus, by symmetrically arranging a plurality of independent communication areas, reasonably dividing the functional blocks, and centrally managing the key connection points, this design effectively improves the current sharing performance and structural stability of the module.

[0066] Similarly, please refer to Figure 12 , the fourth silicon carbide chip Q4 includes a left half chip of the fourth silicon carbide and a right half chip of the fourth silicon carbide arranged in parallel, and the sixth silicon carbide chip Q6 includes a left half chip of the sixth silicon carbide and a right half chip of the sixth silicon carbide arranged in parallel; the patterned surface area on the third AMB board 30 includes: The fifth communication region 310 is located on the right side of the third AMB board 30. The fifth communication region 310 is provided with a pattern region 311 of the right terminal of the second midpoint potential clamping busbar, a pattern region 312 of the right half of the sixth silicon carbide chip, and a pattern region 313 of the drain of the sixth silicon carbide chip; The sixth communication region 320 is located on the left side of the third AMB board 30. The sixth communication region 320 is provided with a pattern region 321 of the left terminal of the second midpoint potential clamping busbar and a pattern region 322 of the left half of the sixth silicon carbide chip; The fifth communication region 310 and the sixth communication region 320 are symmetric about the vertical direction; The seventh communication region 330 is located between the fifth communication region 310 and the sixth communication region 320 and is symmetrically arranged about the vertical direction. The seventh communication region 330 is provided with a pattern region 331 of the upper solder pad of the second bonding wire, a pattern region 332 of the source of the right half of the sixth silicon carbide chip, a pattern region 333 of the source of the left half of the sixth silicon carbide chip, a pattern region 334 of the right solder pad of the midline island bonding wire, a pattern region 335 of the left solder pad of the midline island bonding wire, a pattern region 336 of the right half of the fourth silicon carbide chip, a pattern region 337 of the left half of the fourth silicon carbide chip, and a pattern region 338 of the drain of the fourth silicon carbide chip; The eighth communication region 340 is symmetrically arranged about the vertical direction. The eighth communication region 340 is provided with a pattern region 341 of the pattern region of the DC negative busbar, a pattern region 342 of the source of the right half of the fourth silicon carbide chip, and a pattern region 343 of the source of the left half of the fourth silicon carbide chip; The fifth communication region 310, the sixth communication region 320, the seventh communication region 330, and the eighth communication region 340 are isolated from each other; A pattern region 351 of the source of the sixth silicon carbide chip; A pattern region 352 of the gate of the sixth silicon carbide chip; A pattern region 353 of the second intermediate island; A pattern region 354 of the source of the fourth silicon carbide chip; A pattern region 355 of the gate of the fourth silicon carbide chip.

[0067] Among them, the upper half of the seventh communication region 330 is in a "U" shape. The left half of the sixth silicon carbide chip and the right half of the sixth silicon carbide chip are respectively arranged on both sides of the upper half of the seventh communication region 330 and are symmetrically arranged about the vertical direction; The left half of the fourth silicon carbide chip and the right half of the fourth silicon carbide chip are respectively arranged in the lower half of the fifth communication region 310 and the sixth communication region 320 and are symmetrically arranged about the vertical direction.

[0068] The third AMB plate 30 is arranged in the same way as the first AMB plate 10, and it can bring the same effect, so it will not be described in detail here. It can be understood that the third AMB plate 30 and the first AMB plate 10 are arranged symmetrically about the vertical direction, and the interior of the third AMB plate 30 and the first AMB plate 10 are also arranged symmetrically about the vertical direction. This can achieve a better flow uniformity effect.

[0069] As one implementation method, please refer to Figure 13 The second silicon carbide chip Q2 includes a second silicon carbide left half chip and a second silicon carbide right half chip arranged in parallel; the third silicon carbide chip Q3 includes a third silicon carbide left half chip and a third silicon carbide right half chip arranged in parallel; the patterned surface area on the second AMB board 20 includes: The ninth connecting region 210 located on the right side of the AMB board has a textured area 211 for the solder pads of the first bonding line, a textured area 212 for the right half of the second silicon carbide chip, a textured area 213 for the left half of the second silicon carbide chip, and a textured area 214 for the drain of the second silicon carbide chip. The tenth connecting region 220 has the following textured regions arranged on it: the source region 221 of the right half of the second silicon carbide chip, the source region 222 of the left half of the second silicon carbide chip, the AC busbar textured region 223, the right half of the third silicon carbide chip textured region 224, the left half of the third silicon carbide chip textured region 225, and the drain region 226 of the third silicon carbide chip. Eleventh connected region 230, which includes a textured region 231 for the second bonding line solder pad, a textured region 232 for the right half of the third silicon carbide chip source electrode, and a textured region 233 for the left half of the third silicon carbide chip source electrode; Ninth connected region 210, Tenth connected region 220, and Eleventh connected region 230 are isolated from each other; First textured region 251 and Second textured region 255 of the second silicon carbide chip gate; First textured region 252 and Second textured region 256 of the second silicon carbide chip source electrode; First textured region 253 and Second textured region 258 of the third silicon carbide chip source electrode; First textured region 254 and Second textured region 257 of the third silicon carbide chip gate; Textured region 259 for the marker point; Textured region 261 for the NTC top electrode; Textured region 262 for the NTC bottom electrode.

[0070] Among them, the lower half of the ninth connected region 210 is in the shape of "冂", the left half chip of the second silicon carbide and the right half chip of the second silicon carbide are respectively arranged on both sides of the lower half of the ninth connected region 210, and are symmetrically arranged about the vertical direction; the left half chip of the third silicon carbide and the right half chip of the third silicon carbide are located on both sides of the eleventh connected region 230, and are symmetrically arranged about the vertical direction; the left half chip of the second silicon carbide, the right half chip of the second silicon carbide, the left half chip of the third silicon carbide, and the right half chip of the third silicon carbide are on the same horizontal line.

[0071] It can be understood that in this embodiment, by symmetrically arranging the parallel-connected silicon carbide chips and their corresponding patterned surface regions on the second AMB board 20 and adopting the design method of functional partition isolation, the technical effects of balanced current distribution, reduced loop inductance, and reliable signal detection are achieved.

[0072] It should be understood that the second silicon carbide chip Q2 includes a left half chip of the second silicon carbide and a right half chip of the second silicon carbide arranged in parallel, and the third silicon carbide chip Q3 also includes a left half chip of the third silicon carbide and a right half chip of the third silicon carbide arranged in parallel. These chips are all mounted on the second AMB board 20 and are used to form the lower main bridge arm switching unit in the ANPC three-level topology. Since the silicon carbide MOSFET has high-frequency switching ability, if the electrical paths between multiple parallel-connected chips are asymmetric, it is easy to cause uneven current distribution, which in turn leads to local overheating or a decrease in device life.

[0073] Specifically, the patterned surface region on the second AMB board 20 is divided into multiple isolated connected regions to achieve independent conduction of different electrical functions. The ninth connected region 210 is located on the right side of the AMB board, and the patterned region 211 of the first bonding wire lower solder pad, the patterned region 212 of the right half chip of the second silicon carbide, the patterned region 213 of the left half chip of the second silicon carbide, and the patterned region 214 of the drain of the second silicon carbide chip are arranged thereon. This region directly connects the two parallel-connected second silicon carbide chips Q2 and their common drain terminal on the same conductive surface, enabling current to flow into the two branches from a unified node and avoiding impedance imbalance caused by wiring differences.

[0074] In this process, the lower half of the ninth connected region 210 is in the shape of "冂", and the left half chip of the second silicon carbide and the right half chip of the second silicon carbide are respectively arranged on both sides of the "冂", and are symmetric about the vertical direction. This symmetric layout ensures that the distances from the two chips to the common connection point are equal, further improving the consistency of static and dynamic currents.

[0075] The tenth connecting region 220 centrally houses multiple portions of the source of the second silicon carbide chip Q2 and the third silicon carbide chip Q3, along with related connection points. Specifically, it includes the textured area 221 of the right half source of the second silicon carbide chip, the textured area 222 of the left half source of the second silicon carbide chip, the textured area of ​​the AC busbar 100, the textured area 224 of the right half of the third silicon carbide chip, the textured area 225 of the left half of the third silicon carbide chip, and the textured area 226 of the drain of the third silicon carbide chip. This region serves as the core junction area for power output, connecting the AC output terminal to the midpoint of the upper and lower bridge arms, forming a complete commutation path. Because all critical connections are integrated on a continuous conductive surface, the use of jumpers and bonding wires 90 is reduced, thereby lowering parasitic inductance.

[0076] The eleventh connecting region 230 is independently located on one side of the tenth connecting region 220 and is specifically used to connect the source path of the third silicon carbide chip Q3. It has the textured area 231 for the solder pads under the second bonding line, the textured area 232 for the source of the right half of the third silicon carbide chip, and the textured area 233 for the source of the left half of the third silicon carbide chip. The left and right halves of the third silicon carbide chip are located on opposite sides of the eleventh connecting region 230, maintaining a symmetrical arrangement about the vertical direction to ensure the symmetry and low impedance characteristics of its source circuit.

[0077] The left and right halves of the second silicon carbide chip, the left and right halves of the third silicon carbide chip, and the right half of the third silicon carbide chip are all located on the same horizontal line. This planar arrangement not only facilitates the implementation of automated surface mount technology (SMT) processes but also makes the heat distribution of each chip more uniform, which is conducive to heat dissipation management.

[0078] In addition, to support control and monitoring functions, the second AMB board 20 is equipped with multiple dedicated textured areas: including a first textured area 251 and a second textured area for connecting the gate of the second silicon carbide chip, a corresponding textured area for connecting its source, and gate and source textured areas corresponding to the third silicon carbide chip Q3. These small signal traces are independent of high current paths, reducing the risk of interference. The textured areas of the marker points are used for visual positioning during module assembly, improving production accuracy. The textured areas of the NTC top electrode and the NTC bottom electrode are used to connect to negative temperature coefficient thermistors (NTCs) to achieve real-time monitoring of the module's internal temperature and ensure operational safety.

[0079] As can be seen, by symmetrically arranging the chips on the second AMB board 20 in parallel, dividing the interconnected areas with clear functions and mutual isolation, and placing the key power devices on the same horizontal plane, this design effectively achieves current sharing control among multiple chips, low inductance of the main power circuit, and reliable extraction of temperature and drive signals.

[0080] In summary, this application, without increasing module size, provides a feasible structural implementation path for high-density power modules by achieving a refined circuit layer layout that balances electrical performance, thermal stability, and manufacturability. The symmetrical arrangement of the patterned surface area on the AMB board offers the following main advantages: 1. Superior current sharing performance: Symmetrical arrangement can reduce current imbalance, avoid chip overload, improve switching synchronization, and thus improve current sharing performance.

[0081] 2. More uniform heat distribution: Symmetrical arrangement can reduce thermal stress, optimize radiator efficiency, improve thermomechanical reliability, and thus enhance heat dissipation capacity.

[0082] 3. Reduce parasitic inductance: Symmetrical arrangement can reduce switching overvoltage and electromagnetic interference radiated to the outside, thereby reducing parasitic inductance.

[0083] 4. A symmetrical layout helps to make the overall structure more compact and result in higher power density.

[0084] Based on the above implementation, this application also provides an electronic device, which includes the aforementioned ANPC-type three-level power module. By integrating the aforementioned ANPC-type three-level power module into the electronic device, this embodiment significantly improves the electronic device's power conversion efficiency, power density, and operational stability.

[0085] It should be understood that the electronic device can be applied to high-efficiency power conversion technology devices. Due to its advantages such as high voltage withstand capability, low loss, high switching frequency, and good thermal management, the ANPC-type three-level power module is particularly suitable for industrial and civilian applications with high energy conversion performance requirements.

[0086] For example, in practical applications, electronic devices can be used in the motor drive controller of new energy vehicles. In this scenario, the ANPC-type three-level power module is used as the main inverter unit, responsible for converting the DC power provided by the power battery into AC power to drive a permanent magnet synchronous motor or an asynchronous motor. Since silicon carbide MOSFETs have lower conduction and switching losses than traditional silicon devices, combined with the low parasitic parameter layout and current sharing design in this solution, they can operate stably under high-frequency conditions, thereby reducing filter size, improving system efficiency, and extending vehicle range.

[0087] Furthermore, this electronic device can also be applied to photovoltaic grid-connected inverters. The direct current generated by a photovoltaic power generation system needs to be inverted before being connected to the grid. Inverters using the ANPC topology can output a voltage waveform closer to a sine wave, effectively reducing harmonic content. Combined with the optimized busbar arrangement and AMB board texture design in this solution, electromagnetic interference is further suppressed, improving the system's electromagnetic compatibility and enabling the entire photovoltaic inverter equipment to operate reliably in complex outdoor environments.

[0088] In summary, by integrating the aforementioned high-performance power modules, this electronic device achieves a comprehensive effect of improved efficiency, reduced size, and enhanced reliability without changing the overall system architecture. Overall, it has advantages such as compact structure, high power density, low parasitic inductance, excellent current sharing performance, and strong heat dissipation.

[0089] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0090] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. An ANPC-type three-level power module, characterized in that, The ANPC type three-level power module includes: Heat sink; The heat sink has a first AMB plate, a second AMB plate, and a third AMB plate. The first AMB plate and the third AMB plate are symmetrically arranged in the upper half of the heat sink, and the second AMB plate is arranged in the middle area of ​​the lower half of the heat sink. The first AMB plate and the third AMB plate are arranged vertically, and the second AMB plate is arranged horizontally. The patterned textured surface area located on the upper surface of each of the AMB boards is composed of a conductive metal layer and is used to realize electrical connections in the circuit topology. Multiple silicon carbide MOSFET chips are fixed on the corresponding patterned surface area and electrically connected. Busbar assembly, the busbar assembly being disposed on the AMB plate and electrically connected to the patterned surface area; A signal pin assembly, the signal pin assembly comprising pin components respectively connected to the gate, source and drain of each of the silicon carbide MOSFET chips; The first AMB board, the second AMB board, and the third AMB board are electrically interconnected through connecting wires. The silicon carbide MOSFET chip, together with the busbar assembly and the patterned textured surface area, constitutes an ANPC-type three-level topology.

2. The ANPC-type three-level power module according to claim 1, characterized in that, The busbar assembly includes a DC positive busbar, a DC negative busbar, a first midpoint potential clamping busbar, a second midpoint potential clamping busbar, and an AC busbar. The DC positive busbar and the second midpoint potential clamping busbar are bent metal busbars with the same structure, and the DC negative busbar and the first midpoint potential clamping busbar are bent metal busbars with the same structure. The DC positive busbar is arranged on both sides above the textured surface area of ​​the first AMB board, the first midpoint potential clamping busbar is arranged in the middle above the textured surface area of ​​the first AMB board, the DC negative busbar is arranged in the middle above the textured surface area of ​​the third AMB board, the second midpoint potential clamping busbar is arranged on both sides above the textured surface area of ​​the third AMB board, and the AC busbar is arranged in the middle below the textured surface area of ​​the second AMB board.

3. The ANPC-type three-level power module according to claim 2, characterized in that, The DC positive busbar and the first midpoint potential clamping busbar are arranged in a stacked manner, and the DC positive busbar and the first midpoint potential clamping busbar are not in contact; the DC negative busbar and the second midpoint potential clamping busbar are also arranged in a stacked manner, and the DC negative busbar and the second midpoint potential clamping busbar are not in contact.

4. The ANPC-type three-level power module according to claim 1, characterized in that, The multiple silicon carbide MOSFET chips include a first silicon carbide chip, a second silicon carbide chip, a third silicon carbide chip, a fourth silicon carbide chip, a fifth silicon carbide chip, and a sixth silicon carbide chip. The fourth silicon carbide chip and the sixth silicon carbide chip are arranged on the third AMB board. The second silicon carbide chip and the third silicon carbide chip are arranged on the second AMB board. The first silicon carbide chip includes a first left half silicon carbide chip and a first right half silicon carbide chip connected in parallel. The fifth silicon carbide chip includes a fifth left half silicon carbide chip and a first right half silicon carbide chip connected in parallel. The patterned surface area on the first AMB board includes: A first communication area on the right side of the first AMB board. The first communication area has a textured area for the right terminal of the DC positive busbar, a textured area for the first right half silicon carbide chip, and a textured area for the drain of the first silicon carbide chip. A second communication area on the left side of the first AMB board. The second communication area has a textured area for the left terminal of the DC positive busbar and a textured area for the first left half silicon carbide chip. The first communication area and the second communication area are symmetric about the vertical direction. A third communication area located between the first communication area and the second communication area and symmetrically arranged about the vertical direction. The third communication area has a textured area for the upper solder pad of the first bonding wire, a textured area for the source of the first right half silicon carbide chip, a textured area for the source of the first left half silicon carbide chip, a textured area for the right solder pad of the midline island bonding wire, a textured area for the left solder pad of the midline island bonding wire, a textured area for the fifth right half silicon carbide chip, a textured area for the fifth left half silicon carbide chip, and a textured area for the drain of the fifth silicon carbide chip. A fourth communication area symmetrically arranged about the vertical direction. The fourth communication area has a textured area for the first midpoint potential clamping busbar, a textured area for the source of the fifth right half silicon carbide chip, and a textured area for the source of the fifth left half silicon carbide chip. The first communication area, the second communication area, the third communication area, and the fourth communication area are isolated from each other. A textured area for the source of the first silicon carbide chip. A textured area for the gate of the first silicon carbide chip. A textured area for the first intermediate island. A textured area for the source of the fifth silicon carbide chip. A textured area for the gate of the fifth silicon carbide chip.

5. The ANPC-type three-level power module according to claim 4, characterized in that, The upper half of the third communication area is in a "凵" shape. The fifth left half silicon carbide chip and the fifth right half silicon carbide chip are respectively arranged on both sides of the upper half of the third communication area and symmetrically arranged about the vertical direction. The first left half silicon carbide chip and the first right half silicon carbide chip are respectively arranged in the lower half of the first communication area and the second communication area and symmetrically arranged about the vertical direction.

6. The ANPC-type three-level power module according to claim 1, characterized in that, The multiple silicon carbide MOSFET chips include a first silicon carbide chip, a second silicon carbide chip, a third silicon carbide chip, a fourth silicon carbide chip, a fifth silicon carbide chip, and a sixth silicon carbide chip. The first silicon carbide chip and the fifth silicon carbide chip are arranged on the first AMB board. The second silicon carbide chip and the third silicon carbide chip are arranged on the second AMB board. The fourth silicon carbide chip includes a fourth silicon carbide left half chip and a fourth silicon carbide right half chip connected in parallel. The sixth silicon carbide chip includes a sixth silicon carbide left half chip and a sixth silicon carbide right half chip connected in parallel. The patterned surface area on the third AMB board includes: A fifth communication area located on the right side of the third AMB board. The fifth communication area is provided with a pattern area of the right terminal of the second midpoint potential clamping busbar, a pattern area of the sixth silicon carbide right half chip, and a pattern area of the drain of the sixth silicon carbide chip. A sixth communication area located on the left side of the third AMB board. The sixth communication area is provided with a pattern area of the left terminal of the second midpoint potential clamping busbar and a pattern area of the sixth silicon carbide left half chip. The fifth communication area and the sixth communication area are symmetric about the vertical direction. A seventh communication area located between the fifth communication area and the sixth communication area and symmetrically arranged about the vertical direction. The seventh communication area is provided with a pattern area of the upper solder pad of the second bonding wire, a pattern area of the source of the sixth silicon carbide right half chip, a pattern area of the source of the sixth silicon carbide left half chip, a pattern area of the right solder pad of the midline island bonding wire, a pattern area of the left solder pad of the midline island bonding wire, a pattern area of the fourth silicon carbide right half chip, a pattern area of the fourth silicon carbide left half chip, and a pattern area of the drain of the fourth silicon carbide chip. An eighth communication area symmetrically arranged about the vertical direction. The eighth communication area is provided with a pattern area of the DC negative busbar, a pattern area of the source of the fourth silicon carbide right half chip, and a pattern area of the source of the fourth silicon carbide left half chip. The fifth communication area, the sixth communication area, the seventh communication area, and the eighth communication area are isolated from each other. A pattern area of the source of the sixth silicon carbide chip. A pattern area of the gate of the sixth silicon carbide chip. A pattern area of the second intermediate island. A pattern area of the source of the fourth silicon carbide chip. A pattern area of the gate of the fourth silicon carbide chip.

7. The ANPC-type three-level power module according to claim 6, characterized in that, The upper half of the seventh communication area is in a "U" shape. The sixth silicon carbide left half chip and the sixth silicon carbide right half chip are respectively arranged on both sides of the upper half of the seventh communication area and symmetrically arranged about the vertical direction. The fourth silicon carbide left half chip and the fourth silicon carbide right half chip are respectively arranged in the lower half of the fifth communication area and the sixth communication area and symmetrically arranged about the vertical direction.

8. The ANPC-type three-level power module according to claim 1, characterized in that, The multiple silicon carbide MOSFET chips include a first silicon carbide chip, a second silicon carbide chip, a third silicon carbide chip, a fourth silicon carbide chip, a fifth silicon carbide chip, and a sixth silicon carbide chip. The first silicon carbide chip and the fifth silicon carbide chip are arranged on the first AMB board. The fourth silicon carbide chip and the sixth silicon carbide chip are arranged on the third AMB board. The second silicon carbide chip includes a second left half silicon carbide chip and a second right half silicon carbide chip arranged in parallel. The third silicon carbide chip includes a third left half silicon carbide chip and a third right half silicon carbide chip arranged in parallel; The patterned surface area on the second AMB board includes: A ninth communication area on the right side of the AMB board. The first bonding wire lower solder pad pattern area, the second right half silicon carbide chip pattern area, the second left half silicon carbide chip pattern area, and the second silicon carbide chip drain pattern area are arranged on the ninth communication area; A tenth communication area. The second right half silicon carbide chip source pattern area, the second left half silicon carbide chip source pattern area, the AC busbar pattern area, the third right half silicon carbide chip pattern area, the third left half silicon carbide chip pattern area, and the third silicon carbide chip drain pattern area are arranged on the tenth communication area; An eleventh communication area. The second bonding wire lower solder pad pattern area, the third right half silicon carbide chip source pattern area, and the third left half silicon carbide chip source pattern area are arranged on the eleventh communication area. The ninth communication area, the tenth communication area, and the eleventh communication area are isolated from each other; The first pattern area and the second pattern area of the second silicon carbide chip gate; The first pattern area and the second pattern area of the second silicon carbide chip source; The first pattern area and the second pattern area of the third silicon carbide chip source; The first pattern area and the second pattern area of the third silicon carbide chip gate; The pattern area of the fiducial point; The pattern area of the NTC top surface electrode; The pattern area of the NTC bottom surface electrode.

9. The ANPC-type three-level power module according to claim 8, characterized in that, The lower half of the ninth communication area is in a "冂" shape. The second left half silicon carbide chip and the second right half silicon carbide chip are respectively arranged on both sides of the lower half of the ninth communication area and are symmetrically arranged about the vertical direction; The third left half silicon carbide chip and the third right half silicon carbide chip are located on both sides of the eleventh communication area and are symmetrically arranged about the vertical direction; The second left half silicon carbide chip, the second right half silicon carbide chip, the third left half silicon carbide chip, and the third right half silicon carbide chip are on the same horizontal line.

10. An electronic device, characterized in that, The electronic device includes the ANPC type three-level power module according to any one of claims 1 to 9.

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