Reverse conducting control circuit of cascade structure and power converter

Abstract

This application provides a cascaded reverse conduction control circuit and a power converter, belonging to the field of electronic circuit technology. The pulse width modulation signal is transmitted to the action module via a first driving module. The output terminal of the action module is connected to the gate of a first high-voltage depletion-type transistor (HMT). The sampling terminal of the action module is connected to the first terminal of a detection module. The second terminal of the detection module is connected to the drain of the first HMT. The third terminal of the detection module and the action module are both connected to the source of a low-voltage enhancement-type transistor (LVMT). Logic levels are transmitted to the gate of the LVMT via a second driving module. The detection module detects the voltage and current directions of the cascaded structure. Driven by the detection module, the action module controls the first HMT to conduct. This application simplifies the reverse conduction control strategy for gallium nitride (GaN) power devices and reduces the cost of reverse conduction control for GaN power devices.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more specifically, to a cascaded reverse conduction control circuit and a power converter. Background Technology

[0002] Gallium nitride (GaN) high electron mobility transistors (HNTs) offer advantages such as extremely low gate charge and small output capacitance, enabling faster switching speeds and lower switching losses. In high-frequency, high-efficiency power conversion applications, they exhibit significant performance advantages over traditional silicon-based metal-oxide-semiconductor (SiO2) transistors. Furthermore, the absence of a body diode in GaN HNTs makes zero reverse recovery possible, thus enabling their application in high-frequency power converters.

[0003] However, gallium nitride (GaN) high electron mobility transistors (HEMTs) are inherently depletion-mode power devices. Compared to traditional silicon-based metal-oxide-semiconductor (SiO2) transistors, GaN HEMTs have a higher reverse conduction voltage, and their reverse conduction voltage drop is controlled by the gate-drain voltage. The more negative the gate-source voltage of a GaN HEMT, the larger the absolute value of the voltage difference between the threshold voltage and the gate-source voltage, and the greater the reverse conduction voltage drop. In this case, if the dead time of the GaN HEMT is long, the higher reverse conduction voltage may cause excessive dead time loss, thus affecting the efficiency and performance of the entire system.

[0004] Currently, dead time loss is often reduced by shortening the dead time of gallium nitride high electron mobility transistors (GaN high electron mobility transistors). However, adaptive dead time control technology is complex and has high practical control costs, making it difficult to use widely. Therefore, there is an urgent need for a simple and cost-effective reverse conduction control strategy suitable for GaN high electron mobility transistors. Summary of the Invention

[0005] The purpose of this application is to provide a cascaded reverse conduction control circuit and a power converter, which can simplify the reverse conduction control strategy of gallium nitride power devices and reduce the reverse conduction control cost of gallium nitride power devices.

[0006] The embodiments of this application are implemented as follows: A first aspect of this application provides a cascaded reverse conduction control circuit, the circuit comprising: a cascaded structure to be controlled, a first driving module, a second driving module, an action module, and a detection module. The cascaded structure comprises: a first high-voltage depletion-type transistor and a low-voltage enhancement-type transistor, wherein the source of the first high-voltage depletion-type transistor is connected to the drain of the low-voltage enhancement-type transistor. The input terminal of the first driving module is used to receive the pulse width modulation signal. The output terminal of the first driving module is connected to the first terminal of the action module. The second terminal of the action module is connected to the gate of the first high voltage depletion transistor. The third terminal of the action module is connected to the first terminal of the detection module. The second terminal of the detection module is connected to the drain of the first high voltage depletion transistor. The third terminal of the detection module and the fourth terminal of the action module are both connected to the source of the low voltage enhancement type transistor. The input terminal of the second driving module is used to connect to the logic level, and the output terminal of the second driving module is connected to the gate of the low-voltage enhancement-mode transistor. The detection module is used to detect the voltage and current directions of the cascaded structure, and the action module is used to control the first high-voltage depletion transistor to turn on when both the voltage and current directions are negative.

[0007] As one possible implementation, the above-mentioned action module includes: a first resistor, a second resistor, a first diode, and a PNP transistor; One end of the first resistor is connected to the output terminal of the first driving module. The collector of the PNP transistor is connected to the other end of the first resistor and the gate of the first high-voltage depletion-type transistor. The base of the PNP transistor is connected to one end of the second resistor. The emitter of the PNP transistor is connected to the source of the low-voltage enhancement-type transistor. The other end of the second resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the first end of the detection module.

[0008] As one possible implementation, the detection module includes: a second high-voltage depletion-type transistor and a first Zener diode; The gate of the second high-voltage depletion-type transistor and the anode of the first Zener diode are both connected to the source of the low-voltage enhancement-type transistor. The drain of the second high-voltage depletion-type transistor is connected to the drain of the first high-voltage depletion-type transistor. The source of the second high-voltage depletion-type transistor is connected to the cathode of the first Zener diode and to the cathode of the first diode.

[0009] As one possible implementation, the detection module includes: a third high-voltage depletion-type transistor, a second Zener diode, and a third Zener diode; The gate of the third high-voltage depletion-type transistor and the cathode of the third Zener diode are both connected to the source of the low-voltage enhancement-type transistor. The drain of the third high-voltage depletion-type transistor is connected to the drain of the first high-voltage depletion-type transistor. The source of the third high-voltage depletion-type transistor is connected to the cathode of the second Zener diode and to the cathode of the first diode. The anode of the second Zener diode is connected to the anode of the third Zener diode.

[0010] As one possible implementation, the above-mentioned action module includes: a third resistor, a fourth resistor, a fifth resistor, and a P-type metal-oxide-semiconductor transistor; One end of the third resistor is connected to the output terminal of the first driving module. The drain of the P-type metal-oxide-semiconductor transistor is connected to the other end of the third resistor and the gate of the first high-voltage depletion-type transistor. The source of the P-type metal-oxide-semiconductor transistor and the other end of the fourth resistor are both connected to the source of the low-voltage enhancement-type transistor. The gate of the P-type metal-oxide-semiconductor transistor is connected to one end of the fourth resistor and one end of the fifth resistor. The other end of the fifth resistor is connected to the first terminal of the detection module.

[0011] As one possible implementation, the detection module includes: a fourth high-voltage depletion-type transistor, a fourth Zener diode, and a second diode; The anode of the second diode is connected to the other end of the fifth resistor, and the cathode of the fourth Zener diode is connected to the source of the fourth high-voltage depletion-type transistor and to the cathode of the second diode. The gate of the fourth high-voltage depletion-type transistor and the anode of the fourth Zener diode are both connected to the source of the low-voltage enhancement-type transistor, and the drain of the fourth high-voltage depletion-type transistor is connected to the drain of the first high-voltage depletion-type transistor.

[0012] As one possible implementation, the first high-voltage depletion-type transistor in the above cascaded structure and the high-voltage depletion-type transistor in the detection module are integrated on the same gallium nitride epitaxial wafer.

[0013] As one possible implementation, the first driving module includes a first driving chip; the second driving module includes a second driving chip. The input terminal of the first driver chip is used to receive the pulse width modulation signal, and the output terminal of the first driver chip is connected to the first terminal of the action module. The input terminal of the second driver chip is used to connect to the logic level, and the output terminal of the second driver chip is connected to the gate of the low-voltage enhancement-mode transistor.

[0014] As one possible implementation, the clamping duration of the gate potential of the first high-voltage depletion-type transistor by the above-mentioned action module is synchronized with the duration of the reverse current flowing through the first high-voltage depletion-type transistor.

[0015] A second aspect of this application provides a power converter that includes at least one reverse conduction control circuit of the cascaded structure described in the first aspect above.

[0016] The beneficial effects of the embodiments of this application include: This application provides a cascaded reverse conduction control circuit, which consists of a cascaded structure to be controlled, a first driving module, a second driving module, an action module, and a detection module. The cascaded structure includes a first high-voltage depletion-type transistor and a low-voltage enhancement-type transistor. The drain of the first high-voltage depletion-type transistor is connected to a high-voltage power node, and the source of the first high-voltage depletion-type transistor is connected to the drain of the low-voltage enhancement-type transistor. The source of the low-voltage enhancement-type transistor is grounded. The first driving module has an input terminal for receiving a pulse width modulation (PWM) signal, an output terminal connected to a first terminal of the action module, a second terminal connected to the gate of a first high-voltage depletion-type transistor (HVT), a second terminal connected to the drain of the first HVT, and a third terminal connected to the source of a low-voltage enhancement-type transistor (LVMT). The second driving module has an input terminal for receiving a logic level, and an output terminal connected to the gate of the LVMT. The detection module detects the voltage and current directions of the cascaded structure, and the action module controls the first HVT to conduct under the influence of the PWM signal when both the voltage and current directions are negative. This simplifies the reverse conduction control strategy for gallium nitride (GaN) power devices and reduces the cost of reverse conduction control. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the reverse conduction control circuit of the first cascaded structure provided in the embodiments of this application; Figure 2 A schematic diagram of the reverse conduction control circuit of the second cascade structure provided in the embodiments of this application; Figure 3 A schematic diagram of the reverse conduction control circuit of the third cascade structure provided in the embodiments of this application; Figure 4 A schematic diagram of the reverse conduction control circuit of the fourth cascade structure provided in the embodiments of this application; Figure 5 A schematic diagram of the reverse conduction control circuit of the fifth cascade structure provided in the embodiments of this application; Figure 6 A schematic diagram of the reverse conduction control circuit of the sixth cascade structure provided in the embodiments of this application; Figure 7 This is a reverse conduction test waveform for an existing cascaded structure; Figure 8 A reverse conduction test waveform of a cascaded structure provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of a power converter provided in an embodiment of this application.

[0019] Reference numerals: 10: Reverse conduction control circuit; 101: Cascaded structure; 1011: First high-voltage depletion-type transistor; 1012: Low-voltage enhancement-type transistor; 102: First driver module; 1021: First driver chip; 103: Second driver module; 1031: Second driver chip; 104: Action module; 1041: First resistor; 1042: Second resistor; 1043: First diode; 1044: PNP transistor; 1045: Third... Resistors; 1046: Fourth resistor; 1047: Fifth resistor; 1048: P-type metal-oxide-semiconductor transistor; 105: Detection module; 1051: Second high-voltage depletion-type transistor; 1052: First Zener diode; 1053: Third high-voltage depletion-type transistor; 1054: Second Zener diode; 1055: Third Zener diode; 1056: Fourth high-voltage depletion-type transistor; 1057: Fourth Zener diode; 1058: Second diode; 20: Power converter. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of this application, it should be noted that the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] Currently, dead time loss is often reduced by shortening the dead time of gallium nitride high electron mobility transistors. However, adaptive dead time control technology is quite complex and has high practical control costs, making it difficult to use widely.

[0025] To address this, this application provides a cascaded reverse conduction control circuit. A pulse-width modulation (PWM) signal is input through a first driving module, and a logic level is input through a second driving module. The second driving module controls the switching on and off of the low-voltage enhancement-mode transistor (LVMT) in the cascaded structure based on the input logic level. A detection module detects the voltage and current signals between the drain of the first high-voltage depletion-mode transistor (HMT) and the source of the HMT. When both the voltage and current signals are negative, an action circuit is triggered, causing the action circuit to control the first HMT to conduct based on the PWM signal. This simplifies the reverse conduction control strategy for gallium nitride (GaN) power devices and reduces the cost of reverse conduction control.

[0026] The reverse conduction control circuit and power converter of the cascade structure provided in the embodiments of this application will be explained in detail with reference to the following figures.

[0027] Figure 1 For a cascaded reverse conduction control circuit provided in this application, see [link to relevant documentation]. Figure 1 This application provides a cascaded reverse conduction control circuit 10, which includes: a cascaded structure 101 to be controlled, a first driving module 102, a second driving module 103, an action module 104, and a detection module 105. The cascaded structure 101 includes: a first high-voltage depletion-type transistor 1011 and a low-voltage enhancement-type transistor 1012, with the source of the first high-voltage depletion-type transistor 1011 connected to the drain of the low-voltage enhancement-type transistor 1012.

[0028] The cascaded structure 101 to be controlled can be any cascaded structure 101 requiring reverse conduction control. Each cascaded structure 101 includes a first high-voltage depletion-type transistor 1011 and a low-voltage enhancement-type transistor 1012. The drain of the first high-voltage depletion-type transistor 1011 is connected to a high-voltage power node, such as the output bus of a power factor correction circuit, a switching node in a half-bridge or full-bridge topology, or the primary winding of a transformer. The source of the first high-voltage depletion-type transistor 1011 is connected to the drain of the low-voltage enhancement-type transistor 1012. The source of the low-voltage enhancement-type transistor 1012 is connected to system ground or power ground, and also serves as the fourth terminal of the action module 104, the third terminal of the detection module 105, and the reference ground of the second drive module 103. This application does not specifically limit this.

[0029] The input terminal of the first driving module 102 is used to receive a pulse width modulation signal. The output terminal of the first driving module 102 is connected to the first terminal of the action module 104. The second terminal of the action module 104 is connected to the gate of the first high-voltage depletion-type transistor 1011. The third terminal of the action module 104 is connected to the first terminal of the detection module 105. The second terminal of the detection module 105 is connected to the drain of the first high-voltage depletion-type transistor 1011. The third terminal of the detection module 105 and the fourth terminal of the action module 104 are both connected to the source of the low-voltage enhancement-type transistor 1012.

[0030] It should be noted that the first terminal of the action module 104 is equivalent to an input terminal of the action module 104, used to receive the drive signal output by the first drive module 102; the second terminal of the action module 104 is equivalent to an output terminal of the action module 104, used to output a corresponding control signal to the gate of the first high-voltage depletion-type transistor 1011 in the cascaded structure 1011 to be controlled; the third terminal of the action module 104 is equivalent to a sampling terminal of the action module 104, used to sample the detection result of the detection module 105; the fourth terminal of the action module 104 is equivalent to a ground terminal of the action module 104, through which the action module 104 discharges excess charge to system ground or power ground.

[0031] It should also be noted that the first terminal of the detection module 105 is equivalent to the output terminal of the detection module 105, and the action module 104 obtains the detection result of the detection module 105 through the first terminal of the detection module 105; the second terminal of the detection module 105 is equivalent to one sampling terminal of the detection module 105, and the third terminal of the detection module 105 is equivalent to another sampling terminal of the detection module 105. The second and third terminals of the detection module 105 are used to sample the voltage and current signals between the drain of the first high-voltage depletion-type transistor 1011 and the source of the low-voltage enhancement-type transistor 1012 of the cascaded structure 1011 to be controlled.

[0032] Optionally, the first driving module 102 is used to receive the pulse width modulation signal generated by the external pulse width modulation generator and input the pulse width modulation signal into the action module 104. The action module 104 controls the switching state of the first high-voltage depletion transistor 1011 in the cascaded structure 101 to be controlled based on the actual running direction of the voltage signal and current signal and other electrical energy signals sampled by the detection module 105.

[0033] The input terminal of the second driving module 103 is used to connect to the logic level, and the output terminal of the second driving module 103 is connected to the gate of the low-voltage enhancement transistor 1012.

[0034] Optionally, the second driving module 103 is used to access the logic level generated by the external logic circuit and control the switching state of the low-voltage enhancement transistor 1012 in the cascaded structure 101 to be controlled based on the logic level.

[0035] The detection module 105 is used to detect the voltage and current directions of the cascaded structure 101, and the action module 104 is used to control the first high-voltage depletion transistor 1011 to turn on when both the voltage and current directions are negative.

[0036] Optionally, the detection module 105 is used to detect the direction of the voltage signal and the direction of the current signal between the drain of the first high-voltage depletion-type transistor 1011 and the source of the low-voltage enhancement-type transistor 1012 in the cascaded structure 101 to be controlled. Specifically, the voltage direction refers to the sign of the voltage difference between the drain and source of the first high-voltage depletion-type transistor 1011, and the current direction refers to the direction of current flow between the drain and source of the first high-voltage depletion-type transistor 1011.

[0037] It should be noted that if both the voltage and current directions of the cascaded structure 101 are negative, then the cascaded structure 101 is currently operating in the third quadrant; if both the voltage and current directions of the cascaded structure 101 are positive, then the cascaded structure 101 is currently operating in the first quadrant.

[0038] Optionally, when the detection result obtained by the action module 104 from the detection module 105 via the third terminal indicates that the cascaded structure 101 is currently in the third quadrant, the action module 104 will start to control the first high-voltage depletion transistor 1011 in the cascaded structure 101 to conduct under the action of the pulse width modulation signal input by the first drive module 102, thereby realizing the reverse conduction control of the cascaded structure 101.

[0039] In this embodiment, a reverse conduction control circuit for the cascaded structure is formed by a cascaded structure to be controlled, a first driving module, a second driving module, an action module, and a detection module. The cascaded structure includes a first high-voltage depletion-type transistor and a low-voltage enhancement-type transistor. The drain of the first high-voltage depletion-type transistor is connected to a high-voltage power node, and the source of the first high-voltage depletion-type transistor is connected to the drain of the low-voltage enhancement-type transistor. The source of the low-voltage enhancement-type transistor is grounded. The input terminal of the first driving module is used to receive a pulse width modulation signal. The output terminal of the first driving module is connected to the first terminal of the action module. The second terminal of the action module is connected to the gate of the first high-voltage depletion-type transistor. The second terminal of the detection module is connected to the drain of the first high-voltage depletion-type transistor. The third terminal of the detection module and the fourth terminal of the action module are both connected to the source of the low-voltage enhancement-type transistor. The input terminal of the second driving module is used to receive a logic level, and the output terminal of the second driving module is connected to the gate of the low-voltage enhancement-type transistor. The detection module is used to detect the voltage and current directions of the cascaded structure. The action module is used to control the first high-voltage depletion-type transistor to conduct under the action of the pulse width modulation signal when both the voltage and current directions are negative. This simplifies the reverse conduction control strategy for gallium nitride power devices and reduces the cost of reverse conduction control for gallium nitride power devices.

[0040] An alternative implementation method is described in [reference]. Figure 2 and Figure 3 The action module 104 in the cascaded reverse conduction control circuit 10 provided in this application embodiment includes: a first resistor 1041, a second resistor 1042, a first diode 1043, and a PNP transistor 1044.

[0041] One end of the first resistor 1041 is connected to the output terminal of the first driving module 102. The collector of the PNP transistor 1044 is connected to the other end of the first resistor 1041 and the gate of the first high-voltage depletion-type transistor 1011. The base of the PNP transistor 1044 is connected to one end of the second resistor 1042. The emitter of the PNP transistor 1044 is connected to the source of the low-voltage enhancement-type transistor 1012.

[0042] Optionally, one end of the first resistor 1041 is connected to the output terminal of the first driving module 102 to receive the pulse width modulation signal obtained by the first driving module 102 from the external pulse width modulation generator; optionally, the other end of the first resistor 1041 is connected to the collector of the PNP transistor 1044 and the gate of the first high-voltage depletion-type transistor 1011, respectively; the base of the PNP transistor 1044 is connected to one end of the second resistor 1042; and the emitter of the PNP transistor 1044 is connected to the source of the low-voltage enhancement-type transistor 1012, i.e., connected to system ground or power ground.

[0043] The other end of the second resistor 1042 is connected to the anode of the first diode 1043, and the cathode of the first diode 1043 is connected to the first end of the detection module 105.

[0044] Optionally, the other end of the second resistor 1042 is connected to the anode of the first diode 1043, and the cathode of the first diode 1043 is connected to the first end of the detection module 105 to receive the detection result output by the detection module 105, that is, the trigger signal output by the detection module 105.

[0045] Specifically, when the detection module 105 detects that the cascaded structure 101 is operating in the third quadrant, that is, when the voltage and current directions between the drain and source of the cascaded structure 101 are both negative, the first terminal of the detection module 105 outputs a low-level signal to the action module 104. The low-level signal is transmitted to the base of the PNP transistor 1044 through the first diode 1043 and the second resistor 1042, causing the PNP transistor 1044 to conduct. At this time, the transmitter-collector path of the PNP transistor 1044 pulls the gate potential of the first high-voltage depletion-type transistor 1011 down to the source potential of the first high-voltage depletion-type transistor 1011, that is, down to the source potential of the low-voltage enhancement-type transistor 1012, thereby making the gate-source voltage of the first high-voltage depletion-type transistor 1011 close to zero, and the cascaded structure 101 enters a low reverse conduction voltage drop state, effectively reducing the reverse conduction loss during the dead time. Thus, the action module 104 achieves fast and reliable control of the gate of the first high-voltage depletion transistor 1011. The circuit structure is simple, requires no complex controller, and has good engineering implementation value.

[0046] In one alternative implementation, see [link to implementation details]. Figure 2 The detection module 105 in the cascaded reverse conduction control circuit 10 provided in this application embodiment includes: a second high-voltage depletion-type transistor 1051 and a first Zener diode 1052.

[0047] The gate of the second high-voltage depletion-type transistor 1051 and the anode of the first Zener diode 1052 are both connected to the source of the low-voltage enhancement-type transistor 1012. The drain of the second high-voltage depletion-type transistor 1051 is connected to the drain of the first high-voltage depletion-type transistor 1011. The source of the second high-voltage depletion-type transistor 1051 is connected to the cathode of the first Zener diode 1052 and to the cathode of the first diode 1043.

[0048] Optionally, the gate of the second high-voltage depletion-type transistor 1051 and the anode of the first Zener diode 1052 are both connected to the source of the low-voltage enhancement-type transistor 1012 in the cascaded structure 101, that is, they are all connected to system ground or power reference ground.

[0049] Optionally, the drain of the second high-voltage depletion-type transistor 1051 is connected to the drain of the first high-voltage depletion-type transistor 1011 to monitor the drain potential of the first high-voltage depletion-type transistor 1011 in the cascade structure 101.

[0050] Optionally, the source of the second high-voltage depletion-type transistor 1051 is connected to the cathode of the first Zener diode 1052, and at the same time, it is connected to the cathode of the first diode 1043 in the action module 104, for providing a trigger signal to the action module 104.

[0051] Specifically, when the cascaded structure 101 operates in the first quadrant, that is, when both the voltage and current directions between the drain of the first high-voltage depletion-type transistor 1011 and the source of the low-voltage enhancement-type transistor 1012 are positive, the drain voltage of the first high-voltage depletion-type transistor 1011 is positive, the current of the first high-voltage depletion-type transistor 1011 flows from the drain to the source, and the drain voltage of the first high-voltage depletion-type transistor 1011 is at a high potential. Simultaneously, the gate of the second high-voltage depletion-type transistor 1051 is grounded, the source of the second high-voltage depletion-type transistor 1051 is connected to ground potential through the first Zener diode 1052 and the operating module 104, and the drain is connected to a high potential. Therefore, the gate-source voltage of the second high-voltage depletion-type transistor 1051 is negative, and the second high-voltage depletion-type transistor 1051 is in the off state. At this time, the detection module 105 has no output signal, the action module 104 does not intervene, and the first high-voltage depletion transistor 1011 is normally controlled by the first drive module 102 to switch.

[0052] Specifically, when the cascaded structure 101 operates in the third quadrant, that is, when the drain potential of the first high-voltage depletion transistor 1011 in the cascaded structure 101 is negative, the current of the first high-voltage depletion transistor 1011 flows from the source to the drain, and the pulse width modulation signal connected to the first driving module 102 is at a low level, the drain of the first high-voltage depletion transistor 1011 presents a negative potential. At this time, the drain potential of the second high-voltage depletion transistor 1051 is negative, while the gate of the second high-voltage depletion transistor 1051 is grounded. The source of the second high-voltage depletion transistor 1051 is connected to the drain potential of the second high-voltage depletion transistor 1051 through the first Zener diode 1052. Therefore, the gate-source voltage of the second high-voltage depletion transistor 1051 becomes positively biased, and the gate-source voltage of the second high-voltage depletion transistor 1051 is greater than the preset threshold voltage, so the second high-voltage depletion transistor 1051 quickly turns on.

[0053] Furthermore, after the second high-voltage depletion transistor 1051 is turned on, the source potential of the second high-voltage depletion transistor 1051 is pulled down to the drain potential of the second high-voltage depletion transistor 1051. The negative potential of the drain of the second high-voltage depletion transistor is clamped by the first Zener diode 1052 and transmitted to the base of the PNP transistor 1044 through the first diode 1043 and the second resistor 1042, thereby triggering the action module 104 to be turned on, so as to realize the active control of the gate voltage of the first high-voltage depletion transistor 1011.

[0054] The forward voltage drop of the first Zener diode 1052 determines the voltage threshold for triggering the detection module 105. The detection module 105 will only operate effectively when the negative drain potential of the first high-voltage depletion transistor 1011 is lower than the negative threshold voltage.

[0055] Therefore, by selecting different voltage regulation values ​​for the first Zener diode 1052, or by connecting an additional Zener diode in series with the anode of the first Zener diode 1052, the action threshold voltage of the reverse conduction detection can be flexibly adjusted to meet the requirements of different application scenarios for dead zone loss and anti-interference capability.

[0056] In one alternative implementation, see [link to implementation details]. Figure 3 The detection module 105 in the cascaded reverse conduction control circuit 10 provided in this application embodiment includes: a third high-voltage depletion-type transistor 1053, a second Zener diode 1054, and a third Zener diode 1055.

[0057] The gate of the third high-voltage depletion-type transistor 1053 and the cathode of the third Zener diode 1055 are both connected to the source of the low-voltage enhancement-type transistor 1012. The drain of the third high-voltage depletion-type transistor 1053 is connected to the drain of the first high-voltage depletion-type transistor 1011. The source of the third high-voltage depletion-type transistor 1053 is connected to the cathode of the second Zener diode 1054 and to the cathode of the first diode 1043. The anode of the second Zener diode 1054 is connected to the anode of the third Zener diode 1055.

[0058] Optionally, the gate of the third high-voltage depletion-type transistor 1053 and the cathode of the third Zener diode 1055 are both connected to the source of the low-voltage enhancement-type transistor 1012 in the cascaded structure 101, that is, they are both connected to system ground or power reference ground.

[0059] Optionally, the drain of the third high-voltage depletion-type transistor 1053 is connected to the drain of the first high-voltage depletion-type transistor 1011 to monitor the drain potential of the cascaded structure 101.

[0060] Optionally, the source of the third high-voltage depletion-type transistor 1053 is connected to the cathode of the second Zener diode 1054, and is also connected to the cathode of the first diode 1043 in the action module 104, for providing a trigger signal to the action module 104.

[0061] In addition, the anode of the second Zener diode 1054 is connected to the anode of the third Zener diode 1055 to form a series structure.

[0062] Specifically, when the cascaded structure 101 operates in the third quadrant, that is, when the drain voltage of the first high-voltage depletion-type transistor 1011 in the cascaded structure 101 is negative, the current of the first high-voltage depletion-type transistor 1011 flows from the source to the drain, and the pulse width modulation signal obtained by the first driving module 102 from the external pulse width modulation generator is at a low level, the drain of the first high-voltage depletion-type transistor 1011 presents a negative potential. At this time, the drain potential of the third high-voltage depletion-type transistor 1053 is negative, while the gate of the third high-voltage depletion-type transistor 1053 is grounded. Therefore, the gate-source potential of the third high-voltage depletion-type transistor 1053 becomes positively biased, the gate-source voltage of the third high-voltage depletion-type transistor 1053 is greater than the preset threshold voltage, and the third high-voltage depletion-type transistor 1053 quickly turns on.

[0063] Furthermore, after the third high-voltage depletion-type transistor 1053 is turned on, its source potential is pulled low, forming a current path (flowing from system ground through the third Zener diode 1055 and the second Zener diode 1054 to the source of the third high-voltage depletion-type transistor 1053). Since the anodes of the second Zener diode 1054 and the third Zener diode 1055 are connected, their series connection jointly determines the clamping voltage of the source of the low-voltage enhancement-type transistor.

[0064] Furthermore, depending on the bias state of the Zener diodes, the clamping voltage can be the sum of the reverse breakdown voltages of the two Zener diodes, or a combination of a forward voltage drop and a reverse breakdown voltage, etc. This application does not make any specific limitations on this.

[0065] In one alternative implementation, see [link to implementation details]. Figure 4 The action module 104 in the cascaded reverse conduction control circuit 10 provided in this application embodiment includes: a third resistor 1045, a fourth resistor 1046, a fifth resistor 1047, and a P-type metal-oxide-semiconductor transistor 1048.

[0066] One end of the third resistor 1045 is connected to the output terminal of the first driving module 102. The drain of the P-type metal-oxide-semiconductor transistor 1048 is connected to the other end of the third resistor 1045 and the gate of the first high-voltage depletion-type transistor 1011. The source of the P-type metal-oxide-semiconductor transistor 1048 and the other end of the fourth resistor 1046 are both connected to the source of the low-voltage enhancement-type transistor 1012. The gate of the P-type metal-oxide-semiconductor transistor 1048 is connected to one end of the fourth resistor 1046 and one end of the fifth resistor 1047. The other end of the fifth resistor 1047 is connected to the first terminal of the detection module 105.

[0067] Optionally, one end of the third resistor 1045 is connected to the output terminal of the first driving module 102 to receive the pulse width modulation signal; the other end of the third resistor 1045 is connected to the drain of the P-type metal-oxide-semiconductor transistor 1048 and the gate of the first high-voltage depletion-type transistor 1011 respectively; the source of the P-type metal-oxide-semiconductor transistor 1048 is connected to the other end of the fourth resistor 1046 and together connected to the source of the low-voltage enhancement-type transistor 1012, i.e., system ground or power reference ground.

[0068] Optionally, the gate of the P-type metal-oxide-semiconductor transistor 1048 is connected to one end of the fourth resistor 1046 and one end of the fifth resistor 1047, respectively; the other end of the fifth resistor 1047 is connected to the first end of the detection module 105 for receiving the trigger signal output by the detection module 105.

[0069] Specifically, under normal operating conditions, the pulse width modulation signal output by the first driving module 102 controls the gate of the first high-voltage depletion-type transistor 1011 through the third resistor 1045, achieving normal switching operation. At this time, since the detection module 105 does not detect that the cascaded structure 101 is in the third quadrant state, the first terminal of the detection module 105 outputs a high level, and the fifth resistor 1047 pulls the gate of the P-type metal-oxide-semiconductor transistor 1048 up to the source potential (ground) of the low-voltage enhancement-type transistor 1012 through the fourth resistor 1046. Therefore, the P-type metal-oxide-semiconductor transistor 1048 remains in the off state, which does not affect the normal switching of the first high-voltage depletion-type transistor 1011.

[0070] Optionally, when the cascaded structure 101 operates in the third quadrant and the output of the first driving module 102 is low, the detection module 105 detects that the first high-voltage depletion transistor 1011 is in reverse conduction state. The first terminal of the detection module 105 outputs a low-level signal, which is transmitted to the gate of the P-type metal-oxide-semiconductor transistor 1048 through the fifth resistor 1047, making its gate-source voltage negative (that is, the gate potential of the P-type metal-oxide-semiconductor transistor 1048 is lower than the source potential), satisfying the conduction condition of the P-type metal-oxide-semiconductor transistor 1048, and the P-type metal-oxide-semiconductor transistor 1048 quickly conducts.

[0071] Furthermore, when the P-type metal-oxide-semiconductor transistor 1048 is turned on, its drain potential is pulled down to near its source potential, thereby pulling down the gate of the first high-voltage depletion-type transistor 1011 to ground potential, making its gate-source voltage close to zero. At this time, the first high-voltage depletion-type transistor 1011 enters the conducting state, and the reverse current mainly flows through its channel, greatly reducing the reverse conduction voltage drop, thereby significantly reducing the reverse conduction loss during the dead time.

[0072] It should be noted that the third resistor 1045 serves as a gate drive resistor, limiting the charging and discharging current of the gate of the first high-voltage depletion-type transistor 1011 to prevent overshoot, and also matching the output impedance of the first drive module 102; the fourth resistor 1046 serves as a pull-up resistor, stabilizing the gate of the P-type metal-oxide-semiconductor transistor 1048 at the source potential in the non-operating state, ensuring reliable cutoff of the P-type metal-oxide-semiconductor transistor 1048 and avoiding false triggering; the fifth resistor 1047 serves as a current-limiting resistor, limiting the current between the output terminal of the detection module 105 and the gate of the P-type metal-oxide-semiconductor transistor 1048, and also forming a voltage divider network with the fourth resistor 1046 to adjust the amplitude and response speed of the gate drive voltage.

[0073] In one alternative implementation, see [link to implementation details]. Figure 4 The detection module 105 in the cascaded reverse conduction control circuit 10 provided in this application embodiment includes: a fourth high-voltage depletion-type transistor 1056, a fourth Zener diode 1057, and a second diode 1058.

[0074] The anode of the second diode 1058 is connected to the other end of the fifth resistor 1047, and the cathode of the fourth Zener diode 1057 is connected to the source of the fourth high-voltage depletion-type transistor 1056 and to the cathode of the second diode 1058.

[0075] Optionally, the anode of the second diode 1058 is connected to the other end of the fifth resistor 1047 in the action module 104 to provide a trigger signal to the action module 104; the cathode of the fourth Zener diode 1057 is connected to the source of the fourth high-voltage depletion transistor 1056 and to the cathode of the second diode 1058.

[0076] The gate of the fourth high-voltage depletion-type transistor 1056 and the anode of the fourth Zener diode 1057 are both connected to the source of the low-voltage enhancement-type transistor 1012, and the drain of the fourth high-voltage depletion-type transistor 1056 is connected to the drain of the first high-voltage depletion-type transistor 1011.

[0077] Optionally, the gate of the fourth high-voltage depletion-type transistor 1056 and the anode of the fourth Zener diode 1057 are connected to the source of the low-voltage enhancement-type transistor 1012, i.e., they are all connected to system ground or power reference ground; the drain of the fourth high-voltage depletion-type transistor 1056 is connected to the drain of the first high-voltage depletion-type transistor 1011 for monitoring the drain potential of the cascaded structure 101.

[0078] Specifically, when the cascaded structure 101 operates in the first quadrant, the drain of the first high-voltage depletion-type transistor 1011 is at a high potential. At this time, the drain of the fourth high-voltage depletion-type transistor 1056 is at a high potential, while the gate of the fourth high-voltage depletion-type transistor 1056 is grounded. The gate-source voltage of the fourth high-voltage depletion-type transistor 1056 is negative, therefore, the fourth high-voltage depletion-type transistor 1056 is in the off state.

[0079] Furthermore, the source of the fourth high-voltage depletion transistor 1056 is connected to ground through the fourth Zener diode 1057. However, since the fourth high-voltage depletion transistor 1056 is turned off, no current flows, the detection module 105 has no output signal, the action module 104 does not intervene, and the first high-voltage depletion transistor 1011 is normally controlled by the first drive module 102 to switch.

[0080] Specifically, when the cascaded structure 101 operates in the third quadrant and the pulse width modulation signal obtained by the first driving module 102 from the external pulse width modulation generator is low, the drain voltage of the first high-voltage depletion-type transistor 1011 is negative. At this time, the drain potential of the fourth high-voltage depletion-type transistor 1056 is negative, and the gate of the fourth high-voltage depletion-type transistor 1056 is grounded. Therefore, the gate-source voltage of the fourth high-voltage depletion-type transistor 1056 becomes forward biased, and the gate-source voltage of the fourth high-voltage depletion-type transistor 1056 is greater than the preset threshold voltage, causing the fourth high-voltage depletion-type transistor 1056 to quickly turn on.

[0081] Furthermore, after the fourth high-voltage depletion-type transistor 1056 is turned on, its source potential is pulled down to its drain negative potential, forming a current path (flowing from system ground through the fourth Zener diode 1057 and the second Zener diode 1054 to the source of the fourth high-voltage depletion-type transistor 1056). Since the fourth Zener diode 1057 is in a forward bias state at this time, its forward conduction voltage drop clamps the source voltage of the fourth high-voltage depletion-type transistor 1056 at a preset negative voltage, which is the trigger signal output by the detection module 105. This trigger signal is transmitted to the gate of the P-type metal-oxide-semiconductor transistor 1048 through the second diode 1058 and the fifth resistor 1047.

[0082] Due to the unidirectional conductivity of the second diode 1058, it allows negative signals to be transmitted from the detection module 105 to the action module 104, while preventing the signals from the action module 104 from affecting the detection module 105 in the reverse direction, thus playing the role of isolation and unidirectional transmission.

[0083] In one alternative implementation, see [link to implementation details]. Figure 5 In the reverse conduction control circuit 10 of the cascaded structure provided in this application embodiment, the first high-voltage depletion transistor 1011 in the cascaded structure 101 and the high-voltage depletion transistor in the detection module 105 are integrated on the same gallium nitride epitaxial wafer.

[0084] Optionally, the high-voltage depletion transistor in the detection module 105 can be any one of the second high-voltage depletion transistor 1051, the third high-voltage depletion transistor 1053, and the fourth high-voltage depletion transistor 1056. This application does not specifically limit this.

[0085] Optionally, the first high-voltage depletion-type transistor 1011 and each high-voltage depletion-type transistor in the detection module 105 are both based on a gallium nitride high electron mobility transistor structure. Through selective region doping, gate formation, and source / drain electrode fabrication processes performed on the same epitaxial wafer, high-voltage depletion-type devices with the same epitaxial layer structure are simultaneously formed. These devices share the same gallium nitride epitaxial layer, including but not limited to a nucleation layer, buffer layer, channel layer, barrier layer, and capping layer.

[0086] Specifically, on the gallium nitride epitaxial wafer, different active regions are divided using region isolation technology, which are used to form the first high-voltage depletion transistor 1011 in the cascade structure 101 and the high-voltage depletion transistors obtained in the detection module 105.

[0087] Furthermore, since all high-voltage depletion-type transistors are fabricated on the same epitaxial wafer, they have highly consistent device characteristics, including key parameters such as threshold voltage, transconductance resistance, breakdown voltage, and on-resistance. This enables the high-voltage depletion-type transistor in the detection module 105 to accurately replicate the potential change of the first high-voltage depletion-type transistor 1011, thereby achieving high-fidelity state detection.

[0088] In one alternative implementation, see [link to implementation details]. Figure 6 The first driving module 102 in the cascaded reverse conduction control circuit 10 provided in this application embodiment includes a first driving chip 1021, and the second driving module 103 includes a second driving chip 1031.

[0089] The input terminal of the first driver chip 1021 is used to receive the pulse width modulation signal, and the output terminal of the first driver chip 1021 is connected to the first terminal of the action module 104.

[0090] Optionally, the input terminal of the first driver chip 1021 is used to receive a pulse width modulation signal, which is generated by an external controller and used to control the switching timing and duty cycle of the entire cascaded structure 101.

[0091] Optionally, the output terminal of the first driving chip 1021 is connected to the first terminal of the action module 104 to transmit the pulse width modulation signal after driving enhancement to the gate of the first high voltage depletion transistor 1011, so as to achieve precise control over its turn-on or turn-off.

[0092] The input terminal of the second driver chip 1031 is used to connect to the logic level, and the output terminal of the second driver chip 1031 is connected to the gate of the low-voltage enhancement-mode transistor 1012.

[0093] Optionally, the input terminal of the second driver chip 1031 is used to connect to a logic level, and the output terminal of the second driver chip 1031 is directly connected to the gate of the low-voltage enhancement transistor 1012 to control the turn-on and turn-off of the low-voltage enhancement transistor 1012.

[0094] Optionally, when the cascaded structure 101 is operating normally, the logic level received by the second driver chip 1031 is usually high, causing the second driver chip 1031 to output a high level to the gate of the low-voltage enhancement-type transistor 1012, keeping it in its normally open state. At this time, the switching characteristics of the cascaded structure 101 are mainly determined by the first high-voltage depletion-type transistor 1011, and the first driver chip 1021 controls the gate of the first high-voltage depletion-type transistor 1011 according to the pulse width modulation signal to realize the normal power switching function.

[0095] Optionally, when the reverse conduction control circuit of the cascaded structure enters the protection mode or undervoltage state, the logic level becomes low, the second driver chip 1031 outputs a low level, turns off the low-voltage enhancement transistor 1012, thereby cutting off the current path of the cascaded structure 101 and realizing the safety protection of the system.

[0096] Optionally, the first driver chip 1021 and the second driver chip 1031 may be dedicated driver chips adapted to the characteristics of gallium nitride devices, with functions such as high peak current, fast propagation delay, precise gate voltage clamping and undervoltage lockout protection, to ensure reliable driving of the cascaded structure 101.

[0097] It should be noted that the first driver chip 1021, as the driver of the first high-voltage depletion-type transistor 1011, is responsible for converting the low-voltage pulse-width modulation signal into a gate voltage suitable for driving the first high-voltage depletion-type transistor 1011. Its output typically adopts a push-pull structure to provide sufficient gate charging and discharging current, ensuring that the first high-voltage depletion-type transistor 1011 can switch quickly and reduce switching losses. Simultaneously, the first driver chip 1021 integrates a level-shifting function to adapt to the gate driving requirements of the depletion-type transistor.

[0098] Optionally, the second driver chip 1031 serves as the driver for the low-voltage enhancement transistor 1012 in the cascaded structure 101. Its output logic level is matched with the threshold voltage of the low-voltage enhancement transistor 1012. The second driver chip 1031 can independently control the conduction or turn-off of the low-voltage enhancement transistor 1012, achieving rapid turn-off in circuit startup, protection, or fault conditions, thereby improving circuit safety.

[0099] In one optional implementation, the clamping duration of the gate potential of the first high-voltage depletion transistor 1011 by the action module 104 in the cascaded reverse conduction control circuit 10 provided in this application embodiment is synchronized with the duration of the reverse current flowing through the first high-voltage depletion transistor 1011.

[0100] Optionally, when the cascaded structure 101 is operating in the third quadrant, the detection module 105 detects the drain potential of the first high-voltage depletion transistor 1011 in real time. Once the drain potential of the first high-voltage depletion transistor 1011 is detected to be lower than the preset threshold voltage, the detection module 105 immediately outputs a trigger signal to trigger the action module 104 to act immediately.

[0101] Optionally, after receiving the trigger signal, the action module 104 quickly pulls the gate potential of the first high-voltage depletion transistor 1011 down to the source potential, so that the gate-source voltage of the first high-voltage depletion transistor 1011 is close to 0, and the cascaded structure enters the conduction state, providing a low-resistance channel for reverse current.

[0102] The clamping effect of the action module 104 on the gate potential is not of a fixed duration, but is determined by the continuous state of the trigger signal of the detection module 105. As long as the detection module 105 detects that the drain voltage is lower than the preset threshold voltage, the trigger signal remains valid, and the action module 104 maintains the clamping of the gate. Once the reverse current terminates and the drain voltage rises back above the preset threshold voltage, the trigger signal of the detection module 105 is withdrawn, the action module 104 immediately releases the clamp, and the gate potential of the first high-voltage depletion-type transistor 1011 returns to normal control by the first driving module 102.

[0103] In one alternative implementation, see [link to implementation details]. Figure 7 and Figure 8 The reverse conduction voltage drop of the reverse conduction control circuit 10 in this application is significantly reduced, and the switching loss of the cascaded structure is greatly reduced.

[0104] Figure 9 A power converter provided in this application, see [link to relevant documentation]. Figure 9 This application provides a power converter 20 including at least one reverse conduction control circuit 10 of the above-described cascaded structure.

[0105] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0106] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A cascaded reverse conduction control circuit, characterized in that, include: The cascaded structure to be controlled includes a first driving module, a second driving module, an action module, and a detection module. The cascaded structure includes a first high-voltage depletion-type transistor and a low-voltage enhancement-type transistor, wherein the source of the first high-voltage depletion-type transistor is connected to the drain of the low-voltage enhancement-type transistor. The input terminal of the first driving module is used to receive a pulse width modulation signal. The output terminal of the first driving module is connected to the first terminal of the action module. The second terminal of the action module is connected to the gate of the first high-voltage depletion-type transistor. The third terminal of the action module is connected to the first terminal of the detection module. The second terminal of the detection module is connected to the drain of the first high-voltage depletion-type transistor. The third terminal of the detection module and the fourth terminal of the action module are both connected to the source of the low-voltage enhancement-type transistor. The input terminal of the second driving module is used to connect to a logic level, and the output terminal of the second driving module is connected to the gate of the low-voltage enhancement-mode transistor. The detection module is used to detect the voltage direction and current direction of the cascaded structure, and the action module is used to control the first high-voltage depletion transistor to turn on when both the voltage direction and the current direction are negative.

2. The reverse conduction control circuit of the cascaded structure according to claim 1, characterized in that, The action module includes: a first resistor, a second resistor, a first diode, and a PNP transistor; One end of the first resistor is connected to the output terminal of the first driving module, the collector of the PNP transistor is connected to the other end of the first resistor and the gate of the first high-voltage depletion-type transistor, the base of the PNP transistor is connected to one end of the second resistor, and the emitter of the PNP transistor is connected to the source of the low-voltage enhancement-type transistor. The other end of the second resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the first end of the detection module.

3. The reverse conduction control circuit of the cascaded structure according to claim 2, characterized in that, The detection module includes: a second high-voltage depletion-type transistor and a first Zener diode; The gate of the second high-voltage depletion-type transistor and the anode of the first Zener diode are both connected to the source of the low-voltage enhancement-type transistor. The drain of the second high-voltage depletion-type transistor is connected to the drain of the first high-voltage depletion-type transistor. The source of the second high-voltage depletion-type transistor is connected to the cathode of the first Zener diode and to the cathode of the first diode.

4. The reverse conduction control circuit of the cascaded structure according to claim 2, characterized in that, The detection module includes: a third high-voltage depletion-type transistor, a second Zener diode, and a third Zener diode; The gate of the third high-voltage depletion-type transistor and the cathode of the third Zener diode are both connected to the source of the low-voltage enhancement-type transistor. The drain of the third high-voltage depletion-type transistor is connected to the drain of the first high-voltage depletion-type transistor. The source of the third high-voltage depletion-type transistor is connected to the cathode of the second Zener diode and to the cathode of the first diode. The anode of the second Zener diode is connected to the anode of the third Zener diode.

5. The reverse conduction control circuit of the cascaded structure according to claim 1, characterized in that, The actuation module includes: a third resistor, a fourth resistor, a fifth resistor, and a P-type metal-oxide-semiconductor transistor; One end of the third resistor is connected to the output terminal of the first driving module. The drain of the P-type metal-oxide-semiconductor transistor is connected to the other end of the third resistor and the gate of the first high-voltage depletion-type transistor. The source of the P-type metal-oxide-semiconductor transistor and the other end of the fourth resistor are both connected to the source of the low-voltage enhancement-type transistor. The gate of the P-type metal-oxide-semiconductor transistor is connected to one end of the fourth resistor and one end of the fifth resistor. The other end of the fifth resistor is connected to the first terminal of the detection module.

6. The reverse conduction control circuit of the cascaded structure according to claim 5, characterized in that, The detection module includes: a fourth high-voltage depletion-type transistor, a fourth Zener diode, and a second diode; The anode of the second diode is connected to the other end of the fifth resistor, and the cathode of the fourth Zener diode is connected to the source of the fourth high-voltage depletion-type transistor and to the cathode of the second diode. The gate of the fourth high-voltage depletion-type transistor and the anode of the fourth Zener diode are both connected to the source of the low-voltage enhancement-type transistor, and the drain of the fourth high-voltage depletion-type transistor is connected to the drain of the first high-voltage depletion-type transistor.

7. The reverse conduction control circuit of the cascaded structure according to any one of claims 1-6, characterized in that, The first high-voltage depletion-type transistor in the cascaded structure and the high-voltage depletion-type transistor in the detection module are integrated on the same gallium nitride epitaxial wafer.

8. The reverse conduction control circuit of the cascaded structure according to claim 1, characterized in that, The first driving module includes a first driving chip; the second driving module includes a second driving chip. The input terminal of the first driver chip is used to receive a pulse width modulation signal, and the output terminal of the first driver chip is connected to the first terminal of the action module. The input terminal of the second driver chip is used to connect to a logic level, and the output terminal of the second driver chip is connected to the gate of the low-voltage enhancement-mode transistor.

9. The reverse conduction control circuit of the cascaded structure according to claim 1, characterized in that, The duration of the clamping of the gate potential of the first high-voltage depletion transistor by the action module is synchronized with the duration of the reverse current flowing through the first high-voltage depletion transistor.

10. A power converter, characterized in that, The power converter includes at least one reverse conduction control circuit of the cascaded structure as described in any one of claims 1-9.

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