Dual random dithering frequency and adaptive slope compensation circuit and method for switching power supply

Abstract

This invention relates to the field of switching power supply control technology, and discloses a method and circuit for dual random frequency dithering and adaptive slope compensation in switching power supplies. The method generates a dual-layer independent random sequence based on pseudo-random numbers, and generates a slow random triangular wave frequency dithering signal and a fast random jump frequency dithering signal through layered mapping. The switching cycle duration is obtained through cycle counting and numerical conversion, and the target duty cycle is calculated by combining the input voltage and output voltage reference values. Using the target duty cycle, switching cycle, and system parameters, an adaptive compensation slope value is calculated through a lookup table combined with interpolation or formulas. A digital compensation slope is generated based on the smoothed compensation slope and the cycle synchronization signal. This slope is digitally added to and compared with the inductor current sampling signal to achieve stable LED drive current output. This invention maintains stable output current while effectively suppressing broadband electromagnetic interference, and is suitable for high-reliability applications such as automotive LED drives.

Description

Technical Field

[0001] This invention relates to the field of switching power supply control technology, and more specifically, to a dual random frequency dithering and adaptive slope compensation circuit and method for switching power supplies. Background Technology

[0002] Switching power supplies are widely used in automotive electronic systems, especially in LED driver applications, due to their high efficiency and miniaturization. However, switching power supplies generate fixed-frequency switching noise during operation. This noise manifests as concentrated energy peaks at the fundamental frequency and its harmonics in the frequency domain, which can easily cause electromagnetic interference to sensitive circuits such as in-vehicle communication systems and audio systems, affecting the overall vehicle's electromagnetic compatibility (EMC) performance. Traditional fixed-frequency control methods are insufficient to meet increasingly stringent automotive EMC standards.

[0003] To reduce electromagnetic interference, existing technologies employ frequency dithering to vary the switching frequency within a certain range, dispersing interference energy across a wide frequency band. However, a single frequency dithering method suffers from insufficient energy dispersion, potentially still generating interference peaks in certain frequency bands. Simultaneously, current-mode controlled switching power supplies are prone to subharmonic oscillations when the duty cycle exceeds 50%, necessitating slope compensation. Traditional slope compensation uses a fixed slope; however, when the switching frequency changes due to dithering, the fixed slope cannot adapt to the compensation requirements at different frequencies. This can lead to insufficient compensation at certain frequency points, causing oscillations, or overcompensation, resulting in poor dynamic response and affecting the stability of the output current.

[0004] Therefore, existing technologies suffer from insufficient frequency dithering and slope compensation that cannot adapt to frequency changes, making it difficult to ensure output stability while achieving good electromagnetic compatibility. This limits the performance of switching power supplies in applications such as high-end automotive LED drivers. Summary of the Invention

[0005] This invention provides a dual random frequency dithering and adaptive slope compensation circuit and method for switching power supplies, which solves the technical problems in related technologies where insufficient frequency dithering effect and slope compensation cannot adapt to frequency changes, making it difficult to achieve good electromagnetic compatibility and output stability at the same time.

[0006] This invention provides a method for dual random frequency dithering and adaptive slope compensation in switching power supplies, comprising the following steps: S1, based on the pseudo-random number generator, generates a two-layer independent random sequence, and uses a layered mapping method to obtain a slow random triangular wave dithering signal and a fast random jump dithering signal; S2, based on the real-time operating frequency signal and the system clock, uses cycle counting and numerical conversion methods to obtain the time length value of the current switching cycle; S3, based on the input voltage sample value and the output voltage reference value, uses digital division or lookup table method to obtain the target duty cycle value required to maintain output stability; S4. Based on the target duty cycle value, the current switching cycle value, and system parameters, the adaptive adjustment compensation slope value is obtained by using a lookup table combined with interpolation or parameterized formula calculation method. S5, based on the smoothed adaptive compensation slope value and the switching cycle synchronization signal, adopts the digital slope generation method to obtain a compensation slope signal that matches the current operating frequency; S6, based on the compensation ramp signal and the inductor current sampling signal, uses digital addition and comparison control methods to obtain a stable LED drive current output.

[0007] In a preferred embodiment, the step of generating a two-layer independent random sequence based on a pseudo-random number generator, and using a layered mapping method to obtain a slow random triangular wave dithering signal and a fast random jump dithering signal, includes: A first pseudo-random number generator and a second pseudo-random number generator are constructed based on a linear feedback shift register. Different primitive polynomials are used to configure the feedback structure to obtain the first pseudo-random sequence and the second pseudo-random sequence. Based on the first pseudo-random sequence, a numerical range mapping method is used to map it to the periodic time range of a triangular wave. A slow random triangular wave is constructed using a triangular wave generation circuit, which includes a rising counter, a falling counter, and a control state machine, to obtain a slow random triangular wave dithering signal. Based on the second pseudo-random sequence, a fixed time interval sampling mechanism is adopted, and a timer counter is used to trigger the timed sampling. The pseudo-random number is mapped to the frequency offset range of rapid jump, and a rapid random jump frequency dithering signal is obtained. Based on the reference frequency setting, the slow random triangular wave dithering signal, and the fast random jumping dithering signal, a digital adder is used to superimpose the values ​​of the three signals, and a numerically controlled oscillator is used to convert the frequency to a clock signal to obtain a real-time operating frequency signal with dual random characteristics.

[0008] In a preferred embodiment, the step of obtaining the time length value of the current switching cycle based on the real-time operating frequency signal and the system clock, using cycle counting and numerical conversion methods, includes: Based on the real-time operating frequency signal, an edge detection circuit is used to identify the rising and falling edges of the signal. The rising edge detection signal is used as the start trigger signal of the switching cycle, and the falling edge detection signal is used as the end trigger signal of the cycle. Based on the start trigger signal of the switching cycle, the count value of the cycle counter is cleared to zero. Based on the system clock signal, a synchronous increment counting method is adopted. When the end trigger signal of the cycle is detected, the count value is latched into the cycle value register to obtain the clock pulse count value within the cycle. The time length of the current switching cycle is obtained by multiplying the clock pulse count value within the cycle with the system clock cycle. Data timing alignment is achieved using a pipelined register set, and data delay transmission is achieved using a two-level register set to obtain periodic data for slope compensation calculation.

[0009] In a preferred embodiment, obtaining the target duty cycle value required to maintain output stability based on the input voltage sample value and the output voltage reference value using digital division or a lookup table method includes: The input voltage is sampled using a resistor divider network, analog-to-digital conversion is performed using an ADC, and noise suppression is achieved using a digital filter to obtain the digital sample value of the input voltage. Based on the output voltage reference value, the digital reference value of the output voltage is obtained using the same numerical unit and fixed-point number format as the input voltage sampling value; Based on the volt-second balance principle of Buck-type switching power supplies, a digital divider is used to divide the digital reference value of the output voltage by the digital sample value of the input voltage to obtain the digital representation of the target duty cycle. Based on the digital representation of the target duty cycle, a range limiting circuit is used for numerical constraints to set the minimum and maximum values ​​of the duty cycle, thereby obtaining the target duty cycle value used for slope compensation calculation.

[0010] In a preferred embodiment, the step of obtaining the adaptively adjusted compensation slope value based on the target duty cycle value, the current switching cycle value, and system parameters, using a lookup table combined with interpolation or parameterized formula calculation methods, includes: Based on the inductance value and the output voltage reference value, the inductance current slope calculation formula is used. In a Buck-type switching power supply, the falling slope of the inductance current is equal to the output voltage divided by the inductance value, thus obtaining the falling slope value of the inductance current. Based on the subharmonic oscillation theory of current mode control, the stability criterion is adopted to calculate the duty cycle correlation coefficient. The duty cycle correlation coefficient is multiplied by the inductor current drop slope and then multiplied by the preset margin coefficient to obtain the reference compensation slope value. Based on the period normalization method, an adjustment strategy in which the compensation slope is inversely proportional to the switching period is adopted. The frequency adjustment coefficient is obtained by dividing the reference switching period by the current switching period. The frequency adjustment coefficient is multiplied by the reference compensation slope value to obtain the adaptive compensation slope value that is adapted to the current frequency. Smoothing is performed based on a first-order IIR filter. A weighted average method is used to calculate the adaptive compensation slope value calculated in the current cycle and the compensation slope value used in the previous cycle, resulting in a smoothed adaptive compensation slope value.

[0011] In a preferred embodiment, obtaining the adaptive compensation slope value adapted to the current frequency based on the period normalization method further includes: During the system initialization phase, based on the possible switching cycle range, the frequency adjustment coefficients corresponding to different switching cycles are pre-calculated using an offline calculation method, and the results are stored in a lookup table. Based on the current switching cycle value, the corresponding frequency adjustment coefficient is directly obtained by using a lookup table read operation; Based on the adjustment coefficients and baseline compensation slope values ​​read from the lookup table, a digital multiplier is used to perform multiplication operations to obtain the adaptive compensation slope value.

[0012] In a preferred embodiment, the step of obtaining a compensation ramp signal matching the current operating frequency using a digital ramp generation method based on the smoothed adaptive compensation slope value and the switching cycle synchronization signal includes: Based on the start trigger signal of the switching cycle, the register of the accumulator is cleared to zero by the register reset operation to obtain the initial zero value state of the ramp generator; The slope increment per clock cycle is obtained by multiplying the smoothed adaptive compensation slope value by the system clock cycle time. Based on the slope increment value, the accumulator adds the current accumulated value to the slope increment value at each rising edge of the system clock to obtain a real-time increasing digital ramp signal. Based on the digital ramp signal, a moving average filter is used to suppress high-frequency noise, and an output buffer register is used for timing alignment to obtain a compensated ramp signal for current control.

[0013] In a preferred embodiment, the step of obtaining a stable LED drive current output based on the compensated ramp signal and the inductor current sampling signal, using digital addition and comparison control methods, includes: The analog signal of the inductor current is obtained by acquiring the current sensing resistor or Hall sensor, and the analog-to-digital conversion is performed by a high-speed ADC. The noise is suppressed by digital signal processing methods to obtain the digital sample value of the inductor current. Based on the compensation ramp signal and the digital sampled value of the inductor current, a digital adder is used to superimpose the values ​​of the two signals to obtain the superimposed control signal. Based on the output current reference value, the digital reference value for current control is obtained by using the same numerical unit and fixed-point number format as the control signal. The superimposed control signal is compared with the current reference value in real time using a digital comparator. When the control signal is greater than or equal to the current reference value, a turn-off command is generated. The turn-on and turn-off control logic of the switching transistor is constructed using an RS flip-flop to obtain the switching transistor control command.

[0014] In a preferred embodiment, obtaining a stable LED drive current output further includes: Based on the conduction state of the switching transistor, an inductor energy storage mechanism is adopted, and the inductor current increases linearly. Based on the off state of the switching transistor, a freewheeling diode freewheeling mechanism is adopted, and the inductor current decreases linearly. Based on the output capacitor connected in parallel across the LED load, the pulsating component of the inductor current is filtered, and the duty cycle is kept stable through an adaptive slope compensation mechanism to ensure that the energy stored and released by the inductor remains balanced in each switching cycle, so that the average value of the output current remains constant. Based on the current feedback closed-loop regulation mechanism, the duty cycle is automatically adjusted when the output current deviates from the reference value, so that the output current returns to the reference value and a stable LED drive current output is obtained.

[0015] In a preferred embodiment, a dual random frequency dithering and adaptive slope compensation circuit for a switching power supply is used to perform the steps in the aforementioned dual random frequency dithering and adaptive slope compensation method for a switching power supply, including: The signal generation module generates a two-layer independent random sequence based on a pseudo-random number generator, and uses a layered mapping method to obtain a slow random triangular wave dithering signal and a fast random jump dithering signal. The switching cycle detection module, based on the real-time operating frequency signal and the system clock, uses cycle counting and numerical conversion methods to obtain the time length value of the current switching cycle; The target duty cycle calculation module, based on the input voltage sample value and the output voltage reference value, uses digital division or lookup table method to obtain the target duty cycle value required to maintain output stability; The slope calculation module, based on the target duty cycle value, the current switching cycle value, and system parameters, uses a lookup table combined with interpolation or parameterized formula calculation method to obtain the adaptively adjusted compensation slope value; The compensation ramp signal generation module, based on the smoothed adaptive compensation ramp value and the switching cycle synchronization signal, uses a digital ramp generation method to obtain a compensation ramp signal that matches the current operating frequency. The mode control and output module, based on the compensation ramp signal and the inductor current sampling signal, uses digital addition and comparison control methods to obtain a stable LED drive current output.

[0016] The beneficial effects of this invention are as follows: A dual-layer random frequency dithering mechanism is employed. Slow, random triangular waves are used to achieve wideband energy expansion, while rapid, random frequency jumps refine and disperse the spectrum. The two dithering layers operate independently yet collaboratively, effectively dispersing the interference energy of the switching frequency across a wide bandwidth and preventing concentrated interference peaks. Compared to a single dithering method, dual-layer random frequency dithering more significantly reduces electromagnetic interference peaks, improves electromagnetic compatibility performance, meets stringent automotive electronic electromagnetic compatibility standards, and is suitable for electromagnetically sensitive applications such as high-end automotive LED drivers. An adaptive slope compensation technique is employed, dynamically adjusting the compensation slope based on real-time detected switching cycles to maintain a proper match between the compensation slope and the switching frequency. Through a period normalization method, the compensation slope is adjusted accordingly when the frequency changes due to frequency jitter, ensuring appropriate compensation at different frequencies. This avoids both subharmonic oscillations caused by insufficient compensation and deteriorated dynamic response caused by overcompensation. The adaptive compensation mechanism guarantees the stability of the duty cycle under frequency jitter conditions, ensuring the output current is unaffected by frequency changes. This achieves a balance between electromagnetic compatibility optimization and output stability control, improving system reliability and control accuracy. Attached Figure Description

[0017] Figure 1 This is a flowchart of a dual random frequency dithering and adaptive slope compensation method for a switching power supply according to the present invention. Detailed Implementation

[0018] The subject matter described herein will now be discussed with reference to exemplary embodiments. It should be understood that these embodiments are discussed only to enable those skilled in the art to better understand and implement the subject matter described herein, and changes may be made to the function and arrangement of the elements discussed without departing from the scope of this specification. Various processes or components may be omitted, substituted, or added as needed in the examples. Furthermore, some features described in the examples may be combined in other examples.

[0019] At least one embodiment of the present invention discloses a method for dual random frequency dithering and adaptive slope compensation of a switching power supply, such as... Figure 1 As shown, it includes the following steps: S1, based on the pseudo-random number generator, generates a two-layer independent random sequence, and uses a layered mapping method to obtain a slow random triangular wave dithering signal and a fast random jump dithering signal; Based on the system clock signal and the reference frequency setting, a dual-channel pseudo-random number generation method is used to obtain two independent random frequency dithering signals, so as to achieve a two-layer dispersion of switching frequency interference energy.

[0020] S11. Construct a first pseudo-random number generator based on a linear feedback shift register, and use a primitive polynomial to configure the feedback structure to obtain the first pseudo-random sequence; Based on digital logic circuits, a first pseudo-random number generator is constructed using a linear feedback shift register architecture. A 16-bit shift register is selected as the basic structure, consisting of 16 cascaded D flip-flops, each storing one bit of binary data. A primitive polynomial is used as the feedback polynomial, specifically x. 16+x 14+x 13+x The feedback structure corresponding to the polynomial 11+1 is to perform an XOR operation on the outputs of the 16th, 14th, 13th and 11th bits, and then feed the result back to the input of the 1st bit.

[0021] Driven by the system clock signal, the shift register employs a synchronous triggering method. At each rising edge of the clock, each flip-flop latches the data from the previous stage into the current stage, while the first bit receives a feedback signal. Through this shift and feedback operation, the state of the shift register changes once per clock cycle. Because it uses a primitive polynomial, this shift register can traverse all possible states except the all-zero state, generating a pseudo-random sequence with a period length of 2^16-1, or 65535.

[0022] Based on the 16-bit parallel output of the shift register, a 16-bit binary pseudo-random number is obtained using a parallel reading method. This pseudo-random number is then output as the first pseudo-random sequence. This sequence exhibits good randomness and uniform distribution characteristics, low correlation, and is suitable for generating random frequency dithering signals.

[0023] S12. Construct a second pseudo-random number generator based on a linear feedback shift register, and use a primitive polynomial configuration feedback structure different from the first generator to obtain a second pseudo-random sequence. Based on digital logic circuits, a second pseudo-random number generator is constructed using the same linear feedback shift register architecture as the first generator. A 16-bit shift register is also chosen as the basic structure, but a different primitive polynomial is used to ensure the independence of the two pseudo-random sequences. Specifically, the polynomial chosen is x... 16+x 15+x 13+x The feedback structure corresponding to the polynomial 4+1 is to perform an XOR operation on the outputs of the 16th, 15th, 13th and 4th bits, and then feed the result back to the input of the 1st bit.

[0024] The shift registers are driven by the system clock signal, and the same synchronous triggering method as the first generator is used to keep the two generators clock-synchronized. By using different feedback polynomials, although the two shift registers are driven by the same clock, their state transition sequences are completely different, thus ensuring the independence between the two pseudo-random sequences. The independence of the two sequences is verified by a cross-correlation test method, confirming that the cross-correlation coefficient is within an acceptable range.

[0025] Based on the 16-bit parallel output of the shift register, a 16-bit binary pseudo-random number is obtained using a parallel reading method. This pseudo-random number is then output as a second pseudo-random sequence. This sequence has similar statistical characteristics to the first pseudo-random sequence but different sequence content, and the two are independent of each other.

[0026] S13. Based on the first pseudo-random sequence and the preset triangular wave period range, a slow random triangular wave dithering signal is obtained by using numerical mapping and cumulative counting methods. Based on the 16-bit binary data of the first pseudo-random sequence, a numerical range mapping method is used to map it to the periodic time range of a triangular wave. Specifically, the minimum and maximum values ​​of the triangular wave period are first determined. This range is set according to the frequency expansion requirements of dithering, requiring that the amplitude of the triangular wave frequency change is greater than the amplitude of the rapid random jump but less than the reference frequency value. The 16-bit pseudo-random number is converted into a periodic time value within this range using a linear mapping formula. The mapping formula is to divide the pseudo-random number by 65535, multiply it by the span of the periodic range, and add the minimum periodic value to obtain the randomized triangular wave periodic time.

[0027] Based on the mapped triangular wave period time, a slow random triangular wave is constructed using a triangular wave generation circuit. The triangular wave generation circuit includes a rising counter, a falling counter, and a control state machine. At the beginning of each triangular wave period, the control state machine sets the target count value of the counters according to the current random period time value. This target count value is equal to the period time divided by 2, corresponding to half a period of the triangular wave. The control state machine first starts the rising counter, which increments from zero according to the system clock. When the count value reaches the target count value, the control state machine switches to the falling state and starts the falling counter, decrementing from the target count value. When the count reaches zero, the current triangular wave period ends.

[0028] Based on the cycle end signal of the control state machine, a trigger update mechanism is adopted to read new pseudo-random numbers from the first pseudo-random sequence, re-execute the mapping operation, and obtain the time value of the next triangular wave cycle. In this way, the duration of each cycle of the triangular wave varies randomly, and there is no fixed time relationship between adjacent cycles, forming a time-randomized triangular wave signal.

[0029] Based on the outputs of the rising and falling counters, a data selector selects the currently valid count value according to the state of the control state machine, and uses this count value as the instantaneous amplitude value of the triangular wave. Since the count value rises linearly and then falls linearly within half a cycle, a typical triangular waveform is formed. This triangular wave amplitude value is numerically scaled and mapped to a preset frequency offset range, resulting in a slow, random triangular wave jitter signal represented by the frequency offset. The frequency offset amplitude of this signal linearly increases from its minimum to its maximum value during the rising phase of the triangular wave, and linearly decreases from its maximum value to its minimum value during the falling phase, while the duration of each triangular wave cycle varies randomly, thus achieving a jitter characteristic with regularly changing amplitude but randomized time.

[0030] S14. Based on the second pseudo-random sequence and the preset jump time interval, a fast random jump frequency jitter signal is obtained by using timed sampling and numerical mapping methods. Based on the 16-bit binary data of the second pseudo-random sequence, a fixed time interval sampling mechanism is used to generate fast random transitions. Specifically, a fixed transition time interval is set, which is set to be much smaller than the period of the slow random triangular wave, usually set to an integer multiple of the reference switching period, to ensure that multiple fast transitions can occur within one triangular wave period.

[0031] Based on the transition time interval, a timer / counter is used to implement timed sampling triggering. The timer / counter is driven by the system clock and increments from zero. When the count value reaches the count value corresponding to the preset transition time interval, a sampling trigger signal is generated, and the counter is reset to zero to start the next counting cycle. In this way, the sampling trigger signal is generated periodically at fixed time intervals.

[0032] Based on the sampling trigger signal, a trigger reading mechanism is adopted. Each time the sampling trigger signal arrives, the current 16-bit pseudo-random number is read from the second pseudo-random sequence. This pseudo-random number is mapped to the frequency offset range of the fast jump using a numerical range mapping method. The principle for setting this range is that its maximum offset amplitude is less than the frequency change amplitude of the slow random triangular wave, ensuring that the fast jump is refined and dispersed based on the slow triangular wave. The mapping formula is to divide the pseudo-random number by 65535, multiply it by the span of the frequency offset range, and then subtract half of the span, so that the distribution center of the frequency offset is zero, allowing for upward or downward offset.

[0033] Based on the frequency offset obtained from the mapping, a register latching mechanism is used to latch the current frequency offset into the output register, which serves as the current value of the fast random frequency jittering signal. This value remains unchanged until the next sampling trigger signal arrives, at which point it is updated with a new random offset, forming a step-like jump. Since the jump time is determined by a fixed time interval, and the frequency offset of each jump is determined by a pseudo-random number, the signal exhibits a fast jump characteristic with fixed time but random amplitude.

[0034] S15. Based on the reference frequency setting, the slow random triangular wave dithering signal and the fast random jump dithering signal, a three-way numerical superposition method is used to obtain a real-time working frequency signal with dual random characteristics. Based on the reference frequency setting, the reference frequency is converted into a digital frequency control word using a digital representation. The value of this control word represents the frequency level and serves as the fundamental component of the operating frequency.

[0035] Based on a slow random triangular wave dithering signal and a fast random jump dithering signal, a digital adder is used to superimpose the values ​​of the three signals. Specifically, the reference frequency control word is first added to the frequency offset of the slow random triangular wave dithering signal to obtain the first-level modulated frequency control word. The value of this frequency control word fluctuates slowly around the reference frequency as the slow triangular wave changes, achieving wideband energy expansion.

[0036] Based on the frequency control word modulated at the first level, a second numerical superposition operation is performed, adding it to the frequency offset of the fast random jumping frequency dithering signal to obtain the final real-time operating frequency control word. This control word simultaneously incorporates the wideband extension characteristics of the slow triangular wave and the refined dispersion characteristics of the fast jumping, forming a double-layer randomized frequency modulation effect.

[0037] Based on the final real-time operating frequency control word, a numerically controlled oscillator (CNC) is used to convert the frequency to a clock signal. The CNC receives the frequency control word as input and internally employs fractional frequency division technology to dynamically adjust the output clock frequency according to the control word value. Specifically, the CNC includes a phase accumulator and a waveform generator. The phase accumulator adds the frequency control word to the phase register in each system clock cycle. When the phase register overflows, a carry signal is generated, which drives the waveform generator to produce the transition edge of the output clock. Through this phase accumulation method, the output clock frequency is proportional to the value of the frequency control word, and high-precision frequency adjustment can be achieved.

[0038] Based on the clock signal output by the numerically controlled oscillator, this signal is used as the clock reference for the PWM controller, resulting in a real-time operating frequency signal with dual random characteristics. The frequency of this signal is modulated by both a slow triangular wave and a rapid transition at each moment, exhibiting a complex, non-periodic change in the time domain. In the frequency domain, this effectively disperses the interference energy of the switching frequency across a wide bandwidth, thus avoiding the formation of concentrated interference peaks.

[0039] S2, based on the real-time operating frequency signal and the system clock, uses cycle counting and numerical conversion methods to obtain the time length value of the current switching cycle; Based on the real-time operating frequency signal obtained in step S1, a period detection circuit is used to obtain the time length of the current switching cycle in real time, providing basic data for subsequent adaptive slope compensation calculation.

[0040] S21. Based on the periodic boundary of the real-time operating frequency signal, the edge detection method is used to obtain the switching cycle start trigger signal and the cycle end trigger signal. Based on the real-time operating frequency signal, an edge detection circuit is used to identify the rising and falling edges of the signal. Specifically, the real-time operating frequency signal is input to the data input terminal of a D flip-flop, and the system clock signal is connected to the clock input terminal of the flip-flop. At each rising edge of the system clock, the flip-flop samples the real-time operating frequency signal and latches the sampling result to the output terminal. By comparing the current output of the flip-flop with the output at the previous moment, the transition of the real-time operating frequency signal can be detected.

[0041] Based on the transition detection results, a logical judgment method is used to identify rising and falling edges. When the output is low at the previous moment and high at the current moment, a rising edge is determined to have occurred; when the output is high at the previous moment and low at the current moment, a falling edge is determined to have occurred. The rising edge detection signal is used as the start trigger signal for the switching cycle, marking the beginning of a new switching cycle. The falling edge detection signal is used as the end trigger signal for the cycle, marking the end of the current switching cycle.

[0042] Based on the start and end trigger signals of the switching cycle, a pulse shaping circuit is used to convert the detected transitions into standard single-clock-cycle pulse signals, ensuring that the timing characteristics of the trigger signals meet the requirements of subsequent circuits. These two trigger signals serve as control signals for the cycle counter, used to start and stop the measurement of cycle time.

[0043] S22. Based on the start trigger signal of the switching cycle and the system clock, the clock pulse count value within the cycle is obtained by using an incremental counting method; Based on the start-of-switch cycle trigger signal, a counter reset operation is used. When the start-of-switch cycle trigger signal is detected, the count value of the cycle counter is cleared to zero, preparing for counting in the new cycle. The cycle counter is implemented using a multi-bit binary counter, and the bit width is determined according to the maximum cycle time and the system clock frequency to ensure that the counter does not overflow during the longest switching cycle.

[0044] Based on the system clock signal, a synchronous incrementing counter is used, incrementing the counter value by 1 at each rising edge of the system clock. Since the system clock frequency is fixed and known, each increment of the counter corresponds to a fixed time increment, which is equal to the system clock period. Through continuous incrementing, the counter value reflects the time elapsed from the start of the switching cycle to the current moment in real time.

[0045] Based on the cycle end trigger signal, a count value latching operation is used. When the cycle end trigger signal is detected, the count value of the current cycle counter is latched into the cycle value register. The count value stored in this register is the number of system clock pulses within the current complete switching cycle, representing the duration of the current switching cycle.

[0046] Based on the latched count value, a parallel output method is used to output the contents of the period value register as the clock pulse count value within the period. This count value is a digital quantity, which facilitates subsequent digital calculations and processing.

[0047] S23. Based on the clock pulse count value within the cycle and the system clock cycle, the time length value of the current switching cycle is obtained by using a numerical multiplication conversion method. Based on the clock pulse count within the cycle, a fixed-point multiplier is used to convert the time length numerically. Specifically, the system clock period is a known fixed value, which is represented in fixed-point format, with the number of decimal places set according to the precision requirements. The clock pulse count within the cycle is multiplied by the system clock period to obtain the current switching cycle time length expressed in time units.

[0048] Based on the multiplication result, numerical rounding and bit width adjustment methods are used to adjust the high bit width data output by the multiplier to the bit width required by subsequent circuits. At the same time, the part exceeding the effective bits is rounded to ensure numerical accuracy.

[0049] Based on the calculated time length value, it is stored in a data register and output as the time length value of the current switching cycle. This time length value is expressed in absolute time, usually in nanoseconds or microseconds, which intuitively reflects the duration of the current switching cycle.

[0050] S24. Based on the current switching cycle time length, a pipelined transfer mechanism is used to obtain cycle data for calculating the compensation slope. Based on the current switching cycle duration, a pipelined register set is used to achieve data timing alignment. Specifically, since cycle detection is completed at the end of the current cycle, while the compensation slope calculation is needed at the beginning of the next cycle, the cycle duration needs to be retained until the next cycle.

[0051] Based on a pipelined design approach, a two-stage register system is used to implement delayed data transfer. The first-stage register latches the cycle length at the end of the current cycle, and the second-stage register latches the value of the first-stage register at the beginning of the next cycle and outputs it to the compensation slope calculation module. Through this pipelined structure, while performing cycle detection in the current cycle, the compensation slope is calculated using the detection results from the previous cycle, achieving parallel processing of detection and calculation and ensuring real-time performance.

[0052] Based on the cycle data passed through the pipeline, a data validity flag is used to indicate the validity of the data. When new cycle data is ready, the validity flag is set high, notifying the compensation slope calculation module that it can use this data for calculation. This handshake mechanism using the validity flag ensures the reliability of data transmission and the correctness of timing.

[0053] S3, based on the input voltage sample value and the output voltage reference value, uses digital division or lookup table method to obtain the target duty cycle value required to maintain output stability; Based on the input voltage value obtained by the voltage sampling circuit and the preset output voltage target value, the ideal duty cycle required to maintain output voltage stability under the current operating conditions is obtained by using the duty cycle calculation method.

[0054] S31. Based on the analog input voltage signal, the digital sample value of the input voltage is obtained by using ADC sampling and digitization methods; The input voltage is sampled using a resistor divider network. Two series resistors are used to proportionally divide the input voltage to obtain an analog voltage signal suitable for the ADC input range. The voltage division ratio is determined based on the input voltage range and the ADC reference voltage to ensure that the divided voltage does not exceed the ADC's full-scale input range throughout the entire operating range of the input voltage.

[0055] Based on the analog voltage signal after voltage division, an ADC is used for analog-to-digital conversion. The ADC adopts a successive approximation or pipelined structure with sufficient resolution and sampling rate. The resolution is usually 12 bits or higher to ensure the accuracy of voltage measurement; the sampling rate is set according to the rate of change of the input voltage, usually set to an integer multiple of the switching frequency to ensure timely capture of changes in the input voltage.

[0056] Based on the ADC conversion result, the converted data is read using a digital interface to obtain the digital sample value of the input voltage. The magnitude of this digital value is proportional to the actual input voltage. By multiplying it by the voltage divider ratio and the ADC quantization step size, it can be converted into the actual input voltage value.

[0057] Based on the digital sampled values, a digital filter is used for noise suppression. Specifically, a first-order IIR low-pass filter is used to smooth the continuously sampled digital values. The cutoff frequency of the filter is set to be much lower than the switching frequency but higher than the possible frequency of input voltage changes. This can filter out high-frequency noise and switching ripple introduced during the sampling process, while retaining the true information of input voltage changes.

[0058] Based on the filtered digital sampled value, a data register latch is used to obtain the digital sampled value of the input voltage used for duty cycle calculation. This value represents the current actual input voltage level.

[0059] S32. Based on the output voltage reference value and the control target, a digital reference value for the output voltage is obtained using digital representation and preprocessing methods. Based on the output voltage requirements of LED driver applications, a digital constant register is used to store the output voltage reference value. This reference value is determined according to the forward voltage of the LED and the number of LEDs in series, is preset during the system design phase, and is written to the register through the configuration interface.

[0060] Based on the digital reference value, the same numerical unit and fixed-point format as the input voltage sampling value are used to ensure that the two can be directly used for numerical calculations. Specifically, if the input voltage sampling value is represented in fixed-point number with N decimal places, the output voltage reference value also adopts the same fixed-point number format with N decimal places.

[0061] Based on a standardized output voltage reference value, data alignment and preprocessing operations are performed to prepare it as input data for duty cycle calculation. Preprocessing includes numerical validity checks to ensure the reference value is within a reasonable range and to avoid calculation errors caused by misconfiguration.

[0062] S33. Based on the digital sampled value of the input voltage and the digital reference value of the output voltage, the digital representation of the target duty cycle is obtained by digital division or lookup table method. Based on the volt-second balance principle of Buck switching power supplies, the steady-state duty cycle calculation formula is used to determine that the target duty cycle is equal to the ratio of the output voltage to the input voltage. In an ideal situation, ignoring the voltage drop across the switching transistor and diode, the duty cycle D is calculated as D equals the output voltage divided by the input voltage.

[0063] Based on this calculation formula, a digital divider is used to calculate the duty cycle in real time. The digital divider receives the digital reference value of the output voltage as the dividend and the digital sample value of the input voltage as the divisor, and performs a fixed-point division operation. The result of the division operation is the target duty cycle value, which is a fixed-point number less than 1, and its magnitude directly reflects the percentage of the duty cycle.

[0064] Based on the division operation latency, a pipelined architecture is used to optimize the operation timing. Division operations typically require multiple clock cycles to complete. Through pipelined design, the result of the previous calculation can be used for control while the division operation is being performed in the current cycle, ensuring the continuity of control.

[0065] S34. Based on the digital representation of the target duty cycle, the target duty cycle value used for slope compensation calculation is obtained by using numerical range limitation and output latching methods. Based on the target duty cycle value obtained through calculation or table lookup, a range limiting circuit is used for numerical constraint. Specifically, a minimum and a maximum duty cycle are set. The minimum value is usually set to around 10% to avoid a decrease in control accuracy due to an excessively small duty cycle. The maximum value is usually set to around 90% to provide sufficient margin for slope compensation and to avoid insufficient dead time due to an excessively large duty cycle.

[0066] Based on the range-limited judgment logic, a numerical comparison and condition selection method is used. If the calculated duty cycle value is less than the minimum value, it is limited to the minimum value; if it is greater than the maximum value, it is limited to the maximum value; if it is between the minimum and maximum values, the original value is kept unchanged. This range limitation ensures that the duty cycle is always within the safe operating range.

[0067] Based on the duty cycle value after range limitation, a data register latch is used to obtain the target duty cycle value for calculating the compensation slope. This value serves as a key input parameter for adaptive slope compensation calculation, used to determine the optimal compensation slope at the current operating point.

[0068] S4. Based on the target duty cycle value, the current switching cycle value, and system parameters, the adaptive adjustment compensation slope value is obtained by using a lookup table combined with interpolation or parameterized formula calculation method. Based on the target duty cycle value obtained in step S3 and the current switching cycle value obtained in step S2, an adaptive compensation slope calculation method is used to obtain a compensation slope that can suppress subharmonic oscillations and adapt to the current operating frequency.

[0069] S41. Based on the inductor parameters and the output voltage reference value, the slope of the inductor current decrease is obtained using the slope calculation formula. Based on the inductance value of the inductor in the LED driver circuit, a parameter storage method is adopted, storing the inductance value as a system parameter in the configuration register. The inductance value is determined during the circuit design stage, and a suitable inductor is selected according to the output current ripple requirements and switching frequency range.

[0070] Based on the output voltage reference value and the inductance value, the inductor current slope is calculated using the inductor current slope formula. In a Buck-type switching power supply, when the switching transistor is turned off, the inductor current decreases through the freewheeling diode, and the voltage across the inductor equals the output voltage. According to the inductor voltage-current relationship, the inductor current slope is equal to the output voltage divided by the inductance value.

[0071] Based on the formula for calculating the descent slope, a digital divider or lookup table method is used to calculate the slope. The output voltage reference value is used as the dividend, and the inductance value as the divisor. Fixed-point division is performed to obtain a digital representation of the descent slope. The unit of this slope value is the rate of change of current, typically expressed in amperes per second.

[0072] Based on the calculated descent slope value, a numerical unit conversion method is used to convert it into a unit that matches the sampling signal of the control system. Specifically, if the current sampling signal is represented as a digital quantity after ADC conversion, the physical slope value is multiplied by the current sampling gain and the ADC quantization coefficient to obtain the descent slope value expressed in digital units, which facilitates subsequent digital calculations.

[0073] S42. Based on the target duty cycle and the inductor current drop slope, the subharmonic oscillation stability criterion is used to obtain the reference compensation slope value. Based on the subharmonic oscillation theory of current-mode control, a stability criterion is used to determine the minimum requirement for the compensation slope. The stability condition for subharmonic oscillation is that the compensation slope must be greater than the product of the inductor current descent slope and the duty cycle correlation function. Specifically, the criterion is that the compensation slope should be greater than the descent slope multiplied by the duty cycle divided by 2 minus twice the duty cycle.

[0074] Based on this stability criterion, a parameterized formula is used to calculate the baseline compensation slope. First, the duty cycle correlation coefficient is calculated, which is equal to the duty cycle divided by 2 minus the duty cycle itself. Based on the target duty cycle value, the coefficient is calculated using numerical operations: first, the duty cycle is multiplied by 2; then, 2 is subtracted from the product; finally, the duty cycle is divided by the calculated result to obtain the duty cycle correlation coefficient.

[0075] Based on the duty cycle correlation coefficient and the inductor current drop slope, a digital multiplier is used to multiply the two to obtain the theoretical minimum compensation slope. To ensure sufficient stability margin, a margin factor is multiplied by the theoretical minimum value. The margin factor is typically set to 1.2 to 1.5 times to obtain the reference compensation slope value used in practice. This reference compensation slope is the optimal compensation slope at the nominal switching frequency.

[0076] S43. Based on the reference compensation slope value and the current switching cycle value, the period normalization adjustment method is used to obtain the adaptive compensation slope value that is suitable for the current frequency. Based on the baseline compensation slope value, a period normalization method is used to achieve adaptive frequency adjustment. The role of the compensation slope is to provide sufficient slope compensation within the switching cycle. When the switching cycle changes, if the slope remains unchanged, the accumulated compensation within one cycle will change, causing the compensation effect to deviate from the design target.

[0077] Based on the principle of period normalization, an adjustment strategy is adopted in which the compensation slope is inversely proportional to the switching period. Specifically, a reference switching period is first determined. This period is the period value corresponding to the nominal operating frequency and is the period used to calculate the reference compensation slope. Based on the ratio of the current switching period value to the reference switching period, a digital divider is used to calculate the period ratio.

[0078] Based on the period ratio, the frequency adjustment coefficient is obtained by reciprocal calculation. The frequency adjustment coefficient is equal to the reference switching period divided by the current switching period. When the current period is greater than the reference period, the adjustment coefficient is greater than 1, indicating that the frequency is reduced and the compensation slope needs to be increased; when the current period is less than the reference period, the adjustment coefficient is less than 1, indicating that the frequency is increased and the compensation slope needs to be decreased.

[0079] Based on the frequency adjustment coefficient and the reference compensation slope value, a digital multiplier is used to multiply the two to obtain an adaptive compensation slope value adapted to the current frequency. This slope value is dynamically adjusted as the switching cycle changes. When the frequency changes due to frequency dithering, the compensation slope changes accordingly, ensuring that the same compensation effect is maintained at different frequencies, thereby maintaining the stability of the duty cycle.

[0080] In some embodiments, the calculation of the frequency adjustment coefficient involves division and reciprocal operations, which are computationally complex and time-consuming, potentially affecting real-time performance. A lookup table-based method for obtaining the frequency adjustment coefficient can be used to simplify the calculation process and improve response speed. Specifically, during system initialization, based on the possible switching cycle range, an offline calculation method is used to pre-calculate the frequency adjustment coefficients corresponding to different switching cycles, and the results are stored in a lookup table. The lookup table uses the switching cycle value as the address index and the corresponding adjustment coefficient as the storage content. Based on the current switching cycle value, a lookup table read operation is used to directly obtain the corresponding frequency adjustment coefficient. Based on the adjustment coefficient read from the lookup table and the baseline compensation slope value, a single multiplication operation is performed using a digital multiplier to obtain the adaptive compensation slope value. Because lookup table access is fast and only requires one multiplication operation, the computation time is significantly reduced compared to complete division and reciprocal operations, improving the system's real-time response capability.

[0081] S44. Based on the adaptive compensation slope value, a first-order filtering smoothing method is used to obtain the smoothed adaptive compensation slope value. Based on the adaptive compensation slope value calculated for each switching cycle, a first-order IIR filter is used for smoothing to avoid abrupt changes in the compensation slope between adjacent cycles and prevent discontinuities or glitches in the control signal.

[0082] Smoothing is achieved using a weighted averaging method based on the difference equation of a first-order IIR filter. The difference equation of the filter is: the current output equals the filter coefficient multiplied by the current input plus 1, minus the filter coefficient multiplied by the previous output. The filter coefficients range from 0 to 1, and these coefficients determine the filter's response speed and smoothing effect. Larger coefficients result in a faster response but weaker smoothing; smaller coefficients result in stronger smoothing but slower response.

[0083] Based on the system's dynamic performance requirements, a filter coefficient selection method is adopted, typically setting the filter coefficient to a value between 0.2 and 0.4. This ensures that newly calculated slope values ​​account for 20% to 40% of the weight, while historical slope values ​​account for 60% to 80%. This setting guarantees both the timeliness of slope adjustment, enabling tracking of frequency changes, and provides sufficient smoothing, avoiding the influence of single-calculation errors or measurement noise.

[0084] Based on the recursive calculation of the filter, the filtering operation is implemented using digital multipliers and adders. First, the adaptive compensation slope value calculated in the current cycle is multiplied by the filter coefficient to obtain the weighted component of the new value; then, the compensation slope value used in the previous cycle is multiplied by 1 and the filter coefficient is subtracted to obtain the weighted component of the old value; finally, the two weighted components are added together to obtain the smoothed adaptive compensation slope value actually used in the current cycle.

[0085] Based on the smoothed compensation slope value, a data register latching and updating mechanism is used to save the current smoothed slope value to the historical value register, which serves as the old value input for the next cycle of filtering calculation. Through this recursive updating mechanism, the filter continues to run, performing real-time smoothing of the compensation slope.

[0086] S5, based on the smoothed adaptive compensation slope value and the switching cycle synchronization signal, adopts the digital slope generation method to obtain a compensation slope signal that matches the current operating frequency; Based on the smoothed adaptive compensation slope value obtained in step S4, a digital slope generator is used to generate a real-time compensation slope signal, which is then superimposed on the inductor current sampling signal to achieve adaptive slope compensation.

[0087] S51. Based on the start trigger signal of the switching cycle, the initial zero value state of the ramp generator is obtained by using the register reset method; Based on the switching cycle start trigger signal detected in step S2, this signal is used as the reset control signal for the ramp generator. The ramp generator is implemented using an accumulator structure, which consists of a data register and an adder. The register stores the current accumulated value, and the adder adds the accumulated value to the slope increment at each system clock cycle to obtain a new accumulated value.

[0088] Based on the arrival of the switching cycle start trigger signal, a register reset operation is used to clear the accumulator register to obtain the initial zero value state of the ramp generator. This reset operation ensures that the compensation ramp signal starts from zero level at the beginning of each new switching cycle, guaranteeing the synchronization of the ramp signal with the switching cycle.

[0089] Based on the zero-value state after reset, a status flag is used to indicate that the ramp generator has entered the operating state and is ready to start a new cycle of ramp generation.

[0090] S52. Based on the smoothed adaptive compensation slope value and the system clock cycle, a numerical conversion method is used to obtain the slope increment value for each clock cycle. Based on the smoothed adaptive compensation slope value, a unit-time increment calculation method is used to obtain the value by which the ramp signal should increase within each system clock cycle. The unit of the compensation slope is digital quantity per second, and the system clock cycle is time unit; multiplying the two yields the increment per clock cycle.

[0091] Based on a digital multiplier, fixed-point multiplication is used to multiply the smoothed adaptive compensation slope value by the system clock cycle time to obtain the slope increment value. This increment value is a fixed-point number with the same number of decimal places as the compensation slope, ensuring numerical accuracy.

[0092] Based on the calculated slope increment value, a numerical range check method is used to confirm that the increment value is within a reasonable range, avoiding erroneous accumulation due to abnormal parameters. If the increment value exceeds the expected range, a limiting process is used to restrict it to between the maximum and minimum allowed values.

[0093] Based on the slope increment value after inspection, the data register is latched and the increment value is used as the accumulation step value of the ramp generator for subsequent accumulation calculations.

[0094] S53. Based on the slope increment value and the system clock, a synchronous accumulation method is used to obtain a real-time increasing digital ramp signal; Since the ramp generator is in operation, a synchronous accumulation mechanism is used to generate the ramp signal. At each rising edge of the system clock, the accumulator adds the current accumulated value to the ramp increment value to obtain a new accumulated value, and writes the new value back to the accumulator register.

[0095] Based on the continuous accumulation operation of the accumulator, an overflow detection method is used to monitor whether the accumulated value exceeds the representation range of the register. If an overflow is detected, saturation processing is used to limit the accumulated value to the maximum representation value to prevent errors caused by numerical rollback.

[0096] Based on the output of the accumulator register, the current ramp signal value is obtained using a parallel reading method. This value starts from zero and increases clockwise with a fixed slope increment, forming a linearly rising digital ramp signal. Since the slope increment is determined by the adaptive compensation slope value, different slope values ​​will produce ramp signals with different slopes, thus achieving adaptive adjustment of the ramp slope.

[0097] Based on a real-time incrementing ramp signal, a cycle end detection mechanism is employed. When a cycle end trigger signal is detected, the accumulation operation stops, the current accumulated value remains unchanged, and the system waits for the next cycle start trigger signal to arrive before resetting and restarting. This cycle synchronization mechanism ensures that the ramp signal is strictly aligned with the switching cycle, generating a complete ramp waveform for each cycle.

[0098] S54. Based on the digital ramp signal, a compensation ramp signal for current control is obtained by using digital filtering and output buffering methods. Based on the digital ramp signal output by the accumulator, a digital low-pass filter is used to suppress high-frequency noise. Since the accumulator uses fixed-point arithmetic, there is quantization noise, and there may be a small step during ramp switching. The low-pass filter can smooth these high-frequency components.

[0099] Based on the low-pass filter design, a simple moving average filter is used to average the ramp values ​​of several consecutive sampling points to obtain a smoothed ramp signal. The moving average window length is set according to the system clock frequency and the desired filtering effect, typically choosing 3 to 5 sampling points, which can effectively filter out high-frequency noise without significantly affecting the linearity of the ramp signal.

[0100] Based on the filtered ramp signal, an output buffer register is used for timing alignment. The output buffer register latches the filtered ramp value at each system clock and outputs it to the current control module to ensure the timing stability and predictability of the output signal.

[0101] Based on the output buffered signal, a data validity indication mechanism is employed. A validity flag indicates that the currently output compensation ramp signal is valid and usable data for use by the current control module. This handshake mechanism ensures the reliability of data transmission.

[0102] S6, based on the compensation ramp signal and the inductor current sampling signal, uses digital addition and comparison control methods to obtain a stable LED drive current output; Based on the compensation ramp signal generated in step S5 and the real-time sampled inductor current signal, a current-mode control method is adopted to achieve stable LED constant current drive output.

[0103] S61. Based on the analog signal of inductor current, the digital sampled value of inductor current is obtained by using ADC sampling and digitization methods; Based on the inductor current sampling circuit, an analog signal of the inductor current is obtained using a current sensing resistor or a Hall sensor. The current sensing resistor is connected in series in the inductor current loop, and the voltage across the resistor is proportional to the current flowing through it. This voltage is amplified by a differential amplifier to a range suitable for the ADC input.

[0104] Based on the amplified analog current signal, a high-speed ADC is used for analog-to-digital conversion. Because the current signal changes rapidly during the switching cycle, the ADC sampling rate needs to be sufficiently high, typically set to at least 10 times the switching frequency, to ensure accurate capture of the current waveform details. The ADC resolution is selected to be 12 bits or higher to ensure that the current measurement accuracy meets the control requirements.

[0105] Based on the ADC conversion results, a parallel digital interface is used to read the converted data and obtain the digital sample value of the inductor current. This digital value is calibrated and converted into a current value in amperes or milliamperes for subsequent processing.

[0106] Based on the digital sample values, digital signal processing methods are used for noise suppression and signal conditioning. Specifically, a median filter is used to remove occasional sampling spikes, and a low-pass filter is used to suppress high-frequency noise, resulting in smooth and accurate digital sample values ​​of the inductor current.

[0107] S62. Based on the compensation ramp signal and the digital sampled value of the inductor current, a digital adder is used to perform signal superposition to obtain the superimposed control signal. Based on the compensation ramp signal generated in step S5 and the current digital sampled value of the inductor current, a digital adder is used to superimpose the values ​​of the two signals. The adder is a fixed-point adder, and the two input signals use the same numerical unit and fixed-point format to ensure the correctness of the addition operation.

[0108] Based on the operation of the digital adder, a parallel addition method is adopted to complete the addition operation within a single system clock cycle, resulting in a superimposed control signal. The value of this control signal is equal to the inductor current sample value plus the compensation ramp value, reflecting the equivalent current signal after ramp compensation.

[0109] Based on the superimposed control signal, a numerical overflow detection and saturation processing method is adopted. If the addition operation causes overflow, the result is limited to the maximum representation value to prevent incorrect judgment caused by numerical rollback.

[0110] Based on the processed control signal, a data register is used to latch it and use it as the input signal of the current comparator for comparison with the current reference value.

[0111] S63. Based on the output current reference value, a digital reference value for current control is obtained by using digital representation and preprocessing methods. Based on the requirements of LED constant current driving, a digital constant register is used to store the output current reference value. This reference value is determined according to the rated current of the LED, preset during the system design phase, and written to the register through the configuration interface. For multi-channel LED driver applications, each channel can have an independent current reference value.

[0112] Based on a digital reference value, the same numerical units and fixed-point format as the control signal are used to ensure direct numerical comparison between the two. Specifically, the reference value uses the same quantization unit as the current sampling signal to avoid comparison errors caused by unit inconsistencies.

[0113] Based on a standardized current reference value, data alignment and preprocessing operations are employed, including numerical validity checks and range limiting, to ensure that the reference value is within a reasonable range, thus obtaining a digital reference value for current control used for comparison.

[0114] S64. Based on the superimposed control signal and current reference value, a digital comparator is used to determine the magnitude of the signal and obtain the control command for the switching transistor. Based on the superimposed control signal and current reference value, a digital comparator is used for real-time comparison. The digital comparator is a multi-bit binary comparator that takes two fixed-point numbers as input and outputs the comparison result, including three states: greater than, equal to, and less than.

[0115] Based on the comparison operation of the comparator, a threshold judgment method is adopted. When the control signal is greater than or equal to the current reference value, the comparator outputs a high level, indicating that the inductor current has reached the target value and the switching transistor needs to be turned off; when the control signal is less than the current reference value, the comparator outputs a low level, indicating that the inductor current has not reached the target value and the switching transistor remains on.

[0116] Based on the comparator output, an edge-triggered method is used to generate the switching transistor control command. Specifically, when the comparator output transitions from a low level to a high level, a turn-off command pulse is generated. This pulse is sent to the switching transistor driver circuit through the control logic to trigger the switching transistor to turn off.

[0117] Based on the turn-off instruction and the start signal of the switching cycle, an RS flip-flop is used to construct the turn-on and turn-off control logic for the switching transistor. The start signal of the switching cycle serves as a set input, causing the RS flip-flop to output a high level, driving the switching transistor to turn on; the turn-off instruction serves as a reset input, causing the RS flip-flop to output a low level, driving the switching transistor to turn off. The latching characteristic of the RS flip-flop ensures the stability of the switching transistor's state, unaffected by transient jitter in the comparator output.

[0118] Based on the output of the RS flip-flop, a power amplification and level conversion are performed using a switching transistor drive circuit. This converts the low-voltage, low-current signal of the control logic into a high-voltage, high-current drive signal that can drive the power switching transistor, ultimately controlling the switching transistor's on and off states.

[0119] S65. Based on the periodic on-off action of the switching transistor, an inductor energy storage and freewheeling mechanism is adopted to obtain a stable LED driving current output. Based on the conduction state of the switching transistor, an inductor energy storage mechanism is employed. When the switching transistor is on, the input voltage is applied across the inductor, causing the inductor current to rise linearly, thus storing magnetic field energy. The slope of the inductor current's rise is equal to the input voltage minus the output voltage, divided by the inductance value.

[0120] Based on the off-state of the switching transistor, a freewheeling diode freewheeling mechanism is employed. When the switching transistor is off, the inductor current cannot change abruptly. A freewheeling circuit is formed through the freewheeling diode, allowing the inductor to release its stored magnetic field energy, resulting in a linear decrease in the inductor current. The rate of decrease in the inductor current is equal to the output voltage divided by the inductance value.

[0121] Based on the periodic rise and fall of the inductor current, an output capacitor filtering method is adopted. The output capacitor is connected in parallel across the LED load. The capacitor filters the pulsating component of the inductor current, absorbs the excess energy during the current rise phase, and releases energy to the load during the current fall phase, thereby making the output current tend to be stable.

[0122] Based on the filtering effect of the output capacitor, an energy balance principle is adopted across multiple switching cycles. An adaptive slope compensation mechanism maintains the stability of the duty cycle, ensuring that the energy stored and released by the inductor remains balanced within each switching cycle, thus keeping the average output current constant. Because the compensation slope is adaptively adjusted according to the switching frequency, the duty cycle remains stable even under frequency jitter conditions, and the output current is unaffected by frequency changes.

[0123] Based on stable duty cycle control, a current feedback closed-loop regulation mechanism is adopted. When the output current deviates from the reference value due to load changes or input voltage changes, the change in the current sampling value will cause the control signal to reach the reference value earlier or later, thereby automatically adjusting the duty cycle to bring the output current back to the reference value. Through this negative feedback regulation, precise constant current control of the output current is achieved.

[0124] Based on constant current control of the output current, multiple LEDs are connected in series to form an LED string. A constant current flows through each LED, ensuring that the brightness of each LED is consistent and stable. Because the output current ripple is effectively controlled, the LEDs do not produce perceptible flicker, thus guaranteeing the lighting quality.

[0125] In one embodiment of the present invention, an application example is provided: This invention focuses on the application of high-end automotive matrix headlight LED drive systems. A real-world application example is given below to demonstrate the practical application effect of the technical solution of this invention.

[0126] In the adaptive headlight system of a luxury car, the dual random frequency dithering and adaptive slope compensation technology of this invention is used to achieve LED drive control. This headlight system includes 32 independently controlled LED units, each equipped with a drive circuit based on the technology of this invention. The reference operating frequency of the drive circuit is set to 400kHz, the input voltage is a 12V vehicle power supply, and the output current is 1A, driving three high-power LEDs connected in series.

[0127] The system parameters are set as follows: the period range of the slow random triangular wave is set to 50 microseconds to 150 microseconds, corresponding to a frequency variation range of approximately ±100kHz; the time interval of the fast random jump is set to 5 microseconds, with a frequency offset range of ±20kHz. The first pseudo-random number generator uses a 16-bit linear feedback shift register, with a feedback polynomial of x. 16+x 14+x 13+x 11+1; The second pseudo-random number generator also uses a 16-bit structure, with a feedback polynomial of x. 16+x 15+x 13+x 4+1. The system clock frequency is 100MHz, and the period detection counter is 24-bit. The inductor value is selected as 22 microhenries, and the output capacitor is 47 microfarads.

[0128] Table 1 shows some of the operational data obtained during the actual operation of the system. Table 1, Example of Working Data As can be observed from the data table, under the dual random frequency dithering effect, the operating frequency randomly varies within the range of 387kHz to 412kHz, and the corresponding switching period varies within the range of 2.43µs to 2.58µs. The compensation slope adaptively adjusts according to the changes in the switching period, dynamically changing within the range of 215A / ms to 228A / ms to ensure consistent compensation effects at different frequencies. The target duty cycle remains within a stable range of 0.61 to 0.62, without significant fluctuations due to frequency changes. The output current remains stably maintained near the target value of 1A, with fluctuations between 0.998A and 1.002A, and the current stability meets the design requirements.

[0129] In terms of electromagnetic compatibility testing, the LED driver circuit using this invention, in the CISPR 25 standard conducted interference test, showed that the average interference voltage at all frequency points within the 150kHz to 30MHz frequency band was lower than the Class 5 limit requirement, meeting the stringent automotive electromagnetic compatibility standards. Observing the spectral characteristics of the switching frequency using a spectrum analyzer revealed that the dual random frequency dithering technology effectively dispersed the energy of the switching frequency across a wide bandwidth of 300kHz to 500kHz, without any obvious concentrated interference peaks. The spectrum exhibited a flat noise floor distribution, verifying the effectiveness of the dual random frequency dithering mechanism.

[0130] In terms of output stability testing, the LED output current waveform was observed using an oscilloscope. The peak-to-peak current ripple was controlled within 20mA, accounting for 2% of the average current, far exceeding the design requirement of 5%. Throughout the entire frequency dithering range, the current ripple characteristics remained consistent, without any increase in ripple or subharmonic oscillation due to frequency changes, verifying the effectiveness of the adaptive slope compensation technology.

[0131] As can be seen from the above application examples, the dual random frequency dithering and adaptive slope compensation technology of the present invention can work effectively in actual automotive LED drive applications, while optimizing electromagnetic compatibility and output stability, and meeting the stringent requirements of high-end automotive headlight systems.

[0132] The embodiments of the present invention have been described above. However, the embodiments are not limited to the specific implementation methods described above. The specific implementation methods described above are merely illustrative and not restrictive. Those skilled in the art can make more equivalent embodiments under the guidance of the present embodiments, and all of them are within the protection scope of the present embodiments.

Claims

1. A method for dual random frequency dithering and adaptive slope compensation in a switching power supply, characterized in that, Includes the following steps: S1, based on the pseudo-random number generator, generates a two-layer independent random sequence, and uses a layered mapping method to obtain a slow random triangular wave dithering signal and a fast random jump dithering signal; S2, based on the real-time operating frequency signal and the system clock, uses cycle counting and numerical conversion methods to obtain the time length value of the current switching cycle; S3, based on the input voltage sample value and the output voltage reference value, uses digital division or lookup table method to obtain the target duty cycle value required to maintain output stability; S4. Based on the target duty cycle value, the current switching cycle value, and system parameters, the adaptive adjustment compensation slope value is obtained by using a lookup table combined with interpolation or parameterized formula calculation method. S5, based on the smoothed adaptive compensation slope value and the switching cycle synchronization signal, adopts the digital slope generation method to obtain a compensation slope signal that matches the current operating frequency; S6, based on the compensation ramp signal and the inductor current sampling signal, uses digital addition and comparison control methods to obtain a stable LED drive current output.

2. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 1, characterized in that, The process involves generating a two-layer independent random sequence based on a pseudo-random number generator, and employing a layered mapping method to obtain a slow random triangular wave dithering signal and a fast random jump dithering signal, including: A first pseudo-random number generator and a second pseudo-random number generator are constructed based on a linear feedback shift register. Different primitive polynomials are used to configure the feedback structure to obtain the first pseudo-random sequence and the second pseudo-random sequence. Based on the first pseudo-random sequence, a numerical range mapping method is used to map it to the periodic time range of a triangular wave. A slow random triangular wave is constructed using a triangular wave generation circuit, which includes a rising counter, a falling counter, and a control state machine, to obtain a slow random triangular wave dithering signal. Based on the second pseudo-random sequence, a fixed time interval sampling mechanism is adopted, and a timer counter is used to trigger the timed sampling. The pseudo-random number is mapped to the frequency offset range of rapid jump, and a rapid random jump frequency dithering signal is obtained. Based on the reference frequency setting, the slow random triangular wave dithering signal, and the fast random jumping dithering signal, a digital adder is used to superimpose the values ​​of the three signals, and a numerically controlled oscillator is used to convert the frequency to a clock signal to obtain a real-time operating frequency signal with dual random characteristics.

3. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 1, characterized in that, The method of obtaining the time length value of the current switching cycle based on the real-time operating frequency signal and system clock, using cycle counting and numerical conversion methods, includes: Based on the real-time operating frequency signal, an edge detection circuit is used to identify the rising and falling edges of the signal. The rising edge detection signal is used as the start trigger signal of the switching cycle, and the falling edge detection signal is used as the end trigger signal of the cycle. Based on the start trigger signal of the switching cycle, the count value of the cycle counter is cleared to zero. Based on the system clock signal, a synchronous increment counting method is adopted. When the end trigger signal of the cycle is detected, the count value is latched into the cycle value register to obtain the clock pulse count value within the cycle. The time length of the current switching cycle is obtained by multiplying the clock pulse count value within the cycle with the system clock cycle. Data timing alignment is achieved using a pipelined register set, and data delay transmission is achieved using a two-level register set to obtain periodic data for slope compensation calculation.

4. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 1, characterized in that, The method of obtaining the target duty cycle value required to maintain output stability based on the input voltage sample value and the output voltage reference value, using digital division or lookup table methods, includes: The input voltage is sampled using a resistor divider network, analog-to-digital conversion is performed using an ADC, and noise suppression is achieved using a digital filter to obtain the digital sample value of the input voltage. Based on the output voltage reference value, the digital reference value of the output voltage is obtained using the same numerical unit and fixed-point number format as the input voltage sampling value; Based on the volt-second balance principle of Buck-type switching power supplies, a digital divider is used to divide the digital reference value of the output voltage by the digital sample value of the input voltage to obtain the digital representation of the target duty cycle. Based on the digital representation of the target duty cycle, a range limiting circuit is used for numerical constraints to set the minimum and maximum values ​​of the duty cycle, thereby obtaining the target duty cycle value used for slope compensation calculation.

5. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 1, characterized in that, The adaptive adjustment compensation slope value is obtained based on the target duty cycle value, the current switching cycle value, and system parameters, using a lookup table combined with interpolation or parameterized formula calculation methods, including: Based on the inductance value and the output voltage reference value, the inductance current slope calculation formula is used. In a Buck-type switching power supply, the falling slope of the inductance current is equal to the output voltage divided by the inductance value, thus obtaining the falling slope value of the inductance current. Based on the subharmonic oscillation theory of current mode control, the stability criterion is adopted to calculate the duty cycle correlation coefficient. The duty cycle correlation coefficient is multiplied by the inductor current drop slope and then multiplied by the preset margin coefficient to obtain the reference compensation slope value. Based on the period normalization method, an adjustment strategy in which the compensation slope is inversely proportional to the switching period is adopted. The frequency adjustment coefficient is obtained by dividing the reference switching period by the current switching period. The frequency adjustment coefficient is multiplied by the reference compensation slope value to obtain the adaptive compensation slope value that is adapted to the current frequency. Smoothing is performed based on a first-order IIR filter. A weighted average method is used to calculate the adaptive compensation slope value calculated in the current cycle and the compensation slope value used in the previous cycle, resulting in a smoothed adaptive compensation slope value.

6. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 5, characterized in that, The method for obtaining the adaptive compensation slope value adapted to the current frequency based on the period normalization method also includes: During the system initialization phase, based on the possible switching cycle range, the frequency adjustment coefficients corresponding to different switching cycles are pre-calculated using an offline calculation method, and the results are stored in a lookup table. Based on the current switching cycle value, the corresponding frequency adjustment coefficient is directly obtained by using a lookup table read operation; Based on the adjustment coefficients and baseline compensation slope values ​​read from the lookup table, a digital multiplier is used to perform multiplication operations to obtain the adaptive compensation slope value.

7. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 1, characterized in that, The method, based on the smoothed adaptive compensation slope value and the switching cycle synchronization signal, employs a digital ramp generation method to obtain a compensation ramp signal that matches the current operating frequency, including: Based on the start trigger signal of the switching cycle, the register of the accumulator is cleared to zero by the register reset operation to obtain the initial zero value state of the ramp generator; The slope increment per clock cycle is obtained by multiplying the smoothed adaptive compensation slope value by the system clock cycle time. Based on the slope increment value, the accumulator adds the current accumulated value to the slope increment value at each rising edge of the system clock to obtain a real-time increasing digital ramp signal. Based on the digital ramp signal, a moving average filter is used to suppress high-frequency noise, and an output buffer register is used for timing alignment to obtain a compensated ramp signal for current control.

8. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 1, characterized in that, The method of obtaining a stable LED drive current output based on the compensated ramp signal and the inductor current sampling signal, using digital addition and comparison control, includes: The analog signal of the inductor current is obtained by acquiring the current sensing resistor or Hall sensor, and the analog-to-digital conversion is performed by a high-speed ADC. The noise is suppressed by digital signal processing methods to obtain the digital sample value of the inductor current. Based on the compensation ramp signal and the digital sampled value of the inductor current, a digital adder is used to superimpose the values ​​of the two signals to obtain the superimposed control signal. Based on the output current reference value, the digital reference value for current control is obtained by using the same numerical unit and fixed-point number format as the control signal. The superimposed control signal is compared with the current reference value in real time using a digital comparator. When the control signal is greater than or equal to the current reference value, a turn-off command is generated. The turn-on and turn-off control logic of the switching transistor is constructed using an RS flip-flop to obtain the switching transistor control command.

9. The method for dual random frequency dithering and adaptive slope compensation of a switching power supply according to claim 8, characterized in that, The process of obtaining a stable LED drive current output also includes: Based on the conduction state of the switching transistor, an inductor energy storage mechanism is adopted, and the inductor current increases linearly. Based on the off state of the switching transistor, a freewheeling diode freewheeling mechanism is adopted, and the inductor current decreases linearly. Based on the output capacitor connected in parallel across the LED load, the pulsating component of the inductor current is filtered, and the duty cycle is kept stable through an adaptive slope compensation mechanism to ensure that the energy stored and released by the inductor remains balanced in each switching cycle, so that the average value of the output current remains constant. Based on the current feedback closed-loop regulation mechanism, the duty cycle is automatically adjusted when the output current deviates from the reference value, so that the output current returns to the reference value and a stable LED drive current output is obtained.

10. A dual random frequency dithering and adaptive slope compensation circuit for a switching power supply, used to perform the steps in the dual random frequency dithering and adaptive slope compensation method for a switching power supply as described in any one of claims 1-9, characterized in that, include: The signal generation module generates a two-layer independent random sequence based on a pseudo-random number generator, and uses a layered mapping method to obtain a slow random triangular wave dithering signal and a fast random jump dithering signal. The switching cycle detection module, based on the real-time operating frequency signal and the system clock, uses cycle counting and numerical conversion methods to obtain the time length value of the current switching cycle; The target duty cycle calculation module, based on the input voltage sample value and the output voltage reference value, uses digital division or lookup table method to obtain the target duty cycle value required to maintain output stability; The slope calculation module, based on the target duty cycle value, the current switching cycle value, and system parameters, uses a lookup table combined with interpolation or parameterized formula calculation method to obtain the adaptively adjusted compensation slope value; The compensation ramp signal generation module, based on the smoothed adaptive compensation ramp value and the switching cycle synchronization signal, uses a digital ramp generation method to obtain a compensation ramp signal that matches the current operating frequency. The mode control and output module, based on the compensation ramp signal and the inductor current sampling signal, uses digital addition and comparison control methods to obtain a stable LED drive current output.

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