Voltage equalization control method for multi-module converters

Abstract

This invention relates to the field of multi-module power conversion control and discloses a voltage equalization control method for multi-module converters, comprising: real-time acquisition of the input voltage of each module and the transient load current of the main power circuit; determining the phase shift control priority based on the voltage deviation; extracting the physical hysteresis parameters of the power switch tubes based on the transient load current and determining the pre-bias compensation amount; constructing a bipolar zero-sum phase shift trajectory within a single high-frequency switching cycle. This invention utilizes asymmetric time offset to actively offset the physical switch action deviation, achieving zeroing of the volt-second area within a single cycle and forcibly completing the transformer flux reset, thus resolving the contradiction between voltage equalization depth and magnetic balance from a physical level, and improving the voltage response speed and magnetic circuit operation safety of the multi-module converter system under sudden load changes.

Description

Technical Field

[0001] This invention belongs to the field of multi-module power conversion control technology, and particularly relates to a voltage equalization control method for multi-module converters. Background Technology

[0002] In current multi-module converter systems with a primary-side series and secondary-side parallel architecture, the high-voltage bus voltage is distributed by combining power modules in series and parallel to reduce the voltage stress on individual power transistors. However, due to the physical differences in leakage inductance parameters of the power transformers of each module, drive signal transmission delay, and parasitic parameters, the input voltage distribution of the modules in the primary-side series circuit is uneven, resulting in overvoltage risk for some module power devices. Input voltage equalization is achieved by adjusting the equivalent impedance of each module through phase-shift control strategies. However, the dynamic response speed of voltage equalization is limited by the magnetic balance constraint of the high-frequency power transformer. The sudden phase angle changes generated by the control algorithm disrupt the volt-second area symmetry of the transformer primary winding in a single switching cycle, inducing transient DC bias in the excitation current, leading to core saturation and damage to power devices. Conventional techniques use phase shift rate limiting or dead zone adjustment to limit the depth of phase shift angle adjustment. This approach reduces the system's voltage dynamic equalization capability and causes voltage equalization response lag under load change conditions.

[0003] Besides hardware limitations, at the control logic level, existing technologies often alleviate magnetic circuit safety issues by strengthening bias detection and feedback control. For example, Chinese invention patent CN117955325B discloses a DC bias detection circuit and DC bias suppression method for a phase-shifting full-bridge converter. It cascades four second-order active low-pass filters to construct an eighth-order low-pass filter to extract the DC component of the primary current as the basis for bias control. This type of scheme is a post-processing adjustment of sampling filtering. High-order filters contain group delay and phase lag characteristics. When the system is dealing with extremely fast dynamic scenarios such as step loads, it cannot achieve real-time compensation and tracking of magnetic flux offset. This scheme does not address the nonlinear dynamic physical characteristics such as the Miller effect of power switches that disturb the volt-second product layer. It is difficult to eliminate the time-domain coupling contradiction between energy distribution weight adjustment and magnetic circuit volt-second integral balance from the driving source.

[0004] Therefore, how to break the time-domain coupling between energy extraction and magnetic flux reset in phase-shift control is the technical problem to be solved by this invention. Summary of the Invention

[0005] The present invention aims to solve the physical conflict between the dynamic response speed and the volt-second balance of the high-frequency transformer during the voltage equalization process.

[0006] In this technical solution, a voltage equalization control method for a multi-module converter includes the following steps:

[0007] Step 101: Real-time acquisition of DC bus input voltage of each module and transient load current of main power circuit;

[0008] Step 102: Compare the input voltage of each module with the preset average voltage value to determine the deviation, and sort the energy transmission timing priority of each module in descending order according to the magnitude of the deviation.

[0009] Step 103: Based on the mapping relationship between the magnitude of the transient load current and the physical switching delay time caused by the charging and discharging of the parasitic capacitance of the power switch, determine the pre-bias compensation amount for the PWM comparator register to compensate for the execution time bias error caused by the Miller plateau effect during the turn-on and turn-off phases of the power switch.

[0010] Step 104: Within a complete high-frequency switching cycle, the trigger time of the phase-shifting pulse of each module is determined according to the priority of energy transfer timing, and a pre-bias compensation amount is injected during the process of reloading the PWM comparator register by the PWM control signal to construct a bipolar zero-sum phase-shifting trajectory.

[0011] Step 105: The adjustment depth of the phase shift sequence is limited by the magnetic balance constraint logic. By adjusting the effective phase shift angle width of each module within a switching cycle, the energy distribution weight of the primary winding of the power transformer corresponding to each module on the time axis is changed. Under the premise of maintaining the volt-second balance of the transformer core, the dynamic balance of the input voltage of each module is achieved.

[0012] Preferably, step 102 specifically includes the following sub-steps: step 1021, calculating the absolute value of the deviation between the input voltage and the average voltage of each module; step 1022, arranging the absolute values ​​of the deviation in descending order, and determining the module with the largest absolute value of the deviation as having the highest energy transmission timing priority, for priority impedance adjustment.

[0013] Preferably, the method for compensating for the execution time bias error of the power switch during the turn-on and turn-off phases includes: extracting the gate charge characteristics of the power switch under different load currents, and converting the gate charge characteristics into the corresponding switching action lead or lag time, so as to correct the dead-time symmetry of the PWM drive signal.

[0014] Preferably, step 104 specifically includes the following sub-steps: step 1041, calculating the trigger time correction value of the PWM drive signal in the positive half-cycle; step 1042, determining the offset offset in the negative half-cycle based on the trigger time correction value; step 1043, making the integral of the voltage across the transformer winding with respect to time generate mutually canceling volt-second areas in a single cycle.

[0015] Preferably, the step of adjusting the energy distribution weight of each module on the time axis includes: changing the effective conduction time ratio of the primary winding of each module by moving the starting position of the effective phase shift angle of each module within the switching cycle, thereby changing the equivalent impedance presented by the primary winding in the primary series circuit.

[0016] Preferably, the step of using magnetic balance constraint logic to limit the adjustment depth of the phase shift sequence includes: obtaining the critical value of the saturation flux of the transformer core, calculating the maximum allowable asymmetric time deviation under the critical value, and using the maximum asymmetric time deviation as the boundary constraint for energy transmission timing priority adjustment.

[0017] Preferably, after reconstructing the energy distribution weights of the primary windings of the power transformers corresponding to each module on the time axis, the method further includes the following steps: monitoring the convergence rate of the input voltage of each module; when the convergence rate is lower than the set sensitivity threshold, increasing the adjustment coefficient of the effective phase shift angle width.

[0018] Preferably, the step of achieving dynamic equalization of the input voltage of each module further includes: comparing the input voltage of each module in real time, and when the input voltage of any module exceeds the safety threshold of 600V, removing the phase shift rate limitation and adjusting the effective phase shift angle width through the bipolar zero-sum phase shift trajectory.

[0019] Preferably, the step of reconstructing the equivalent impedance of each module in the primary circuit includes: calculating the voltage scalar shared by each module in the primary series circuit based on the energy transfer timing priority, and adjusting the triggering timing of the PWM drive signal in the positive and negative half cycles to make the transformer of each module generate an asymmetrical impedance response in a single cycle.

[0020] Compared with existing technologies, the voltage equalization control method for multi-module converters of the present invention has the following advantages:

[0021] 1. In the voltage equalization control of a multi-module converter, by constructing a bipolar zero-sum phase-shift trajectory within a single high-frequency switching cycle, the triggering time of the PWM drive signal in the positive and negative half-cycles is changed, so that the voltage across the transformer windings is integrated with respect to time to generate mutually offset volt-second areas within a single cycle. Since this mechanism forces the magnetic flux reset through an asymmetric time offset on the time axis, it eliminates the physical constraints on the phase shift adjustment depth in the converter control. When the system faces severe input voltage fluctuations, it can cancel the traditional phase shift rate limiting protection, achieve rapid reconstruction of the equivalent impedance, and avoid capacitor overvoltage failure caused by the lag in the inter-module voltage equalization response.

[0022] 2. By extracting the transient load current of the main power circuit and physically mapping it to the physical hysteresis asymmetry parameter of the power switch, a pre-bias compensation amount is actively injected during the reload process of the digital controller's comparator register. This mechanism accurately smooths out the switching time deviation caused by the Miller effect and parasitic capacitance charging and discharging of semiconductor devices, solves the distortion problem between the ideal digital instructions and the underlying physical execution interface, makes the excitation current of the transformer core return to zero at the end of each switching cycle, blocks the accumulation path of DC bias of magnetic flux, and enhances the operational reliability of multi-module series systems under high frequency and full load conditions. Attached Figure Description

[0023] Figure 1 This is a flowchart of the bipolar zero-sum phase-shifting voltage equalization control of the present invention;

[0024] Figure 2 This is a system architecture diagram of the present invention that integrates physical error hedging and magnetic balance constraints. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0026] It should be noted that all directional and positional terms used in this invention, such as: up, down, left, right, front, back, vertical, horizontal, inner, outer, top, bottom, transverse, longitudinal, center, etc., are only used to explain the relative positional relationship and connection between components in a specific state (as shown in the accompanying drawings). They are only for the convenience of describing this invention and do not require that this invention be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. In addition, the descriptions of "first," "second," etc., in this invention are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated.

[0027] In the description of this invention, unless otherwise explicitly specified and limited, the terms installation, connection, and linking should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0028] In the description of this specification, references to the terms "an embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example, and the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0029] A voltage equalization control method for a multi-module converter includes the following steps:

[0030] Step 101: Real-time acquisition of DC bus input voltage of each module and transient load current of main power circuit;

[0031] Step 102: Compare the input voltage of each module with the preset average voltage value to determine the deviation, and sort the energy transmission timing priority of each module in descending order according to the magnitude of the deviation.

[0032] Step 103: Based on the mapping relationship between the magnitude of the transient load current and the physical switching delay time caused by the charging and discharging of the parasitic capacitance of the power switch, determine the pre-bias compensation amount for the PWM comparator register to compensate for the execution time bias error caused by the Miller plateau effect during the turn-on and turn-off phases of the power switch.

[0033] Step 104: Within a complete high-frequency switching cycle, the trigger time of the phase-shifting pulse of each module is determined according to the priority of energy transfer timing, and a pre-bias compensation amount is injected during the process of reloading the PWM comparator register by the PWM control signal to construct a bipolar zero-sum phase-shifting trajectory.

[0034] Step 105: The adjustment depth of the phase shift sequence is limited by the magnetic balance constraint logic. By adjusting the effective phase shift angle width of each module within a switching cycle, the energy distribution weight of the primary winding of the power transformer corresponding to each module on the time axis is changed. Under the premise of maintaining the volt-second balance of the transformer core, the dynamic balance of the input voltage of each module is achieved.

[0035] Preferably, step 102 specifically includes the following sub-steps: step 1021, calculating the absolute value of the deviation between the input voltage and the average voltage of each module; step 1022, arranging the absolute values ​​of the deviation in descending order, and determining the module with the largest absolute value of the deviation as having the highest energy transmission timing priority, for priority impedance adjustment.

[0036] Preferably, the method for compensating for the execution time bias error of the power switch during the turn-on and turn-off phases includes: extracting the gate charge characteristics of the power switch under different load currents, and converting the gate charge characteristics into the corresponding switching action lead or lag time, so as to correct the dead-time symmetry of the PWM drive signal.

[0037] Preferably, step 104 specifically includes the following sub-steps: step 1041, calculating the trigger time correction value of the PWM drive signal in the positive half-cycle; step 1042, determining the offset offset in the negative half-cycle based on the trigger time correction value; step 1043, making the integral of the voltage across the transformer winding with respect to time generate mutually canceling volt-second areas in a single cycle.

[0038] Preferably, the step of adjusting the energy distribution weight of each module on the time axis includes: changing the effective conduction time ratio of the primary winding of each module by moving the starting position of the effective phase shift angle of each module within the switching cycle, thereby changing the equivalent impedance presented by the primary winding in the primary series circuit.

[0039] Preferably, the step of using magnetic balance constraint logic to limit the adjustment depth of the phase shift sequence includes: obtaining the critical value of the saturation flux of the transformer core, calculating the maximum allowable asymmetric time deviation under the critical value, and using the maximum asymmetric time deviation as the boundary constraint for energy transmission timing priority adjustment.

[0040] Preferably, after reconstructing the energy distribution weights of the primary windings of the power transformers corresponding to each module on the time axis, the method further includes the following steps: monitoring the convergence rate of the input voltage of each module; when the convergence rate is lower than the set sensitivity threshold, increasing the adjustment coefficient of the effective phase shift angle width.

[0041] Preferably, the step of achieving dynamic equalization of the input voltage of each module further includes: comparing the input voltage of each module in real time, and when the input voltage of any module exceeds the safety threshold of 600V, removing the phase shift rate limitation and adjusting the effective phase shift angle width through the bipolar zero-sum phase shift trajectory.

[0042] Preferably, the step of reconstructing the equivalent impedance of each module in the primary circuit includes: calculating the voltage scalar shared by each module in the primary series circuit based on the energy transfer timing priority, and adjusting the triggering timing of the PWM drive signal in the positive and negative half cycles to make the transformer of each module generate an asymmetrical impedance response in a single cycle.

[0043] Example 1: In a DC distribution network conversion environment with a rated DC bus voltage of 1500V, a high-frequency conversion system composed of multiple power modules connected in series on the input side and parallel on the secondary side is used. When a step change occurs on the load side, causing a transient disturbance of 200V / μs in the DC bus potential, the modules in the primary-side series circuit experience an input voltage imbalance due to the 5% dispersion of the power transformer leakage inductance parameters and the inconsistency of the dynamic impedance of the power devices. This causes the input voltage of some modules to tend towards the 600V safe withstand voltage limit of the power devices. The system needs to adjust the phase shift angle within the response time to reshape the equivalent impedance of each module to reduce the overvoltage module potential. There is a physical constraint between the phase shift angle step change disrupting the volt-second area symmetry of the transformer winding in a single switching cycle, thereby inducing the excitation current to generate DC bias and causing core saturation damage. In the multi-module series system of this invention, since the total rated input bus voltage is between 1200V and 1500V, In a series circuit consisting of four power modules, ideally, the average static DC voltage shared by each module should be within the physically safe steady-state range of 300V to 375V. However, the rated breakdown voltage limit of the individual high-frequency semiconductor power transistors and bus support capacitors used in each power module in this solution is 650V. Considering the transient dynamic overshoot that will inevitably be caused by the switching of high-power step loads in industrial power distribution networks, and in accordance with the voltage stress derating principle of reserving a 10% safety margin in power electronics engineering design, the upper limit of the absolute transient voltage that each module can withstand is locked at 600V. Once the DC bus input voltage of a module exceeds this hard limit, it indicates that the device of that module is approaching the failure threshold of avalanche breakdown. At this time, the system must unconditionally release the phase shift rate safety limit protection set by the software layer and implement a forced voltage drop on the overvoltage module at the highest dynamic speed of impedance reconstruction, thereby ensuring the hardware survival rate of the system under extreme load change scenarios.

[0044] At the lowest level of the controller, the digital controller collects the DC bus input voltage of each module and the transient load current of the main power circuit in real time. It compares the input voltage of each module with the preset average voltage value and sorts the energy transfer timing priority of each module in descending order according to the magnitude of the deviation. The digital controller determines the target phase shift adjustment time for a specific module caused by the voltage deviation. The digital controller extracts the physical hysteresis asymmetry parameters of the power switch transistor in this module due to the Miller plateau effect from the nonlinear switching hysteresis quantization mapping table of the power device based on the currently collected transient load current. During the current high-frequency switching cycle of the power module, the pulse width modulation generator of the digital controller performs asymmetric reloading on the comparator register. During the positive half-cycle conduction interval of the switching cycle, the trigger time of the pulse width modulation signal controlling the primary-side full-bridge lag arm switching transistor of the module is advanced by an additional time increment. To increase the proportion of energy extracted from the primary-side series bus and reduce its input voltage during the positive half-cycle of the module, and within the negative half-cycle conduction interval of the same switching cycle, the triggering time of the corresponding opposite bridge arm switch is delayed by a pre-bias time amount equal to... and The sum of these factors allows for the construction of a phase-shifting trajectory with bipolar zero-sum characteristics within a single switching cycle. By offsetting the transient inertial deviation of the power MOSFET during the turn-on and turn-off phases through asymmetric time offset, the integral of the physical voltage actually borne by the primary winding of the high-frequency transformer of this module with respect to time converges to zero within a single cycle. Without setting a phase shift rate limit, the cumulative path of the excitation current DC bias is blocked. The system reshapes the equivalent impedance under sudden load conditions, and the input voltage of the overvoltage module recovers to a safe voltage balance state within a 500μs response time, ensuring that the transformer core maintains volt-second balance during timing adjustment.

[0045] Example 2: The current test system consists of four power modules connected in series on the input side and parallel on the secondary side. The DC input power supply is set to 1200V, and the programmable electronic load has a rated power of 20kW. The voltage sampling circuit is equipped with four high-precision Hall voltage sensors with a range of 0V to 800V and a linearity better than 0.1%, used to monitor the DC bus input voltage of each module. The current sampling circuit is equipped with a Rogowski coil with a bandwidth of 2MHz to acquire the transient load current of the main power circuit. By setting a 5% to 10% leakage inductance parameter deviation in the primary winding of the high-frequency transformer in each module, the physical hysteresis parameter in this invention can directly capture the rising or falling edge details of the power transistor switching transient due to the physical bandwidth limitation of the Rogowski coil. The precise acquisition is not based on macroscopic acquisition of a single switching waveform, but rather on monitoring the DC component accumulated in the transformer excitation current due to the volt-second area asymmetry using a Rogowski coil. Furthermore, by performing closed-loop feedback calculations on the changing trend of the DC component over multiple switching cycles, the nanosecond-level time offset residual generated by the power transistor during physical-level execution is derived through reverse iteration. This enables cross-scale accurate identification of high-frequency physical errors using a low-bandwidth sensor. Additionally, broadband noise with a signal-to-noise ratio of 20dB is superimposed onto the voltage acquisition channel to simulate input voltage distribution imbalance and industrial electromagnetic interference environments. The sampling period of the digital controller is also considered. Based on the converter switching frequency Confirmed, when At 100kHz, to ensure that the energy transfer timing priority rearrangement is supported within a single switching cycle, the sampling frequency is set to 10 times the switching frequency, and the sampling period is... Determined to be 1 Furthermore, in the actual operation of capturing the DC component of the excitation current using a Rogowski coil, the Rogowski coil cannot directly maintain a static DC signal due to its low-frequency cutoff characteristics. Therefore, the DC component of this invention... The monitoring is indirectly characterized by the asymmetry trend of the positive and negative half-wave peak envelopes at the integrator output over dozens of consecutive high-frequency switching cycles. Specifically, the physical output signal of the Rogowski coil used in this invention is an induced voltage proportional to the rate of change of the current passing through it. This voltage signal is conditioned by a high-speed active hardware integrator and then input to the analog-to-digital conversion channel of the digital controller. Although the conditioned signal loses the static DC component with absolute zero potential due to the low-frequency DC blocking characteristic of the integrator, the complete AC waveform profile of the high-frequency excitation current is preserved with high fidelity. When the transformer induces a biased magnetization trend in the excitation current due to unidirectional volt-second area asymmetry, the transient operating point of the transformer core will shift towards the saturation knee of the magnetization curve, which causes its... The equivalent magnetizing inductance decreases sharply during the half-cycle of the bias direction, thus generating a significant nonlinear high-frequency spike warp at the peak end of the corresponding positive or negative half-cycle of the primary current, while the current waveform in the opposite half-cycle maintains a normal linear slope. Since this nonlinear warp only occurs within a specific half-cycle of a single switching cycle, its corresponding AC spike frequency is much higher than the low-frequency cutoff frequency of the Rogowski coil and the hardware integrator. Therefore, an asymmetry difference immediately arises between the absolute values ​​of the positive and negative half-cycle peak voltages at the integrator output. The digital controller calculates the algebraic difference between the positive and negative envelope peak values ​​of this AC spike waveform in each high-frequency switching cycle by differentially sampling the positive and negative envelope peak values. This algebraic difference is used as an indirect characterization of the DC bias of the magnetizing current. The deterministic physical criteria perfectly circumvent the limitations of physical sensors in measuring static DC components. Specifically, when volt-second area asymmetry causes unidirectional bias in the magnetic core, the inductive saturation characteristic of the transformer excitation current leads to nonlinear warping of the primary current in one half-cycle. The Rogowski coil captures the asymmetric distortion rate of this high-frequency AC spike and transmits it to the digital controller. The differential recursive smoothing estimator inside the controller then performs continuous... The peak difference within each switching cycle is accumulated to extract the bias magnetization integral, which is deterministically positively correlated with the DC component of the excitation current. In the discrete control software layer of the digital controller, this differential recursive smoothing estimator is used in the current... Within each switching cycle, the peak value of the positive half-cycle of the integrator output waveform is first synchronously acquired via an analog-to-digital converter. With the negative half-cycle peak sampling value The transient asymmetry deviation is obtained by performing a subtraction operation. Subsequently, the estimator invokes an internally configured circular first-in-first-out temporary queue, the length of which is strictly configured to the preset total number of cycles. The estimator will use the currently calculated transient deviation. Write to the tail of the queue, and simultaneously pop the latched first item from the head of the queue. Historical deviation from one period ago Finally, the algorithm unit performs differential recursive smoothing iterative calculations, and its discrete recursive formula is: In the formula This is the updated value of the bias integral output during the current switching cycle. This output value directly serves as a smoothed filtered digital signal that quantitatively reflects the DC bias trend of the excitation current. Its data format is a 32-bit floating-point number, which is directly transmitted to the subsequent step adjustment control register. Based on this, the digital controller uses the bias integral as the input disturbance source for the system closed-loop feedback. Using a preset integral convergence step algorithm, with nanosecond-level as the minimum adjustment resolution, it successively fine-tunes the dead zone edge of the positive and negative half-cycles of the drive signal. When the bias integral is offset to below the preset safety threshold, the currently accumulated timing correction corresponds to the nanosecond-level time bias residual caused by the Miller plateau and device discreteness, thereby realizing cross-scale physical error reverse closed-loop identification. In order to completely eliminate the control lag caused by the above-mentioned multi-cycle long-delay accumulation identification mechanism when the system responds to sudden load changes, this invention splits the entire voltage equalization control loop into independent transient feedforward channels and steady-state feedback channels. Among them, the digital controller captures the transient load current of the main power loop in real time at a sampling frequency of 1MHz. Once the load current change rate is detected to exceed the preset transient jump threshold, the algorithm unit immediately disables the slow feedback correction loop that relies on multi-cycle integration with the Rogowski coil, and instead directly utilizes the transient load current acquired during the current switching cycle. Real-time retrieval of a one-dimensional mapping table in random access memory to instantly generate the required physical hysteresis parameters within the current single switching cycle. Phase shift adjustment time with target The feedforward reference combination directly reloads the pulse width modulation comparator register to construct a bipolar zero-sum phase-shift trajectory. Since this transient feedforward action directly bypasses the accumulation process of multi-cycle bias trends, it ensures rapid reconstruction of the primary-side equivalent impedance and immediate zeroing of the volt-second area within the first cycle of the transient state with a sudden load change. The time-bias residual identified by the aforementioned multi-cycle long-delay accumulation is only superimposed on the feedforward reference as a slow adaptive drift correction factor after the system enters the quasi-steady state. This architecturally achieves time-domain decoupling between rapid transient response and accurate steady-state calibration. The pre-bias compensation amount... Derived from the turn-on delay time of power switching transistors under different drain currents With shutdown delay time The physical mapping relationship, based on the currently collected transient load current. By retrieving physical hysteresis parameters and correcting the volt-second area deviation caused by switching actions through asymmetric time offset, at the physical execution level, the digital controller's pulse width modulation generator integrates a high-resolution HRPWM peripheral. The internal counting clock frequency is selected to be more than 100 times the sampling frequency. The HRPWM peripheral has sub-nanosecond pulse edge stepping capability, ensuring the sub-microsecond offset calculated by the digital controller. and It directly converts the duty cycle edge jump of the physical drive signal, eliminating the physical limitation of the sampling period on the phase shift control resolution.

[0046] The experimental group employed a voltage equalization control method for multi-module converters. Control group A used evenly distributed phase-shift control without injecting asymmetric compensation, while control group B injected a fixed compensation exceeding the physical mapping range by 50%. Under the condition that the load stepped from 20% to 80% of the rated power, the DC bus input voltage of module one in control group A increased from 300.2V to 385.6V, and the DC component of the transformer excitation current... The voltage accumulated from 0.05A to 1.42A over 5 switching cycles; control group B generated a residual inter-module voltage difference of 15.4V, accompanied by high-frequency potential oscillations; the experimental group showed a voltage difference of 425.6V after a load step change. Within s, the target phase shift adjustment time determined by the digital controller It is 0.45 s, physical hysteresis asymmetric parameter It is 0.12 s; At this time, the maximum deviation of the input voltage of each module in the test group decreased from 85.4V to 2.8V, and the DC component of the excitation current The voltage was maintained below 0.08A. In different voltage deviation gradient tests, as the initial voltage deviation between modules increased from 20V to 100V, the voltage equalization convergence time showed a trend of increasing with the degree of deviation. When the initial voltage deviation exceeded 120V, the voltage regulation rate tended to level off because the phase shift angle adjustment range was limited by the maximum duty cycle boundary. The construction of the bipolar zero-sum phase shift trajectory corrected the physical execution deviation of the power switch, and the input voltage of each module recovered to equilibrium under the condition of sudden load change. The high-frequency transformer core maintained volt-second balance during the adjustment process. This is the DC bus input voltage. This is the transient load current. The sampling period is For switching frequency, For physical hysteresis asymmetric parameters, Due to the delay in opening time, To delay the shutdown time, This is the DC component of the excitation current. The target phase shift adjustment time.

[0047] Example 3: In high-frequency power electronic conversion scenarios, when an input series-connected secondary-side parallel system composed of multiple power modules faces a 15% dispersion in the parasitic parameters of the power devices, the modules in the primary circuit experience substantial volt-second area asymmetry due to the inconsistency between the turn-on and turn-off delays during the switching process. This results in the DC bus input voltage of each module being affected. Deviation from preset average voltage The system addresses the voltage equalization barrier caused by inconsistencies in the microscopic actions of devices through a physical hysteresis parameter calibration procedure. This procedure utilizes a dual-pulse experimental platform to collect the turn-on delay time of the power module under a load current gradient ranging from 0A to 50A. With shutdown delay time And calculate the corresponding physical hysteresis asymmetric parameters at each current sampling point. ,in, for and The algebraic difference value, the obtained data is expressed as transient load current. A one-dimensional image table is formed for indexing and stored in the random access memory of the digital controller.

[0048] The digital controller periodically acquires the DC bus input voltage of each module. And calculate the algebraic average of the current voltages of all modules to update the voltage mean. The algorithm unit establishes the energy transfer timing priority based on the voltage of each module and the direction and magnitude of its deviation. Voltage values ​​higher than the average voltage are prioritized. Furthermore, the module with the largest absolute value of the deviation is assigned the highest priority; the digital controller calculates the target phase shift adjustment time based on the deviation. The specific calculation formula is as follows: ,in, The target phase shift adjustment time. For impedance adjustment gain coefficient, This is the DC bus input voltage. This is the average voltage.

[0049] During the pulse width modulation signal generation stage, the pulse width modulation generator of the digital controller calculates... And retrieved from the one-dimensional mapping table The overloaded pulse width modulation comparator register, during the positive half-cycle conduction interval of the switching cycle, advances the triggering time of the control lag arm switch by an additional time amount. This extends the energy extraction time of the module during the positive half-cycle and reduces its input voltage; during the negative half-cycle conduction interval of the same switching cycle, the trigger time of the corresponding opposite bridge arm switch is delayed by a pre-bias time amount, which is equal to... and The arithmetic sum is used to construct a bipolar zero-sum phase-shift trajectory within a single switching cycle. Before performing the arithmetic summation, the digital controller pre-establishes... Polarity mapping rule: Define the direction of energy interference caused by the power transistor's turn-off delay being greater than its turn-on delay as positive, and if the current deviation... The aim is to reduce the energy in that direction. By substituting positive values ​​into the calculation, the hysteresis offset of the negative half-cycle is increased, thereby generating an equivalent energy offset in the reverse cycle. Through this real-time matching of algebraic signs, it is ensured that the compensation amount can force the volt-second area to zero within a single cycle, regardless of the direction of the physical hysteresis, thus avoiding the problem of magnetic bias aggravation caused by sign mismatch. The above-mentioned asymmetric drive logic based on register count value fine-tuning realizes real-time offsetting of the time bias error of the power switch during the physical switching stage, so that the physical volt-second integral borne by the primary winding of the high-frequency transformer in both the positive and negative half-cycles converges to zero, blocking the accumulation path of DC bias of the excitation current. Experimental data show that after adopting this calibration procedure, the multi-module converter system maintains the input voltage deviation of each module within 1.5% of the rated voltage range under load change conditions. Each module achieves autonomous adjustment of equivalent impedance through the reshaping of the underlying timing weights, completing the system-level voltage equalization response on the foundation of maintaining the stability of the transformer magnetic circuit.

[0050] Example 4: In a high-frequency DC power distribution conversion scenario, due to parameter drift caused by the power switching transistors under continuous thermal stress, which varies with junction temperature, the preset physical hysteresis mapping table becomes mismatched with the current switching characteristics of the devices. The system adjusts the voltage equalization deviation caused by device aging through a low-level online timing self-calibration process. This process is implemented at the DC bus input voltage of each module. When the steady-state deviation continuously exceeds 2% of the rated value, the digital controller triggers the power module to enter micro-pulse detection mode. In micro-pulse detection mode, the digital controller utilizes the idle period of the power converter's dead time to inject an extremely narrow voltage pulse with a pulse width lower than the power device's turn-on threshold and without causing a change in the main circuit's energy flow direction into a specific bridge arm. The current sensor synchronously captures the charging and discharging current waveform of the switching transistor's parasitic capacitance under this micro-disturbance, thereby extracting real-time characteristic values ​​reflecting the actual switching delay of the device. Since this detection action occurs in the inactive region of energy transfer, it is crucial to obtain the physical hysteresis correction factor. At the same time, it will not interfere with the normal bus voltage regulation process. The current sampling loop captures the turn-off time residual of the switching transistor under extremely small current, and the physical hysteresis correction factor is determined by calculating the difference between this residual and the reference value in the one-dimensional mapping table. The core physical basis for the micro-pulse detection mechanism here to accurately characterize the Miller platform's action delay under high current full-load conditions lies in the gate-drain parasitic capacitance inside the semiconductor power device and the equivalent output capacitance formed by the junction. It possesses a characteristic sensitivity coefficient that is completely synchronized with the junction temperature of the core semiconductor inside the device. Although the narrow pulse amplitude of 30ns to 50ns is low and does not cause the main circuit of the power transistor to cross the macroscopic turn-on threshold, thus exhibiting a weak charge and discharge current in the milliampere range, the transient slope and peak timing of the charging waveform of this microcurrent as it flows through the gate drive circuit are entirely dependent on the internal integrated gate resistor determined by the current junction temperature. and capacitor The product of physical constants; because the underlying core cause of the bias error in the Miller platform switching action under high current full load conditions is also due to the junction temperature rise caused by continuous thermal stress. and The nonlinear parameter drift of the Miller platform under high current and high voltage has a completely consistent physical evolution trajectory and a deterministic proportional mapping relationship with the micro-charging delay change trend under low voltage micro-pulse. This invention is based on this common junction temperature physical link. By extracting micro-delay features in the safe inactive range, it can achieve cross-scale accurate inversion of the thermal drift of the Miller platform under full load dynamic execution. In actual operation, the micro-pulse detection mode is initiated by the digital controller during the transition between transient and steady state of the converter and the dead zone overlap conduction period of the full-bridge complementary switching transistors. The digital controller controls the pulse width modulation generator to emit a narrow pulse signal with a duration of only 30ns to 50ns. Although the amplitude of the pulse reaches the gate drive level, the power transistor remains blocked during this period because the duration is much lower than the delay threshold required for the main power circuit of the switching transistor to turn on, thus ensuring that the energy flow direction of the main circuit does not change. At this time, the detection micro-pulse only detects the gate parasitic capacitance and the drain-source equivalent output capacitance of the switching transistor. A weak charge and discharge operation is performed, generating a charge and discharge current waveform in the milliampere range. This weak current signal is amplified and impedance-transformed by a high-speed differential broadband amplifier circuit connected in parallel across the low-inductance shunt resistor in the main circuit, conditioning it into a voltage signal that conforms to the range of the digital controller's analog-to-digital converter interface. The ADC sampling unit of the digital controller uses the trigger event of an internal high-resolution timer to synchronously start high-frequency oversampling at the instant the micropulse is emitted, capturing the rising edge timing and peak drop point of the charge and discharge current. This allows the extraction of micro-switching action delay characteristic values ​​reflecting the current actual junction temperature state of the device, thereby completing self-calibration. To convert the captured current waveform characteristic values ​​into a physical hysteresis correction factor for correcting the pulse width modulation timing, further processing is performed. The mathematical operation unit inside the digital controller performs the following mapping and calculation steps: First, the high-resolution timer directly calculates the characteristic value of the actual capacitor charging duration under the current micropulse based on the counter difference between the start time of the current rising edge and the peak drop point when the current falls to a specified threshold. Next, the controller retrieves the standard micro-pulse charging time constant, pre-calibrated by the system at a standard reference junction temperature of 25°C, from the non-volatile memory. And calculate the thermal drift residuals of the two. Finally, the algorithm unit substitutes the residual into the one-dimensional linear compensation equation. In the scaling process, the formula is used to perform scale mapping. The physical hysteresis correction factor is calculated and output based on the dimensionless proportionality coefficient obtained through a two-pulse thermal simulation experiment. The data type is a signed high-precision integer, whose value directly corresponds to the primary color clock step level that needs to be fine-tuned in the pulse width modulation register, thus completing the closed-loop quantization conversion of the micro signal into the macro control timing compensation quantity.

[0051] When the digital controller detects the impedance adjustment gain coefficient When the output is at the maximum phase shift angle limiting boundary for 10 consecutive switching cycles and the voltage deviation between modules has not converged, the algorithm unit will correct the factor. Injection of physical hysteresis asymmetric parameters The computational circuit, by reconstructing the asymmetric phase-shifting sequence containing time offset compensation, intervenes in the counter reload logic of the pulse width modulation generator, so that the difference in the triggering time of the drive pulse in the positive and negative half cycles cancels out the physical time delay caused by thermal effects. As the corrected bipolar zero-sum phase-shifting trajectory is loaded into the pulse width modulation comparison register, the physical volt-second integral of the primary winding of the high-frequency transformer converges to zero in a single cycle, and the DC bus input voltage deviation of each module is reduced to a balanced level of 0.8% while the load remains unchanged.

[0052] Example 5: Magnetic balance constraint operator in DC-DC converter systems with power density requirements exceeding 30kW / L and employing high-frequency silicon carbide devices. Based on the working magnetic flux density of the power transformer core Magnetic core cross-sectional area and the number of turns of the primary winding The digital controller will use the magnetic balance constraint operator. Defined as the dynamic limiting boundary value of the phase shift adjustment time, and the volt-second balance state of the primary winding of the high-frequency transformer is monitored in real time during the voltage equalization adjustment process; when the target phase shift adjustment time calculated by the algorithm unit... Exceeding magnetic equilibrium constraint operator When the defined safety threshold is met, the pulse width modulation generator locks the trigger time of the phase-shifting pulse at the time determined by the magnetic balance constraint operator. The latest operating point is determined to limit the excessive expansion of the volt-second area on one side of the transformer, thereby maintaining the bidirectional excitation symmetry of the magnetic core during the dynamic equilibrium process and ensuring the DC component of the excitation current is controlled. It remains within a physically safe range of below 0.1A even under drastic load fluctuations, eliminating the potential for magnetic circuit saturation induced by rapid impedance reconstruction. According to Faraday's law of electromagnetic induction, under a specific DC bus input voltage... To prevent the transformer core from entering the unidirectional saturation region, it is necessary to control the voltage across the primary winding to ensure that the time integral of the voltage across the primary winding does not exceed the physical limit of magnetic flux change in any conduction direction. This requires a magnetic balance constraint operator. The calculation formula is as follows: ,in, Indicates the maximum permissible asymmetric phase shift time deviation; This represents the working magnetic flux density of the magnetic core, and its value range is determined by the saturation magnetic flux density of the magnetic core material, ranging from 0.2T to 0.3T. Indicates the effective cross-sectional area of ​​the magnetic core; Indicates the number of turns in the primary winding of the transformer; This indicates that the DC bus input voltage of each module is collected in real time.

[0053] During the initialization phase when the system switches from standby to full-load operation, the digital controller establishes the average voltage value through a voltage reference calibration process. The sampling weights are used by the controller to measure the DC bus input voltage of each module during the first switching cycle after the power circuit is closed. The system captures data and uses a moving average filtering algorithm to determine the average potential from eight consecutive sampling points, thus filtering out potential deviations caused by sensor temperature drift and sampling noise. The algorithm unit stores the obtained global average potential into a comparison reference register for energy transfer timing priority, which serves as the subsequent target phase shift adjustment time. The initial logic origin is calculated. As the converter load current rises from zero to the rated point, the digital controller adjusts the bias of the comparison reference register based on the identification results of the impedance sensitivity of each module. This ensures that in a large-scale multi-module cluster deployment environment, the equivalent impedance adjustment of each power module can be anchored on a unified physical reference, realizing the logical closed loop of the system-level voltage equalization control method. To eliminate the reference drift contradiction caused by the nonlinear oscillation of the hardware impedance of each module during the initial closing transient, the global potential average value stored in the comparison reference register is converted to a dynamic adaptive tracking mode after initialization. After the system enters the full-load operation state, the digital controller does not use the fixed potential calculated in the first cycle as the static dead zone anchor point, but introduces a reference correction logic based on a moving window. Specifically, in each subsequent switching cycle, the controller removes the sampling interference of the voltage extreme value module in real time, dynamically calculates the sliding arithmetic mean of the input voltage of the remaining controllable modules, and dynamically refreshes the value of the comparison reference register accordingly. At the same time, the algorithm unit will use the real-time identified impedance sensitivity of each module. As a weighting term of the dynamic compensation factor, the dynamic potential mean is finely biased, so that during the impedance reconstruction process caused by the primary-side leakage inductance dispersion, the logic origin of the controller can adaptively drift coaxially with the fluctuation of the total bus voltage of the actual main circuit. This achieves a seamless and smooth evolution from transient initialization to dynamic steady-state control in terms of timing, ensuring the self-consistency of the closed-loop system. This is the DC bus input voltage. The average voltage. The target phase shift adjustment time. For magnetic balance constraint operators, For the working magnetic flux density, The cross-sectional area of ​​the magnetic core is... This refers to the number of turns in the primary winding. The DC component of the excitation current, impedance sensitivity Used to characterize the target phase shift adjustment time. Incremental change in DC bus input voltage When a change occurs, the digital controller executes the following identification procedure during system operation: Obtain the current module's continuous... DC bus input voltage within one switching cycle Change ; Calculate the target phase shift adjustment time within the corresponding time period. Algebraic change According to the formula Determine impedance sensitivity ,in, For impedance sensitivity; This refers to the change in voltage. The time offset increment is used to identify the impedance sensitivity. When the preset gain limit threshold is exceeded, the algorithm unit reduces the impedance adjustment gain coefficient. The value is selected to prevent voltage oscillation caused by excessive impedance adjustment in multi-module loops. The identification mechanism enables the control logic to identify and compensate for differences in physical leakage inductance and parasitic parameters of each module online.

[0054] The embodiments of this application have been described above with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other. This application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit of this application and the scope of protection of this invention, and all of these forms are within the protection scope of this application.

Claims

1. A voltage equalization control method for a multi-module converter, characterized in that, Includes the following steps: Step 101: Real-time acquisition of DC bus input voltage of each module and transient load current of main power circuit; Step 102: Compare the input voltage of each module with the preset average voltage value to determine the deviation, and sort the energy transmission timing priority of each module in descending order according to the magnitude of the deviation. Step 103: Based on the mapping relationship between the magnitude of the transient load current and the physical switching delay time caused by the charging and discharging of the parasitic capacitance of the power switch, determine the pre-bias compensation amount for the PWM comparator register to compensate for the execution time bias error caused by the Miller plateau effect during the turn-on and turn-off phases of the power switch. Step 104: Within a complete high-frequency switching cycle, the trigger time of the phase-shifting pulse of each module is determined according to the priority of energy transfer timing, and a pre-bias compensation amount is injected during the process of reloading the PWM comparator register by the PWM control signal to construct a bipolar zero-sum phase-shifting trajectory. Step 105: The adjustment depth of the phase shift sequence is limited by the magnetic balance constraint logic. By adjusting the effective phase shift angle width of each module within a switching cycle, the energy distribution weight of the primary winding of the power transformer corresponding to each module on the time axis is changed. Under the premise of maintaining the volt-second balance of the transformer core, the dynamic balance of the input voltage of each module is achieved.

2. The voltage equalization control method for a multi-module converter according to claim 1, characterized in that, Step 102 specifically includes the following sub-steps: Step 1021, calculate the absolute value of the deviation between the input voltage and the average voltage of each module; Step 1022, sort the absolute values ​​of the deviation in descending order, and determine the module with the largest absolute value of the deviation as having the highest energy transmission timing priority, which is used to prioritize impedance adjustment.

3. The voltage equalization control method for a multi-module converter according to claim 1, characterized in that, Methods for compensating for timing errors in the turn-on and turn-off phases of power switches include: extracting the gate charge characteristics of the power switch under different load currents and converting the gate charge characteristics into corresponding switching action lead or lag times to correct the dead-time symmetry of the PWM drive signal.

4. The voltage equalization control method for a multi-module converter according to claim 1, characterized in that, Step 104 specifically includes the following sub-steps: Step 1041, calculate the correction value of the trigger time of the PWM drive signal in the positive half-cycle; Step 1042, determine the offset offset in the negative half-cycle based on the correction value of the trigger time; Step 1043, make the integral of the voltage across the transformer winding with respect to time generate mutually canceling volt-second areas in a single cycle.

5. A voltage equalization control method for a multi-module converter according to claim 1, characterized in that, The steps to adjust the energy distribution weight of each module on the time axis include: changing the effective conduction time ratio of the primary winding of each module by moving the starting position of the effective phase shift angle of each module within the switching cycle, thereby changing the equivalent impedance presented by the primary winding in the primary series circuit.

6. The voltage equalization control method for a multi-module converter according to claim 1, characterized in that, The steps for limiting the adjustment depth of the phase shift sequence using magnetic balance constraint logic include: obtaining the critical value of the saturation flux of the transformer core, calculating the maximum allowable asymmetric time deviation under the critical value, and using the maximum asymmetric time deviation as the boundary constraint for adjusting the energy transmission timing priority.

7. A voltage equalization control method for a multi-module converter according to claim 1, characterized in that, After reconstructing the energy distribution weights of the primary windings of the power transformers corresponding to each module on the time axis, the following steps are also included: monitoring the convergence rate of the input voltage of each module; when the convergence rate is lower than the set sensitivity threshold, increasing the adjustment coefficient of the effective phase shift angle width.

8. A voltage equalization control method for a multi-module converter according to claim 1, characterized in that, The steps to achieve dynamic equalization of the input voltage of each module also include: comparing the input voltage of each module in real time, and when the input voltage of any module exceeds the safety threshold of 600V, removing the phase shift rate limitation and adjusting the effective phase shift angle width through the bipolar zero-sum phase shift trajectory.

9. A voltage equalization control method for a multi-module converter according to claim 1, characterized in that, The steps for reconstructing the equivalent impedance of each module in the primary circuit include: calculating the voltage scalar shared by each module in the primary series circuit based on the energy transfer timing priority; and adjusting the triggering timing of the PWM drive signal in the positive and negative half cycles to make the transformer of each module generate an asymmetrical impedance response in a single cycle.

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