Adaptive impedance adjusting circuit and radio frequency energy harvesting chip

Abstract

This invention discloses an adaptive impedance adjustment circuit and an RF energy harvesting chip. The circuit includes a self-tuning switched capacitor array and an amplitude detection circuit. The input of the amplitude detection circuit is connected to the output of a voltage doubler rectifier circuit in the RF energy harvesting chip, used to detect the amplitude of the voltage output by the voltage doubler rectifier circuit and feed back an internal amplitude detection signal to the self-tuning switched capacitor array. The control terminal of the self-tuning switched capacitor array receives a first digital configuration signal from outside the chip and the internal amplitude detection signal fed back by the amplitude detection circuit. The RF port is connected between the RF input node of the chip and ground. The self-tuning switched capacitor array is configured to set a reference or initial state for impedance tuning according to the digital configuration signal, and dynamically adjust the equivalent capacitance value of the matching network according to the reference or initial state. In this embodiment, adaptive adjustment of the input impedance of the RF energy harvesting chip is achieved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to an adaptive impedance adjustment circuit and a radio frequency energy harvesting chip. Background Technology

[0002] Radio frequency (RF) energy harvesting technology captures RF electromagnetic energy from the environment and converts it into DC power to power low-power electronic devices. It is one of the key technologies for realizing battery-free IoT nodes. Its core performance indicator, sensitivity (i.e., the minimum incident RF power at which the chip can start and work normally), directly determines the chip's working distance and applicable scenarios. The conjugate matching between the antenna and the chip's input impedance is the most critical factor that determines energy transmission efficiency and thus affects sensitivity.

[0003] However, achieving and maintaining optimal impedance matching in practical applications presents numerous challenges: First, antenna impedance is affected by its physical dimensions, surrounding dielectric materials, and mounting environment; second, the chip's input impedance drifts with variations in process technology, operating temperature, and input RF power levels. Traditional solutions involve using fixed or manually adjustable matching networks (such as inductors and capacitors) external to the chip, but this increases system size, cost, and complexity, and cannot adapt to dynamically changing environments. Some research employs on-chip adjustable capacitor arrays, but their control signals typically require external microcontrollers or complex digital state machines, leading to increased system power consumption and design complexity, making them unsuitable for passive chips where static power consumption needs to be controlled in the microwatt range.

[0004] Therefore, there is an urgent need for an adaptive matching circuit that can be fully integrated into the chip, consumes extremely low power, and can automatically and intelligently adjust the chip's input impedance according to the real-time received signal strength, so as to maximize energy harvesting efficiency and improve the chip's sensitivity and robustness under a wide range of operating conditions. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides an adaptive impedance adjustment circuit and a radio frequency energy harvesting chip to achieve adaptive adjustment of the impedance input to the radio frequency energy harvesting chip.

[0006] To address the aforementioned technical problems, this invention also provides an adaptive impedance adjustment circuit, which includes: a self-tuning switched capacitor alignment circuit and an amplitude detection circuit. The input terminal of the amplitude detection circuit is connected to the output terminal of the voltage doubler rectifier circuit in the radio frequency energy harvesting chip, and is used to detect the amplitude of the voltage output by the voltage doubler rectifier circuit and to feed back the internal amplitude detection signal to the self-tuning switched capacitor array. The control terminal of the self-tuning switched capacitor array receives a first digital configuration signal from outside the chip and an internal amplitude detection signal fed back by the amplitude detection circuit. The RF port of the self-tuning switched capacitor array is connected between the RF input node of the chip and ground. The self-tuning switched capacitor array is configured to set a reference or initial state for impedance tuning based on the digital configuration signal, and to dynamically adjust the equivalent capacitance value of the matching network based on the reference or initial state, so as to achieve adaptive adjustment of the impedance of the RF energy harvesting core input.

[0007] Optionally, the first digital configuration signal is a multi-bit binary signal.

[0008] Optionally, the amplitude detection circuit includes a voltage divider network, an adjustable threshold hysteresis comparator, and a Schmitt trigger; The voltage divider network is used to divide and sample the voltage output by the voltage doubler rectifier circuit to obtain the sampled voltage; The first input terminal of the adjustable threshold hysteresis comparator is used to receive the sampled voltage, and the second input terminal of the adjustable threshold hysteresis comparator is used to receive the reference voltage. The Schmitt trigger is connected to the output of the adjustable threshold hysteresis comparator and is used to shape and debouncing the output signal of the adjustable threshold hysteresis comparator, and to output the internal amplitude detection signal.

[0009] Optionally, the comparison threshold of the adjustable threshold hysteresis comparator is adjusted in multiple stages by a second digital configuration signal input externally.

[0010] Optionally, the adjustable threshold hysteresis comparator includes a pair of differential input transistors, and the differential input transistors are composed of multiple transistor units connected in parallel, with each transistor unit connected in series with a switching transistor. The switching on and off of the switching transistor is controlled by the second digital configuration signal, and the comparison threshold of the adjustable threshold hysteresis comparator is adjusted by changing the number of effective transistors connected in parallel.

[0011] Optionally, the self-tuning switched capacitor array consists of multiple parallel capacitor tuning branches and is a binary weighted capacitor array; wherein the on / off state of each capacitor tuning branch is controlled by the tuning control logic determined by the first digital configuration signal and the internal amplitude detection signal.

[0012] Optionally, the capacitor tuning branch includes a first capacitor, a second capacitor, a first switching transistor, a first bias transistor, and a second bias transistor; The first capacitor and the second capacitor are connected in series between the radio frequency input node and ground. The source and drain of the first switch are respectively connected to the series node of the first capacitor and the second power supply, and the gate of the first switch receives the bit control signal generated by the tuning control logic. The first bias transistor and the second bias transistor are connected between the source and drain of the first switching transistor and ground to balance the DC potential across the first switching transistor.

[0013] Optionally, the first capacitor and the second capacitor are metal-insulator-metal capacitors; The first switching transistor, the first bias transistor, and the second bias transistor are NMOS transistors.

[0014] Optionally, the capacitance values ​​in the plurality of parallel capacitor tuning branches are in a binary weighted relationship, and the size of the switching transistor in each capacitor tuning branch is in a corresponding binary weighted relationship.

[0015] In addition, this embodiment of the invention also provides a radio frequency (RF) energy harvesting chip, which includes: an adaptive impedance adjustment circuit, a voltage doubler rectifier circuit, and a low dropout linear regulator; the voltage doubler rectifier circuit is used to convert the RF signal received by the antenna into a DC voltage; the adaptive impedance adjustment circuit is connected to the output terminal of the voltage doubler rectifier circuit and the RF input node; the low dropout linear regulator is used to regulate the DC voltage output by the voltage doubler rectifier circuit; wherein, the input terminal of the digital configuration signal of the adaptive impedance adjustment circuit is configured to receive a control signal from outside the RF energy harvesting chip.

[0016] In this embodiment of the invention, dynamic impedance matching is achieved through an adaptive impedance adjustment circuit, ensuring that the maximum power transmission point can be approached at different distances and in different environments, significantly improving the chip's read sensitivity and effective operating range; the entire adaptive adjustment loop adopts a low-power analog and minimized digital logic design; the circuit is fully integrated inside the chip, requiring no external adjustable components, simplifying system design and reducing overall cost and size; the tuning process is completely autonomous, requiring no external intervention, improving the system's reliability and environmental adaptability. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a schematic diagram of the structure of the adaptive impedance adjustment circuit in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structural composition of the amplitude detection circuit in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of the voltage divider network in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the adjustable threshold hysteresis comparator in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the Schmitt trigger in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of the self-tuning switched capacitor array in an embodiment of the present invention; Figure 7 This is a diagram illustrating the adjustment effect of the adaptive impedance adjustment circuit in this embodiment of the invention. Figure 8 This is a schematic diagram of the structure of the radio frequency energy harvesting chip in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Example 1, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of the adaptive impedance adjustment circuit in an embodiment of the present invention.

[0021] like Figure 1 As shown, an adaptive impedance adjustment circuit includes a self-tuning switched capacitor array and an amplitude detection circuit. The input terminal of the amplitude detection circuit is connected to the output terminal of a voltage doubler rectifier circuit in the RF energy harvesting chip, used to detect the amplitude of the voltage output by the voltage doubler rectifier circuit and feed back an internal amplitude detection signal to the self-tuning switched capacitor array. The control terminal of the self-tuning switched capacitor array receives a first digital configuration signal from outside the chip and the internal amplitude detection signal fed back by the amplitude detection circuit. The RF port of the self-tuning switched capacitor array is connected between the RF input node of the chip and ground. The self-tuning switched capacitor array is configured to set a reference or initial state for impedance tuning according to the digital configuration signal, and dynamically adjust the equivalent capacitance value of the matching network according to the reference or initial state to achieve adaptive adjustment of the impedance input to the RF energy harvesting chip.

[0022] Specifically, the adaptive impedance adjustment circuit mainly consists of two parts: a self-tuning switched capacitor array and an amplitude detection circuit. The amplitude detection circuit receives the voltage VDD2 output from the voltage doubler rectifier circuit in the RF energy harvesting chip and outputs an internal amplitude detection signal to the self-tuning switched capacitor array. The control terminal of the self-tuning switched capacitor array receives the first digital configuration signal (X_RF_CCTL<2:0>) from outside the chip and the internal amplitude detection signal fed back by the amplitude detection circuit, thereby realizing tuning control. The external configuration signal sets the tuning baseline, and the internal detection signal directs the specific tuning step based on this baseline. The two work together to change its equivalent capacitance C_tune, thereby adjusting the chip input impedance Z_in. The approximation of Z_in to the conjugate value of the antenna impedance improves the power transmission efficiency, which in turn causes the VDD2 voltage to rise. The risen VDD2 is sampled and compared again by the detection module, forming a closed-loop feedback.

[0023] In a specific implementation of the present invention, the first digital configuration signal is a multi-bit binary signal.

[0024] Specifically, the first digital configuration signal is a multi-bit binary signal; preferably, it is a three-bit binary signal (X_RF_CCTL<2:0>).

[0025] In a specific implementation of this invention, the amplitude detection circuit includes a voltage divider network, an adjustable threshold hysteresis comparator, and a Schmitt trigger. The voltage divider network is used to divide and sample the voltage output by the voltage doubler rectifier circuit to obtain a sampled voltage. The first input terminal of the adjustable threshold hysteresis comparator is used to receive the sampled voltage, and the second input terminal of the adjustable threshold hysteresis comparator is used to receive a reference voltage. The Schmitt trigger is connected to the output terminal of the adjustable threshold hysteresis comparator and is used to shape and debouncing the output signal of the adjustable threshold hysteresis comparator, and output the internal amplitude detection signal.

[0026] Furthermore, the comparison threshold of the adjustable threshold hysteresis comparator is adjusted in multiple stages by an externally input second digital configuration signal.

[0027] Furthermore, the adjustable threshold hysteresis comparator includes a pair of differential input transistors, and the differential input transistors are composed of multiple parallel transistor units, each transistor unit being connected in series with a switching transistor. The switching on and off of the switching transistor is controlled by the second digital configuration signal, and the comparison threshold of the adjustable threshold hysteresis comparator is adjusted by changing the number of effective transistors connected in parallel.

[0028] Specifically, such as Figure 2As shown, the amplitude detection circuit includes a voltage divider network, an adjustable threshold hysteresis comparator, and a Schmitt trigger; the voltage divider network is as follows: Figure 3 As shown, the adjustable threshold hysteresis comparator is as follows: Figure 4 As shown, the Schmitt trigger is as follows Figure 5 As shown, the voltage divider network samples VDD2 to obtain VDD2_DIV; VDD2_DIV and the reference voltage Vref are fed together into an adjustable threshold hysteresis comparator; the key feature of this comparator is that its threshold can be programmed via the digital signal GCTL1<2:0>; as shown Figure 4 As shown, the input transistors of the comparator are not single transistors, but are composed of five parallel NMOS units; the drain paths of four of these units are controlled by their respective switches; a 3-to-8 decoder generates a total of eight-bit switch control signals according to GCTL1<2:0>, with four bits grouped together to control the left and right input transistors respectively; by turning on different numbers of parallel units, the width-to-length ratio (W / L) of the effective input transistors can be changed, thereby precisely setting the input voltage difference (i.e., the detection threshold) required for the comparator to flip; this design achieves "progressive" multi-level detection of carrier amplitude; the output of the comparator is shaped by a Schmitt trigger and then sent as an amplitude detection signal to the self-tuning switched capacitor array module.

[0029] The voltage divider network is mainly used to divide the voltage output of the voltage doubler rectifier circuit to obtain the sampling voltage; the adjustable threshold hysteresis comparator receives the sampling voltage at its first input terminal and a reference voltage at its second input terminal; the Schmitt trigger is connected to the output terminal of the adjustable threshold hysteresis comparator and is used to shape and debouncing the output signal and output the internal amplitude detection signal.

[0030] The comparison threshold of the adjustable threshold hysteresis comparator can be adjusted in multiple steps via an externally input second digital configuration signal (GCTL1<2:0>).

[0031] The adjustable threshold hysteresis comparator includes a pair of differential input transistors, each consisting of multiple parallel transistor units, with each transistor unit connected in series with a switching transistor. The switching on and off of the switching transistors is controlled by a second digital configuration signal (GCTL1<2:0>), and the detection threshold of the comparator is adjusted by changing the number of effective transistors connected in parallel.

[0032] In a specific implementation of the present invention, the self-tuning switched capacitor array is composed of multiple parallel capacitor tuning branches and is a binary weighted capacitor array; wherein the on / off state of each capacitor tuning branch is controlled by the tuning control logic determined by the first digital configuration signal and the internal amplitude detection signal.

[0033] Furthermore, the capacitor tuning branch includes a first capacitor, a second capacitor, a first switching transistor, a first bias transistor, and a second bias transistor; wherein, the first capacitor and the second capacitor are connected in series between the RF input node and ground; the source and drain of the first switching transistor are respectively connected to the series node of the first capacitor and the second power supply, and the gate of the first switching transistor receives the bit control signal generated by the tuning control logic; the first bias transistor and the second bias transistor are connected between the source and drain of the first switching transistor and ground to balance the DC potential across the first switching transistor.

[0034] Furthermore, the first capacitor and the second capacitor are metal-insulator-metal capacitors; the first switching transistor, the first bias transistor, and the second bias transistor are NMOS transistors.

[0035] Furthermore, the capacitance values ​​in the multiple parallel capacitor tuning branches have a binary weighted relationship, and the size of the switching transistor in each capacitor tuning branch has a corresponding binary weighted relationship.

[0036] Specifically, people Figure 6 As shown, the self-tuning switched capacitor array consists of three parallel capacitor tuning branches. One basic branch is illustrated: two MIM capacitors C1 and C2 are connected in series between the RF node and ground; the gate of the NMOS switch NM3 is connected to the control bit, and its source and drain are connected to the middle node of the two capacitors, respectively; two NMOS bias transistors (NM1, NM2) ensure that the DC potentials of the source and drain of the switch are clamped near ground, thus ensuring the port voltage balance of the switch in the off and on states and maintaining the Q value of the array; when the control bit is high, NM3 is turned on, and capacitors C1 and C2 are AC short-circuited through the switch, equivalent to the series connection of capacitors C1 and C2 into the circuit. When the control bit is low, NM3 is turned off, and the capacitors in this branch are disconnected; by controlling the switching states of the three such branches (weights 1, 2, and 4 respectively), eight different capacitance values ​​from 0 to 7 can be achieved, thus realizing step-by-step impedance adjustment.

[0037] Among them, the first capacitor and the second capacitor are metal-insulator-metal capacitors; the switching transistor and the bias transistor are NMOS transistors; the capacitance values ​​in the three capacitor tuning branches have a binary weight relationship, and the size of the switching transistor in each branch also has a corresponding binary weight relationship.

[0038] like Figure 7The diagram shows the effect of the adaptive impedance adjustment circuit. In the initial impedance mismatch state, both the radio frequency carrier signal (RF) and the power supply voltage (VDD2) of the voltage doubler rectifier circuit exhibit amplitude attenuation. By introducing a closed-loop impedance adjustment mechanism, the system can dynamically optimize the impedance matching degree between the chip and the antenna, thereby significantly improving the carrier signal amplitude and power supply voltage level (the diagram shows that under the maximum mismatch condition, it takes 8 iterations of adjustment to achieve optimal matching).

[0039] The tuning behavior of the self-tuning switched capacitor array is jointly controlled by the external digital configuration signal (X_RF_CCTL<2:0>) and the internal amplitude detection signal. Its tuning control logic is embodied in a direct signal coupling method: the internal amplitude detection signal serves as a tuning enable or trigger signal; while the external digital configuration signal (X_RF_CCTL<2:0>) directly serves as the data signal for selecting a specific capacitor branch (or branch combination). When the internal amplitude detection signal is valid, the capacitor configuration currently set by X_RF_CCTL<2:0> is applied to the capacitor array. If the mismatch persists, the value of X_RF_CCTL<2:0> can be changed through internal state or external sequence to gradually switch the capacitor configuration until the match is improved. This design realizes the synergy between external programmable preset and internal automatic trigger.

[0040] In this embodiment of the invention, the adaptive impedance adjustment circuit achieves fully automatic impedance matching through an on-chip integrated negative feedback loop. First, an initial tuning state is loaded based on the externally input digital configuration signal (X_RF_CCTL<2:0>). Its operation begins with real-time monitoring of the RF rectifier output voltage VDD2 by the progressive carrier amplitude detection module. The level of VDD2 directly reflects the matching status between the antenna and the chip, as well as the received power level. When environmental, process, or input power changes cause impedance mismatch, VDD2 decreases, and its voltage divider value VDD2_DIV decreases accordingly. An adjustable threshold hysteresis comparator... The VDD2_DIV is compared with the reference voltage Vref. Once it falls below a preset threshold, its output flips. This flip signal is shaped and de-jittered by a Schmitt trigger to generate a stable tuning control signal. This signal drives the self-tuning switched capacitor array module, which dynamically adjusts the binary weighted capacitor value connected to the antenna port by controlling the on / off state of the switching transistor NM3, thereby changing the chip's input impedance Z_in. The approximation of Z_in to the conjugate value of the antenna impedance improves power transmission efficiency, thus causing the VDD2 voltage to rise. The risen VDD2 is then sampled and compared again by the detection module, forming a closed-loop feedback. This process continues until the system dynamically converges to a matched and optimized equilibrium state, achieving autonomous tracking and locking of the maximum power transmission point under broad conditions.

[0041] like Figure 8As shown, an RF energy harvesting chip includes: an adaptive impedance adjustment circuit, a voltage doubler rectifier circuit, and a low-dropout linear regulator; the voltage doubler rectifier circuit is used to convert the RF signal received by the antenna into a DC voltage; the adaptive impedance adjustment circuit is connected to the output terminal of the voltage doubler rectifier circuit and the RF input node; the low-dropout linear regulator is used to regulate the DC voltage output by the voltage doubler rectifier circuit; wherein, the input terminal of the digital configuration signal of the adaptive impedance adjustment circuit is configured to receive a control signal from outside the RF energy harvesting chip.

[0042] Specifically, Figure 8 The differential antenna in the circuit receives radio frequency signals (RF1, RF2) in the 860-960MHz band. The radio frequency rectifier circuit (voltage doubler rectifier charge pump) converts the radio frequency energy into DC voltage VDD2; the adaptive impedance adjustment circuit is connected between the VDD2 detection point and the matching network of the antenna; the low dropout linear regulator (LDO) regulates VDD2 to generate a stable VREG power supply.

[0043] In this embodiment of the invention, dynamic impedance matching is achieved through an adaptive impedance adjustment circuit, ensuring that the maximum power transmission point can be approached at different distances and in different environments, significantly improving the chip's read sensitivity and effective operating range; the entire adaptive adjustment loop adopts a low-power analog and minimized digital logic design; the circuit is fully integrated inside the chip, requiring no external adjustable components, simplifying system design and reducing overall cost and size; the tuning process is completely autonomous, requiring no external intervention, improving the system's reliability and environmental adaptability.

[0044] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, which may include: read-only memory (ROM), random access memory (RAM), disk or optical disk, etc.

[0045] Furthermore, the above description provides a detailed overview of the adaptive impedance adjustment circuit and radio frequency energy harvesting chip provided in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. An adaptive impedance adjustment circuit, characterized in that, The adaptive impedance adjustment circuit includes: a self-tuning switched capacitor array and an amplitude detection circuit; The input terminal of the amplitude detection circuit is connected to the output terminal of the voltage doubler rectifier circuit in the radio frequency energy harvesting chip, and is used to detect the amplitude of the voltage output by the voltage doubler rectifier circuit and to feed back the internal amplitude detection signal to the self-tuning switched capacitor array. The control terminal of the self-tuning switched capacitor array receives a first digital configuration signal from outside the chip and an internal amplitude detection signal fed back by the amplitude detection circuit. The RF port of the self-tuning switched capacitor array is connected between the RF input node of the chip and ground. The self-tuning switched capacitor array is configured to set a reference or initial state for impedance tuning based on the digital configuration signal, and to dynamically adjust the equivalent capacitance value of the matching network based on the reference or initial state, so as to achieve adaptive adjustment of the impedance of the RF energy harvesting core input.

2. The adaptive impedance adjustment circuit according to claim 1, characterized in that, The first digital configuration signal is a multi-bit binary signal.

3. The adaptive impedance adjustment circuit according to claim 1, characterized in that, The amplitude detection circuit includes a voltage divider network, an adjustable threshold hysteresis comparator, and a Schmitt trigger. The voltage divider network is used to divide and sample the voltage output by the voltage doubler rectifier circuit to obtain the sampled voltage; The first input terminal of the adjustable threshold hysteresis comparator is used to receive the sampled voltage, and the second input terminal of the adjustable threshold hysteresis comparator is used to receive the reference voltage. The Schmitt trigger is connected to the output of the adjustable threshold hysteresis comparator and is used to shape and debouncing the output signal of the adjustable threshold hysteresis comparator, and to output the internal amplitude detection signal.

4. The adaptive impedance adjustment circuit according to claim 3, characterized in that, The comparison threshold of the adjustable threshold hysteresis comparator is adjusted in multiple stages by an externally input second digital configuration signal.

5. The adaptive impedance adjustment circuit according to claim 4, characterized in that, The adjustable threshold hysteresis comparator includes a pair of differential input transistors, and the differential input transistors are composed of multiple transistor units connected in parallel, with each transistor unit connected in series with a switching transistor. The switching on and off of the switching transistor is controlled by the second digital configuration signal, and the comparison threshold of the adjustable threshold hysteresis comparator is adjusted by changing the number of effective transistors connected in parallel.

6. The adaptive impedance adjustment circuit according to claim 1, characterized in that, The self-tuning switched capacitor array consists of multiple parallel capacitor tuning branches and is a binary weighted capacitor array; the on / off state of each capacitor tuning branch is controlled by the tuning control logic determined by the first digital configuration signal and the internal amplitude detection signal.

7. The adaptive impedance adjustment circuit according to claim 6, characterized in that, The capacitor tuning branch includes a first capacitor, a second capacitor, a first switching transistor, a first bias transistor, and a second bias transistor. The first capacitor and the second capacitor are connected in series between the radio frequency input node and ground. The source and drain of the first switch are respectively connected to the series node of the first capacitor and the second power supply, and the gate of the first switch receives the bit control signal generated by the tuning control logic. The first bias transistor and the second bias transistor are connected between the source and drain of the first switching transistor and ground to balance the DC potential across the first switching transistor.

8. The adaptive impedance adjustment circuit according to claim 7, characterized in that, The first capacitor and the second capacitor are metal-insulator-metal capacitors; The first switching transistor, the first bias transistor, and the second bias transistor are NMOS transistors.

9. The adaptive impedance adjustment circuit according to claim 6, characterized in that, The capacitance values ​​in the multiple parallel capacitor tuning branches are related by binary weights, and the dimensions of the switching transistors in each capacitor tuning branch are related by corresponding binary weights.

10. A radio frequency energy harvesting chip, characterized in that, The radio frequency energy harvesting chip includes: The adaptive impedance regulation circuit, voltage doubler rectifier circuit, and low dropout linear regulator as described in any one of claims 1-9; The voltage doubler rectifier circuit is used to convert the radio frequency signal received by the antenna into a DC voltage; the adaptive impedance adjustment circuit is connected to the output terminal of the voltage doubler rectifier circuit and the radio frequency input node; the low dropout linear regulator is used to regulate the DC voltage output by the voltage doubler rectifier circuit. The input terminal of the digital configuration signal of the adaptive impedance adjustment circuit is configured to receive a control signal from outside the radio frequency energy harvesting chip.

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