Low-power bluetooth soc adaptive clock gating structure and chip

Abstract

This invention discloses a low-power Bluetooth SoC adaptive clock gating structure and chip. The structure includes a clock source, a backbone clock network, a baseband logic state machine with an internal RF wake-up counter, and an adaptive integrated clock gating macrocell connected to an RF warning feedforward. The macrocell is divided into an environmental sensing region containing a ring oscillator network and a gating logic region containing asymmetric configuration logic gates. The first transistor in the inverter sub-unit and the pull-up transistors within the logic gates are located within a continuously shared N-type well surrounded by a grounded P-type substrate contact ring. The macrocell includes a dynamic compensation unit that dynamically determines the compensation window based on the delay count value and activates the parallel drive buffer. This application can achieve zero-delay, high-precision voltage drop feedback, eliminate glitches and metastability generated during RF wake-up, and reduce unnecessary switching power consumption.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit structure technology, specifically to a low-power Bluetooth SOC adaptive clock gating structure and chip, which is applied to the low-power Bluetooth SOC chip of a continuous dynamic blood glucose monitor. Background Technology

[0002] Continuous glucose monitoring (CGM) devices use miniature high-resistance button batteries to power their internal low-power Bluetooth SoC chips. These chips frequently switch between prolonged deep sleep states and extremely short burst broadcast states. Existing clock gating designs use fixed enable signal setup times, leaving more than necessary timing margins to cover worst-case process corners and extreme high and low temperatures. This results in excessively wide clock duty cycles under normal temperature and high-pressure environments, causing unnecessary flips in the clock tree buffer and increasing dynamic power consumption. Due to the high battery resistance, the transient current surges when the RF power amplifier is turned on, leading to severe local voltage drops. This transient voltage drop reduces the driving capability of the logic gates within the integrated clock gating unit, causing a slower clock signal rise time or glitches, which in turn leads to metastability or data latching errors in the baseband control state machine. Furthermore, most existing solutions use independent on-chip temperature and voltage sensors to acquire physical states. Because these sensors are located far from the physical layout area where the main clock tree is located, there are thermal gradients and trace delays, making it impossible to accurately and in real-time reflect the actual physical environment changes experienced by the clock gating unit. Summary of the Invention

[0003] This application provides a low-power Bluetooth SOC (System on Chip) adaptive clock gating structure and chip, which solves the clock glitches caused by voltage drops during RF turn-on transients and the problem of excessive switching power consumption caused by fixed timing margins.

[0004] This application provides a low-power Bluetooth SoC adaptive clock gating structure, including a clock source, a backbone clock network, a baseband logic state machine, and an adaptive integrated clock gating macrocell. The baseband logic state machine includes a radio frequency (RF) enable counter, configured to send a warning pulse signal via an RF warning feedforward line after a preset number of clock cycles before the external RF module enables the RF power amplifier. The adaptive integrated clock gating macrocell is connected to the RF warning feedforward line and is divided into an environmental sensing region and a gating logic region on the semiconductor physical layout. The environmental sensing region includes a ring oscillator network composed of multi-level discretely distributed inverter sub-units. Each inverter sub-unit contains a first transistor. The gating logic region contains logic gates, including a network of pull-up transistors and pull-down transistors. The first transistor and the pull-up transistors are located within a shared, continuous N-type well on the semiconductor physical layout, and a grounded P-type substrate contact ring surrounds the shared N-type well. The logic gates employ an asymmetric configuration. The pull-down transistor network contains low-threshold-voltage NMOS (N-type Metal-Oxide-Semiconductor) transistors, while the pull-up transistors contain high-threshold-voltage PMOS (P-type Metal-Oxide-Semiconductor) transistors. The adaptive integrated clock-gated macrocell incorporates parallel drive buffers. These buffers dynamically determine the size of the enable signal setup time compensation window based on the output delay count of the ring oscillator network and activate upon receiving a warning pulse signal.

[0005] Specifically, the threshold voltage of the low threshold voltage NMOS transistor is reduced by a first preset value compared to the threshold voltage of the standard NMOS transistor; the logic gate is specifically configured as an AND gate; the first transistor is configured as a PMOS transistor; and the pull-up transistor is composed of multiple high threshold voltage PMOS transistors connected in parallel.

[0006] The adaptive integrated clock-gated macrocell also includes a multiplexer; the RF warning feedforward is connected to the control terminal of the multiplexer; when no warning pulse signal is received, the multiplexer selects to output a single drive signal; when a warning pulse signal is received, the multiplexer switches the output path and activates the parallel drive buffer within one clock cycle, so that the output drive capability of the adaptive integrated clock-gated macrocell is configured to a preset multiple when no warning pulse signal is received; wherein, the preset number of clock cycles is configured to 3 clock cycles, and the preset multiple is configured to 3 times.

[0007] The adaptive integrated clock-gated macrocell is equipped with a dynamic compensation unit, which is based on the formula... The size of the enable signal setup time compensation window is dynamically determined; where, This indicates the size of the enable signal setup time compensation window, K represents the preset constant proportional coefficient, and D... val D represents the current output delay count value of the ring oscillator network. ref T represents the reference delay count value. clk This indicates the system master clock cycle.

[0008] The environmental sensing region and the gated logic region form a physical-level thermal coupling structure and a potential coupling structure through a continuously shared N-type well; the grounded P-type substrate contact ring becomes a continuous physical closed loop, surrounding the outermost boundary of the continuously shared N-type well; multi-level discretely distributed inverter sub-units are arranged in a semi-enclosed array along the periphery of the gated logic region on the semiconductor physical layout, so that the local temperature gradient of the ring oscillator network and the temperature gradient of the logic gate inside the gated logic region maintain physical continuity.

[0009] In one embodiment, the first preset value is configured as a constant voltage value in the range of 150 mV to 200 mV; the adaptive integrated clock-gated macrocell has a control input terminal, which is connected to the RF warning feedforward line and the external enable signal input line, respectively.

[0010] The gated logic area also includes a latch module; the data input terminal of the latch module receives an external enable signal, the clock input terminal of the latch module receives the master clock signal, and the output terminal of the latch module is connected to the input terminal of the logic gate.

[0011] The adaptive integrated clock gating macrocell has an adjustable delay line module inside. The adjustable delay line module is connected in series before the data input terminal of the latch module and is configured to adjust the physical length of the transmission path delay from the external enable signal to the data input terminal of the latch module according to the output delay count value.

[0012] This application also provides a low-power Bluetooth chip, including the aforementioned low-power Bluetooth SOC adaptive clock gating structure.

[0013] This application also provides a continuous dynamic blood glucose monitor, including the aforementioned low-power Bluetooth chip.

[0014] This application eliminates the thermal gradient deviation of the environmental sensor by deeply coupling the sensitive transistor of the environmental sensing area and the gated logic transistor in a continuous shared N-type well on the physical layout, thus achieving high-precision voltage drop feedback with zero delay. Through asymmetric transistor threshold configuration and feedforward pulse signal mechanism, the steepness of the clock signal edge under extreme transient voltage drops is ensured at the physical level, eliminating glitches and metastability problems generated during RF wake-up. Combined with dynamic formula compensation, the timing margin is reduced, effectively eliminating the power consumption caused by redundant switching and improving the overall power utilization efficiency. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall structure provided in an embodiment of the present invention.

[0016] Figure 2 This is a partially enlarged schematic diagram provided in an embodiment of the present invention.

[0017] Explanation of reference numerals in the attached figures

[0018] In the diagram: 101-Clock source, 102-Main clock network, 103-Baseband logic state machine, 104-Adaptive integrated clock gate macrocell, 105-RF warning feedforward, 106-External RF module, 107-Main power supply network, 108-Internal voltage regulator, 109-RF enable counter, 201-Environmental sensing area, 202-Gated logic area, 203-Inverter sub-unit, 204-Ring oscillator network, 205-Logic gate, 206-Latch module, 207-First transistor, 208-Pull-up transistor, 209-Pull-down transistor network, 210-Continuously shared N-type well, 211-Grounded P-type substrate contact ring, 212-Dynamic compensation unit, 213-Adjustable delay line module. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] like Figure 1 As shown, this application provides a low-power Bluetooth SoC adaptive clock gating structure, mainly arranged on the semiconductor silicon substrate of the low-power Bluetooth chip. The entire system architecture includes a reference timing generation section and a dynamic gating cutoff section. Specifically, the structure includes a clock source 101, a backbone clock network 102, a baseband logic state machine 103, an adaptive integrated clock gating macrocell 104, an RF warning feedforward line 105, and an external RF module 106. To maintain the power supply and reference pulse operation of the entire SoC system, the system is also equipped with a main power supply network 107 and an internal voltage regulator 108. The internal voltage regulator 108 can specifically be a low-dropout linear regulator or a DC-DC converter, configured to extract energy from a high internal resistance battery and convert it into a working voltage; the clock source 101 specifically uses a high-frequency crystal oscillator or a phase-locked loop circuit to generate a reference master clock signal. By increasing the basic hardware support for power supply and voltage regulation, the normal start-up and electrical closed loop of the subsequent clock gating adjustment function are ensured.

[0021] In terms of signal connectivity, the baseband logic state machine 103 is connected in series between the clock source 101 and the backbone clock network 102 for scheduling according to the Bluetooth communication protocol. An adaptive integrated clock gating macrocell 104 is located at a branch node of the backbone clock network 102 and is configured to control the toggling action of the clock signal output to the external RF module 106. The adaptive integrated clock gating macrocell 104 has a control input terminal, which is connected to both the RF warning feedforward line 105 and the external enable signal input line, thereby implementing a dual verification mechanism for clock on / off states.

[0022] The baseband logic state machine 103 internally includes an RF turn-on counter 109. This RF turn-on counter 109 is responsible for synchronously tracking the timing state of the RF protocol stack. In conventional designs, the RF power amplifier turn-on is often sudden and the voltage drop time cannot be predicted in advance. However, in this embodiment, the RF turn-on counter 109 is configured to send a hardware warning pulse signal, transitioning from a low level to a high level, to the adaptive integrated clock gating macrocell 104 via the RF warning feedforward line 105 three clock cycles before the external RF module 106 actually turns on the RF power amplifier. By issuing the feedforward warning three clock cycles in advance, the downstream circuit has sufficient time window to cope with the significant voltage drop caused by transient internal resistance discharge. It should be noted that the parameter of three clock cycles is a preferred configuration, and those skilled in the art can adjust it to other numerical periods with equivalent predictive effect based on the rising slope of the RF turn-on current.

[0023] like Figure 2 As shown, Figure 2 This demonstrates the microscopic distribution characteristics of the adaptive integrated clock gating macrocell 104 at the semiconductor physical layout level. The adaptive integrated clock gating macrocell 104 is divided into two closely adjacent physical parts: an environment sensing region 201 and a gated logic region 202. The environment sensing region 201 contains a ring oscillator network 204 composed of multi-level discretely distributed inverter sub-units 203. The gated logic region 202 mainly handles the verification of the enable signal and the release or blocking of the clock pulse, and internally contains logic gates 205 and latch modules 206. The data input terminal of the latch module 206 receives the external enable signal, the clock input terminal receives the master clock signal, and the output terminal is connected to the input terminal of the logic gate 205. Each stage of the inverter sub-units 203 contains a PMOS transistor (i.e., the first transistor 207) and an NMOS transistor connected in series. All levels of inverter sub-units 203 are connected in parallel to the same power rail and ground rail on the semiconductor physical layout. The logic gate 205 is specifically configured as an AND gate, and internally contains a pull-up transistor 208 and a pull-down transistor network 209.

[0024] In terms of physical topology, the ring oscillator network 204 is divided into discrete inverter sub-units 203, arranged in a surrounding manner around the gated logic region 202. On the layout surface, the first transistor 207 in the inverter sub-unit 203 and the pull-up transistor 208 of the logic gate 205 inside the gated logic region are placed together within a continuously shared N-type well 210. A continuous grounded P-type substrate contact ring 211 is provided around the periphery of this continuously shared N-type well 210, forming a continuous physical closed loop and constituting a physical isolation boundary. The environmental sensing region 201 and the gated logic region 202 form a physical-level thermal coupling structure and potential coupling structure through the continuously shared N-type well 210. Furthermore, the multi-level discretely distributed inverter sub-units 203 are arranged in a semi-enclosed array along the periphery of the gated logic region 202, ensuring that the local temperature gradient of the ring oscillator network 204 and the temperature gradient of the internal logic gate 205 maintain physical continuity. By sharing a continuous N-well layout, the sensitive transistors and working logic transistors in the sensor experience completely identical silicon substrate temperatures and transient carrier fluctuations, thereby achieving high-precision physical state feedback that characterizes the true voltage drop amplitude with zero delay.

[0025] Inside the gated logic region 202, logic gate 205 employs an asymmetric dual-threshold voltage configuration. Specifically, the pull-down transistor network 209 of logic gate 205 uses low-threshold voltage NMOS transistors, whose channel doping concentration has been specially adjusted so that the threshold turn-on voltage of the low-threshold voltage NMOS transistor is reduced by a constant voltage value (i.e., a first preset value) in the range of 150 mV to 200 mV compared to the threshold voltage of a standard NMOS transistor. Simultaneously, the pull-up transistor 208 of logic gate 205 is composed of multiple high-threshold voltage PMOS transistors connected in parallel. This asymmetric configuration of low-threshold pull-down transistors and high-threshold pull-up transistors not only blocks subthreshold leakage current during deep sleep when facing extreme transient voltage drops, but also ensures that the falling edge of the clock signal is quickly pulled down to ground level, preventing glitches caused by insufficient clock signal drive.

[0026] In terms of dynamic timing adjustment, the adaptive integrated clock gating macrocell 104 is equipped with a dynamic compensation unit 212 and an adjustable delay line module 213. The output of the ring oscillator network 204 is connected to an on-chip delay line digital converter (CDD) to output an output delay count value reflecting the current combined state of process, voltage, and temperature. The on-chip delay line CDD is a digital auxiliary circuit integrated within the adaptive integrated clock gating macrocell. Its input receives the oscillation pulse signal of the ring oscillator network and directly maps the number of oscillation cycles of the ring oscillator network per unit time to the output delay count value through time-to-digital conversion. This converter is physically located adjacent to the environmental sensing area and shares the same power rail with the ring oscillator network to ensure that the delay count value accurately reflects the real-time process deviations, voltage drops, and temperature fluctuations experienced by the gating logic area. The adjustable delay line module 213 is connected in series before the data input of the latch module 206. Specifically, the system performs dynamic compensation parsing calculations, that is, determines the physical duration of the compensation window based on the offset of the current count value relative to the reference count value. The dynamic compensation unit 212 dynamically matches the time window when the enable signal arrives at the latch module 206 ahead of time based on the output delay count value. In a preferred embodiment, the above dynamic adjustment process is achieved through the following formula:

[0027]

[0028] in, The value of D represents the size of the enable signal setup time compensation window, used to characterize the physical transmission delay that the adjustable delay line module 213 needs to increase or decrease; K represents a preset constant proportional coefficient, which is a dimensionless compensation coefficient calibrated based on a specific semiconductor process, and in this embodiment its value range is set to 0.8 to 1.2; val This represents the current output delay count value of the ring oscillator network 204, which changes dynamically with varying degrees of real-time supply voltage drops; D ref This represents the reference delay count value at room temperature and rated operating voltage, indicating calibration data for an ideal operating environment; T clk This represents the system master clock period. The adjustable delay line module 213 inside the adaptive integrated clock gating macrounit 104 calculates... The value of K is adjusted to control the physical length of the transmission path delay from the external enable signal to the data input. This formula-based dynamic analytical compensation precisely reduces redundant timing margins under normal temperature conditions, thereby significantly reducing the ineffective switching dynamic power consumption of the master clock network. It should be noted that the range of K values ​​is only an example; those skilled in the art can calibrate and replace the coefficient values ​​according to specific process nodes.

[0029] To withstand the large voltage drop impact during RF turn-on, the output stage of the adaptive integrated clock-gated macrocell 104 also integrates a multiplexer and a parallel drive buffer. The RF warning feedforward line 105 is connected to the control terminal of the multiplexer. In the normal state where no warning pulse signal is received, the multiplexer selects to output a single drive signal to maintain a low-power mode. However, when the adaptive integrated clock-gated macrocell 104 receives a hardware warning pulse signal issued three clock cycles in advance, the multiplexer will forcibly switch its internal output path to take over hardware control and activate the parallel drive buffer during this period. This operation instantly increases the total output drive capability of the adaptive integrated clock-gated macrocell 104 to three times the level before receiving the warning within one clock cycle, until the warning pulse signal falls back to a low level. By forcibly waking up the additional drive buffer path through pulse feedforward, compensation for the large current drive caused by transient voltage drops is achieved.

[0030] This application also provides a low-power Bluetooth chip that integrates the aforementioned low-power Bluetooth SoC adaptive clock gating structure within a silicon substrate. Due to the built-in gating macrocell with thermal coupling sensing and dynamic feedforward compensation characteristics, this chip exhibits excellent anti-interference capabilities and low overall clock tree power consumption under harsh power supply conditions. This hardware-level improvement effectively adapts to the power supply environment of micro-devices.

[0031] In another application scenario, this application provides a continuous glucose monitoring (CGM) device. This CGM device internally houses a high-internal-resistance coin cell battery and is electrically connected to the aforementioned low-power Bluetooth chip containing an adaptive clock gating structure. By deploying a control chip with a clock gating structure, logic latching errors caused by a large instantaneous current drop due to the battery's internal resistance are effectively suppressed when the monitor performs periodic blood glucose measurements and broadcasts the results via radio frequency bursts.

[0032] In summary, the embodiments of this application, by placing the inverter-sensitive transistor and gated logic transistor in a closed loop of continuously shared N-type wells and a surrounding grounded P-type substrate on the physical layout, form a good thermal coupling structure and potential coupling environment, thereby acquiring high-precision voltage drop feedback data with zero delay. Through the asymmetric dual-threshold transistor configuration of the logic gates, combined with the forced triggering of the RF-enabled feedforward multiplexer and a 3x increase in drive capability, the steepness of the clock signal edge is ensured at the physical level, eliminating the risk of metastability during the transition from deep sleep to RF burst state. At the same time, by using a precise dynamic compensation formula, the size of the establishment time compensation window is automatically adjusted, avoiding unnecessary buffer flipping, ultimately achieving a synergistic gain of low power consumption and high stability in continuous glucose monitoring devices.

[0033] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A low-power Bluetooth SoC adaptive clock gating structure, characterized in that, This includes a clock source, a backbone clock network, a baseband logic state machine, and an adaptive integrated clock gating macrocell; The baseband logic state machine includes a radio frequency (RF) enable counter. The baseband logic state machine is configured to send a warning pulse signal via an RF warning feedforward line after a preset number of clock cycles before the external RF module enables the RF power amplifier. The adaptive integrated clock-gated macrocell is connected to the RF warning feedforward line and is divided into an environmental sensing region and a gated logic region on the semiconductor physical layout. The environmental sensing region includes a ring oscillator network composed of multi-level discretely distributed inverter sub-units. Each inverter sub-unit contains a first transistor. The gated logic region contains logic gates, each logic gate including a pull-up transistor and a pull-down transistor network. The first transistor is connected to the... The pull-up transistors are all located in a continuous shared N-type well on the semiconductor physical layout, and a grounded P-type substrate contact ring is arranged around the periphery of the continuous shared N-type well; the logic gates adopt an asymmetric configuration, the pull-down transistor network includes low threshold voltage NMOS transistors, and the pull-up transistors include high threshold voltage PMOS transistors; the adaptive integrated clock gate macrocell is provided with parallel drive buffers, and the adaptive integrated clock gate macrocell dynamically determines the size of the enable signal setup time compensation window according to the output delay count value of the ring oscillator network, and activates the parallel drive buffers when the warning pulse signal is received.

2. The low-power Bluetooth SOC adaptive clock gating structure as described in claim 1, characterized in that, The threshold voltage of the low threshold voltage NMOS transistor is reduced by a first preset value relative to the threshold voltage of the standard NMOS transistor; the logic gate is specifically configured as an AND gate; the first transistor is configured as a PMOS transistor; the pull-up transistor is composed of multiple high threshold voltage PMOS transistors connected in parallel.

3. The low-power Bluetooth SOC adaptive clock gating structure as described in claim 2, characterized in that, The adaptive integrated clock-gated macrocell also includes a multiplexer; the RF warning feedforward is connected to the control terminal of the multiplexer; when no warning pulse signal is received, the multiplexer selects to output a single drive signal; when the warning pulse signal is received, the multiplexer switches the output path and activates the parallel drive buffer within one clock cycle, so that the output drive capability of the adaptive integrated clock-gated macrocell is configured to a preset multiple when no warning pulse signal is received; wherein, the preset number of clock cycles is configured to be 3 clock cycles, and the preset multiple is configured to be 3 times.

4. The low-power Bluetooth SOC adaptive clock gating structure as described in claim 1, characterized in that, The adaptive integrated clock-gated macrocell is equipped with a dynamic compensation unit, which is based on the formula... The size of the enable signal setup time compensation window is dynamically determined; wherein, This indicates the size of the enable signal setup time compensation window, where K represents the preset constant proportional coefficient, and D... val D represents the current output delay count value of the ring oscillator network. ref T represents the reference delay count value. clk This indicates the system master clock cycle.

5. The low-power Bluetooth SOC adaptive clock gating structure as described in claim 1, characterized in that, The environmental sensing area and the gated logic area form a physical-level thermal coupling structure and a potential coupling structure through the continuously shared N-type well; the grounded P-type substrate contact ring forms a continuous physical closed loop, surrounding the outermost boundary of the continuously shared N-type well; the multi-level discretely distributed inverter sub-units are arranged in a semi-enclosed array on the semiconductor physical layout along the periphery of the gated logic area, so that the local temperature gradient of the ring oscillator network and the temperature gradient of the logic gate inside the gated logic area maintain physical continuity.

6. The low-power Bluetooth SOC adaptive clock gating structure as described in claim 2, characterized in that, The first preset value is configured as a constant voltage value in the range of 150 mV to 200 mV; the adaptive integrated clock gate macrocell has a control input terminal, which is connected to the RF warning feedforward line and the external enable signal input line respectively.

7. The low-power Bluetooth SOC adaptive clock gating structure as described in claim 1, characterized in that, The gated logic area also includes a latch module; the data input terminal of the latch module receives an external enable signal, the clock input terminal of the latch module receives a master clock signal, and the output terminal of the latch module is connected to the input terminal of the logic gate.

8. The low-power Bluetooth SOC adaptive clock gating structure as described in claim 7, characterized in that, The adaptive integrated clock gating macro unit is equipped with an adjustable delay line module. The adjustable delay line module is connected in series before the data input terminal of the latch module and is configured to adjust the physical length of the transmission path delay from the external enable signal to the data input terminal of the latch module according to the output delay count value.

9. A low-power Bluetooth chip, characterized in that, Includes the low-power Bluetooth SoC adaptive clock gating structure as described in claim 1.

10. A continuous dynamic blood glucose monitor, characterized in that, Including the low-power Bluetooth chip as described in claim 9.

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