Programmable clock network modules and arrays

Abstract

A programmable clock network module and array, relating to integrated circuit technology, are disclosed. The module comprises a first clock network unit, a second clock network unit, and a drive test unit. The programmable clock network module has two connection terminals in each of the up, down, left, and right directions. This invention features testability, low skewness, low duty cycle loss, low power consumption, and improved clock jitter.

Description

Technical Field

[0001] This invention relates to integrated circuit technology. Background Technology

[0002] Because traditional FPGAs have large process feature sizes, small integration scales, and low operating frequency requirements, traditional fixed clock networks can meet the flexibility and configurability needs of different functional modules.

[0003] Traditional clock networks are generally divided into fixed vertical global clock channels and horizontal regional clock routing channels. Fixed vertical global clock channels are usually located at the center of the chip, and their driving range is limited.

[0004] As FPGA process feature sizes become smaller (below 20nm) and integration scales approach the billion-gate level, it will become increasingly difficult for traditional clock networks to drive FPGAs of this scale, leading to various problems such as increased skew, increased duty cycle loss, and increased power consumption. Summary of the Invention

[0005] The technical problem to be solved by this invention is to provide a programmable clock network structure with self-test functionality. This clock network features testability, low skewness, low duty cycle loss, low power consumption, and improved clock jitter, making it particularly suitable for high-frequency signals.

[0006] The technical solution adopted by the present invention to solve the aforementioned technical problem is: 1. A programmable clock network module, characterized in that it includes a first clock network unit, a second clock network unit, and a drive test unit; the programmable clock network module has two connection ends in each of the up, down, left, and right directions.

[0007] According to the signal transmission direction, the first clock network unit includes a 3-to-1 selector (101), a tri-state inverter (102), a buffer (103), a 3-to-1 selector (104), a tri-state inverter (105), and a buffer (106) connected in a sequential loop. The output terminal of the tri-state inverter (102) serves as the first upper connection terminal, and the output terminal of the tri-state inverter (105) serves as the first lower connection terminal.

[0008] The first input of the three-to-one selector (101) is connected to the output of the buffer (106), the second input is connected to the reference point A, and the third input is connected to the reference point C.

[0009] The first input of the three-to-one selector (104) is connected to the output of the buffer (103), the second input is connected to the reference point A, and the third input is connected to the reference point C.

[0010] The reference point C is connected to the first left-side output terminal (HCLK1);

[0011] The first input of the 2-to-1 selector (120) is connected to the output of the buffer (103), the second input is connected to the reference point B, and the output is connected to the reference point C through the tri-state inverter (121).

[0012] According to the signal transmission direction, the second clock network unit includes a 3-to-1 selector (107), a tri-state inverter (108), a buffer (109), a 3-to-1 selector (110), a tri-state inverter (111), and a buffer (112) connected in a sequential loop. The output terminal of the tri-state inverter (108) serves as the second upper connection terminal, and the output terminal of the tri-state inverter (111) serves as the second lower connection terminal.

[0013] The first input of the three-to-one selector (107) is connected to the output of the buffer (112), the second input is connected to the reference point B, and the third input is connected to the reference point C.

[0014] The first input of the three-to-one selector (110) is connected to the output of the buffer (109), the second input is connected to the output of the buffer (103), and the third input is connected to the reference point C.

[0015] The drive testing unit includes:

[0016] Three-state inverter (122) and three-state inverter (123), reference point C is connected to the input terminal of three-state inverter (122) and the output terminal of three-state inverter (123), and the output terminal of three-state inverter (122) and the input terminal of three-state inverter (123) are connected to the first right-side connection terminal;

[0017] A 2-to-1 selector (113) has its first input connected to the output of a buffer (109), its second input connected to the output of a buffer (112), and its output connected to the input of a delay selector module (114). The output of the delay selector module (114) is connected to the first input of a global clock driver module (117) via a flip-flop module (115). The input port CE is connected to the second input of the global clock driver module (117) via a flip-flop module (116). The output of the global clock driver module (117) is connected to reference point D via a tri-state inverter (118). Reference point D is connected to the input of a self-test module (119), and the output of the self-test module (119) is connected to reference point A.

[0018] Three-state inverter (124) and three-state inverter (125), reference point D is connected to the input terminal of three-state inverter (124) and the output terminal of three-state inverter (125), and the output terminal of three-state inverter (124) and the input terminal of three-state inverter (125) are connected to the second right-side connection terminal;

[0019] Reference point D is connected to the global clock terminal GCLK through leaf clock buffer (126).

[0020] The buffer is a buffer with Schmitt trigger function.

[0021] The present invention also provides a programmable clock network array, which is composed of programmable clock network modules arranged in an array;

[0022] In two adjacent programmable clock network modules, the first lower connection terminal of the upper module is connected to the first upper connection terminal of the lower module, and the second lower connection terminal of the upper module is connected to the second upper connection terminal of the lower module.

[0023] In two adjacent programmable clock network modules, the first right-side connection terminal of the left module is connected to the first left-side connection terminal of the right module, and the second right-side connection terminal of the left module is connected to the second left-side connection terminal of the right module.

[0024] This invention implements a programmable clock network structure with self-test function. The clock network has the characteristics of being testable, having low skew, improving clock jitter, low duty cycle loss, and low power consumption. Attached Figure Description

[0025] Figure 1 This is the module circuit diagram of the present invention.

[0026] Figure 2 This is a circuit diagram of a buffer with Schmitt trigger function.

[0027] Figure 3 This is the circuit diagram of the delay selector module.

[0028] Figure 4 This is the circuit diagram of the global clock driver module.

[0029] Figure 5 This is the circuit diagram for the self-test module.

[0030] Figure 6 This is the circuit diagram of the positive and negative inverter module.

[0031] Figure 7 This is a circuit diagram of a leaf clock buffer.

[0032] Figure 8 This is a circuit diagram of a three-state inverter. Detailed Implementation

[0033] See Figure 1 The clock network module of the present invention includes a first clock network unit, a second clock network unit, and a drive test unit; the programmable clock network module has two connection terminals in each of the up, down, left, and right directions.

[0034] According to the signal transmission direction, the first clock network unit includes a 3-to-1 selector (101), a tri-state inverter (102), a buffer (103), a 3-to-1 selector (104), a tri-state inverter (105), and a buffer (106) connected in a sequential loop. The output terminal of the tri-state inverter (102) serves as the first upper connection terminal, and the output terminal of the tri-state inverter (105) serves as the first lower connection terminal.

[0035] The first input of the three-to-one selector (101) is connected to the output of the buffer (106), the second input is connected to the reference point A, and the third input is connected to the reference point C.

[0036] The first input of the three-to-one selector (104) is connected to the output of the buffer (103), the second input is connected to the reference point A, and the third input is connected to the reference point C.

[0037] The reference point C is connected to the first left-side output terminal (HCLK1);

[0038] The first input of the 2-to-1 selector (120) is connected to the output of the buffer (103), the second input is connected to the reference point B, and the output is connected to the reference point C through the tri-state inverter (121).

[0039] According to the signal transmission direction, the second clock network unit includes a 3-to-1 selector (107), a tri-state inverter (108), a buffer (109), a 3-to-1 selector (110), a tri-state inverter (111), and a buffer (112) connected in a sequential loop. The output terminal of the tri-state inverter (108) serves as the second upper connection terminal, and the output terminal of the tri-state inverter (111) serves as the second lower connection terminal.

[0040] The first input of the three-to-one selector (107) is connected to the output of the buffer (112), the second input is connected to the reference point B, and the third input is connected to the reference point C.

[0041] The first input of the three-to-one selector (110) is connected to the output of the buffer (109), the second input is connected to the output of the buffer (103), and the third input is connected to the reference point C.

[0042] The drive testing unit includes:

[0043] Three-state inverter (122) and three-state inverter (123), reference point C is connected to the input terminal of three-state inverter (122) and the output terminal of three-state inverter (123), and the output terminal of three-state inverter (122) and the input terminal of three-state inverter (123) are connected to the first right-side connection terminal;

[0044] A 2-to-1 selector (113) has its first input connected to the output of a buffer (109), its second input connected to the output of a buffer (112), and its output connected to the input of a delay selector module (114). The output of the delay selector module (114) is connected to the first input of a global clock driver module (117) via a flip-flop module (115). The input port CE is connected to the second input of the global clock driver module (117) via a flip-flop module (116). The output of the global clock driver module (117) is connected to reference point D via a tri-state inverter (118). Reference point D is connected to the input of a self-test module (119), and the output of the self-test module (119) is connected to reference point A.

[0045] Three-state inverter (124) and three-state inverter (125), reference point D is connected to the input terminal of three-state inverter (124) and the output terminal of three-state inverter (125), and the output terminal of three-state inverter (124) and the input terminal of three-state inverter (125) are connected to the second right-side connection terminal;

[0046] Reference point D is connected to the global clock terminal GCLK through leaf clock buffer (126).

[0047] Specifically, tri-state inverters (118, 121, 122, 123, 124, 125) for horizontal clocks (left-right direction) and tri-state inverters (102, 105, 108, 111) for vertical clocks (up-down direction) can enable the shutdown or interconnection of horizontal and vertical clocks in adjacent clock domains or within a clock domain. Both types of tri-state inverters include a clock enable control terminal. When the module is not working, the clock signal of this part of the module is prevented from toggling via a control signal. Only when the control signal is valid can the clock of this part of the module work normally. By controlling the clock enable terminal, fine-grained clock management is achieved, and clock network power consumption is reduced.

[0048] Buffers with Schmitt trigger characteristics (103, 106, 109, 112) can reduce clock jitter and improve clock signal quality.

[0049] The three-to-one selector (101, 104, 107, 110) can select different paths for clock conduction by configuring the selector, thereby realizing various clock routing.

[0050] The two-to-one selector (113, 120) can select different path clocks by configuring the selector, thereby realizing various clock routing.

[0051] The delay selector module (114) can perform fine-grained control of the clock delay throughout the clock network, which can minimize clock skew and achieve beneficial skew optimization to improve clock frequency.

[0052] The positive and negative inverter modules (115, 116) enable the output signal and input signal to be positive or negative according to the configuration signal.

[0053] The global clock driver module (117) with enable function provides interference-free clock gating. When the module is not working, the clock signal of this part of the module is prevented from toggling by the control signal. Only when the control signal is valid can the clock of this part of the module work normally. By controlling the clock enable terminal, fine-grained clock management and reduced power consumption of the clock network can be achieved.

[0054] The self-test module (119) can realize the self-test function of clock signal.

[0055] The leaf clock buffer (126) distributes the clock to the logic resources through the interconnect module. The leaf clock buffer includes a clock enable control terminal. When the module is not working, the clock signal of this part of the module is prevented from toggling through the control signal. Only when the control signal is valid can the clock of this part of the module work normally. By controlling the clock enable terminal, fine-grained clock management is achieved and the power consumption of the clock network is reduced.

[0056] Figure 1 This is a clock network architecture within a clock domain. A clock domain (module) is represented as a cell in an array that makes up the entire chip.

[0057] The horizontal clock HCLK3 is directly connected to the horizontal clock HCLK1 in its adjacent right-hand clock domain. The horizontal clock HCLK4 is directly connected to the horizontal clock HCLK2 in its adjacent right-hand clock domain. The vertical clock VCLK1 is directly connected to the vertical clock VCLK2 in its adjacent upper-hand clock domain. The vertical clock VCLK4 is directly connected to the vertical clock VCLK3 in its adjacent upper-hand clock domain. This forms the entire chip clock network.

[0058] Horizontal clocks HCLK1 and HCLK3 are on the upper layer, and HCLK2 and HCLK4 are on the lower layer. Vertical clocks VCLK1 and VCLK2 are on the upper layer, and VCLK3 and VCLK4 are on the lower layer. The upper-layer clock transmission is loadless, enabling fast transmission and primarily used to transmit clock signals to the required clock domain with high quality. The lower-layer clocks are mainly used to transmit clock signals to various logic resources. During clock transmission, the upper-layer clocks first transmit the clock signal to the required clock domain with minimal loss, and then the lower-layer clocks transmit the clock signal to the corresponding logic resource. This transmission method effectively reduces clock network skew, clock jitter, and power consumption.

[0059] By configuring the control terminal of the horizontal clock tri-state inverter (122), the horizontal clock HCLK1 can be directly transmitted to the horizontal clock HCLK3, and then transmitted to the clock domain adjacent to it.

[0060] By configuring the control terminal of the horizontal clock tri-state inverter (123), the horizontal clock HCLK3 can be directly transmitted to the horizontal clock HCLK1, thereby transmitting the clock in the adjacent clock domain to this clock domain.

[0061] By configuring the control terminals of a buffer (103) with Schmitt trigger characteristics, a three-to-one selector (104), and a vertical clock tri-state inverter (105), the vertical clock VCLK1 can be directly transmitted to the vertical clock VCLK2, and then transmitted to the clock domain adjacent to it.

[0062] By configuring the control terminals of a buffer (106) with Schmitt trigger characteristics, a three-to-one selector (101), and a vertical clock tri-state inverter (102), the vertical clock VCLK2 can be directly transmitted to the vertical clock VCLK1, and then transmitted to the adjacent clock domain.

[0063] By configuring the control terminals of a buffer (109) with Schmitt trigger characteristics, a three-to-one selector (110), and a vertical clock tri-state inverter (111), the vertical clock VCLK4 can be directly transmitted to the vertical clock VCLK3, and then transmitted to the clock domain adjacent to it.

[0064] By configuring the control terminals of a buffer (112) with Schmitt trigger characteristics, a three-to-one selector (107), and a vertical clock tri-state inverter (108), the vertical clock VCLK3 can be directly transmitted to the vertical clock VCLK4, and then transmitted to the clock domain adjacent to it.

[0065] By configuring the control terminals of the three-to-one selector (101) and the vertical clock tri-state inverter (102), the horizontal clock HCLK1 can be transmitted to the vertical clock VCLK1.

[0066] By configuring the control terminals of the three-to-one selector (104) and the vertical clock tri-state inverter (105), the horizontal clock HCLK1 can be transmitted to the vertical clock VCLK2.

[0067] By configuring the control terminals of the three-to-one selector (107) and the vertical clock tri-state inverter (108), the horizontal clock HCLK1 can be transmitted to the vertical clock VCLK4.

[0068] By configuring the control terminals of the three-to-one selector (110) and the vertical clock tri-state inverter (111), the horizontal clock HCLK1 can be transmitted to the vertical clock VCLK3.

[0069] By configuring the control terminals of a buffer (103) with Schmitt trigger characteristics, a 2-to-1 selector (120), and a horizontal clock tri-state inverter (121), the vertical clock VCLK1 can be transmitted to the horizontal clock HCLK1.

[0070] By configuring the control terminals of a buffer (103) with Schmitt trigger characteristics, a three-to-one selector (110), and a vertical clock tri-state inverter (111), the vertical clock VCLK1 can be transmitted to the vertical clock VCLK3.

[0071] By configuring the control terminals of a buffer (106) with Schmitt characteristics, a 2-to-1 selector (120), and a horizontal clock tri-state inverter (121), the vertical clock VCLK2 can be transmitted to the horizontal clock HCLK1.

[0072] By configuring the control terminals of a buffer (106) with Schmitt characteristics, a three-to-one selector (107), and a vertical clock tri-state inverter (108), the vertical clock VCLK2 can be transmitted to the vertical clock VCLK4.

[0073] By configuring the control terminals of a buffer (112) with Schmitt trigger characteristics, a two-to-one selector (113), a delay selector module (114), a positive-to-negative converter module (115, 116), a global clock driver module with enable function (117), and a horizontal clock tri-state inverter (118), the vertical clock VCLK3 can be transmitted to the horizontal clock HCLK2.

[0074] By configuring the control terminals of a buffer (109) with Schmitt trigger characteristics, a two-to-one selector (113), a delay selector module (114), a positive-to-negative converter module (115, 116), a global clock driver module with enable function (117), and a horizontal clock tri-state inverter (118), the vertical clock VCLK4 can be transmitted to the horizontal clock HCLK2.

[0075] By configuring the control terminal of the leaf clock buffer (126), the horizontal clock HCLK2 can be transmitted to the global clock GCLK, and then transmitted to each logic resource through the interconnect module.

[0076] By configuring the control terminal of the horizontal clock tri-state inverter (124), the horizontal clock HCLK2 can be transmitted to the horizontal clock HCLK4, and then transmitted to the clock domain adjacent to it.

[0077] By configuring the control terminal of the horizontal clock tri-state inverter (125), the horizontal clock HCLK4 can be transmitted to the horizontal clock HCLK2, thereby transmitting the clock in the adjacent clock domain to the local clock domain.

[0078] In special cases, the horizontal clock HCLK2 can be transmitted to the vertical clock VCLK1 by configuring the control terminals of the self-test module (119), the three-to-one selector (101), and the vertical clock tri-state inverter (102); or the horizontal clock HCLK2 can be transmitted to the vertical clock VCLK2 by configuring the control terminals of the self-test module (119), the three-to-one selector (104), and the vertical clock tri-state inverter (105); this mode is the test mode.

[0079] All selector switches in this invention employ transmission gates or tri-state inverters, significantly reducing duty cycle losses compared to previous methods using NMOS single-transistor transmission. Furthermore, the use of numerous interference-free clock gating mechanisms allows clock switching to be disabled when not needed, thereby reducing power consumption.

[0080] The specification and accompanying drawings have fully explained the principles and necessary technical details of the present invention, and those skilled in the art can implement the present invention based on them. The peripheral circuits related to the present invention will not be described in detail here.

Claims

1. A programmable clock network module, characterized in that, It includes a first clock network unit, a second clock network unit, and a drive test unit; the programmable clock network module has two connection terminals in each of the up, down, left, and right directions.

2. The programmable clock network module as described in claim 1, characterized in that, According to the signal transmission direction, the first clock network unit includes a 3-to-1 selector (101), a tri-state inverter (102), a buffer (103), a 3-to-1 selector (104), a tri-state inverter (105), and a buffer (106) connected in a sequential loop. The output terminal of the tri-state inverter (102) serves as the first upper connection terminal, and the output terminal of the tri-state inverter (105) serves as the first lower connection terminal. The first input of the three-to-one selector (101) is connected to the output of the buffer (106), the second input is connected to the reference point A, and the third input is connected to the reference point C. The first input of the three-to-one selector (104) is connected to the output of the buffer (103), the second input is connected to the reference point A, and the third input is connected to the reference point C. The reference point C is connected to the first left-side output terminal (HCLK1); The first input of the 2-to-1 selector (120) is connected to the output of the buffer (103), the second input is connected to the reference point B, and the output is connected to the reference point C through the tri-state inverter (121). According to the signal transmission direction, the second clock network unit includes a 3-to-1 selector (107), a tri-state inverter (108), a buffer (109), a 3-to-1 selector (110), a tri-state inverter (111), and a buffer (112) connected in a sequential loop. The output terminal of the tri-state inverter (108) serves as the second upper connection terminal, and the output terminal of the tri-state inverter (111) serves as the second lower connection terminal. The first input of the three-to-one selector (107) is connected to the output of the buffer (112), the second input is connected to the reference point B, and the third input is connected to the reference point C. The first input of the three-to-one selector (110) is connected to the output of the buffer (109), the second input is connected to the output of the buffer (103), and the third input is connected to the reference point C.

3. The programmable clock network module as described in claim 3, characterized in that, The drive testing unit includes: Three-state inverter (122) and three-state inverter (123), reference point C is connected to the input terminal of three-state inverter (122) and the output terminal of three-state inverter (123), and the output terminal of three-state inverter (122) and the input terminal of three-state inverter (123) are connected to the first right-side connection terminal; A 2-to-1 selector (113) has its first input connected to the output of a buffer (109), its second input connected to the output of a buffer (112), and its output connected to the input of a delay selector module (114). The output of the delay selector module (114) is connected to the first input of a global clock driver module (117) via a flip-flop module (115). The input port CE is connected to the second input of the global clock driver module (117) via a flip-flop module (116). The output of the global clock driver module (117) is connected to reference point D via a tri-state inverter (118). Reference point D is connected to the input of a self-test module (119), and the output of the self-test module (119) is connected to reference point A. Three-state inverter (124) and three-state inverter (125), reference point D is connected to the input terminal of three-state inverter (124) and the output terminal of three-state inverter (125), and the output terminal of three-state inverter (124) and the input terminal of three-state inverter (125) are connected to the second right-side connection terminal; Reference point D is connected to the global clock terminal GCLK through leaf clock buffer (126).

4. The programmable clock network module as described in claim 3, characterized in that, The buffer is a buffer with Schmitt trigger function.

5. A programmable clock network array, characterized in that, The programmable clock network modules described in claim 3 are arranged in an array; In two adjacent programmable clock network modules, the first lower connection terminal of the upper module is connected to the first upper connection terminal of the lower module, and the second lower connection terminal of the upper module is connected to the second upper connection terminal of the lower module. In two adjacent programmable clock network modules, the first right-side connection terminal of the left module is connected to the first left-side connection terminal of the right module, and the second right-side connection terminal of the left module is connected to the second left-side connection terminal of the right module.

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