Low power lin bus receiver circuit
By using a current mirror structure of high-voltage PLDMOS and NLDMOS transistors in the LIN bus receiving circuit, the voltage difference between the LIN bus and VBAT is sampled. The path is closed in the recessive state and the current is compared in the dominant state, which solves the problem of increased power consumption caused by leakage current in the traditional LIN bus receiving circuit and realizes a low-power circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI CHIPANALOG MICROELECTRONICS LTD
- Filing Date
- 2025-10-11
- Publication Date
- 2026-06-02
AI Technical Summary
Traditional LIN bus receiver circuits continuously sample the LIN bus voltage, leading to increased DC leakage current and chip power consumption. This is especially problematic in low-power applications, as it shortens battery life and increases the burden of system thermal management.
The system employs a first current mirror composed of two high-voltage PLDMOS transistors and two high-voltage NLDMOS transistors. By sampling the voltage difference between the LIN bus and the power supply VBAT, it closes the path from the LIN bus to ground in the recessive state of the LIN bus to reduce static power consumption; and opens the path and performs current comparison in the dominant state to achieve precise control of the threshold voltage.
In the recessive state of the LIN bus, the path from the LIN bus to ground is completely shut down, resulting in zero static power consumption. In the dominant state, the threshold voltage is precisely controlled, reducing the overall power consumption of the chip and solving the power consumption problem caused by leakage current in traditional solutions.
Smart Images
Figure CN121037158B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and more specifically to a low-power LIN bus receiver circuit. Background Technology
[0002] Currently, LIN bus receiver circuits employ two main architectures to detect and determine bus levels. The first approach attenuates the LIN bus voltage using a resistor divider network, then compares it to a reference voltage obtained by VBAT voltage division to identify the bus state. The second approach converts the LIN bus voltage into a current signal and compares it to a reference current generated based on VBAT to determine the logic level. Both methods rely on direct sampling of the bus voltage, enabling relatively reliable communication reception under various operating conditions.
[0003] However, both of these traditional solutions have a significant drawback: due to the need for continuous sampling of the LIN bus voltage in the circuit structure, a DC leakage current path from the LIN bus to ground (GND) is unavoidable. This leakage current not only leads to additional static power consumption but also significantly increases the overall power consumption of the chip. In low-power applications, especially in new energy vehicle electronic systems, this power consumption problem will shorten battery life and increase the burden of system thermal management, thus limiting the application potential of LIN nodes in energy-sensitive scenarios.
[0004] Therefore, a new technological solution is needed. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a low-power LIN bus receiving circuit to at least solve the problem of leakage current causing additional static power consumption and increasing the overall power consumption of the chip in traditional solutions.
[0006] The embodiments of the present invention provide the following technical solutions:
[0007] This invention provides a low-power LIN bus receiver circuit, comprising:
[0008] The first current mirror is composed of two high-voltage PLDMOS transistors. The sources of the two high-voltage PLDMOS transistors are respectively connected to the power supply VBAT, the drain of one high-voltage PLDMOS transistor is connected to the LIN bus, and the drain of the other high-voltage PLDMOS transistor is connected to the node Vc. The node Vc is grounded.
[0009] Two high-voltage NLDMOS transistors are connected together, with their gates connected in series to the node Vc. The drain of one high-voltage NLDMOS transistor is connected to the power supply VBAT, and its source is grounded and connected to one input terminal of the comparator. The drain of the other high-voltage NLDMOS transistor is connected between the LIN bus and the drain of one high-voltage PLDMOS transistor, and its source is grounded and connected to the other input terminal of the comparator.
[0010] When the LIN bus switches from dominant to recessive, the potential difference between the power supply VBAT and the LIN bus is less than the threshold voltage of the high-voltage PLDMOS transistor, and the current flowing through the two high-voltage PLDMOS transistors tends to 0, so that the two high-voltage NLDMOS transistors are turned off.
[0011] Furthermore, the power supply VBAT is connected to the drain of the corresponding NLDMOS transistor via a first resistor.
[0012] Furthermore, the drain of the high-voltage NLDMOS transistor is connected between the LIN bus and the drain of the high-voltage PLDMOS transistor via a second resistor.
[0013] Furthermore, the gates of the two high-voltage PLDMOS transistors are interconnected, and the gate of one high-voltage PLDMOS transistor is connected to its own drain, while the drain of the other high-voltage PLDMOS transistor is connected to the LIN bus through a third resistor.
[0014] The drain of the corresponding high-voltage NLDMOS transistor is connected between the third resistor and the LIN bus via the second resistor.
[0015] Furthermore, the node Vc is grounded via a fourth resistor.
[0016] Furthermore, the source of the high-voltage NLDMOS transistor connected to the power supply VBAT is grounded through the first NMOS transistor and the third NMOS transistor;
[0017] The source of the high-voltage NLDMOS transistor is connected to the drain of the third NMOS transistor, the drain of the third NMOS transistor is connected to its own gate, the source of the third NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded.
[0018] The first NMOS transistor is connected to the input terminal of the comparator to output a first comparison current to the comparator.
[0019] Furthermore, the source of the high-voltage NLDMOS transistor connected to the LIN bus is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded.
[0020] The second NMOS transistor is connected to the input terminal of the comparator to output a second comparison current to the comparator.
[0021] Furthermore, it also includes a fourth NMOS transistor, and a second current mirror is formed between the fourth NMOS transistor and the second NMOS transistor;
[0022] At this time, the drain of the second NMOS transistor is connected to its own gate, the gate of the second NMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the input terminal of the comparator, and the source of the fourth NMOS transistor is grounded.
[0023] Furthermore, the drain of the fourth NMOS transistor is connected to the input terminal of the comparator via a third current mirror;
[0024] The third current mirror consists of two MOS transistors whose gates are connected to each other.
[0025] Furthermore, it also includes a fifth NMOS transistor, and a fourth current mirror is formed between the fifth NMOS transistor and the first NMOS transistor;
[0026] At this time, the drain of the first NMOS transistor is connected to its own gate, the gate of the first NMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the input terminal of the comparator, and the source of the fifth NMOS transistor is grounded.
[0027] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least:
[0028] The present invention discloses a low-power LIN bus receiving circuit. By using a first current mirror composed of two high-voltage PLDMOS transistors and two high-voltage NLDMOS transistors, the circuit can completely shut down the path from the LIN bus to ground when the LIN bus is in a recessive state, so that the static power consumption is 0. Furthermore, when the LIN bus is toggling, the threshold voltage of the LIN bus can be precisely controlled by sampling the current from the LIN bus and the power supply VBAT to ground. Attached Figure Description
[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0030] Figure 1This is a circuit diagram of a low-power LIN bus receiving circuit according to an embodiment of the present invention. Detailed Implementation
[0031] The embodiments of this application will now be described in detail with reference to the accompanying drawings.
[0032] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0034] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0035] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.
[0036] Traditional LIN bus receiver circuits require sampling the bus ground, which increases the leakage current from the bus to ground, thereby increasing the overall power consumption of the chip.
[0037] In view of this, the inventors conducted in-depth research and improvement on the recessive and dominant states of LIN and the structural properties of MOS transistors, and discovered that by sampling the voltage difference between the LIN bus ground and VBAT voltages through PLDMOS, the path from the LIN bus to ground is closed in the recessive state, thereby making the power consumption in the recessive state almost zero, thus reducing the overall static power consumption of the chip.
[0038] Based on this, the embodiments of this specification propose a processing solution: such as Figure 1 As shown, this invention provides a low-power LIN bus receiving circuit. It uses two high-voltage PLDMOS transistors and a third resistor R3 to sample the voltage difference between the LIN bus and the power supply VBAT. When the LIN bus transitions from dominant to recessive, if the voltage difference between the power supply VBAT and the LIN bus is less than the threshold voltage of the PLDMOS transistors, the current flowing through the two PLDMOS transistors becomes zero. This ultimately brings the voltage at node Vc close to zero, shutting down the two NLDMOS transistors. At this point, the path from the LIN bus and the power supply VBAT to ground is closed, and the current flowing out of the two NLDMOS transistors is almost zero. This means the two NLDMOS transistors cannot output current to subsequent circuits, making the static power consumption of the entire circuit approach zero. This ultimately solves the problem of increased overall chip power consumption caused by leakage current in traditional solutions.
[0039] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.
[0040] like Figure 1 As shown, a low-power LIN bus receiving circuit of the present invention includes a first current mirror composed of two high-voltage PLDMOS transistors and two high-voltage NLDMOS transistors. The sources of the two high-voltage PLDMOS transistors are respectively connected to the power supply VBAT, the drain of one high-voltage PLDMOS transistor is connected to the LIN bus, and the drain of the other high-voltage PLDMOS transistor is connected to node Vc, which is grounded. The gates of the two high-voltage NLDMOS transistors are connected in series to node Vc. The drain of one high-voltage NLDMOS transistor is connected to the power supply VBAT, and its source is grounded and connected to one input terminal of a comparator. The drain of the other high-voltage NLDMOS transistor is connected between the LIN bus and the drain of the first high-voltage PLDMOS transistor, and its source is grounded and connected to the other input terminal of the comparator. When the LIN bus switches from dominant to recessive, the potential difference between the power supply VBAT and the LIN bus is less than the threshold voltage of the high-voltage PLDMOS transistors, and the current flowing through the two high-voltage PLDMOS transistors tends to 0, so that the two high-voltage NLDMOS transistors are turned off.
[0041] Specifically, the two high-voltage PLDMOS transistors include PLD1 and PLD2. The drain of PLD1 is connected to its own gate and then connected to the gate of PLD2 to form the first current mirror. The sources of both PLD1 and PLD2 are connected to the power supply VBAT.
[0042] Among them, the two high-voltage NLDMOS transistors include NLD1 and NLD2. The drain of NLD2 is connected to the drain of PLD1 through the second resistor R2, the third resistor R3, and the drain of NLD1 is connected to the power supply VBAT. The gates of NLD1 and NLD2 are connected in series and then connected to node Vc.
[0043] In this embodiment of the invention, the two high-voltage PLDMOS transistors sample the voltage difference between the LIN bus and VBAT. When the LIN bus is recessive, the voltage of the LIN bus is close to the voltage of the power supply VBAT, and the voltage of node Vc approaches 0, so as to turn off the two NLDMOS transistors, thereby making the current from the LIN bus and the power supply VBAT to ground zero, thus closing the path between the LIN bus and the power supply VBAT to ground. When the LIN bus switches to dominant and the bus voltage decreases, the voltage difference between the LIN bus and the power supply VBAT increases, so as to make the voltage of node Vc greater than the threshold voltage of the two high-voltage NLDMOS transistors, thereby turning on the high-voltage NLDMOS transistors, so as to form a path between the LIN bus, the power supply VBAT to ground, and generate a corresponding current. Then the current is compared to obtain the output.
[0044] Preferably, the power supply VBAT is connected to the drain of the corresponding high-voltage NLDMOS transistor through the first resistor R1 to prevent high voltage and high current from directly entering the comparator, and it is also used for current limiting and threshold calibration functions.
[0045] Preferably, the drain of the high-voltage NLDMOS transistor is connected between the LIN bus and the drain of a high-voltage PLDMOS transistor through a second resistor R2.
[0046] The second resistor R2 is used to convert the LIN bus voltage into a mirrorable current signal to avoid the high voltage acting directly on the low voltage comparator.
[0047] The second resistor R2 is also used to limit current when the LIN bus is short-circuited to ground or subjected to ESD.
[0048] Preferably, the gates of the two high-voltage PLDMOS transistors are interconnected, and the gate of one high-voltage PLDMOS transistor is connected to its own drain. The drain of one high-voltage PLDMOS transistor is connected to the LIN bus through a third resistor R3. The drain of the corresponding high-voltage NLDMOS transistor is connected between the third resistor R3 and the LIN bus through a second resistor R2.
[0049] The third resistor R3 is used to provide a DC path from the drain of PLD1 to the LIN bus, so that the LIN bus voltage is moved to the drain of PLD1, allowing the current mirror composed of PLD1 / PLD2 to truly obtain the voltage difference between the power supply VBAT and the LIN bus.
[0050] Among them, two high-voltage PLDMOS transistors and the third resistor R3 are used to sample the voltage difference between the LIN bus and the power supply VBAT.
[0051] Preferably, node Vc is grounded through a fourth resistor R4, where the fourth resistor R4 is used to convert the current mirrored from PLD2 into voltage Vc, and at the same time to give Vc a certain reference of "0V at zero current", so that Vc is low enough when LIN is recessive, allowing NLD1 / NLD2 to be reliably turned off.
[0052] Preferably, the source of the high-voltage NLDMOS transistor connected to the power supply VBAT is grounded through the first NMOS transistor NM1 and the third NMOS transistor NM3; the source of the high-voltage NLDMOS transistor is connected to the drain of the third NMOS transistor NM3, the drain of the third NMOS transistor NM3 is connected to its own gate, the source of the third NMOS transistor NM3 is connected to the drain of the first NMOS transistor NM1, and the source of the first NMOS transistor NM1 is grounded; wherein, the first NMOS transistor NM1 is connected to the input terminal of the comparator to output a first comparison current to the comparator.
[0053] Furthermore, the source of the high-voltage NLDMOS transistor connected to the LIN bus is connected to the drain of the second NMOS transistor NM2, and the source of the second NMOS transistor NM2 is grounded; wherein, the second NMOS transistor NM2 is connected to the input terminal of the comparator to output a second comparison current to the comparator.
[0054] Furthermore, it also includes a fourth NMOS transistor NM4, and a second current mirror is formed between the fourth NMOS transistor NM4 and the second NMOS transistor NM2; at this time, the drain of the second NMOS transistor NM2 is connected to its own gate, the gate of the second NMOS transistor NM2 is connected to the gate of the fourth NMOS transistor NM4, the drain of the fourth NMOS transistor NM4 is connected to the input terminal of the comparator, and the source of the fourth NMOS transistor NM4 is grounded.
[0055] The second NMOS and the fourth NMOS form a second current mirror, which enables the fourth NMOS transistor NM4 to sample the current of the second NMOS transistor NM2.
[0056] Furthermore, the drain of the fourth NMOS transistor NM4 is connected to the input of the comparator through the third current mirror; the third current mirror consists of two MOS transistors whose gates are connected to each other.
[0057] The third current mirror includes MOSFETs M1 and M2. The drain of MOSFET M1 is connected to the drain of the fourth NMOS transistor NM4. The drain of MOSFET M2 is connected to the input of the comparator. The sources of MOSFETs M1 and M2 are both connected to the voltage VDD.
[0058] Among them, MOSFET M2 can sample the current supplied to MOSFET M1 by the fourth NMOS transistor NM4 and transmit the current to the input of the comparator.
[0059] This includes a fifth NMOS transistor NM5, which forms a fourth current mirror with the first NMOS transistor NM1. At this time, the drain of the first NMOS transistor NM1 is connected to its own gate, the gate of the first NMOS transistor NM1 is connected to the gate of the fifth NMOS transistor NM5, the drain of the fifth NMOS transistor NM5 is connected to the input of the comparator, and the source of the fifth NMOS transistor NM5 is grounded. The fifth NMOS transistor NM5 is used to sample the current of the first NMOS transistor NM1, and the current of the first NMOS transistor NM1 is the current output by the power supply VBAT.
[0060] This invention samples the voltage difference between the LIN bus and the power supply VBAT using two high-voltage PLDMOS transistors. When the LIN bus is in a recessive state (the LIN bus voltage and VBAT are approximately equal), the path from the LIN bus and the power supply VBAT to ground is closed, thereby reducing static power consumption. When the LIN bus switches to a dominant state, the path from the LIN bus and the power supply VBAT to ground is quickly opened, the current from the LIN bus to ground and the current from the power supply VBAT to ground are sampled, and the two are compared.
[0061] The working principle of this invention is as follows:
[0062] When the LIN bus switches from dominant to recessive, if the power supply VBAT – LIN bus voltage < |Vth_PLD| (Vth_PLD is the threshold voltage of PLD1 and PLD2):
[0063] At this time, the current flowing through PLD1 is almost zero because PLD2 and PLD1 form a current mirror. Therefore, the current flowing out of PLD2 and the current flowing into the fourth resistor R4 are both close to zero, so Vc≈0, thus turning off NLD1 and NLD2. This closes the path from the LIN bus and the power supply VBAT to GND. The current flowing from NLD1 and NLD2 into the first NMOS transistor NM1 and the second NMOS transistor NM2 is also almost zero because the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 form current mirrors with the second NMOS transistor NM2 and the first NMOS transistor NM1, respectively. Therefore, the current in the fourth NMOS transistor NM4 and the fifth NMOS transistor NM5 is also almost zero, and the static power consumption of the entire current is zero.
[0064] When LIN switches from recessive to explicit, if VBAT – LIN > |Vth_PLD| is satisfied:
[0065] At this point, the current flowing through PLD1 is mirrored onto PLD2, causing a voltage drop across the fourth resistor R4. This makes the voltage at node Vc > Vth_NLD (where Vth_NLD is the threshold voltage of NLD1 and NLD2), thus turning on NLD1 and NLD2. This allows the power supply VBAT and the LIN bus to flow through the first NMOS transistor NM1 and the second NMOS transistor NM2 to GND. The current from the power supply VBAT to GND is mirrored to the fifth NMOS transistor NM5 through the current mirror between the first NMOS transistor NM1 and the fifth NMOS transistor NM5. The current from the LIN bus to GND is mirrored to the second NMOS transistor NM2 and the fourth NMOS transistor NM4, and the current mirror between MOS transistor M1 and MOS transistor M2. The currents of the fifth NMOS transistor NM5 and MOS transistor M2 are compared at Va and output through the subsequent buffer.
[0066] Furthermore, the comparator's flip threshold is calculated as follows:
[0067] The first NMOS transistor NM1, the second NMOS transistor NM2, and the third NMOS transistor NM3 have the same dimensions, and their VGS is assumed to be the same, i.e., VGS_NM1 = VGS_NM2 = VGS_NM3 = VGS, and R1 (the resistance of the first resistor R1) = R2 (the resistance of the second resistor R2) = R. NLD1 and NLD2 are in the linear region and are relatively large; therefore, their VDS voltage drop can be considered almost zero. Thus, the currents flowing through the first NMOS transistor NM1 and the second NMOS transistor NM2 are respectively:
[0068] I_NM1=(VBAT-2VGS) / R, I_NM2=(LIN-VGS) / R;
[0069] The first NMOS transistor NM1 and the fifth NMOS transistor NM5, the second NMOS transistor NM2 and the fourth NMOS transistor NM4, and MOS transistors M1 and M2 form current mirrors with size ratios of 2:1, 1:1, and 1:1, respectively. Therefore:
[0070] I_NM5=I_NM1 / 2=(VBAT-2VGS) / 2R, I_M2=I_M1=I_NM4=I_NM2=(LIN-VGS) / R;
[0071] When the comparator is at the flip-off threshold, I_M2=I_NM5 is satisfied, and the flip-off threshold voltage of the comparator Vth_LIN=VBAT / 2 can be obtained.
[0072] Compared to traditional LIN bus receiving circuits, this invention can completely shut down the path from the LIN bus to GND when the LIN bus is in a recessive state, resulting in zero static power consumption. When the LIN bus is toggling, the threshold voltage of the LIN bus can be precisely controlled by sampling the current from the LIN bus, the power supply VBAT to GND.
[0073] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.
[0074] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A low-power LIN bus receiver circuit, characterized in that, include: A first current mirror is formed by two high-voltage PLDMOS transistors. The sources of the two high-voltage PLDMOS transistors are respectively connected to the power supply VBAT. The drain of one high-voltage PLDMOS transistor is connected to the LIN bus, and the drain of the other high-voltage PLDMOS transistor is connected to node Vc, which is grounded. The gates of the two high-voltage PLDMOS transistors are connected to each other, and the gate of one high-voltage PLDMOS transistor is connected to its own drain. The drain of the other high-voltage PLDMOS transistor is connected to the LIN bus through a third resistor. Two high-voltage NLDMOS transistors are connected together, with their gates connected in series to the node Vc. The drain of one high-voltage NLDMOS transistor is connected to the power supply VBAT, and its source is grounded and connected to one input terminal of the comparator. The drain of the other high-voltage NLDMOS transistor is connected between the LIN bus and the drain of one high-voltage PLDMOS transistor, and its source is grounded and connected to the other input terminal of the comparator. The drain of the corresponding high-voltage NLDMOS transistor is connected between the third resistor and the LIN bus through the second resistor. The third resistor is used to provide a DC circuit from the drain of the high-voltage PLDMOS transistor to the LIN bus and to move the LIN bus voltage to the drain of the high-voltage NLDMOS transistor, so that the current mirror formed by the two high-voltage PLDMOS transistors can obtain the voltage difference between the power supply VBAT and the LIN bus. When the LIN bus switches from dominant to recessive, the potential difference between the power supply VBAT and the LIN bus is less than the threshold voltage of the high-voltage PLDMOS transistor, and the current flowing through the two high-voltage PLDMOS transistors tends to 0, so that the two high-voltage NLDMOS transistors are turned off.
2. The low-power LIN bus receiving circuit according to claim 1, characterized in that, The power supply VBAT is connected to the drain of the corresponding NLDMOS transistor through a first resistor.
3. The low-power LIN bus receiving circuit according to claim 2, characterized in that, The drain of the high-voltage NLDMOS transistor is connected between the LIN bus and the drain of the high-voltage PLDMOS transistor via a second resistor.
4. The low-power LIN bus receiving circuit according to claim 1, characterized in that, The node Vc is grounded via a fourth resistor.
5. The low-power LIN bus receiving circuit according to any one of claims 1-4, characterized in that, The source of the high-voltage NLDMOS transistor connected to the power supply VBAT is grounded through the first NMOS transistor and the third NMOS transistor; The source of the high-voltage NLDMOS transistor is connected to the drain of the third NMOS transistor, the drain of the third NMOS transistor is connected to its own gate, the source of the third NMOS transistor is connected to the drain of the first NMOS transistor, and the source of the first NMOS transistor is grounded. The first NMOS transistor is connected to the input terminal of the comparator to output a first comparison current to the comparator.
6. The low-power LIN bus receiving circuit according to claim 5, characterized in that, The source of the high-voltage NLDMOS transistor connected to the LIN bus is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is grounded. The second NMOS transistor is connected to the input terminal of the comparator to output a second comparison current to the comparator.
7. The low-power LIN bus receiving circuit according to claim 6, characterized in that, It also includes a fourth NMOS transistor, and a second current mirror is formed between the fourth NMOS transistor and the second NMOS transistor; At this time, the drain of the second NMOS transistor is connected to its own gate, the gate of the second NMOS transistor is connected to the gate of the fourth NMOS transistor, the drain of the fourth NMOS transistor is connected to the input terminal of the comparator, and the source of the fourth NMOS transistor is grounded.
8. The low-power LIN bus receiving circuit according to claim 7, characterized in that, The drain of the fourth NMOS transistor is connected to the input terminal of the comparator through the third current mirror; The third current mirror consists of two MOS transistors whose gates are connected to each other.
9. The low-power LIN bus receiving circuit according to any one of claims 7-8, characterized in that, It also includes a fifth NMOS transistor, and a fourth current mirror is formed between the fifth NMOS transistor and the first NMOS transistor; At this time, the drain of the first NMOS transistor is connected to its own gate, the gate of the first NMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fifth NMOS transistor is connected to the input terminal of the comparator, and the source of the fifth NMOS transistor is grounded.