Space-borne multiple-input clock taming system, method and program product

Abstract

This application provides a spaceborne multi-input clock discipline system, method, and program product. The system uses a controller to detect the presence of a continuous clock reference signal in real time. When the signal is normal, it not only uses its high precision to discipline the adjustable frequency converter but also samples and stores the second control signal in this state. If the continuous clock reference fails, the stored value is immediately recalled to maintain the control voltage of the adjustable frequency converter, avoiding frequency jumps and phase abrupt changes during phase-locked loop (PLL) lockout or relocking processes, thus achieving seamless maintenance of the output clock. Simultaneously, the system automatically initiates a backup discipline process based on a pulsed clock reference signal, and smoothly switches the control source after it stabilizes, ensuring long-term frequency accuracy.

Description

Technical Field

[0001] This application relates to the field of satellite technology, and more specifically, to a spaceborne multi-input clock discipline system, method, and program product. Background Technology

[0002] In spaceborne applications such as satellite navigation, deep space exploration, and communication payloads, high-precision time and frequency systems are the core foundation for coherent processing, ranging, and communication. Typically, spaceborne equipment needs to generate and "tame" a locally required high-frequency clock based on an externally input reference signal to ensure long-term stability and low short-term phase noise of the output clock. Common reference signals include a 10MHz sinusoidal reference from a spaceborne atomic clock and a 1PPS pulse from a timing receiver.

[0003] In existing technologies, clock discipline mostly employs a single phase-locked loop (PLL) circuit. This circuit phase-detects an external reference source (e.g., 10MHz) with the feedback signal from a local voltage-controlled crystal oscillator (VCO), and after loop filtering, generates a voltage-controlled voltage to lock the crystal oscillator output to an integer multiple of the reference source frequency. However, this single-path approach has significant drawbacks: in the complex space environment, single-event events, equipment aging, or link failures can cause transient or permanent interruptions in the input reference signal. When the sole reference source suddenly disappears, a typical PLL will experience a rapid frequency drift due to loss of lock, or significant phase adjustment during reacquisition, resulting in frequency jumps or phase abrupt changes in the output clock. For spaceborne systems requiring continuous phase-coherent processing (such as communication demodulation and pseudorange measurement), such jumps can lead to serious consequences such as increased communication error rates, a sharp increase in ranging errors, and even receiver lockout. Summary of the Invention

[0004] The purpose of this application is to provide a spaceborne multi-input clock discipline system, method, and program product to improve the problem in the prior art that the output clock phase jump or frequency change will occur when a single reference source fails.

[0005] In a first aspect, embodiments of this application provide a spaceborne multi-input clock discipline system, including: A controller is coupled to a continuous clock reference signal provider and a pulsed clock reference signal provider, respectively. The controller is used to generate a first control signal based on the pulsed clock reference signal input to the pulsed clock reference signal provider. A continuous clock reference circuit is used to generate a second control signal based on the continuous clock reference signal input at the continuous clock reference signal provider terminal; An adjustable frequency converter is coupled to the continuous clock reference circuit and the controller, respectively, and is used to generate an output clock signal according to the applied control signal; The controller is configured to: Detect the presence of the continuous clock reference signal; If present, the adjustable frequency converter is controlled to output according to the second control signal, and the second control signal is sampled and the sampled value is stored in the memory. If not, the latest stored sample value is read from the memory, and the sample value is applied as a control signal to the adjustable frequency to maintain its output; and a discipline process is initiated to generate a first control signal based on the pulsed clock reference signal. After the discipline process is determined to be stable, the control signal of the adjustable frequency is switched to the first control signal.

[0006] In the above implementation process, the controller monitors the presence of the continuous clock reference signal in real time. When the signal is normal, it not only uses its high precision to discipline the adjustable frequency converter, but also samples and stores the second control signal in this state. Once the continuous clock reference fails, the stored value is immediately recalled to maintain the control voltage of the adjustable frequency converter, avoiding frequency jumps and phase abrupt changes during the phase-locked loop (PLL) unlocking or relocking process, thus achieving seamless maintenance of the output clock. Simultaneously, the system automatically initiates a backup discipline process based on the pulsed clock reference signal, and smoothly switches the control source after it stabilizes, ensuring long-term frequency accuracy. Compared to existing technologies relying on a single PLL, this solution significantly improves the single-event failure resistance and output continuity of the spaceborne clock system in complex space environments, meeting the requirements of communication, ranging, and other coherent processing for clock jump-free and high reliability.

[0007] Optionally, the controller is further configured to: record the control signals of the adjustable frequency converter at different times to form a historical data sequence; when it is detected that neither the continuous clock reference signal nor the pulse clock reference signal exists, predict the signal change trend of the control signal according to the historical data sequence, and output the control signal to the adjustable frequency converter according to the signal change trend.

[0008] In the above implementation process, by continuously recording the historical control signal data of the adjustable frequency transducer during normal system operation, an aging drift trend sequence is formed. In the extreme case where both the continuous clock reference signal and the pulse clock reference signal fail, the controller can fit the change law of the control signal based on the historical data and output the control signal to the adjustable frequency transducer in an open loop according to this trend. This mechanism effectively compensates for the deficiency of traditional discipline circuits in maintaining accuracy when both sources are lost. It enables the system to achieve predictive compensation based on the inherent aging law of the crystal oscillator even without any external reference, keeping the output frequency deviation within a small range for a long time. This significantly extends the autonomous high-precision operation time of spaceborne equipment in deep space or extreme environments, avoids rapid clock drift or system lockout caused by the failure of all reference sources, and improves the fault tolerance, reliability, and mission survivability of the spaceborne clock system.

[0009] Optionally, the continuous clock reference circuit includes a phase comparator coupled to the adjustable frequency converter. The phase comparator is used to compare the phase of the continuous clock reference signal with the feedback signal of the adjustable frequency converter and then output a second control signal.

[0010] In the above implementation process, by integrating a phase comparator into the continuous clock reference circuit, the system can use analog phase-locked loop technology to quickly and accurately lock the adjustable frequency unit to the external continuous clock reference signal, and output a low phase noise and highly stable clock signal.

[0011] Optionally, the continuous clock reference circuit further includes a filter coupled to the phase comparator, the output of the filter being coupled to the control terminal of the adjustable frequency unit, for filtering and outputting the second control signal output by the phase comparator.

[0012] In the above implementation process, by introducing a filter into the continuous clock reference circuit, the output signal of the phase comparator is smoothed, the short-term stability of the output clock is improved, and a high-quality data source is provided for subsequent voltage sampling and aging simulation.

[0013] Optionally, the continuous clock reference circuit further includes a voltage detector coupled to the output of the filter, used to acquire the second control signal output by the filter and output it to the controller.

[0014] In the above implementation process, by integrating a voltage detector into the continuous clock reference circuit, periodic and high-precision acquisition and storage of the second control signal are achieved, providing reliable data support for seamless switching and aging simulation.

[0015] Optionally, the voltage detector is specifically used to periodically sample the second control signal, and then average the multiple sampled data collected in each sampling period and send them to the controller.

[0016] In the above implementation process, by adopting a multi-point collection and averaging method in each sampling period, the anti-interference ability and long-term consistency of the collected data are significantly improved, providing a highly reliable data foundation for seamless switching and aging simulation.

[0017] Optionally, the sampling period is determined based on the satellite's orbital period.

[0018] In the above implementation process, by synchronizing the sampling period of the voltage detector with the satellite orbit period, the interference caused by the periodic fluctuations of the environment can be eliminated, so that the collected voltage value can more accurately reflect the long-term aging trend of the crystal oscillator rather than the instantaneous environmental disturbance.

[0019] Optionally, the system further includes a voltage output device coupled between the controller and the adjustable frequency converter, the voltage output device being used to perform digital-to-analog conversion on the first control signal.

[0020] In the above implementation process, the signal conversion is realized through the voltage output device, and the output of the voltage output device is adjusted by the controller. This achieves slow and high-precision discipline based on 1PPS pulse signal, which can provide a reliable backup discipline path after continuous clock reference failure, and ensure the long-term frequency accuracy of the output clock.

[0021] Optionally, the system further includes a switcher coupled to the controller, the continuous clock reference circuit, and the adjustable frequency converter, the switcher being used to switch the control signal source of the control terminal of the adjustable frequency converter.

[0022] In the above implementation process, a switch controlled by the controller enables flexible and seamless switching between the primary discipline path, the hold path, and the backup discipline path, providing a hardware foundation for seamless redundancy of the spaceborne multi-input clock discipline system.

[0023] Optionally, the system further includes an LDO regulator coupled to the controller for providing operating voltage to the logic chip, which distributes the output clock signal of the adjustable frequency converter into multiple clock outputs.

[0024] In the above implementation process, by adding an adjustable LDO regulator, a manageable power supply is provided for the logic chip, and the logic chip expands the single high-precision clock into multiple synchronous outputs, which meets the distributed clock requirements of complex onboard electronic systems, while enhancing the power management flexibility and reliability of the system.

[0025] Secondly, embodiments of this application provide a spaceborne multi-input clock discipline method, applied to the controller in the aforementioned system, the method comprising: Detect the presence of a continuous clock reference signal at the continuous clock reference signal provider. If present, the adjustable frequency converter is controlled to output according to the second control signal, and the second control signal is sampled and the sampled value is stored in the memory. If it does not exist, the latest stored sample value is read from the memory and applied as a control signal to the adjustable frequency converter to maintain its output; Initiate the discipline process by generating a first control signal based on the pulsed clock reference signal; After confirming that the taming process is stable, the control signal of the adjustable frequency device is switched to the first control signal.

[0026] Thirdly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the steps of the method provided in the second aspect above.

[0027] Fourthly, embodiments of this application provide a computer program product, including computer program instructions, which are read and executed by a processor to perform the steps in the method provided in the second aspect above.

[0028] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing embodiments of this application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 A schematic diagram of the structure of a spaceborne multi-input clock discipline system provided in this application embodiment; Figure 2 A detailed structural schematic diagram of a spaceborne multi-input clock discipline system provided in this application embodiment; Figure 3A flowchart of a spaceborne multi-input clock discipline method provided in an embodiment of this application. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0032] It should be noted that the terms "system" and "network" in the embodiments of this invention can be used interchangeably. "Multiple" refers to two or more; therefore, in the embodiments of this invention, "multiple" can also be understood as "at least two". "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0033] It should also be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.

[0034] This application provides a spaceborne multi-input clock discipline system. The system uses a controller to detect the presence of a continuous clock reference signal in real time. When the signal is normal, it not only uses its high precision to discipline the adjustable frequency converter but also samples and stores a second control signal in this state. If the continuous clock reference fails, the system immediately recalls the stored value to maintain the control voltage of the adjustable frequency converter, avoiding frequency jumps and phase abrupt changes during phase-locked loop (PLL) lockout or relocking, thus achieving seamless maintenance of the output clock. Simultaneously, the system automatically initiates a backup discipline process based on a pulsed clock reference signal, and smoothly switches the control source after it stabilizes, ensuring long-term frequency accuracy.

[0035] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of a spaceborne multi-input clock discipline system 100 provided in an embodiment of this application. The system 100 includes modules such as a controller 110, a continuous clock reference circuit 120, and an adjustable frequency converter 130.

[0036] The input terminal of the controller 110 is coupled to the continuous clock reference signal provider and the pulsed clock reference signal provider respectively. The controller 110 is used to generate a first control signal based on the pulsed clock reference signal input from the pulsed clock reference signal provider.

[0037] The continuous clock reference signal provider (not shown in the figure) here can refer to an interface or port in the onboard equipment used to output a continuous, periodic waveform signal. This provider can be integrated into the input of controller 110 and the input of continuous clock reference circuit 120. This provider is typically connected to a high-precision frequency source, such as an onboard atomic clock or a high-stability crystal oscillator. Its output signal is a continuous clock reference signal, typically characterized by stable frequency, continuous waveform (such as a 10MHz sine wave or square wave), and phase information carried in each cycle, making it suitable for fast phase-locked loop discipline. In this system, the continuous clock reference signal provider serves as the primary reference source, providing a frequency reference with high short-term stability for the system.

[0038] The pulsed clock reference signal provider (not shown in the figure) refers to the interface or port in the spaceborne equipment used to output discrete pulse signals. This provider can be integrated into the input of controller 110. This provider is typically connected to a Global Navigation Satellite System (GNSS) timing receiver, such as a Global Positioning System (GPS), BeiDou, or Galileo receiver. Its output signal is a pulsed clock reference signal, typically characterized by outputting one narrow pulse per second (1PPS), with the rising edge of the pulse precisely corresponding to an integer second. This type of signal has no information between adjacent pulses and a slow discipline speed, but it has high long-term frequency accuracy (traceable to the time reference of the satellite navigation system). In this system, the pulsed clock reference signal provider serves as a backup / calibration reference source for long-term drift correction.

[0039] The controller 110 is typically implemented by a microcontroller unit (MCU), digital signal processor (DSP), or field-programmable gate array (FPGA), and is responsible for functions such as signal detection, algorithm calculation, memory access, and switching control.

[0040] The continuous clock reference circuit 120 is used to generate a second control signal based on the continuous clock reference signal input at the continuous clock reference signal provider terminal.

[0041] The continuous clock reference circuit 120 is an analog circuit module that may contain devices such as a phase detector and a filter. It can compare the phase of the input continuous clock reference signal with the feedback signal of the adjustable frequency unit 130 and output a smooth analog voltage, i.e., the second control signal.

[0042] The adjustable frequency unit 130 is coupled to the continuous clock reference circuit 120 and the controller 110 respectively, and is used to generate an output clock signal according to the control signal applied to its control terminal.

[0043] An adjustable frequency converter 130 refers to an oscillator whose output frequency can be adjusted by an external control voltage, typically implemented as a voltage-controlled crystal oscillator (VCXO) or a temperature-controlled crystal oscillator (OCXO). Its control terminal voltage has a linear or approximately linear relationship with the output frequency.

[0044] To prevent a common phase-locked loop from rapidly drifting its output frequency due to loss of lockout when the main reference source suddenly disappears, or from undergoing a large phase adjustment to relock, resulting in phase jumps or frequency abrupt changes in the output clock, this solution configures the controller 110 to: detect the presence of a continuous clock reference signal; if present, control the adjustable frequency converter 130 to output under the control of a second control signal, sample the second control signal, and store the sampled value in memory; if absent, read the latest stored sampled value from memory and apply it as a control signal to the adjustable frequency converter 130 to maintain its output; and initiate a discipline process to generate a first control signal based on a pulsed clock reference signal. After confirming that the discipline process is stable, the controller switches the control signal of the adjustable frequency converter 130 to the first control signal.

[0045] In a practical implementation, it is assumed that after the system is powered on, the onboard atomic clock normally outputs a 10MHz sine wave, and the timing receiver normally outputs a 1PPS pulse. In some embodiments, the controller 110 can receive a spun signal from the continuous clock reference signal provider through a spun signal detection pin. This spun signal can be obtained by splitting it through a low-capacitance, high-isolation buffer before the continuous clock reference signal enters the continuous clock reference circuit 120, in order to avoid interference with the main signal path. The controller 110 can be configured with a timer and an input capture unit for real-time monitoring of the spun signal. The detection process can adopt a dual judgment strategy of level and period, specifically including: First, the controller 110 uses a comparator or Schmitt trigger to determine whether there is a valid level transition on the input pin. If the signal is continuously high or low for more than a preset threshold (such as 100 microseconds), it is determined to be a level failure; second, if the level is normal, the controller 110 starts a timer to continuously measure the width of multiple signal periods. Since the continuous clock reference signal is a 10MHz sine wave, its theoretical period is 100 nanoseconds. The controller 110 continuously captures, for example, 10 complete rising edge-to-rising edge intervals, calculates the average period, and compares it with a theoretical value (e.g., 100 nanoseconds). If the average period deviates from the theoretical value by more than a preset tolerance (e.g., ±10%), or if a valid rising edge is not captured for several consecutive times (e.g., no edge change within 10 consecutive expected periods), the controller determines that the signal frequency is abnormal or the signal is lost.

[0046] To combat transient glitches caused by single-event transients, the controller 110 employs a de-jitter confirmation mechanism: only after multiple consecutive detection cycles (e.g., three consecutive times, each detection window being 10 cycles) have determined that the signal is abnormal, is the continuous clock reference signal finally confirmed to be invalid, i.e., non-existent. For example, during normal operation, the controller 110 executes a detection process every 1 millisecond, measuring the average width of 10 cycles each time. If no valid cycle is measured for three consecutive times (i.e., within 3 milliseconds) or the cycle deviation is too large, the signal loss is confirmed. This dual judgment combined with de-jitter confirmation effectively distinguishes between transient noise interference and actual signal failure, avoiding erroneous switching due to misjudgment, while ensuring a rapid response when the signal is truly lost (typically completing detection and triggering subsequent seamless switching processes within milliseconds).

[0047] If the above judgment confirms the presence of the signal, the controller 110 can directly connect the second control signal output by the continuous clock reference circuit 120 to the control terminal of the adjustable frequency converter 130. At this time, the adjustable frequency converter 130 (e.g., a VCXO nominally rated at 100MHz) adjusts its output frequency according to the voltage value of the second control signal, quickly locking to an integer multiple of 10MHz (e.g., 100MHz), and maintaining low phase noise output.

[0048] Simultaneously, controller 110 initiates the sampling process for the second control signal. The voltage value at the output of the continuous clock reference circuit 120 can be continuously acquired in a high-impedance manner using an internally integrated ADC (Analog-to-Digital Converter) or an external ADC. The acquired voltage value is then stored in memory. This memory can be external or internally integrated, and can be non-volatile, such as Flash, EEPROM (Electrically Erasable Programmable Read-Only Memory), or FRAM (Ferroelectric Random Access Memory), to store the sampled voltage value, ensuring data integrity even after system power failure or reference source failure.

[0049] In the complex space environment, single-event effects can cause momentary interruptions or anomalies in the 10MHz signal. Controller 110 continuously monitors the level and frequency of the 10MHz signal. Once signal loss is detected (e.g., no rising edge is detected for 10 consecutive cycles), indicating the absence of a continuous clock reference signal, the switching process is immediately initiated.

[0050] First, controller 110 reads the latest saved sampled value, i.e., the voltage value, from memory. Then, it outputs this voltage value through its internal DAC (Digital-to-Analog Converter) and connects the input of adjustable frequency unit 130 to the DAC output. Since the voltage output by the DAC is almost identical to the output voltage of the continuous clock reference circuit 120 just before the failure, the control voltage of the adjustable frequency unit 130 does not change abruptly, thus maintaining its output frequency and phase, achieving seamless switching. This process is typically completed in a short time, much faster than the relocking time of the phase-locked loop, thereby avoiding communication errors or ranging jumps.

[0051] After achieving seamless hold, controller 110 needs to establish a new discipline path as soon as possible to avoid frequency drift caused by relying solely on open-loop hold for an extended period. This path is based on a 1PPS pulse signal output from the pulsed clock reference signal provider, and is implemented as follows: The controller 110 divides the output clock (e.g., 100MHz) of the adjustable frequency converter 130 and feeds it back to an edge comparator inside the controller 110. Simultaneously, a 1PPS pulse signal is also input to this comparator. The controller 110 compares the time difference between the rising edge of the 1PPS pulse and the most recent rising edge of the feedback clock at a rate of once per second. Based on the comparison result, the controller 110 runs a digital proportional-integral (PI) algorithm to gradually adjust its output value (i.e., the first control signal). For example, if the rising edge of the feedback clock is detected to be 10 nanoseconds earlier than the 1PPS pulse, it indicates that the output frequency of the adjustable frequency converter 130 is too high. The controller 110 reduces the output value by a step (e.g., 0.5mV), thereby slightly lowering the crystal oscillator frequency. After hundreds of comparisons (which may take hundreds of seconds), the output value converges to a value that precisely synchronizes the output clock with the 1PPS pulse. At this point, the controller 110 determines that the discipline process has stabilized.

[0052] Subsequently, the controller 110 connects the first control signal it outputs to the control terminal of the adjustable frequency unit 130. From this point on, the system is completely controlled and disciplined by the 1PPS pulse signal. Although the discipline speed is slow, the long-term frequency accuracy is not much different from that of the satellite time signal.

[0053] In the above implementation process, the controller 110 detects the presence of the continuous clock reference signal in real time. When the signal is normal, it not only uses its high precision to discipline the adjustable frequency converter 130, but also samples and stores the second control signal in this state. Once the continuous clock reference fails, the stored value is immediately recalled to maintain the control voltage of the adjustable frequency converter 130, avoiding frequency jumps and phase changes during the phase-locked loop (PLL) unlocking or relocking process, thus achieving seamless maintenance of the output clock. At the same time, the system automatically initiates a backup discipline process based on the pulsed clock reference signal, and smoothly switches the control source after it stabilizes, ensuring long-term frequency accuracy. Compared with existing technologies that rely on a single PLL, this solution significantly improves the single-event failure resistance and output continuity of the spaceborne clock system in complex space environments, meeting the requirements of communication, ranging, and other coherent processing for clock jump-free and high reliability.

[0054] Based on the above embodiments, in order to avoid the system failing to work properly when both input clock sources fail, the controller 110 is also configured to: record the control signals of the adjustable frequency converter 130 at different times to form a historical data sequence; when it is detected that neither the continuous clock reference signal nor the pulse clock reference signal is present, predict the signal change trend of the control signal according to the historical data sequence, and output the control signal to the adjustable frequency converter 130 according to the signal change trend.

[0055] When both input clock sources fail, the system enters a fully open-loop hold mode. In this mode, the controller 110 cannot obtain frequency or phase correction information from any external reference signal and must rely on statistical learning of the long-term aging behavior of the adjustable frequency converter 130 (e.g., a voltage-controlled crystal oscillator) to maintain output accuracy. Therefore, the controller 110 is pre-configured to continuously record the control signal value applied to the control terminal of the adjustable frequency converter 130 and its corresponding timestamp during normal system operation (i.e., when at least one reference signal is present), forming a historical data sequence and storing it in memory (e.g., Flash). This control signal can be a digitized DAC input code value or a converted voltage value.

[0056] Because satellite payloads have regular orbital periods (e.g., a low-Earth orbit satellite orbits the Earth every 90-100 minutes), the controller 110 typically records data in units of orbital periods. At the end of each orbital period, the average control signal value of the current period (i.e., the average value of the voltage samples obtained from the previous sampling) along with the orbital number or absolute time is stored in a historical data table. The length of the historical data table is configurable; for example, storing data from the most recent 256 orbital periods is sufficient to reflect the aging and drift trends of the crystal oscillator over several days to several months.

[0057] When the controller 110 confirms through the aforementioned detection methods that neither the continuous clock reference signal (10MHz) nor the pulsed clock reference signal (1PPS) exists, the system enters a dual-source failure state. At this time, the controller 110 immediately reads the historical data sequence from the memory and calls the preset prediction algorithm to deduce the changing trend of the control signal over a future period of time.

[0058] The core idea of ​​the prediction algorithm can be that the aging drift of a crystal oscillator is usually slow and monotonic, and the change of its control voltage over time can be fitted using a low-order polynomial (such as a linear or quadratic function). Specifically, the controller 110 uses time as the x-axis and historical control signal values ​​as the y-axis to fit an optimal curve using the least squares method. For example, if historical data shows that the DAC output value gradually increases from 1.230V to 1.235V over the past 30 track cycles, and the rate of increase is basically constant, then the controller 110 chooses linear fitting, obtaining the formula V(t) = V0 + k*t, where V0 is the most recently recorded control signal value (e.g., 1.235V), and k is the average rate of change per unit time (e.g., +0.000167V per day). If the aging shows an accelerating or decelerating trend, a quadratic function V(t) = at can be used. 2 The +bt+c method is used for fitting to obtain higher prediction accuracy.

[0059] After fitting, controller 110 calculates the required control signal value at fixed time intervals (e.g., per second or per orbit cycle) according to the fitted trend, and outputs this value to the control terminal of adjustable frequency converter 130 via DAC. Because controller 110 maintains a high-precision real-time clock internally, the system can accurately keep time even without external reference, thus recursively controlling the voltage along the time axis. For example, assuming the dual-source failure time is orbit cycle T0, and the fitted linear rate of change is +0.0005V per orbit cycle, then the voltage output by controller 110 in the nth orbit cycle after the failure is V. n =V T0 +0.0005×n, where V T0 This is the most recently recorded control signal value. When the adjustable frequency unit 130 is a high-stability, temperature-controlled crystal oscillator, its corresponding control voltage changes extremely slowly. Through the aforementioned predictive open-loop output, the system can maintain the frequency deviation of the output clock within 50 ppb for several days or even weeks, greatly extending the effective operating time under dual-source failure conditions.

[0060] It should be noted that, to address the aging characteristics of different crystal oscillators, the prediction algorithm in controller 110 can adaptively select the fitting order. During normal system operation, controller 110 periodically refits historical data using the latest acquired control signal values ​​and evaluates the fitting residuals. If the residuals indicate that the linear fit is sufficiently accurate, the linear model continues to be used; if the residuals continue to increase, it automatically switches to a quadratic or higher-order model. Furthermore, when the dual-source failure state persists for a considerable period, prediction errors gradually accumulate. Controller 110 can periodically check if any reference signal has recovered. Once any reference signal is detected to be valid again, the system immediately exits the fully open-loop prediction mode and re-enters the normal closed-loop discipline or switching process, thereby correcting any deviations that may have accumulated during prolonged open-loop operation.

[0061] In the above implementation process, by continuously recording the historical control signal data of the adjustable frequency converter 130 during normal system operation, an aging drift trend sequence is formed. In the extreme case where both the continuous clock reference signal and the pulse clock reference signal fail, the controller 110 can fit the change law of the control signal based on the historical data and output the control signal to the adjustable frequency converter 130 in open loop according to this trend. This mechanism effectively compensates for the defect of traditional discipline circuits in maintaining accuracy when both sources are lost. It enables the system to achieve predictive compensation based on the inherent aging law of the crystal oscillator even without any external reference, keeping the output frequency deviation within a small range for a long time. This significantly extends the autonomous high-precision operation time of the spaceborne equipment in deep space or extreme environments, avoids rapid clock drift or system lockout caused by the failure of all reference sources, and improves the fault tolerance, reliability, and mission survivability of the spaceborne clock system.

[0062] The following is a detailed description of the system structure of this solution, such as... Figure 2 As shown. In some embodiments, the continuous clock reference circuit 120 includes a phase comparator 122 coupled to the adjustable frequency converter 130. The phase comparator 122 is used to compare the phase of the continuous clock reference signal with the feedback signal of the adjustable frequency converter 130 and output a second control signal.

[0063] The phase comparator 122 is a circuit that compares the phase difference (or time difference) between two signals of the same frequency. Common implementations include analog phase detectors (such as double-balanced mixers or XOR gate phase detectors) or digital-to-digital converters. The phase comparator 122 outputs a signal (such as voltage or current) proportional to the phase difference, which is the second control signal.

[0064] The feedback signal of the adjustable frequency unit 130 refers to a signal output from the output terminal of the adjustable frequency unit 130 (voltage-controlled crystal oscillator). It can usually be reduced to the same frequency as the reference signal by a frequency divider (e.g., 100MHz divided to 10MHz) and then sent back to the phase comparator 122 to form a closed-loop negative feedback.

[0065] The second control signal can be an analog voltage signal output by the phase comparator 122, which directly reflects the instantaneous phase error between the reference signal and the feedback signal. This signal is applied to the control terminal of the adjustable frequency unit 130 to correct its output frequency.

[0066] When the system is operating normally, the continuous clock reference signal provider (e.g., a spaceborne atomic clock) outputs a highly stable 10MHz sine wave. This signal can first pass through a buffer and then be split into two paths: one path enters the phase comparator 122 of the continuous clock reference circuit 120, and the other path is sent to the controller 110 for presence detection.

[0067] The 100MHz clock signal output from the adjustable frequency unit 130 (such as a voltage-controlled crystal oscillator nominally rated at 100MHz) can be down-divided into a 10MHz square wave by an integer divider (division ratio of 10). This divided feedback signal is also fed into the phase comparator 122. The phase comparator 122 employs an analog phase detector in the form of a double-balanced mixer, with its two inputs receiving a 10MHz sinusoidal reference signal and a 10MHz square wave feedback signal, respectively. The phase detector outputs a voltage proportional to the phase difference between the two signals, which contains both DC and high-frequency harmonic components.

[0068] For example, when the rising edge of the feedback signal is exactly aligned with the zero-crossing point of the reference signal (phase difference is 0), the phase detector outputs a DC voltage of the standard value Vmid, such as 1.25V. If the feedback signal lags behind the reference signal (e.g., 10 nanoseconds, corresponding to a 36-degree phase difference), the phase detector output voltage will rise to 1.27V; if it leads, it will drop to 1.23V. This output voltage changes linearly with the phase difference, and the slope of the change is called the phase detection gain (e.g., 20 mV / degree).

[0069] The output of phase comparator 122 can be directly fed into the control terminal of adjustable frequency converter 130. When controller 110 connects the output of phase comparator 122 to the control terminal of adjustable frequency converter 130, the system forms a closed-loop phase-locked loop. Adjustable frequency converter 130 adjusts its output frequency according to the voltage represented by the second control signal: as the voltage increases, the frequency increases; as the voltage decreases, the frequency decreases. The feedback signal changes accordingly, and phase comparator 122 detects the new phase error and adjusts its output again. After a negative feedback process of several milliseconds to tens of milliseconds, a steady state is finally reached: the phase difference between the feedback signal and the reference signal is locked at a fixed value, and the second control signal stabilizes at the corresponding voltage. At this time, the output frequency of adjustable frequency converter 130 is equal to an integer multiple of the reference frequency (e.g., 10MHz × 10 = 100MHz), and has the same long-term stability and extremely low short-term phase noise as the reference source.

[0070] For example, initially, the free oscillation frequency of the adjustable frequency unit 130 might be 99.999MHz, resulting in a significant phase drift of the feedback signal relative to the reference signal. The phase detector outputs an error voltage (e.g., 1.35V), which is applied to the control terminal of the voltage-controlled crystal oscillator to increase its frequency. As the frequency approaches 100MHz, the phase difference gradually decreases, and the error voltage drops. When the crystal oscillator frequency is precisely 100MHz and the phase is aligned, the error voltage stabilizes at 1.25V, and locking is complete.

[0071] In this embodiment, the output of phase comparator 122 (the second control signal) is not only used to drive the adjustable frequency converter 130, but is also periodically sampled by the controller 110 via the ADC and stored in the memory for subsequent seamless switching and aging simulation. In addition, phase comparator 122 itself may not contain any intelligent control logic and is implemented entirely by analog circuitry, ensuring low latency and high reliability of the discipline path.

[0072] In the above implementation process, by integrating a phase comparator 122 into the continuous clock reference circuit 120, the system can use analog phase-locked loop technology to quickly and accurately lock the adjustable frequency unit 130 to the external continuous clock reference signal, and output a low phase noise and highly stable clock signal.

[0073] Based on the above embodiments, the continuous clock reference circuit 120 further includes a filter 124, which is coupled to the phase comparator 122, and the output terminal of the filter 124 is coupled to the control terminal of the adjustable frequency unit 130. The filter 124 is used to filter the second control signal output by the phase comparator 122 and then output it.

[0074] Filter 124 is a circuit capable of extracting a smooth DC component (or low-frequency component) from a signal containing high-frequency noise and ripple. In this system, filter 124 can be a low-pass filter (LPF), such as a passive RC filter, an active filter (such as a second- or third-order filter constructed from operational amplifiers), or a charge pump filter. Its main function is to filter out high-frequency harmonics, reference leakage signals, and random noise in the output signal of phase comparator 122, retaining a clean error voltage.

[0075] In the continuous clock reference circuit 120, the output of the phase comparator 122 is directly coupled to the input of the filter 124 (this coupling can be DC or AC, depending on the specific circuit). The output of the filter 124 is then connected to the control terminal of the adjustable frequency converter 130. When the system selects the continuous clock reference circuit 120 as the discipline source, the controller 110 applies the filtered second control signal to the adjustable frequency converter 130.

[0076] In this embodiment, filter 124 can be a classic passive second-order low-pass filter, composed of resistors and capacitors (or an active filter can be used to obtain better roll-off characteristics). The cutoff frequency of the filter needs to be much lower than the operating frequency of phase comparator 122 (e.g., 10MHz), typically set between tens and hundreds of kilohertz, to ensure the filtering out of the reference frequency and its harmonics while retaining the error signal within the loop bandwidth. For spaceborne applications, filter 124 also needs to be radiation hardened, using ceramic capacitors and metal film resistors to avoid parameter abrupt changes caused by single-event effects.

[0077] Understandably, the waveform before filtering may be pulsed or stepped, containing abundant high-frequency components. For example, when the frequency of the adjustable frequency converter 130 is too low, the phase comparator 122 outputs a pulse sequence with a duty cycle greater than 50%, the average value of which is higher than the midpoint voltage. If this pulse sequence is directly applied to the control terminal of the adjustable frequency converter 130, the crystal oscillator will still experience an equivalent average voltage due to the limited response speed of the crystal oscillator control terminal (typically on the order of microseconds to milliseconds). However, a small frequency disturbance will be generated due to the instantaneous overshoot of the rising and falling edges of the pulses, leading to a deterioration in the short-term stability of the output clock.

[0078] After filtering the voltage signal output by the phase comparator 122, the filter 124 outputs a smooth signal. The waveform of this smooth signal is a smooth DC line that changes only slowly with the phase difference. This smooth voltage is applied to the control terminal of the adjustable frequency unit 130 (such as a voltage-controlled crystal oscillator), so that the crystal oscillator frequency is stable and the phase noise is low.

[0079] In addition, the filtered second control signal, besides driving the adjustable frequency converter 130, is also sampled by the controller 110 via an ADC (the sampling point is usually located at the output of filter 124). Since filter 124 has eliminated high-frequency noise, the voltage value acquired by the ADC is more stable and accurate, directly reflecting the locking state of the phase-locked loop. These sampled values ​​are stored in Flash memory, providing a reliable data foundation for subsequent seamless switching and aging simulation.

[0080] In the above implementation process, by introducing a filter 124 into the continuous clock reference circuit 120, the output signal of the phase comparator 122 is smoothed, which improves the short-term stability of the output clock and provides a high-quality data source for subsequent voltage sampling and aging simulation.

[0081] Based on the above embodiments, the continuous clock reference circuit 120 further includes a voltage detector 126, which is coupled to the output terminal of the filter 124, for acquiring the second control signal output by the filter 124 and outputting it to the controller 110.

[0082] The voltage detector 126 is a circuit capable of sampling, quantizing, and converting analog voltage signals into digital quantities (or transmitting them to the controller 110). In this system, the voltage detector 126 is typically composed of an ADC. Its core function is to convert continuous analog voltages into discrete digital values ​​for the controller 110 to read and process.

[0083] In the continuous clock reference circuit 120, the input of the voltage detector 126 is directly coupled (or can be coupled through a high-impedance buffer) to the output of the filter 124. This high-impedance connection is to avoid introducing an additional load into the voltage detector 126, thus not affecting the voltage accuracy of the filter 124 output or interfering with the normal operation of the phase-locked loop. The buffer can be a unity-gain operational amplifier (such as a rail-to-rail op-amp) with an input impedance in the megaohm range and an extremely low output impedance, capable of driving the subsequent ADC.

[0084] The core component of the voltage detector 126 is the ADC (Analog-to-Digital Converter). Depending on the system's requirements for sampling accuracy and speed, ADCs with different resolutions and sampling rates can be selected. In this embodiment, a 12-bit successive approximation ADC can be used, with a sampling rate configurable to several thousand times per second and a resolution of approximately 1 mV (when the reference voltage is 3.3V). The ADC's reference voltage is typically taken from the system's high-precision reference source (such as an external precision voltage reference chip) to ensure the accuracy and temperature stability of the measurement results.

[0085] The controller 110 can communicate with the ADC via a Serial Peripheral Interface (SPI) or an Inter-Integrated Circuit (I2C) bus, periodically triggering conversions and reading the conversion results. In some implementations, to reduce the impact of single-event effects in spaceborne environments, a verification mechanism (such as CRC (Cyclic Redundancy Check)) can be added between the ADC and the controller 110, and critical signal lines can be protected during PCB (Printed Circuit Board) layout.

[0086] The second control signal acquired by voltage detector 126 is the key data source for the seamless switching mechanism. When controller 110 detects a failure of the continuous clock reference signal, it immediately reads the latest stored voltage value from memory and outputs that voltage. Since the output value is almost exactly the same as the actual voltage output by filter 124 just before the failure, the control voltage of adjustable frequency unit 130 will not change abruptly, thus avoiding phase or frequency jumps in the output clock.

[0087] Furthermore, the historical data sequence (voltage values ​​stored according to the orbital period) collected by voltage detector 126 also forms the basis for subsequent aging trend prediction in the event of dual-source failure. By analyzing the variation patterns of these historical data, controller 110 fits the variation curve of crystal oscillator control voltage over time, thereby achieving predictive open-loop hold without any reference signal.

[0088] In the above implementation process, by integrating a voltage detector 126 into the continuous clock reference circuit 120, periodic and high-precision acquisition and storage of the second control signal are achieved, providing reliable data support for seamless switching and aging simulation.

[0089] In some implementations, the voltage detector 126 does not sample continuously. Instead, the voltage detector 126 can be used to periodically sample the second control signal and then average the multiple sampled data collected in each sampling period before sending them to the controller 110.

[0090] The sampling period refers to the time interval between two consecutive data acquisitions initiated by the voltage detector 126. This sampling period can be determined manually according to requirements. Alternatively, in some implementations, the sampling period is determined based on the satellite's orbital period. The satellite's orbital period refers to the time required for the satellite to complete one orbit around the Earth. For low Earth orbit satellites, the orbital period is approximately 90–120 minutes; for geostationary orbit satellites, the orbital period is 24 hours. This implementation uses a low Earth orbit satellite with an orbital period of approximately 100 minutes as an example for illustration.

[0091] Voltage detector 126 does not sample at fixed time intervals (e.g., every second or every minute), but instead sets the sampling period to match the satellite's orbital period. This is because, during satellite operation, its external environment (such as temperature, solar radiation, and the Earth's magnetic field) changes periodically with its orbital position. These environmental factors directly affect the output frequency of the adjustable frequency unit 130 (e.g., a crystal oscillator) and the voltage-controlled voltage of the phase-locked loop. By sampling at the same phase point in each orbital period (e.g., when the satellite passes over the equator or a reference point), interference from periodic environmental fluctuations can be eliminated, allowing the collected voltage values ​​to more accurately reflect the long-term aging trend of the crystal oscillator rather than instantaneous environmental disturbances.

[0092] In practice, the controller 110 acquires an orbital period timing signal (e.g., one pulse per orbit) from the onboard timing system or navigation receiver. Whenever this timing signal arrives, the controller 110 triggers the voltage detector 126 to start a sampling cycle. The length of the sampling cycle is not equal to the entire orbital cycle, but rather refers to the interval between two sampling actions being equal to one orbital cycle; each sampling action itself lasts only a very short time (e.g., tens of milliseconds), during which multi-point acquisition and averaging calculations are completed.

[0093] For example, a low-Earth orbit satellite has an orbital period of 100 minutes. The satellite platform generates a hardware interrupt signal at the ascending node (the point where the satellite enters the Northern Hemisphere from the Southern Hemisphere) of each orbital period. Upon receiving this interrupt, the controller 110 immediately activates the voltage detector 126 to sample the signal. This means that the system only samples the second control signal once every 100 minutes (one orbit around the Earth), rather than once per second or minute.

[0094] In each sampling period (i.e., each orbital period), the voltage detector 126 does not collect data from just one point, but rather continuously collects multiple data points. This is done to overcome transient noise common in spaceborne environments, such as brief voltage spikes caused by single-event effects, power supply ripple, or electromagnetic interference. Single-point sampling is easily misled by these outliers, while multi-point averaging effectively filters out random noise and outliers.

[0095] Within each sampling period, the voltage detector 126 continuously performs N analog-to-digital conversions at a fixed sampling interval (e.g., 1 millisecond), where N is typically an integer between 8 and 16. For example, if N is 10, 10 sample data points can be collected. These 10 sample data points can then be averaged to obtain the average value, which is stored as the sample value for that sampling period.

[0096] To further suppress abnormal spikes, the maximum and minimum values ​​of the 10 raw data points can be removed first, and then the average of the remaining 8 data points can be calculated. This processing can be accomplished by simple logic within the voltage detector 126, or by the controller 110 through software after reading the raw data.

[0097] The controller 110 stores the average voltage value collected in each orbit cycle into a memory, forming a historical data sequence. When the continuous clock reference signal (10MHz) fails, the controller 110 immediately reads the latest (i.e., the previous orbit cycle) stored average voltage value and outputs this value through the DAC to achieve seamless switching. When both reference sources fail, the controller 110 reads the historical average value sequence of the most recent orbit cycles, predicts the future voltage change trend through function fitting, and outputs the control voltage in open loop according to this trend.

[0098] In the above implementation process, by synchronizing the sampling period of the voltage detector 126 with the satellite orbit period and adopting a multi-point acquisition and averaging method in each sampling period, the anti-interference ability and long-term consistency of the acquired data are significantly improved, providing a highly reliable data foundation for seamless switching and aging simulation.

[0099] Based on the above embodiments, the system 100 may further include a voltage output device 140, which is coupled between the controller 110 and the adjustable frequency device 130, and is used to perform digital-to-analog conversion on the first control signal.

[0100] When generating the first control signal, the controller 110 compares the pulsed clock reference signal with the feedback signal of the adjustable frequency converter 130 at the edge and adjusts the output voltage according to the comparison result to generate the first control signal.

[0101] Voltage output unit 140 is a circuit that converts digital control signals into analog voltages, typically a DAC. Its input side receives digital code values ​​from controller 110, and its output side generates an analog voltage proportional to these values. This analog voltage is used to adjust the output frequency of adjustable frequency unit 130. The DAC's resolution (e.g., 12-bit, 16-bit) and output range (e.g., 0–3.3V) must be matched to the voltage-controlled sensitivity of adjustable frequency unit 130.

[0102] A voltage output unit 140 (DAC) is coupled between the controller 110 and the adjustable frequency unit 130. Specifically, the digital output port (such as SPI or parallel bus) of the controller 110 is connected to the input interface of the DAC, and the analog output of the DAC is connected to the control terminal of the adjustable frequency unit 130. When the system switches to a standby disciplined path, the controller 110 connects the output of the DAC to the adjustable frequency unit 130.

[0103] Meanwhile, the pulsed clock reference signal provider (such as 1PPS output from a GNSS receiver) is directly connected to an input pin of controller 110 with rising edge interrupt functionality. The output clock of adjustable frequency unit 130 (e.g., 100MHz) is first passed through a programmable divider (the division ratio can be set to 100,000,000) to obtain a 1Hz square wave signal, which is also fed back to another input capture pin of controller 110. Controller 110 is internally configured with a high-precision timer (resolution up to 1 nanosecond) to record the arrival times of the two rising edges.

[0104] Controller 110 can perform edge-compare operations once per second. At the rising edge of each 1PPS pulse, the input capture hardware of controller 110 latches the current timer count, denoted as T_pps. Immediately afterwards, controller 110 waits for the next rising edge of the feedback signal (a 1Hz square wave after frequency division) and latches its timing, denoted as T_fb. Since both signals are pulses per second, but their phases may differ, controller 110 calculates the time difference Δt = T_fb - T_pps. If the rising edge of the feedback signal leads 1PPS, Δt is positive; if it lags, Δt is negative (or the absolute deviation is obtained through modulo operation). This time difference reflects the cumulative phase error of the adjustable frequency converter 130's output frequency relative to the 1PPS reference: when the output frequency is accurate, Δt should stabilize at a fixed value (typically 0 or half a cycle); when the frequency is too high, Δt will gradually increase (or decrease, depending on the defined direction).

[0105] Based on the time difference Δt obtained from each measurement, controller 110 operates a digital proportional-integral (PI) controller to gradually adjust the output code value of the DAC, thereby changing the analog voltage applied to the adjustable frequency converter 130. The input of the PI controller is the error e = Δt (in nanoseconds), and the output is the correction amount for the DAC code value.

[0106] After the controller 110 calculates the new DAC code value, it writes it to the voltage output unit 140 (DAC) through the communication interface. The DAC converts it into an analog voltage, which is the first control signal (in analog form). After multiple iterations (usually taking tens to hundreds of seconds), the error e converges to near zero. At this point, the first control signal stabilizes at a fixed voltage value, and the output frequency of the adjustable frequency unit 130 is precisely synchronized to 1PPS.

[0107] When the system switches from a hold state after the failure of the continuous clock reference signal to a backup disciplined path, controller 110 needs to connect the first control signal (already stabilized) of the DAC output to the adjustable frequency converter 130. Before this, controller 110 first allows the DAC to output an initial voltage, which is the latest sampled value read from memory (i.e., the voltage output by the continuous clock reference circuit 120 before the failure). Then, controller 110 initiates a 1PPS-based edge comparison and PI regulation process, gradually adjusting the DAC voltage from this initial value until convergence. Since the initial value is already very close to the final steady-state value (because the crystal oscillator control voltage indicated by the two reference sources should theoretically be consistent), the frequency change during the regulation process is very smooth and will not cause significant jumps in the output clock. Once the PI controller determines that the error is less than a threshold (e.g., ±2ns), controller 110 considers the disciplined process stable and maintains the DAC output as the final control source.

[0108] In the above implementation process, slow and high-precision discipline based on 1PPS pulse signal is achieved through edge comparison and digital PI adjustment in voltage output unit 140 (DAC) and controller 110. It can provide a reliable backup discipline path after continuous clock reference failure, and ensure the long-term frequency accuracy of the output clock.

[0109] Based on the above embodiments, the system 100 may further include a switch 150, which is coupled to the controller 110, the continuous clock reference circuit 120, and the adjustable frequency converter 130. The switch 150 is used to switch the source of the control signal at the control terminal of the adjustable frequency converter 130.

[0110] The switch 150 is a multiplexer composed of electronic switches, typically implemented using analog switches (such as CMOS (Complementary Metal-Oxide-Semiconductor) transmission gates) or relays. In this system, the switch 150 has two inputs and one output. The two inputs are connected to: the second control signal (analog voltage) output from the continuous clock reference circuit 120, and the output voltage of the voltage output unit 140 (including the holding voltage reconstructed from the memory by the DAC and the first control signal generated by the voltage output unit 140 (DAC). Alternatively, there could be two inputs, one connected to the DAC and the other to the memory). The output is connected to the control terminal of the adjustable frequency unit 130. The switch 150 is controlled by the digital output pin of the controller 110 and can connect any input to the output according to instructions.

[0111] The source of the control signal can refer to the source of the voltage signal applied to the control terminal of the adjustable frequency converter 130. In this system, the control signal of the adjustable frequency converter 130 can come from three different paths: the main discipline path (continuous clock reference circuit 120), the hold path (sampled values ​​stored directly from the DAC output), and the backup discipline path (DAC output generated based on 1PPS).

[0112] The core component of the switch 150 can be a single-pole triple-throw (SP3T) analog switch or a combination of two single-pole double-throw (SPDT) switches. For example, three independent CMOS analog switches with low on-resistance, low leakage current, and break-before-make characteristics can be used to avoid a brief short circuit between the two signal sources during switching.

[0113] The specific link is as follows: First input terminal (IN1): Connected to the output terminal of filter 124 in continuous clock reference circuit 120 (i.e., the second control signal).

[0114] Second input (IN2): Connects to the output of voltage output unit 140 (DAC). This DAC outputs a holding voltage read from memory when the continuous clock fails.

[0115] The third input (IN3): Also connected to the output of voltage output unit 140 (DAC). Note that the second and third inputs actually come from the same DAC, but logically represent two different output values. For physical differentiation, two independent DACs can be used, or a single DAC can be used but output through different time slices. For simplicity, this implementation uses two independent DACs: DAC_A is used to output the holding voltage, and DAC_B is used to output the first control signal based on 1PPS discipline. IN2 of switch 150 is connected to DAC_A, and IN3 is connected to DAC_B.

[0116] Output (OUT): The control voltage input pin connected to the adjustable frequency unit 130 (voltage-controlled crystal oscillator).

[0117] Controller 110 controls switch 150 via two general-purpose input / output (GPIO) pins (or a 2-bit binary code). For example, code 00 selects IN1 (primary path), 01 selects IN2 (hold path), and 10 selects IN3 (alternate disciplined path). Switch 150 has internal level shifting and drive circuitry to ensure rapid switching action in response to changes in control signals.

[0118] The controller 110 dynamically switches the control signal source of the adjustable frequency converter 130 according to the system's operating status. The entire process is divided into the following three main states: (1) Normal state (continuous clock reference signal present): Controller 110 outputs code 00, and switch 150 connects IN1 (output of continuous clock reference circuit 120) to adjustable frequency converter 130. At this time, adjustable frequency converter 130 is under closed-loop control of phase-locked loop and outputs a low phase noise clock. At the same time, controller 110 periodically samples the second control signal through voltage detector 126 and stores the average value of the samples in memory. Although DAC_A and DAC_B are not output to the crystal oscillator, they can be preloaded with historical values ​​or kept static.

[0119] (2) Hold state during continuous clock failure: When controller 110 detects the loss of the 10MHz signal, it immediately outputs code 01, and switch 150 disconnects IN1 and connects IN2 (output of DAC_A). Under the instruction of controller 110, DAC_A outputs the latest stored voltage value. Since the output voltage of DAC_A is almost the same as the output voltage of the continuous clock reference circuit 120 before the failure, the control voltage of the adjustable frequency converter 130 does not change abruptly, realizing seamless switching. At this time, the adjustable frequency converter 130 is in open-loop hold state, and the output frequency remains unchanged.

[0120] (3) Switching after standby discipline stabilization: During the hold-state, controller 110 initiates a 1PPS-based discipline process: by edge comparison and PI adjustment, the output voltage of DAC_B (first control signal) is gradually adjusted. After convergence of tens to hundreds of seconds, the output voltage of DAC_B stabilizes at a value that allows the adjustable frequency converter 130 to be precisely synchronized with the 1PPS value. After the controller 110 detects that the error is less than the threshold, it outputs code 10, and switcher 150 disconnects IN2 and connects IN3 (output of DAC_B). Since the output of DAC_B is already very close to the output of DAC_A (theoretically, they should be consistent because they both reflect the correct crystal oscillator control voltage), this switch will not cause a significant frequency jump. At this point, the system has completely switched to the 1PPS-based standby discipline path.

[0121] In some implementations, to ensure the reliability of the switch 150, a disconnect-before-close mechanism can be configured. For example, the internal design of an analog switch ensures that during switching, the currently connected path is disconnected first, and then the target path is closed, with a very short idle time in between. During this period, the control terminal of the adjustable frequency converter 130 is in a high-impedance state, but since the crystal oscillator control terminal usually has a capacitor to ground, the charge on the capacitor can maintain a constant voltage, so the output frequency will not be disturbed.

[0122] For spaceborne applications, the switch 150 should be a radiation-hardened analog switch, or current-limiting resistors and clamping diodes should be added to the input and output terminals of a regular switch to prevent single-event transients from causing switch malfunctions.

[0123] In some implementations, controller 110 may also have a default state: when controller 110 itself is reset or fails, switch 150 should fix the output to continuous clock reference circuit 120 (main path) through hardware pull-down resistors to ensure that the system has at least one default clock source.

[0124] In this method, the switch 150 works closely with the voltage detector 126, the memory, and the voltage output device 140: the voltage detector 126 is responsible for collecting the control voltage of the main path, the memory stores the voltage, the voltage output device 140 (DAC) is responsible for preparing the holding voltage or the backup discipline voltage before switching, and the switch 150 is responsible for completing the connection at the correct time.

[0125] In the above implementation process, a switch 150 controlled by the controller 110 enables flexible and seamless switching between the primary discipline path, the hold path, and the backup discipline path, providing a hardware foundation for seamless redundancy of the spaceborne multi-input clock discipline system.

[0126] Based on the above embodiments, the system 100 may further include an LDO regulator 160 coupled to the controller 110 for providing operating voltage to the logic chip, which is used to distribute the output clock signal of the adjustable frequency converter 130 into multiple clock outputs.

[0127] The LDO regulator 160 refers to a low dropout regulator, a power management chip that provides a stable DC voltage when the input voltage is slightly higher than the output voltage. Compared to switching power supplies, LDOs have advantages such as low output ripple, low electromagnetic interference, and simple circuitry, making them suitable for powering noise-sensitive clock distribution logic chips. In this embodiment, the LDO also features enable control and output voltage regulation functions, allowing the controller 110 to dynamically adjust its output voltage via a digital interface.

[0128] A logic chip is a digital integrated circuit used for clock distribution, buffering, and driving, such as a clock fan-out buffer or a zero-delay buffer. This chip receives one input clock (e.g., 100MHz from an adjustable frequency converter 130) and, through an internal multiplexer driver, generates multiple clock signals of the same frequency, in phase, or configurable phase, which are then sent to the onboard communication unit, ranging unit, data processing unit, etc. Logic chips typically operate at 1.8V, 2.5V, or 3.3V and require a stable, low-noise power supply.

[0129] The input of LDO regulator 160 can be connected to an onboard primary power supply (e.g., +5V or +3.3V bus), and the output is directly connected to the power supply pin (VDD) of the logic chip. The LDO's ground pin is connected to ground. The LDO's enable pin (EN) is connected to a GPIO pin of controller 110: a high level enables the LDO output, and a low level disables the output. For LDOs with adjustable output voltage, a portion of its feedback voltage divider network can be adjusted by controller 110 via a digital potentiometer or DAC, or, by selecting a digital LDO with an I2C interface, controller 110 can directly write the set voltage value into the register.

[0130] The clock input pin of the logic chip is connected to the output of the adjustable frequency converter 130. The multiple output pins of the logic chip (e.g., 4, 8, or 12) are connected to the clock input ports of various onboard functional modules. The enable pin of the logic chip can also be controlled by the controller 110 to cut off certain outputs when needed to save power.

[0131] In some implementations, the controller 110 not only controls the switching of the LDO, but also dynamically adjusts the LDO's output voltage according to system power consumption requirements or the operating state of the clock distribution logic chip. For example, when certain clock output channels are turned off, the current required by the logic chip decreases, and the controller 110 can instruct the LDO to reduce its output voltage (e.g., from 3.3V to 2.5V) to save onboard power. For digital LDOs with I2C interfaces, the controller 110 sends the setpoint via the bus; for analog LDOs, the controller 110 outputs a reference voltage to the LDO's feedback node via a DAC to achieve voltage regulation.

[0132] In addition, the controller 110 monitors the output voltage and temperature of the LDO (via the ADC integrated within the LDO or an external sensor). If an abnormal drop in output voltage or overheating is detected, the controller 110 can quickly shut down the LDO and switch to a backup power path, or restart the discipline process to prevent the logic chip from outputting an incorrect clock edge due to power supply abnormalities.

[0133] After receiving a single clock signal from the adjustable frequency converter 130, the logic chip first performs shaping and level conversion (e.g., converting a sine wave to a square wave) through an internal input buffer. Then, the signal is fed into a clock distribution network, typically composed of multiple inverters or differential buffers, to drive multiple output channels. The delays of all output channels are designed to be essentially the same to ensure minimal phase difference between clock signals. For applications requiring strict in-phase operation, the logic chip can also provide a zero-delay buffer function, compensating for the device's own propagation delay through a feedback loop.

[0134] In the event of a continuous clock reference signal failure or a dual-source failure, the output clock frequency of the adjustable frequency converter 130 may experience a slight drift. However, as long as the controller 110 maintains the crystal oscillator control voltage through hold or deduction, the output clock will still maintain high accuracy. At this time, the stable voltage provided by the LDO to the logic chip ensures that the clock distribution path does not introduce additional jitter or bit errors. Even if the system is in a predictive hold mode due to a dual-source failure, the logic chip can still reliably distribute the clock output from the adjustable frequency converter 130 to each load until the reference signal is restored.

[0135] In the above implementation process, by adding an adjustable LDO regulator 160 to the controller 110, a manageable power supply is provided for the logic chip, and the logic chip expands the single high-precision clock into a multi-channel synchronous output, which meets the distributed clock requirements of the complex onboard electronic system, while enhancing the power management flexibility and reliability of the system.

[0136] Based on the same inventive concept described above, please refer to Figure 3 , Figure 3 A flowchart of a spaceborne multi-input clock discipline method provided in this application embodiment, the method being applied to the controller of the above-mentioned system, includes the following steps: Step S210: Detect whether the continuous clock reference signal exists at the continuous clock reference signal provider.

[0137] Step S220: If present, control the adjustable frequency converter to output under the control of the second control signal, sample the second control signal, and store the sampled value in the memory.

[0138] Step S230: If it does not exist, read the latest stored sample value from the memory and apply the sample value as a control signal to the adjustable frequency converter to maintain its output.

[0139] Step S240: Initiate the discipline process of generating the first control signal based on the pulsed clock reference signal; Step S250: After confirming that the taming process is stable, switch the control signal of the adjustable frequency device to the first control signal.

[0140] The detailed implementation process of this method can be found in the relevant descriptions in the foregoing embodiments. For the sake of brevity, it will not be elaborated further here.

[0141] Understandably, the two steps described above—reading the latest stored sample value from the memory and initiating the discipline process to generate the first control signal when it is determined that the continuous clock reference signal does not exist—can theoretically be executed simultaneously, or they can be executed sequentially, without any special limitation here.

[0142] In this scheme, the controller continuously monitors the presence of a continuous clock reference signal (e.g., 10MHz), employing a dual judgment strategy of level and period to ensure rapid and accurate identification of signal failure. When the signal is present, the controller transfers control of the adjustable frequency converter (voltage-controlled crystal oscillator) to the second control signal generated by the continuous clock reference circuit, and simultaneously initiates periodic sampling: within each track cycle, the voltage values ​​of multiple second control signals are continuously collected by a voltage detector, averaged, and stored in memory. This process pre-reserves a historical voltage reference for subsequent seamless switching. Once a failure of the continuous clock reference signal is detected, the controller immediately reads the latest saved sample value from memory and applies this voltage directly to the control terminal of the adjustable frequency converter through a voltage output unit (DAC). Since this voltage value is almost identical to the actual control voltage at the instant before the failure, a seamless hold of the output clock is achieved. Simultaneously, the controller initiates a backup discipline process based on a pulsed clock reference signal (1PPS): by measuring the time difference between 1PPS and the adjustable frequency converter feedback signal through edge comparison, a PI algorithm is run to gradually adjust the DAC output voltage, generating the first control signal. After the taming process converges and stabilizes (error is less than the preset threshold), the controller smoothly switches the control source of the adjustable frequency converter to the first control signal, completing the transition from the primary path to the backup path.

[0143] Throughout the process, the controller, through unified scheduling logic and hardware interfaces (ADC, DAC, switching, and storage access), achieved seamless connection and intelligent maintenance of dual redundant reference sources, ensuring high reliability and high precision output of the onboard clock system in the event of single-source failure or even dual-source failure.

[0144] This application provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it performs the method process executed by the electronic device in the above method embodiments.

[0145] This embodiment discloses a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can perform the methods provided in the above-described method embodiments, such as including: Detect the presence of a continuous clock reference signal at the continuous clock reference signal provider. If present, the adjustable frequency converter is controlled to output according to the second control signal, and the second control signal is sampled and the sampled value is stored in the memory. If it does not exist, the latest stored sample value is read from the memory and applied as a control signal to the adjustable frequency converter to maintain its output; Initiate the discipline process by generating a first control signal based on the pulsed clock reference signal; After confirming that the taming process is stable, the control signal of the adjustable frequency device is switched to the first control signal.

[0146] In summary, this application provides a spaceborne multi-input clock discipline system, method, and program product. This system uses a controller to detect the presence of a continuous clock reference signal in real time. When the signal is normal, it not only uses its high precision to discipline the adjustable frequency converter but also samples and stores the second control signal in this state. Once the continuous clock reference fails, the stored value is immediately recalled to maintain the control voltage of the adjustable frequency converter, avoiding frequency jumps and phase abrupt changes during phase-locked loop (PLL) lockout or relocking processes, thus achieving seamless maintenance of the output clock. Simultaneously, the system automatically initiates a backup discipline process based on a pulsed clock reference signal, and smoothly switches the control source after it stabilizes, ensuring long-term frequency accuracy.

[0147] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0148] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0149] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0150] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0151] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A spaceborne multi-input clock discipline system, characterized in that, include: A controller is coupled to a continuous clock reference signal provider and a pulsed clock reference signal provider, respectively. The controller is used to generate a first control signal based on the pulsed clock reference signal input to the pulsed clock reference signal provider. A continuous clock reference circuit is used to generate a second control signal based on the continuous clock reference signal input at the continuous clock reference signal provider terminal; An adjustable frequency converter is coupled to the continuous clock reference circuit and the controller, respectively, and is used to generate an output clock signal according to the applied control signal; The controller is configured to: Detect the presence of the continuous clock reference signal; If present, the adjustable frequency converter is controlled to output according to the second control signal, and the second control signal is sampled and the sampled value is stored in the memory. If it does not exist, the latest stored sample value is read from the memory and applied as a control signal to the adjustable frequency converter to maintain its output; And initiate a discipline process to generate a first control signal based on the pulsed clock reference signal. After determining that the discipline process is stable, switch the control signal of the adjustable frequency unit to the first control signal.

2. The system according to claim 1, characterized in that, The controller is further configured to: record the control signals of the adjustable frequency converter at different times to form a historical data sequence; when it is detected that neither the continuous clock reference signal nor the pulse clock reference signal exists, predict the signal change trend of the control signal according to the historical data sequence, and output the control signal to the adjustable frequency converter according to the signal change trend.

3. The system according to claim 1, characterized in that, The continuous clock reference circuit includes a phase comparator coupled to the adjustable frequency converter. The phase comparator is used to compare the phase of the continuous clock reference signal with the feedback signal of the adjustable frequency converter and then output a second control signal.

4. The system according to claim 3, characterized in that, The continuous clock reference circuit further includes a filter, which is coupled to the phase comparator. The output of the filter is coupled to the control terminal of the adjustable frequency unit, and is used to filter the second control signal output by the phase comparator before outputting it.

5. The system according to claim 4, characterized in that, The continuous clock reference circuit also includes a voltage detector coupled to the output of the filter, used to acquire the second control signal output by the filter and output it to the controller.

6. The system according to claim 5, characterized in that, The voltage detector is specifically used to periodically sample the second control signal, and then average the multiple sampled data collected in each sampling period and send them to the controller.

7. The system according to claim 6, characterized in that, The sampling period is determined based on the satellite's orbital period.

8. The system according to claim 1, characterized in that, The system also includes a voltage output device coupled between the controller and the adjustable frequency converter, the voltage output device being used to perform digital-to-analog conversion on the first control signal.

9. The system according to claim 1, characterized in that, The system also includes a switcher coupled to the controller, the continuous clock reference circuit, and the adjustable frequency converter. The switcher is used to switch the control signal source of the control terminal of the adjustable frequency converter.

10. The system according to claim 1, characterized in that, The system also includes an LDO regulator coupled to the controller for providing operating voltage to the logic chip, which distributes the output clock signal of the adjustable frequency converter into multiple clock outputs.

11. A method for disciplining a spaceborne multi-input clock, characterized in that, The method, applied to a controller in any one of the systems described in claims 1-10, comprises: Detect the presence of a continuous clock reference signal at the continuous clock reference signal provider. If present, the adjustable frequency converter is controlled to output according to the second control signal, and the second control signal is sampled and the sampled value is stored in the memory. If it does not exist, the latest stored sample value is read from the memory and applied as a control signal to the adjustable frequency converter to maintain its output; Initiate the discipline process by generating a first control signal based on the pulsed clock reference signal; After confirming that the taming process is stable, the control signal of the adjustable frequency device is switched to the first control signal.

12. A computer program product, characterized in that, It includes computer program instructions, which are read and executed by a processor to perform the method as described in claim 11.

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