Analog-to-digital converter and method for increasing its dynamic range

Abstract

An analog-to-digital converter (ADC) includes: an integrator configured to provide an analog output signal; a quantizer configured to generate and provide a digital output signal based on the analog output signal from the integrator; a detection module configured to detect a saturation state of the analog output signal from the integrator; a determination module configured to determine a loss value of the analog output signal and generate and provide a loss quantization signal; and a processing module configured to, in response to the occurrence of saturation in the analog output signal, perform compensation processing on the digital output signal from the quantizer based on the loss quantization signal from the determination module. This disclosure improves the dynamic range of the analog-to-digital converter without significantly increasing cost and power consumption by calculating the loss quantization value and performing compensation processing when the sampled value of the analog-to-digital converter becomes saturated.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuits, and more specifically, to an analog-to-digital converter and a method for improving the dynamic range of the same. Background Technology

[0002] An analog-to-digital converter (ADC) is a device used to convert analog signals into digital signals. Sigma-Delta ADCs are high-precision analog-to-digital converters based on oversampling and noise shaping techniques, widely used in mobile cellular networks (such as 4G, 5G, and 6G) ​​and broadband wireless communications (such as Wi-Fi). In broadband mobile communication systems, signal bandwidth continuously increases, and the modulation techniques used (such as OFDM) typically have high peak-to-average power ratios (PAPR). Furthermore, the complex wireless communication environment introduces strong adjacent-channel interference and blocking signals. Traditional Sigma-Delta ADCs are prone to internal node saturation and clipping when processing such high PAPR, wideband signals; for example, the integrator output is particularly susceptible to saturation.

[0003] In existing technologies, methods such as increasing the oversampling rate (OSR) or using multi-bit quantizers instead of single-bit quantizers are commonly used to improve the dynamic range of Sigma-Delta ADCs, but these methods lead to a significant increase in system power consumption or hardware cost. While dither injection can improve nonlinear distortion under small signals, its improvement effect on hardware saturation and limiting problems caused directly by large-amplitude signals is limited. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this disclosure is to provide an analog-to-digital converter and a method for improving the dynamic range of the same, for improving the dynamic range of a Sigma-Delta ADC without significantly increasing cost and power consumption.

[0005] According to one aspect of this disclosure, an analog-to-digital converter is provided, comprising: an integrator configured to provide an analog output signal; a quantizer configured to generate and provide a digital output signal based on the analog output signal from the integrator; a detection module configured to detect a saturation state of the analog output signal from the integrator, and generate and provide a saturation state signal indicating whether the analog output signal is saturated; a determination module configured to determine a loss value of the analog output signal in response to the saturation state signal from the detection module indicating that the analog output signal is saturated, and generate and provide a loss quantization signal indicating the loss value of the analog output signal; and a processing module configured to perform compensation processing on the digital output signal from the quantizer based on the loss quantization signal from the determination module in response to the saturation state signal from the detection module indicating that the analog output signal is saturated.

[0006] Optionally, the analog-to-digital converter further includes a digital decimation filter configured to downsample and filter the digital output signal from the quantizer, and provide the downsampled and filtered digital output signal to the processing module.

[0007] Optionally, the analog-to-digital converter further includes a group delay compensation module, which is configured to perform group delay compensation on the saturation state signal from the detection module and the loss quantization signal from the determination module, and provide the group delay compensated signal to the processing module.

[0008] Optionally, the analog-to-digital converter further includes a digital decimation filter configured to downsample and filter the compensated signal from the processing module.

[0009] Optionally, the loss quantization signal includes a static loss, the determining module includes a static calculation module and a storage module, the storage module is configured to store a loss mapping table, and the static calculation module is configured to determine the static loss of the analog output signal based on the loss mapping table from the analog output signal from the integrator.

[0010] Optionally, the loss quantization signal includes dynamic loss, the determining module includes a dynamic calculation module and an acquisition module, the acquisition module is configured to acquire real-time parameters that change dynamically in the operating environment of the analog-to-digital converter, and the dynamic calculation module is configured to determine the dynamic loss of the analog output signal based on the analog output signal from the integrator and the real-time parameters.

[0011] Optionally, the loss quantization signal includes static loss and dynamic loss. The determination module includes a hybrid determination module, a storage module, and an acquisition module. The storage module is configured to store a loss mapping table. The acquisition module is configured to acquire dynamically changing real-time parameters in the operating environment of the analog-to-digital converter. The hybrid determination module is configured to determine the static loss of the analog output signal based on the loss mapping table from the analog output signal from the integrator, and to determine the dynamic loss of the analog output signal based on the analog output signal from the integrator and the real-time parameters. The loss quantization signal is then determined based on the static loss and the dynamic loss.

[0012] According to another aspect of this disclosure, a method for improving the dynamic range of an analog-to-digital converter is provided, the analog-to-digital converter including an integrator and a quantizer, the method comprising: detecting a saturation state of an analog output signal of the integrator and generating a saturation state signal indicating whether the analog output signal is saturated; in response to the saturation state signal indicating that the analog output signal is saturated, determining a loss value of the analog output signal and generating a loss quantization signal indicating the loss value of the analog output signal; and performing compensation processing on the digital output signal of the quantizer according to the loss quantization signal.

[0013] Optionally, the method further includes: downsampling and filtering the digital output signal of the quantizer, wherein the compensation processing step includes: performing compensation processing on the downsampled and filtered digital output signal based on the loss quantization signal.

[0014] Optionally, it further includes: performing group delay compensation on the saturation state signal and the loss quantization signal, wherein the compensation processing step includes: performing compensation processing on the downsampled and filtered digital output signal based on the loss quantization signal after group delay compensation.

[0015] Optionally, it also includes downsampling and filtering the compensated digital output signal.

[0016] Optionally, the loss quantization signal includes static loss, and the determination step includes: determining the static loss based on the analog output signal of the integrator and according to a pre-stored loss quantization table.

[0017] Optionally, the loss quantization signal includes dynamic loss, and the determination step includes: determining the dynamic loss based on the analog output signal of the integrator and real-time parameters obtained from the operating environment of the analog-to-digital converter.

[0018] Optionally, the loss quantization signal includes static loss and dynamic loss, and the determination step includes: determining the static loss based on the analog output signal of the integrator by querying a pre-stored loss quantization table; determining the dynamic loss based on the analog output signal of the integrator and real-time parameters obtained from the operating environment of the analog-to-digital converter; and determining the loss quantization signal based on the static loss and the dynamic loss.

[0019] As described above, this disclosure improves the dynamic range of the analog-to-digital converter without significantly increasing cost and power consumption by calculating the loss quantization value when the sampled value of the analog-to-digital converter reaches saturation and by performing compensation processing on the sampled signal. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments of this disclosure or the prior art will be briefly introduced below. It should be understood that these drawings only depict several embodiments of this disclosure and should not be considered as limiting the scope of this disclosure.

[0021] Figure 1 The diagram illustrates the working principle of a traditional Sigma-Delta analog-to-digital converter.

[0022] Figure 2 A logic block diagram of an analog-to-digital converter 100 according to an embodiment of the present disclosure is shown.

[0023] Figure 3 A flowchart illustrating a method for constructing a loss mapping table according to an embodiment of the present disclosure is shown.

[0024] Figure 4 A flowchart is shown of a method for real-time calculation of signal loss values ​​according to an embodiment of the present disclosure.

[0025] Figure 5 A flowchart is shown of a method for loss calculation based on a hybrid mode of two implementations, namely querying a pre-stored loss mapping table and real-time calculation, according to an embodiment of the present disclosure.

[0026] Figure 6 A schematic diagram illustrating the working principle of an analog-to-digital converter 100 performing compensation processing in the high sampling rate domain according to an embodiment of the present disclosure is shown.

[0027] Figure 7 A schematic diagram illustrating the working principle of an analog-to-digital converter 100 performing compensation processing in the low sampling rate domain according to an embodiment of the present disclosure is shown.

[0028] Figure 8A flowchart of a method for improving the dynamic range of an analog-to-digital converter according to another embodiment of the present disclosure is shown. Detailed Implementation

[0029] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0030] To facilitate the description of the analog-to-digital converter disclosed herein, a conventional Sigma-Delta type analog-to-digital converter will first be introduced.

[0031] Figure 1 The diagram illustrates the working principle of a traditional Sigma-Delta analog-to-digital converter. A traditional Sigma-Delta analog-to-digital converter (hereinafter referred to as Sigma-Delta ADC) typically includes an amplifier, a modulator, and a digital decimation filter. (Reference) Figure 1 As shown, the amplifier can be a programmable gain amplifier used to amplify the analog input signal V_in, and its gain can be dynamically adjusted to adapt to input signals of different amplitudes. In some possible embodiments, the amplifier can also be a fixed gain amplifier, operational amplifier, or other devices with signal amplification functions.

[0032] The modulator is the core module of a Sigma-Delta ADC, composed of "Sigma" (summation / integration) and "Delta" (difference) units, and typically includes an integrator, quantizer, and feedback loop. (Reference) Figure 1 As shown, the error summer can be used to calculate the difference V_err between the analog input signal V_in and the feedback signal V_fb. This difference V_err is accumulated by the integrator, converting the "instantaneous error" into a "cumulative error" to achieve time-domain expansion of the signal energy. In a Sigma-Delta ADC, both the amplifier and the integrator are analog devices with finite linear input / output ranges. When the difference between the analog input signal V_in and the feedback signal V_fb is too large, the integrator output will exceed its linear operating range (i.e., the saturation region), causing the modulator to lose its normal noise shaping capability, and the integrator output will be "limited" to near its maximum value.

[0033] The analog output signal of the integrator is quantized into a digital signal by a quantizer. The digital output signal of the quantizer is then fed back to the error summer at the input via a digital-to-analog converter, forming a closed-loop negative feedback. (Reference) Figure 1 As shown, the quantizer can be a 1-bit comparator, the digital output signal is the bit stream, and the digital-to-analog converter is the feedback DAC. Specifically, a 1-bit comparator corresponds to a 1-bit feedback DAC, and the 1-bit feedback DAC has only two levels. Its linearity is determined by the absolute value accuracy of the two levels, not by the matching accuracy between components. Using a 1-bit comparator eliminates mismatch error and results in extremely low harmonic distortion, thus achieving very high linearity. However, using… Figure 1 In the illustrated embodiment, when the 1-bit comparator is used as a quantizer, the integrator must generate a large output swing to "carry" the error information in order to accurately represent an analog signal using two levels. When the input signal V_in has a large amplitude, the amplitude of the integrator's analog output signal becomes very large, making it very easy to enter the saturation region, resulting in noise shaping failure and severe distortion.

[0034] In some possible embodiments, the quantizer can also be a multi-bit quantizer. When using a multi-bit quantizer, although increasing the number of quantization levels can significantly reduce the swing of the analog output signal of the integrator, and at the same oversampling rate, a multi-bit quantizer can provide higher stability margin and a larger dynamic range; however, a multi-bit quantizer corresponds to a multi-bit feedback DAC, its circuit structure is more complex, the overall analog circuit design is more difficult, and power consumption and chip area will also increase significantly.

[0035] The closed-loop structure of a modulator can push low-frequency quantization noise to higher frequencies; that is, the noise power spectrum is suppressed in the low-frequency range and enhanced in the high-frequency range. This process is called noise shaping. The higher the order of the modulator, the stronger its ability to push low-frequency quantization noise to higher frequencies. To achieve this powerful noise shaping capability, the modulator must perform high-gain integration and feedback of the quantization error. This results in the quantization error becoming highly structured and exhibiting complex correlations with the input signal. When the input signal to the quantizer is correlated and has a small amplitude, the nonlinear characteristics of the quantizer interact with this correlated error, producing deterministic, non-random distortion.

[0036] To further address the issue of ADC signal distortion under small signal conditions, dithering injection techniques are often introduced in Sigma-Delta ADCs. (Reference) Figure 1As shown, dithering injection injects a low-amplitude random noise signal into the quantizer input via a noise source. Specifically, this could be Gaussian white noise or a pseudo-random sequence. This low-amplitude random noise signal can disrupt the periodicity of the quantizer, converting deterministic distortion into random noise, thereby improving nonlinear distortion under small signals. However, its improvement effect is limited for hardware saturation and limiting problems directly caused by large-amplitude signals.

[0037] Digital decimation filters can be used to process high-sampling-rate digital signals from modulator outputs that contain high-frequency noise. (Reference) Figure 1 As shown, the digital decimation filter is a digital filter bank, which may include a CIC (Cascaded Integrator-Comb) filter and an anti-aliasing FIR (Finite Impulse Response) filter. The CIC filter is mainly used for downsampling, reducing the high-sampling-rate digital signal to the Nyquist sampling rate, thus reducing the amount of data for subsequent processing. The anti-aliasing FIR filter is mainly used for low-pass filtering to remove high-frequency quantization noise from the signal while retaining useful information within the signal bandwidth.

[0038] Sampling frequency of Sigma-Delta ADC Much higher than the Nyquist frequency, it mainly reduces the quantization noise power per unit bandwidth by increasing the number of sampling points. In existing technologies, improving the dynamic range of a Sigma-Delta ADC mainly relies on increasing its oversampling rate, which can be expressed by the following formula (1):

[0039] (1)

[0040] in, This indicates the sampling frequency of the Sigma-Delta ADC. This represents the signal bandwidth. Therefore, to increase the oversampling rate while ensuring the signal bandwidth, it is necessary to increase the sampling rate. Increasing the sampling rate means requiring a high-frequency sampling clock several times the signal bandwidth, which leads to a significant increase in system power consumption and cost.

[0041] There is an urgent need for a solution to improve the dynamic range of analog-to-digital converters without significantly increasing cost and power consumption for existing Sigma-Delta ADCs.

[0042] Figure 2 A logic block diagram of an analog-to-digital converter 100 according to an embodiment of the present disclosure is shown. Figure 2The dashed boxes and dashed connections represent optional modules and optional connection relationships, respectively. (Reference) Figure 2 As shown, the analog-to-digital converter 100 may include an integrator 210, a quantizer 220, a digital decimation filter 230, a detection module 310, a determination module 320, and a processing module 330. The integrator 210 may contain analog circuitry, while the quantizer 220 and digital decimation filter 230 may both be implemented using digital circuitry. Specifically, for example, the integrator 210 may include an operational amplifier, the quantizer 220 may be a one-bit comparator or a multi-bit quantizer, and the digital decimation filter 230 may include a CIC decimation filter and an anti-aliasing FIR filter. The detection module 310 may be implemented using analog circuitry, for example, a one-bit comparator, while the determination module 320 and processing module 330 may both be implemented using digital circuitry.

[0043] The output signal of integrator 210 can be an analog output signal, which can be converted into a digital output signal by quantizer 220. Detection module 310 can detect whether the analog output signal of integrator 210 is saturated and generate a saturation signal. This saturation signal can serve as an input signal and enable signal for determination module 320 and processing module 330. Specifically, when the saturation signal indicates that the analog output signal of integrator 210 is not saturated, determination module 320 and processing module 330 are in a sleep state. At this time, the digital output signal of quantizer 220 is directly input to digital decimation filter 230 for downsampling and filtering to obtain the high-resolution digital output signal of the Sigma-Delta ADC. When the saturation signal indicates that the analog output signal of integrator 210 is saturated, determination module 320 and processing module 330 operate normally. At this time, the digital output signal of the quantizer 220 can first be downsampled and filtered by the digital decimation filter 230, and then input into the processing module 330 for compensation processing, finally obtaining the high-resolution digital output signal of the Sigma-Delta ADC; the digital output signal of the quantizer 220 can also be downsampled and filtered by the processing module 330, and then input into the digital decimation filter 230 for compensation processing, finally obtaining the high-resolution digital output signal of the Sigma-Delta ADC.

[0044] In some possible embodiments, the detection module 310 can be used to detect whether the analog output signal of the integrator is saturated and generate a saturation signal, which can serve as an enable signal for the determination module 320 and the processing module 330. Specifically, when the analog output signal of the integrator is saturated, the saturation signal can be high, controlling the determination module 320 and the processing module 330 to start; when the analog output signal of the integrator is not saturated, the saturation signal can be low, and the determination module 320 and the processing module 330 are in a sleep state. That is, the determination module 320 and the processing module 330 will only start when the detection module 310 detects that the analog output signal of the integrator is saturated.

[0045] The detection module 310 can be a 1-bit comparator implemented using analog circuitry, with a preset comparison threshold, such as M. The detection module 310 can detect the amplitude of the analog output signal of the integrator in real time. If the amplitude exceeds the comparison threshold M, a high-level saturation state signal is generated to indicate that the analog output signal is saturated; if the amplitude does not exceed the comparison threshold M, a low-level saturation state signal is generated to indicate that the analog output signal is not saturated. When the saturation state signal is high, it can also be used as a calculation basis for the determination module. Specifically, for example, the determination module 320 can calculate the saturation duration of the ADC by counting the levels of the saturation state signal.

[0046] In practical operation, Sigma-Delta ADCs may be affected by various factors, causing the integrator's input-output relationship to enter the nonlinear region, resulting in saturation of the analog output signal. These factors include, but are not limited to, signal distribution, bandwidth, channel conditions, and interference conditions. Among these, signal distribution and bandwidth are relatively static and stable factors. For example, the OFDM signal frequently used in 5G communication approximately follows a Rayleigh distribution or a specific distribution in amplitude, and its peak-to-average power ratio (PAPR) has a statistically characteristic range. Its signal distribution is a priori information of the system determined by the communication standard and modulation and coding scheme. Similarly, signal bandwidth, such as the carrier bandwidth of a device using the Sigma-Delta ADC disclosed herein, is also predefined by the network configuration and communication standard, with values ​​such as 20MHz or 100MHz, representing a pre-set fixed configuration. Channel conditions and interference conditions are factors that change in real time. In real-world applications of the Sigma-Delta ADC disclosed herein, factors such as user movement causing the device to move, or changes in the device's environment, can lead to drastic changes in channel characteristics within a very short timeframe, such as rapid signal fading within milliseconds. Similarly, devices using the Sigma-Delta ADC disclosed herein may also be subject to random, unpredictable, and constantly varying levels of interference, such as co-channel or adjacent-channel interference from other devices or systems.

[0047] To address the impact of the aforementioned different types of factors on the Sigma-Delta ADC, the design of the determination module 320 in this disclosure can be based on various implementation methods. For example, one implementation method involves offline simulation of the Sigma-Delta ADC based on the relatively static and stable factors mentioned above, thereby constructing a loss mapping table and pre-stored it in the ADC. Then, in actual operation, the corresponding quantization loss can be obtained by looking up the table based on the observed input parameters. Another implementation method involves receiving the real-time changing factors mentioned above, and calculating the loss value of the analog output signal in real time based on these real-time changing factors and the analog output signal of the integrator. The loss value may include the energy loss value or amplitude loss value of the analog output signal, or other forms of quantization loss. Furthermore, another implementation method can be a hybrid mode of querying the pre-stored loss mapping table and real-time calculation. That is, while constructing the loss mapping table for the relatively static and stable factors, the signal loss value is calculated in real time for the real-time changing factors, and then the final signal loss value is obtained based on the calculation results of the two implementation methods. The determination module 320 can be used to calculate the loss value of the analog output signal of the integrator and generate a loss quantization signal. The loss quantization signal can provide a quantitative basis for the compensation processing of the processing module, such as how much signal amplitude compensation is needed to restore signal accuracy.

[0048] In some possible embodiments, the loss quantization signal may include a static loss, and the determination module 320 may include a static calculation module and a storage module. The storage module may be used to store a loss mapping table. The static calculation module may, based on the analog output signal of the integrator, query the pre-stored loss mapping table to obtain the static loss of the analog output signal, and provide the static loss to the processing module 330 for subsequent compensation processing. For example, the storage module may be the ROM of the ADC chip. The loss mapping table may be used to represent a mapping relationship, such as the mapping relationship between the instantaneous overload level of the analog output signal of the integrator and the loss value of the analog output signal. Figure 3 A flowchart illustrating a method for constructing a loss mapping table according to an embodiment of the present disclosure is shown. Exemplarily, the construction of the loss mapping table can be achieved based on the following steps:

[0049] S110: Establish a system model for simulating the Sigma-Delta ADC. The system model may include a model of the nonlinear characteristics of the modulator in the Sigma-Delta ADC and a filter with a specific bandwidth.

[0050] S120: Inject a signal with known characteristics. The signal may conform to a specific distribution and have a specific signal bandwidth, such as a signal corresponding to OFDM or PAPR characteristics;

[0051] S130: Simulate the saturation state of the analog output signal of the integrator in a Sigma-Delta ADC and measure the corresponding loss value. Specifically, for example, the power of the injected signal with known characteristics can be gradually increased to trigger the saturation state of the analog output signal of the integrator, and key observation values ​​of the input and output signals at the time of saturation are recorded. For example, the observation values ​​of the input signal may include the integrator overload level, the duration of saturation, and the signal power before saturation. The output signal may include the average energy difference or peak energy difference between the ideal sampled value and the actual limited sampled value of the ADC due to the saturation phenomenon.

[0052] S140: Construct a loss mapping table. A loss mapping table is created by mapping the input signal at saturation in S130 to the observed values ​​of the output signal under different input signal powers and different saturation levels. For example, the loss mapping table can be a multidimensional lookup table, which can be pre-programmed into the ROM of the ADC chip.

[0053] During the construction of the loss mapping table, high-precision offline simulation of the Sigma-Delta ADC was performed to pre-calculate and store the input-output mapping relationships of the Sigma-Delta ADC under various typical operating scenarios. Therefore, in actual operation, the static calculation module can directly use the key observation value of the integrator's analog output signal, such as the instantaneous overload level, as the address to query the pre-stored loss mapping table to obtain the corresponding loss estimate of the analog output signal. This scheme can replace complex real-time calculations with smaller circuit overhead, offering high speed and low power consumption.

[0054] In some possible embodiments, the loss quantization signal may further include dynamic loss, and the determination module 320 may include a dynamic calculation module and an acquisition module. The acquisition module may be used to acquire real-time parameters that are dynamically changing in the operating environment of the analog-to-digital converter. The dynamic calculation module may calculate the dynamic loss of the analog output signal in real time based on the analog output signal of the integrator and the real-time parameters, and provide the dynamic loss to the processing module 330 for subsequent compensation processing. For example, the acquisition module may include a channel estimation module for estimating the attenuation coefficient of the current channel in the actual operating environment; the acquisition module may also include an interference detection module for estimating the power of interference signals in the actual operating environment. Based on the real-time parameters acquired by the acquisition module, the dynamic calculation module may use mathematical formulas to calculate the loss value of the analog output signal of the integrator in real time, in conjunction with known signal statistical models. Figure 4A flowchart illustrating a method for real-time calculation of signal loss values ​​according to an embodiment of this disclosure is shown. For example, for OFDM signals commonly used in 5G communication, the process of real-time calculation of the loss value of the analog output signal of the integrator may include the following steps:

[0055] S210: Variable definition. For OFDM signals, the original signal distribution can be represented by the following formula (2):

[0056] (2)

[0057] in, , Both expressed their expectations.

[0058] The distribution of the noise signal received by the receiving module can be represented by the following formula (3):

[0059] (3)

[0060] in, .

[0061] When the original signal reaches a saturation state, the saturation threshold is defined as... After saturation, the OFDM signal distribution can be represented by the following formula (4):

[0062] (4)

[0063] Nonlinear distortion introduced by the saturation of the original signal Its power is .

[0064] S220: Calculate the original signal-to-noise ratio and the signal-to-noise ratio after saturation.

[0065] The original signal-to-noise ratio (SNR) is the ratio of the signal power to the noise power of the original OFDM signal in the linear domain, and can be calculated using the following formula (5):

[0066] (5)

[0067] The corresponding dB value can be calculated using the following formula (6):

[0068] (6)

[0069] After saturation occurs, the total noise includes the original noise. and distortion noise The total noise power of the two is Since the effect of saturation on the average power of the original signal is negligible, the power of the OFDM signal is approximately preserved. Therefore, the signal-to-noise ratio after saturation can be calculated using the following formula (7):

[0070] (7)

[0071] The corresponding dB value can be calculated using the following formula (8):

[0072] (8)

[0073] S230: Calculate the signal-to-noise ratio loss.

[0074] Signal-to-noise ratio loss (9)

[0075] Substitute formulas (6) and (8) into the above expression, and utilize the properties of logarithms. The signal-to-noise ratio loss is obtained.

[0076] Simplify and eliminate get:

[0077] (10)

[0078] For Gaussian signals Distortion noise The power can be calculated through integration. Specifically, let the normalized threshold be... (The ratio of the threshold to the signal standard deviation) then:

[0079] (11)

[0080] By variable substitution Simplifying, we get:

[0081] (12)

[0082] in, It is the cumulative distribution function (CDF) of the standard normal distribution. It is the probability density function (PDF) of the standard normal distribution.

[0083] Will Substituting the expression into the above formula (10), we obtain the complete signal-to-noise ratio loss formula:

[0084] (13)

[0085] in, This represents the original signal-to-noise ratio.

[0086] During the real-time calculation of the loss value of the analog output signal of the integrator, the determining module 320 can acquire dynamically changing real-time parameters in the operating environment of the analog-to-digital converter through the acquiring module. In actual operation, the dynamically changing real-time parameters can be various types of parameters, including but not limited to the channel attenuation coefficient and interference signal power mentioned above. In the same application scenario, the two different implementation methods of real-time calculation and querying a pre-stored loss mapping table are essentially two different methods of simulating the same function. Therefore, when there are too many types of real-time parameters, that is, when there are too many input variables of the same function, if the implementation method of constructing a loss mapping table is used, the amount of information that needs to be pre-stored will increase accordingly, thereby increasing the cost of the storage circuit. However, if the real-time calculation implementation method is used, this situation can be avoided, and the accuracy of the signal loss value calculation can be improved.

[0087] In some possible embodiments, the determination module 320 may further include at least one set of comparators or quantizers for converting the analog signal output by the integrator into a digital signal before inputting it into the subsequent static calculation module and dynamic determination module for processing. The determination module 320 may also calculate the loss value of the integrator's output signal based on a hybrid mode of querying a pre-stored loss mapping table and real-time calculation. Figure 5 A flowchart illustrating a method for loss calculation based on a hybrid approach combining querying a pre-stored loss map and real-time computation, according to an embodiment of this disclosure, is shown. Exemplarily, loss calculation based on this hybrid approach may include the following steps:

[0088] S310: Construct the core lookup table. The core lookup table can be constructed using the aforementioned method for constructing the loss mapping table, based on the two static factors of signal distribution and bandwidth. Specifically, for example, a three-dimensional core lookup table:

[0089] (Signal type index, bandwidth index, overload level) → Reference loss value.

[0090] S320: Calculate the real-time offset. Based on the channel gain and interference signal power obtained by the acquisition module in the dynamic calculation module, a real-time offset is calculated. For the specific calculation method, please refer to the aforementioned implementation method of real-time calculation.

[0091] S330: Calculate the final loss estimate. Based on the pre-stored core lookup table and the real-time offset calculated in real time, the final loss estimate is calculated:

[0092] Final loss estimate Benchmark loss value obtained from table lookup Real-time offset. (14)

[0093] In the hybrid mode described above, the determination module 320 can quickly process stable and complex nonlinear mappings through a core lookup table, while correcting dynamically changing parts through lightweight real-time computation, thereby achieving a balance between ADC performance and cost.

[0094] In some possible embodiments, the Sigma-Delta ADC may include a digital decimation filter that can be used to downsample and filter the digital output signal of the quantizer. The digital output signal of the quantizer is in a high sampling rate domain before downsampling and filtering, and in a low sampling rate domain after downsampling and filtering.

[0095] In some possible embodiments, when the saturation state signal from the detection module 310 indicates that the analog output signal is saturated, the processing module 330 can perform compensation processing on the digital output signal from the quantizer 220 based on the loss quantization signal from the determination module 320 to restore the signal's authenticity, avoid signal distortion caused by saturation, and thus improve the dynamic range of the Sigma-Delta ADC. When the analog output signal of the integrator is saturated, the processing module 330 can perform compensation processing on the quantizer's digital output signal in the high sampling rate domain based on the saturation state signal and the loss quantization signal. Figure 6 A schematic diagram illustrating the working principle of an analog-to-digital converter 100 performing compensation processing in the high sampling rate domain according to an embodiment of the present disclosure is shown.

[0096] refer to Figure 6As shown, saturation detection can be used as an example of detection module 310, the limiting energy estimation module can be used as an example of determination module 320, saturation post-processing can be used as an example of processing module 330, and the bitstream can be used as an example of the digital output signal of the quantizer. Saturation post-processing can include a saturation sample compensation module for compensating the bitstream. In the high sampling rate domain, the bitstream has not yet undergone downsampling, thus preserving all original details. Processing module 330 compensates the bitstream in the high sampling rate domain, which is equivalent to directly repairing the saturation distortion of the integrator's analog output signal on the noise-shaped original data stream. This fully utilizes the rich original details of the high-frequency signal to achieve higher compensation accuracy. Specifically, in application scenarios such as base stations, test and measurement instruments, and high-end radar, where dynamic range and signal fidelity requirements are extremely high, the analog-to-digital converter 100 of this disclosure can adopt a compensation processing method in the high sampling rate domain to maximize the restoration of signal authenticity.

[0097] In some possible embodiments, when the analog output signal of the integrator becomes saturated, the processing module 330 can perform compensation processing on the digital output signal of the quantizer in the low sampling rate domain based on the saturation signal and the loss quantization signal. Figure 7 A schematic diagram illustrating the working principle of an analog-to-digital converter 100 performing compensation processing in the low sampling rate domain according to an embodiment of the present disclosure is shown.

[0098] refer to Figure 7 As shown, saturation detection can be used as an example of detection module 310, the limiting energy estimation module can be used as an example of determination module 320, saturation post-processing can be used as an example of processing module 330, and the bit stream can be used as an example of the digital output signal of the quantizer. Saturation post-processing can include low-pass filtering, group delay alignment, and saturation sample interpolation modules. Processing module 330 can perform low-pass filtering on the saturation state signal output by the detection module and the loss quantization signal output by the determination module, making the saturation state signal and the loss quantization signal cleaner and more stable, reducing the complexity of subsequent processing. After downsampling and filtering by the CIC decimation filter and the anti-aliasing FIR filter, the digital output signal of the quantizer has a fixed group delay. For example, the delay of the CIC decimation filter is related to its decimation factor. If there is a time difference when signals from different paths arrive at the saturation sample interpolation module, it will cause a "misalignment" in the compensation. For example, when the saturation state signal has arrived but the digital output signal of the quantizer has not yet arrived, the compensation will be misaligned, thus introducing new errors. Therefore, before compensating the digital output signal of the quantizer, the processing module 330 can also perform group delay compensation on the saturation state signal and the loss quantization signal so that they are time-aligned with the digital output signal after downsampling and filtering.

[0099] When the processing module 330 performs compensation processing on the digital output signal of the quantizer in the low sampling rate domain, the amount of data in the digital output signal is greatly reduced because it has already undergone downsampling and filtering. Therefore, the compensation processing is simpler and consumes less power. Specifically, in application scenarios where power consumption and cost are sensitive, such as smartphones, IoT modules, and portable devices, the analog-to-digital converter 100 of this disclosure can adopt a compensation processing method in the low sampling rate domain, which has lower power consumption and implementation complexity and is easy to integrate.

[0100] In some possible embodiments, the processing module may perform compensation processing on the digital output signal of the quantizer by at least one of the following compensation methods: interpolation compensation, lookup table correction compensation, or linear threshold compensation.

[0101] Interpolation compensation can be expressed by the following formula (15):

[0102] (15)

[0103] in This is an estimate of the energy or amplitude loss from a given module, used to reflect the distortion quantization value of the integrator's analog output signal when saturation occurs; These are interpolation functions, such as polynomial interpolation, transform domain interpolation, minimum mean square error interpolation, etc. Indicates the sample used for interpolation. The number of before and after samples required.

[0104] The lookup table correction compensation can be expressed by the following formula (16):

[0105] (16)

[0106] in, This is a lookup table pre-generated based on the output of the determined module.

[0107] Linear threshold compensation can be expressed by the following formula (17):

[0108] (17)

[0109] in, This is the loss estimate from the defined module.

[0110] This disclosure also proposes a method for improving the dynamic range of an analog-to-digital converter. Figure 8A flowchart of a method for improving the dynamic range of an analog-to-digital converter according to another embodiment of the present disclosure is shown. The method is applied to a Sigma-Delta analog-to-digital converter, which includes an integrator and a quantizer.

[0111] S410: Detect the saturation state of the analog output signal of the integrator and generate a saturation state signal indicating whether the analog output signal is saturated;

[0112] S420: In response to the saturation state signal indicating that the analog output signal has reached a saturation state, determine the loss value of the analog output signal and generate a loss quantization signal indicating the loss value of the analog output signal;

[0113] S430: Compensate the digital output signal of the quantizer according to the loss quantization signal.

[0114] The above-mentioned methods for improving the dynamic range of analog-to-digital converters can be based on Figure 2 The analog-to-digital converter 100 shown is implemented here. Therefore, for more details about the above method, please refer to the description of the analog-to-digital converter 100 above, which will not be repeated here.

[0115] The above description and accompanying drawings illustrate some embodiments of the subject matter of the invention to enable those skilled in the art to practice embodiments of the subject matter of the invention. Other embodiments may include structural, logical, electrical, procedural, and other variations. Therefore, although the invention has been described with reference to specific examples, these specific examples are intended to be exemplary only and not to limit the invention. It will be apparent to those skilled in the art that changes, additions, or deletions can be made to the disclosed embodiments without departing from the spirit and scope of the invention.

Claims

1. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes: An integrator, configured to provide an analog output signal; A quantizer, configured to generate and provide a digital output signal based on the analog output signal from the integrator; A detection module is configured to detect the saturation state of the analog output signal from the integrator, and generate and provide a saturation state signal indicating whether the analog output signal is saturated. A determination module is configured to determine the loss value of the analog output signal in response to a saturation state signal from the detection module indicating that the analog output signal has reached a saturation state, and to generate and provide a loss quantization signal indicating the loss value of the analog output signal. A processing module is configured to compensate the digital output signal from the quantizer based on a loss quantization signal from the determining module, in response to a saturation state signal from the detection module indicating that the analog output signal has reached a saturation state.

2. The analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter further includes a digital decimation filter configured to downsample and filter the digital output signal from the quantizer, and provide the downsampled and filtered digital output signal to the processing module.

3. The analog-to-digital converter according to claim 2, characterized in that, The analog-to-digital converter further includes a group delay compensation module, which is configured to perform group delay compensation on the saturation state signal from the detection module and the loss quantization signal from the determination module, and provide the group delay compensated signal to the processing module.

4. The analog-to-digital converter according to claim 1, characterized in that, The analog-to-digital converter also includes a digital decimation filter configured to downsample and filter the compensated signal from the processing module.

5. The analog-to-digital converter according to claim 1, characterized in that, The loss quantization signal includes a static loss. The determination module includes a static calculation module and a storage module. The storage module is configured to store a loss mapping table. The static calculation module is configured to determine the static loss of the analog output signal based on the analog output signal from the integrator and according to the loss mapping table.

6. The analog-to-digital converter according to claim 1, characterized in that, The loss quantization signal includes dynamic loss, and the determination module includes a dynamic calculation module and an acquisition module. The acquisition module is configured to acquire real-time parameters that change dynamically in the operating environment of the analog-to-digital converter, and the dynamic calculation module is configured to determine the dynamic loss of the analog output signal based on the analog output signal from the integrator and the real-time parameters.

7. The analog-to-digital converter according to claim 1, characterized in that, The loss quantization signal includes static loss and dynamic loss. The determination module includes a hybrid determination module, a storage module, and an acquisition module. The storage module is configured to store a loss mapping table. The acquisition module is configured to acquire dynamically changing real-time parameters in the operating environment of the analog-to-digital converter. The hybrid determination module is configured to determine the static loss of the analog output signal based on the analog output signal from the integrator according to the loss mapping table, and to determine the dynamic loss of the analog output signal based on the analog output signal from the integrator and the real-time parameters. The loss quantization signal is then determined based on the static loss and the dynamic loss.

8. A method for improving the dynamic range of an analog-to-digital converter, characterized in that, The analog-to-digital converter includes an integrator and a quantizer, and the method includes: The saturation state of the analog output signal of the integrator is detected, and a saturation state signal indicating whether the analog output signal has reached a saturation state is generated; In response to the saturation state signal indicating that the analog output signal has reached a saturation state, the loss value of the analog output signal is determined, and a loss quantization signal indicating the loss value of the analog output signal is generated; The digital output signal of the quantizer is compensated based on the loss quantization signal.

9. The method according to claim 8, characterized in that, Also includes: The digital output signal of the quantizer is downsampled and filtered. The compensation processing step includes: performing compensation processing on the downsampled and filtered digital output signal based on the loss quantization signal.

10. The method according to claim 9, characterized in that, Also includes: Group delay compensation is performed on the saturation state signal and the loss quantization signal. The compensation processing step includes: performing compensation processing on the downsampled and filtered digital output signal based on the loss quantization signal after group delay compensation.

11. The method according to claim 8, characterized in that, Also includes: The compensated digital output signal is downsampled and filtered.

12. The method according to claim 8, characterized in that, The loss quantization signal includes static loss, and the determination step includes: determining the static loss based on the analog output signal of the integrator and according to a pre-stored loss quantization table.

13. The method according to claim 8, characterized in that, The loss quantization signal includes dynamic loss, and the determination step includes: determining the dynamic loss based on the analog output signal of the integrator and real-time parameters obtained from the operating environment of the analog-to-digital converter.

14. The method according to claim 8, characterized in that, The loss quantization signal includes static loss and dynamic loss, and the determination step includes: Based on the analog output signal of the integrator, the static loss is determined by querying the pre-stored loss quantization table; The dynamic loss is determined based on the analog output signal of the integrator and real-time parameters obtained from the operating environment of the analog-to-digital converter. The loss quantization signal is determined based on the static loss and the dynamic loss.

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