A control method applied to a serial peripheral interface of a beamforming chip, the beamforming chip and a radio frequency front end

Abstract

This application provides a control method for a serial peripheral interface applied to a beamforming chip, a beamforming chip, and an RF front-end. The serial peripheral interface includes a first register and a data output unit. The method includes: the first register being controlled by a mode selection input signal to switch between multiple different modes; the clock input to the first register being a first clock signal, and the clock input to the data output unit being a second clock signal, the second clock signal being generated from the first clock signal based on an inverter. This control method improves flexibility while maintaining accuracy.

Description

Technical Field

[0001] This application relates to the field of interfaces, and more specifically, to a control method for a serial peripheral interface applied to a beamforming chip, the beamforming chip, and the radio frequency front end. Background Technology

[0002] In multi-device electronic systems, such as phased array systems, it is often necessary to configure and control a large number of integrated circuits simultaneously. The Serial Peripheral Interface (SPI) is widely used as the core control interface due to its simple structure and high transmission rate. However, existing SPI implementations have some limitations when scaling up to different system sizes.

[0003] First, in traditional SPI, each device needs to be configured with a dedicated Chip Select (CS) signal. This leads to a corresponding increase in the number of CS lines as the number of devices increases, resulting in a shortage of controller pin resources, complex printed circuit board (PCB) routing, and consequently, limited system scalability.

[0004] In response to this, various different models exist in related technologies, such as the daisy-chain model. In the daisy-chain model, multiple devices are connected in series, with the output of an upstream device serving as the input of a downstream device. This model can reduce the chip select signals required by multiple devices, simplify board layout, and is suitable for smaller-scale systems. However, this model has the following drawbacks: data must pass through upstream devices sequentially, resulting in latency; and if one device in the chain fails, all its downstream devices may be affected, indicating poor fault tolerance.

[0005] Meanwhile, in related technologies, there is also a physical addressing mode. In physical addressing mode, a unique address is assigned to each device in the SPI command protocol, and the target device is identified by the address. This mode enables direct random access to devices, ensuring that a failure of one device will not block communication with other devices, making it suitable for large systems. However, this mode also has the following drawbacks: it requires more chip select lines and more complex wiring, thereby increasing the use of controller pins and the complexity of printed circuit board design.

[0006] Since different modes are suitable for different system sizes, there is an urgent need to provide a flexible SPI control method that allows system manufacturers to flexibly select different modes in the same hardware, thereby making it suitable for different system sizes. Summary of the Invention

[0007] This application provides at least one control method for a serial peripheral interface of a beamforming chip, a beamforming chip, and an RF front-end. In the control method, a first register can be controlled by a mode selection input signal to achieve flexible switching between multiple different modes. At the same time, a first clock signal is input to the clock of the first register, and a second clock signal generated by the first clock signal based on an inverter is input to the clock of the data output unit. This ensures accurate data transmission in different modes, that is, it can improve flexibility while ensuring accuracy.

[0008] In a first aspect, this application provides a control method for a serial peripheral interface applied to a beamforming chip, wherein the serial peripheral interface includes a first register data output unit.

[0009] The method includes: The first register is controlled by a mode selection input signal to switch between multiple different modes; The clock input of the first register is a first clock signal, and the clock input of the data output unit is a second clock signal, which is generated by the first clock signal based on an inverter.

[0010] Secondly, this application also provides a beamforming chip applied to the control method of the foregoing embodiments. The beamforming chip includes multiple chip identification pins and a mode selection input signal pin. The multiple chip identification pins and the mode selection input signal pin are arranged adjacent to the power supply pin and the ground pin in the pin arrangement.

[0011] Thirdly, this application also provides a radio frequency front end applied to the control method of the foregoing embodiments.

[0012] In summary, this application provides a control method for a serial peripheral interface applied to a beamforming chip, a beamforming chip, and an RF front-end. The serial peripheral interface includes a first register and a data output unit. The method includes: the first register being controlled by a mode selection input signal to switch between multiple different modes; a first clock signal being input to the clock of the first register, and a second clock signal being input to the clock of the data output unit, the second clock signal being generated by the first clock signal based on an inverter. In the above control method, the first multiplexer MUX1 can be controlled by the mode selection input signal to achieve flexible switching between different modes. Simultaneously, by inputting the first clock signal to the clock of the first register and the second clock signal generated by the first clock signal based on an inverter to the clock of the data output unit, accurate data transmission in different modes can be guaranteed. In other words, accuracy can be guaranteed while improving flexibility.

[0013] Other advantages of this application will be explained in more detail in conjunction with the following description and figures.

[0014] It should be understood that the above description is merely an overview of the technical solution of this application, so as to enable a general understanding of the technical means of this application and to implement it in accordance with the contents of the specification. In order to make the above and other objects, features and advantages of this application more apparent and understandable, specific embodiments of this application are illustrated below. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. The accompanying drawings are incorporated in and constitute a part of this specification. These drawings illustrate embodiments conforming to this application and are used together with the specification to explain the technical solutions of this application. It should be understood that the drawings only illustrate certain embodiments of this application and should not be considered as a limitation on the scope of protection. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. Furthermore, the same reference numerals denote the same components throughout the drawings. In the drawings: Figure 1 This application provides a schematic diagram of the structure of a serial peripheral interface for a beamforming chip. Figure 2 A flowchart illustrating a control method for a serial peripheral interface of a beamforming chip provided in an embodiment of this application; Figure 3 The clock generation circuit provided in the embodiments of this application; Figure 4 A first embodiment of a serial peripheral interface based on a beamforming chip is provided for the purposes of this application. Figure 5 A second embodiment of a serial peripheral interface based on a beamforming chip is provided for the purposes of this application. Figure 6 A flowchart illustrating a control method for a second multiplexer provided in an embodiment of this application; Figure 7 A third embodiment of a serial peripheral interface based on a beamforming chip is provided for the purposes of this application. Figure 8 A flowchart illustrating a control method for a third multiplexer provided in an embodiment of this application; Figure 9 A fourth embodiment of a circuit for a serial peripheral interface based on a beamforming chip provided in this application; Figure 10 A pin diagram of a beamforming chip provided in an embodiment of this application; Figure 11 This application provides a system-level embodiment under the physical addressing mode. Figure 12 This is a system-level embodiment of the daisy-chain mode provided in the embodiments of this application. Detailed Implementation

[0016] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0017] In the description of embodiments of this application, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the disclosed features, figures, steps, behaviors, components, portions or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, figures, steps, behaviors, components, portions or combinations thereof.

[0018] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A alone, A and B at the same time, and B alone.

[0019] The terms "first," "second," etc., are used only for ease of description to distinguish identical or similar technical features and should not be construed as indicating or implying the relative importance or number of these technical features. Therefore, a feature defined by "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, the term "multiple" means two or more.

[0020] In multi-device electronic systems, such as phased array systems, it is often necessary to configure and control a large number of integrated circuits simultaneously. SPI is widely used as the core control interface due to its simple structure and high transmission rate. However, existing SPI implementations have some limitations when scaling up to different system sizes.

[0021] First, in traditional SPI, each device needs to be configured with a dedicated chip select signal. This leads to a corresponding increase in the number of CS lines as the number of devices increases, resulting in a shortage of controller pin resources, complex printed circuit board wiring, and thus limiting system scalability.

[0022] In response to this, various different models exist in related technologies, such as the daisy-chain model. In the daisy-chain model, multiple devices are connected in series, with the output of an upstream device serving as the input of a downstream device. This model can reduce the chip select signals required by multiple devices, simplify board layout, and is suitable for smaller-scale systems. However, this model has the following drawbacks: data must pass through upstream devices sequentially, resulting in latency; and if one device in the chain fails, all its downstream devices may be affected, indicating poor fault tolerance.

[0023] Meanwhile, physical addressing mode also exists in related technologies. In physical addressing mode, a unique address is assigned to each device in the SPI command protocol, and the target device is identified by the address. This mode enables direct random access to devices, ensuring that a failure of one device will not block communication with other devices, making it suitable for large systems. However, this mode also has the following disadvantages: it requires more chip select lines and more complex wiring, thereby increasing the use of controller pins and the complexity of printed circuit board design.

[0024] Since different modes are suitable for different system sizes, there is an urgent need to provide a flexible SPI control method that allows system manufacturers to flexibly select different modes in the same hardware, thereby making it suitable for different system sizes.

[0025] In view of this, this application provides a control method for a serial peripheral interface of a beamforming chip, a beamforming chip, and an RF front end. In the above control method, a first register can be controlled by a mode selection input signal to achieve flexible switching between different modes. At the same time, a first clock signal is input to the clock of the first register, and a second clock signal generated by the first clock signal based on an inverter is input to the clock of the data output unit. This ensures accurate data transmission in different modes, that is, it can improve flexibility while ensuring accuracy.

[0026] The serial peripheral interface of the beamforming chip provided in this application will be described below through interface embodiments, such as... Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of a serial peripheral interface of a beamforming chip provided in an embodiment of this application. The serial peripheral interface includes a first register and a data output unit: the output terminal of the first register is connected to the data output unit for data output.

[0027] The following describes the control method for the serial peripheral interface of a beamforming chip provided in this application using method embodiments, such as... Figure 2 As shown, Figure 2This is a flowchart illustrating a control method for a serial peripheral interface of a beamforming chip provided in an embodiment of this application. The method includes: S201, The first register is controlled by the mode selection input signal to switch between different modes.

[0028] Specifically, such as Figure 1 As shown, the first register can be applied to different modes, that is, the first register can be controlled by the mode selection input signal (MODE) to switch between multiple different modes. The mode selection input signal is used to determine which specific mode to operate in.

[0029] In practical applications, the mode selection input signal can be set to operate in the first mode when the MODE pin is connected to a logic low level, and to operate in the second mode when it is connected to a logic high level. It should be noted that in practical applications, the logic polarity of the mode selection input signal can also be reversed.

[0030] In the above control method, the first register can be controlled by the mode selection input signal to achieve flexible switching between different modes. This breaks the limitation of serial peripheral interfaces in related technologies that can only support a single mode. As a result, it allows relevant personnel to flexibly select between different modes according to the specific system scale, thus improving flexibility.

[0031] S202, the clock input of the first register is a first clock signal, and the clock input of the data output unit is a second clock signal, which is generated by the first clock signal based on the inverter.

[0032] Specifically, such as Figure 1 As shown, the first clock signal refers to the clock signal input to the first register, and the second clock signal refers to the clock signal input to the data output unit.

[0033] The second clock signal can be generated from the first clock signal using an inverter, such as... Figure 3 As shown, the second clock signal (clk2) can be derived from the first clock signal (clk1) through an inverter. In this case, as... Figure 1 As shown, due to the clock control bit of the clk2 input data output unit, the rising edge of the external clock signal (SCLK) (which is also the rising edge of clk2) can be used to output data to the serial data output (SDO) line, ensuring the correct timing relative to the sampling edge of the SPI master, thereby ensuring accurate data transmission in different modes.

[0034] In other words, the control method in this embodiment can improve flexibility while ensuring accuracy.

[0035] In one possible implementation, the method further includes: The first clock signal is generated by the chip select signal and the external clock signal; when the chip select signal is valid, the first clock signal is activated; when the chip select signal is invalid, the first clock signal is muted.

[0036] Specifically, the first clock signal is generated from the chip select signal and an external clock signal, such as... Figure 3 As shown, the chip select signal (CSB) is combined with the external clock signal (SCLK) through an AND gate after passing through an inverter to generate clk1.

[0037] When the chip select signal is active, the first clock signal is activated; when the chip select signal is inactive, the first clock signal is muted. In practical applications, the chip select signal can be active low. Therefore, when the chip select signal is low, the first clock signal is activated; when the chip select signal is high, the chip select signal remains inactive, and the first clock signal is muted. By muting the first clock signal when the chip select signal is inactive, it is possible to prevent unselected devices from unexpectedly switching on or off, reducing the power consumption of the entire digital core and preventing erroneous device toggling. The first clock signal can serve as the base clock for generating subsequent timing signals.

[0038] In one possible implementation, the first register is used to receive and store command fields and / or input data from the first device; in S201, the first register is controlled by a mode selection input signal to switch between multiple different modes, including: In the first mode, the first device is the master device, and the first register outputs the input data of the future autonomous device to the target static register corresponding to the command field. In the second mode, the first device is the upstream device, and the first register outputs the input data from the upstream device to the downstream device.

[0039] Specifically, the input of the first register is connected to the first device and is used to receive and temporarily store command fields and / or input data from the first device. In practical applications, the first register can be a shift register, which includes control bits and data bits. The control bits of the shift register correspond to the command fields from the first device, and the data bits of the shift register correspond to the input data, such as... Figure 1 As shown, the control bits can include "R / W, BC, CHIP_ADDRESS, REGISTER_ADDRESS", and the data bits can include "DATA". These will be explained in detail below: "R / W: A control bit that specifies whether the operation is a write (0) or a read (1). This control bit is only valid in the first mode and is ignored in the second mode."

[0040] BC: A control bit that specifies whether only the target device with the matching address executes the command, or whether all devices on the SPI bus execute the command simultaneously. This control bit is only valid in the first mode and is ignored in the second mode.

[0041] CHIP_ADDRESS: Specifies the physical address of the specific target device to which data needs to be transferred. It is only valid in the first mode and is ignored in the second mode.

[0042] REGISTER_ADDRESS: Specifies the address of the static register to be written to in both modes, or the address of the static register to be read in the first mode, meaning it is valid in both modes.

[0043] DATA: The payload data to be output. In the first mode, the first device is the master device. During a write operation in the first mode, a shift register shifts in the command field and input data from the master device and transmits the data to the target static register corresponding to the command field. In other possible embodiments, the target static register can also be a storage unit that needs to be read and written. During a read operation in the first mode, the shift register receives the command field from the master device and directly outputs the data from the target static register corresponding to the command field to the master device. In practice, in the first mode, the slave device has a unique hardware identifier (CHIP ID) and compares the address field (CHIP ADDRESS) in the command field with the CHIP ID, performing read and write operations only when the address matches (or a broadcast command is encountered).

[0044] In the second mode, serial commands and data output by the master device are transmitted sequentially along a serial link consisting of multiple slave devices, with the first device referring to the upstream device in the link. Driven by a clock signal, each slave device's shift register simultaneously shifts in serial data from the upstream device and shifts out its currently stored data to the downstream device via a serial output. In the second mode, the shifting process continues until the commands and data sent by the master device have passed through all slave devices in the link, and the master device receives the data shifted out sequentially by each slave device via a serial data return path. In the second mode, the chip ID of each slave device is ignored.

[0045] In the circuit described above, switching between the first and second modes can be achieved through a shift register, breaking the limitation of serial peripheral interfaces in related technologies that can only support a single mode. This allows for flexible selection between different modes based on the specific system scale, thus improving flexibility.

[0046] In one possible implementation, the serial peripheral interface further includes a second register, and the method also includes: In the second mode, the data in the second register is input to the first register so that the data in the second register can be shifted and output to the downstream device in the next shift operation.

[0047] Specifically, such as Figure 4 As shown, considering that data flows continuously between upstream and downstream devices in the chain in the second mode, a second register (i.e., the read pointer register) is specifically set up to store the address pointer value (READ_ADDRESS) in order to meet the data readback requirements in the second mode. When the master device needs to read data from a certain internal register of a slave device in the chain, it first writes the address of the target register to the slave device's dedicated read pointer register through a write operation. Then, the control logic block selects the corresponding internal static register according to the address value in this read pointer register and loads its data content into a shift register so that it can be shifted and output to the downstream device in the next shift operation and finally received by the master device. This achieves non-destructive, addressable reading of the internal registers of any slave device in the chain.

[0048] In one possible implementation, the serial peripheral interface further includes a first multiplexer MUX1, and the method further includes: In the first mode, the first multiplexer MUX1 outputs the data from the second register; In the second mode, the first multiplexer MUX1 outputs the data from the first register, where the data portion of the first register comes from the second register.

[0049] Specifically, such as Figure 4 As shown, Figure 4 This application provides a first embodiment of a serial peripheral interface based on a beamforming chip. The serial peripheral interface further includes a first multiplexer MUX1. The first input terminal of the first multiplexer MUX1 is connected to the output terminal of a shift register, the second input terminal is connected to the output terminal of a static register to be transmitted, and the output terminal is connected to a data output unit. That is, the first input terminal of the first multiplexer MUX1 is connected to the shift register, and the second input terminal is connected to the static register to be transmitted.

[0050] In the first mode (MODE=0 in this example), the first multiplexer MUX1 directly outputs the data from the static register to be transmitted. In the second mode (MODE=1 in this example), the first multiplexer MUX1 outputs the data from the shift register, where the data portion comes from the static register to be transmitted.

[0051] In one possible implementation, the serial peripheral interface further includes a second multiplexer MUX2, and the method further includes: The second multiplexer MUX2 is controlled by the mode selection input signal and the chip select signal; The mode selection input signal is used to switch the mode that the second multiplexer MUX2 needs to respond to; The chip select signal is used to control the input of input data in the first mode, and to control the sequential input of input data and data in the second register in the second mode.

[0052] Specifically, such as Figure 5 As shown, Figure 5 A second embodiment of a serial peripheral interface based on a beamforming chip provided in this application provides a second multiplexer MUX2 between the control bit and the data bit of the first register.

[0053] The first input of the second multiplexer MUX2 is connected to the output of the control bit of the first register, the second input is connected to the output of the second register, and the output is connected to the input of the data bit of the first register.

[0054] When the serial peripheral interface also includes a second multiplexer MUX2, in order to achieve accurate data transmission, such as Figure 6 As shown, the second multiplexer MUX2 is controlled by the mode selection input signal and the chip select signal, such as... Figure 5 As shown, the chip select signal, after passing through an inverter, is ORed with the mode select input signal through an OR gate to control the second multiplexer MUX2.

[0055] The mode selection input signal is used to determine the mode that the second multiplexer MUX2 needs to respond to, that is, to determine the specific mode that the second multiplexer MUX2 needs to respond to between the first mode and the second mode by using the mode selection input signal.

[0056] The chip select signal is used to control the input of input data in the first mode, and to control the sequential input of input data and data in the second register in the second mode.

[0057] In one possible implementation, the method further includes: In the first mode, when the chip select signal is valid, the second multiplexer MUX2 inputs the input data to the data bits of the first register; In the second mode, when the chip select signal is valid, the second multiplexer MUX2 inputs the input data to the data bits of the first register. After the input data is shifted, the chip select signal changes from valid to invalid, and the second multiplexer MUX2 then inputs the data from the second register to the data bits of the first register.

[0058] Specifically, in the first mode, the first device is the master device. When the chip select signal (CSB) is valid, the second multiplexer MUX2 shifts the input data of the master device to the data bits of the shift register so that the input data can be output to the target static register according to the address matching.

[0059] In the second mode, the first device is the upstream device. When the chip select signal is valid, the second multiplexer MUX2 first shifts the input data from the upstream device to the data bits of the shift register. After the input data shift is complete, the chip select signal (CSB) changes from valid to invalid. At this time, the data bits of the shift register are output to the target static register. Simultaneously, the second multiplexer MUX2 inputs the data from the static register to be transmitted to the data bits of the shift register. That is, through the transition of the chip select signal (CSB) from valid to invalid, data download from the shift register to the target static register and data upload from the static register to the shift register are simultaneously achieved.

[0060] exist Figure 5 In the illustrated embodiment, the chip select signal (CSB) is active low; however, in an alternative embodiment, it can also be implemented as an active high signal without affecting the functional operation.

[0061] In one possible implementation, the serial peripheral interface further includes a third multiplexer MUX3, and the method further includes: The third multiplexer MUX3 is controlled by the chip select signal; When the chip select signal is active, the first clock signal is applied to the data bits of the first register through the third multiplexer MUX3 so that input data is input to the data bits of the first register.

[0062] Specifically, such as Figure 7 As shown, Figure 7 A third embodiment of a serial peripheral interface based on a beamforming chip is provided for the present application. In the third embodiment, the circuit further includes a third multiplexer MUX3.

[0063] The first input of the third multiplexer MUX3 is connected to the first clock signal, the second input is connected to a high level, and the output is connected to the clock input of the data bits of the first register.

[0064] like Figure 7 As shown, the third multiplexer MUX3 is used to connect the first clock signal to the clock input of the data bits of the first register, such as... Figure 8 As shown, the operation of the third multiplexer MUX3 is controlled by the chip select signal. In this embodiment, the chip select input can be active low. However, in an alternative embodiment, it can also be implemented as an active high signal, which does not affect the functional operation.

[0065] When the chip select signal is active, i.e. when the chip select signal is low, the first clock signal is applied to the data bits of the first register through the third multiplexer MUX3, so that the input data is shifted to the data bits of the first register, thereby ensuring the correct timing of the input data transmission.

[0066] In one possible implementation, the method further includes: After the input data is shifted into the first register, the chip select signal changes from an active state to an inactive state, generating a latch signal; In the first mode, the latch signal triggers the output of input data from the data bits of the first register; In the second mode, the latch signal triggers the output of input data from the data bits of the first register and triggers the input of data from the second register to the data bits of the first register.

[0067] Specifically, after the input data shift is complete, the chip select signal will change from an active state to an inactive state. That is, when the chip select signal changes from a low level to a high level, the rising edge of the chip select signal will generate a latch signal through the third multiplexer MUX3.

[0068] The latch signal can achieve different effects in two modes. In the first mode, the latch signal triggers the input data to be exported from the data bits of the first register. In the second mode, the latch signal triggers the input data to be exported from the data bits of the first register and triggers the data in the second register to be shifted to the data bits of the first register, preparing for the next shift operation.

[0069] exist Figure 7 In the illustrated embodiment, the chip select signal (CSB) is active low; however, in an alternative embodiment, it can be implemented as active high without affecting the functional operation.

[0070] In one possible implementation, the method further includes: The chip select signal and the mode select input signal are combined through an AND gate to generate a latch signal.

[0071] Specifically, such as Figure 3 As shown, the chip select signal and the mode selection input signal can be combined through an AND gate to generate latching signals that can have different effects in different modes.

[0072] In one possible implementation, the serial peripheral interface further includes a delay unit, and the method further includes: When the chip select signal is active, the first clock signal is applied to the data bits of the first register through the third multiplexer MUX3 and the delay unit.

[0073] Specifically, such as Figure 7 As shown, in the second embodiment, the circuit further includes a delay unit.

[0074] The input of the delay unit is connected to the output of the third multiplexer MUX3, and the output is connected to the clock control bit of the data bit of the first register.

[0075] When the chip select signal is active, the first clock signal is applied to the data bits of the first register through the third multiplexer MUX3 and the delay unit, so that the first clock signal can reach the command bits and data bits of the first register in sequence.

[0076] In one possible implementation, the serial peripheral interface further includes a third register and a fourth multiplexer MUX4, the third register being used to store data from the second register in the second mode, and the method further includes: The fourth multiplexer MUX4 is controlled by the output path control signal to switch between outputting data from the first register and data from the third register, so that in the second mode, the data from the first register and the data from the third register are output sequentially.

[0077] Specifically, such as Figure 9 As shown, Figure 9 A fourth embodiment of a serial peripheral interface circuit based on a beamforming chip provided in this application further includes a third register (DATA2) and a fourth multiplexer MUX4. The input of the third register is connected to the output of the second register, and the output is connected to the second input of the fourth multiplexer MUX4.

[0078] The first input of the fourth multiplexer MUX4 is connected to the output of the first register, the second input is connected to the output of the third register, and the output is connected to the first input of the first multiplexer MUX1.

[0079] The third register is located between the second register and the second input of the fourth multiplexer MUX4, and is configured in parallel with the first register. The third register is used to store data from the static register to be transmitted in the second mode.

[0080] In the first mode (MODE=0 in this example), the fourth multiplexer MUX4 has no function. If the master device needs to read static register data from the slave device, the data to be transmitted from the static register will be directly output to the master device through the first multiplexer MUX1.

[0081] In the second mode, the fourth multiplexer MUX4 outputs input data from the upstream device to the downstream device via a shift register, and outputs data from the static register to be transmitted to the downstream device via a secondary shift register. That is, in the second mode, the fourth multiplexer MUX4 selects to output the data from the first register and the data from the third register sequentially.

[0082] The fourth multiplexer MUX4 is controlled by the output path control signal (READ_SEL_2). Under the control of this output path control signal, the fourth multiplexer MUX4 can output the data of the first register, and the fourth multiplexer MUX4 can also output the data of the third register, thereby realizing the selection of the output path.

[0083] When the mode selection input signal (MODE) is in the second mode, the data from the static register to be transmitted stored in the secondary shift register is first output to the downstream device by the fourth multiplexer MUX4. After the data output of the static register to be transmitted is completed, the fourth multiplexer MUX4 switches to the shift register so as to output the input data from the upstream device to the downstream device.

[0084] In one possible implementation, the method further includes: The first clock signal and the mode selection input signal are combined through an AND gate to generate an intermediate time signal that is applied to the first mode; The chip select signal and the mode select input signal are combined through an AND gate to generate a latch signal for the second mode; The intermediate time signal and the latched signal are combined through an OR gate to generate a third clock signal; The clock control bit of the third register receives the third clock signal.

[0085] Specifically, such as Figure 3 As shown, since the chip select signal is not used as a clock input in the first mode, the first clock signal and the mode selection input signal can be combined through an AND gate to selectively mask the chip select signal in the first mode and generate an intermediate time signal (clk_int) for the first mode.

[0086] Meanwhile, in the second mode, the chip select signal and the mode selection input signal are combined through an AND gate to generate a latch signal applied to the second mode. For example, the rising edge of the chip select signal can be used as the latch signal. In the second mode, the latch signal triggers the input data to be exported from the data bits of the first register and triggers the data in the second register to be shifted to the data bits of the first register.

[0087] To address this, the intermediate time signal and the latch signal are combined using an OR gate to generate a third clock signal (clk3), as follows: Figure 9 As shown, the third clock signal is input to the clock control bit of the third register to achieve accurate timing control of the data in the third register.

[0088] In one possible implementation, the first register is a shift register.

[0089] In one possible implementation, the second register is a static register to be transferred.

[0090] In one possible implementation, the third register is a secondary shift register, meaning the shift register and the secondary shift register can be configured in parallel.

[0091] In one possible implementation, the first mode is the physical addressing mode, and the second mode is the daisy chain mode.

[0092] Specifically, in this application, the first mode can be the physical addressing mode, and the second mode can be the daisy chain mode.

[0093] Therefore, this application provides a control method for a serial peripheral interface applied to a beamforming chip. The serial peripheral interface includes a register and a data output unit. The method includes: a first register being controlled by a mode selection input signal to switch between multiple different modes; a first clock signal being input to the clock of the first register; and a second clock signal being input to the clock of the data output unit, wherein the second clock signal is generated by an inverter based on the first clock signal. In the above control method, the first register can be controlled by the mode selection input signal to achieve flexible switching between different modes. Simultaneously, the first clock signal is input to the clock of the first register, and the second clock signal generated by an inverter based on the first clock signal is input to the clock of the data output unit, thereby ensuring accurate data transmission in different modes. In other words, it can improve flexibility while ensuring accuracy.

[0094] The method flowcharts for embodiments of this application describe certain operations as different steps performed in a certain order. Such flowcharts are illustrative and not restrictive. Some steps described herein may be grouped together and performed in a single operation, or some steps may be divided into multiple sub-steps, and some steps may be performed in an order different from that shown herein. The various steps shown in the flowcharts may be implemented in any way by any circuit structure and / or tangible mechanism (e.g., by software running on a computer device, hardware (e.g., logic functions implemented by a processor or chip), and / or any combination thereof).

[0095] Those skilled in the art will understand that in the methods described in the above specific embodiments, the order in which the steps are written does not imply a strict execution order, and the specific execution order of each step should be determined by its function and possible internal logic.

[0096] Based on this, the present application also provides a beamforming chip. The beamforming chip applies any of the control methods for the serial peripheral interface based on the beamforming chip provided above. The beamforming chip includes multiple control signal pins and a mode selection input signal pin. The multiple control signal pins and the mode selection input signal pin are arranged adjacent to the power supply pin and the ground pin in the pin arrangement.

[0097] Specifically, such as Figure 10 As shown, Figure 10 This is a pin diagram of a beamforming chip provided in an embodiment of this application. The beamforming chip may include multiple chip identification pins (in... Figure 11 The middle label is CID[4:0]) and a mode selection input signal pin (in Figure 11 The pins marked "MODE" are multiple chip identifier pins and mode selection input signal pins that are all connected to the power supply pins in the pinout. Figure 10 The pin marked as VDD) and the ground pin (in Figure 10 The adjacent layout is indicated by GND.

[0098] Because the chip identification pins are located close to the power and ground pins, configuration signals can be hard-connected to logic high or low levels without requiring lengthy PCB traces or additional routing complexity. This layout also minimizes crosstalk with high-speed interface signals such as SCLK, SDI, and SDO, and reduces the number of vias and routing layers required for array-level integration.

[0099] It should be noted that, Figure 10 The number of chip identifier pins shown (five) is merely an example and does not constitute a limitation. This invention can employ any suitable number of chip identifier inputs or logic level allocation schemes. Similarly, the pin arrangement shown is merely an example and can also utilize equivalent layouts in various packages (such as flip-chip, ball grid array, wafer-level, or leadframe packages).

[0100] Based on this, the embodiments of this application also provide a radio frequency front-end, which applies any of the control methods for the serial peripheral interface based on beamforming chips provided above.

[0101] To facilitate a better understanding of this application, the physical addressing mode and daisy chain mode mentioned in this application will be described below based on system-level embodiments.

[0102] Figure 11 and Figure 12The system-level embodiments provided in this application each include multiple beamforming chips that integrate the serial peripheral interfaces described in this application. The system-level embodiments demonstrate how the same system-level embodiment example can be configured to operate in physical addressing mode or daisy-chain mode according to system requirements. These two system-level embodiments are provided for illustrative purposes only and are not intended to limit the scope of this application.

[0103] exist Figure 11 In the system-level embodiment, it is configured in physical addressing mode. The host provides multiple chip select signals (CSB<0:2>) to independently activate devices in each row of the array. The host transmits data via shared signal lines (including SCLK, LOAD, SDI, and SDO). Each beamforming chip compares the CHIP_ADDRESS bit in the received command field with its assigned chip identifier (CID[4:0]). Only the beamforming chip whose chip identifier matches the command field accepts the data transaction, while all other beamforming chips ignore the transaction (unless the command field specifies a broadcast operation).

[0104] This two-dimensional addressing scheme, which selects rows via CSB and devices via internal addressing, allows the host to directly access any beamforming chip in the array. This configuration is particularly advantageous in large arrays because physical addressing provides low-latency random access and fault tolerance, ensuring that the failure of a single device does not affect communication with other devices.

[0105] exist Figure 12 In the system implementation, a daisy-chain configuration is used. In this configuration, devices within a row are connected in series, meaning the serial data output (SDO) of one device is coupled to the serial data input (SDI) of the next device in the chain. The host transmits data through the first device in the chain, and each device shifts the data using its internal shift register before passing it to the next device. The chip select module (CSB<0:2>) is again responsible for selecting which row of devices to activate, while the daisy-chain connection determines the order of devices within the row.

[0106] The daisy-chain pattern reduces pin count and simplifies printed circuit board (PCB) routing, making it particularly useful in small arrays where simplicity of design and pin minimization are more critical than random access capability or fault tolerance. However, this pattern introduces latency because data must propagate sequentially through upstream devices and depends on the proper functioning of all devices in the chain.

[0107] In the description of this specification, references to terms such as "some possible implementations," "some implementations," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that implementation or example is included in at least one implementation or example of this application, and the aforementioned terms do not necessarily refer to the same implementation or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more implementations or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different implementations or examples described in this specification, as well as the features of different implementations or examples.

[0108] While the spirit and principles of this application have been described above with reference to several specific embodiments, it should be understood that this application is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined. This application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A control method for a serial peripheral interface applied to a beamforming chip, characterized in that, The serial peripheral interface includes a first register and a data output unit; the method includes: The first register is controlled by a mode selection input signal to switch between multiple different modes; The clock input of the first register is a first clock signal, and the clock input of the data output unit is a second clock signal, which is generated by the first clock signal based on an inverter.

2. The control method according to claim 1, characterized in that, The method further includes: The first clock signal is generated by the chip select signal and an external clock signal; when the chip select signal is valid, the first clock signal is activated; when the chip select signal is invalid, the first clock signal is muted.

3. The control method according to claim 1, characterized in that, The first register is used to receive and store command fields and / or input data from the first device. The first register is controlled by a mode selection input signal to switch between multiple different modes, including: In the first mode, the first device is the master device, and the first register outputs the input data from the master device to the target static register corresponding to the command field. In the second mode, the first device is an upstream device, and the first register outputs the input data from the upstream device to the downstream device.

4. The control method according to claim 3, characterized in that, The serial peripheral interface further includes a second register, and the method further includes: In the second mode, the data of the second register is input to the first register so that the data of the second register can be shifted and output to the downstream device in the next shift operation.

5. The control method according to claim 4, characterized in that, The serial peripheral interface further includes a first multiplexer MUX1, and the method further includes: In the first mode, the first multiplexer MUX1 outputs the data from the second register; In the second mode, the first multiplexer MUX1 outputs the data from the first register, wherein part of the data in the first register comes from the second register.

6. The control method according to claim 5, characterized in that, The serial peripheral interface further includes a second multiplexer MUX2, and the method further includes: The second multiplexer MUX2 is controlled by the mode selection input signal and the chip select signal; The mode selection input signal is used to switch the mode that the second multiplexer MUX2 needs to respond to; The chip select signal is used to control the input of the input data in the first mode, and to control the sequential input of the input data and the data in the second register in the second mode.

7. The control method according to claim 6, characterized in that, The method further includes: In the first mode, when the chip select signal is valid, the second multiplexer MUX2 inputs the input data to the data bits of the first register; In the second mode, when the chip select signal is valid, the second multiplexer MUX2 inputs the input data to the data bits of the first register, and after the input data is shifted, the chip select signal changes from a valid state to an invalid state, and the second multiplexer MUX2 then inputs the data from the second register to the data bits of the first register.

8. The control method according to claim 6, characterized in that, The serial peripheral interface further includes a third multiplexer MUX3, and the method further includes: The third multiplexer MUX3 is controlled by the chip select signal; When the chip select signal is active, the first clock signal is applied to the data bits of the first register through the third multiplexer MUX3, so that the input data is input to the data bits of the first register.

9. The control method according to claim 8, characterized in that, The method further includes: After the input data is shifted into the first register, the chip select signal changes from an active state to an inactive state, generating a latch signal; In the first mode, the latch signal triggers the input data to be output from the data bits of the first register; In the second mode, the latch signal triggers the output of the input data from the data bit of the first register and triggers the input of the data from the second register to the data bit of the first register.

10. The control method according to claim 9, characterized in that, The method further includes: The chip select signal and the mode selection input signal are combined using an AND gate to generate the latch signal.

11. The control method according to claim 8, characterized in that, The serial peripheral interface further includes a delay unit, and the method further includes: When the chip select signal is active, the first clock signal is applied to the data bits of the first register through the third multiplexer MUX3 and the delay unit.

12. The control method according to claim 5, characterized in that, The serial peripheral interface further includes a third register and a fourth multiplexer MUX4, wherein the third register is used to store data from the second register in the second mode, and the method further includes: The fourth multiplexer MUX4 is controlled by an output path control signal to switch between outputting data from the first register and data from the third register, so that in the second mode, the data from the first register and the data from the third register are output sequentially.

13. The control method according to claim 12, characterized in that, The method further includes: The first clock signal and the mode selection input signal are combined through an AND gate to generate an intermediate time signal applied to the first mode; The chip select signal and the mode selection input signal are combined through an AND gate to generate a latch signal applied to the second mode; The intermediate time signal and the latch signal are combined through an OR gate to generate a third clock signal; The clock input of the third register is the third clock signal.

14. The control method according to claim 1, characterized in that, The first register is a shift register.

15. The control method according to claim 4, characterized in that, The second register is the static register to be transferred.

16. The control method according to claim 12, characterized in that, The third register is a secondary shift register.

17. The control method according to claim 3, characterized in that, The first mode is the physical addressing mode, and the second mode is the daisy chain mode.

18. A beamforming chip, characterized in that, The beamforming chip, applied to any one of claims 1-17, includes a plurality of chip identification pins and a mode selection input signal pin, wherein the plurality of chip identification pins and the mode selection input signal pin are arranged adjacent to power supply pins and ground pins in a pin arrangement.

19. A radio frequency front end, characterized in that, Applied to the control method as described in any one of claims 1-17.

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