Multi-interface compatible national secret sm3 / sm4 algorithm hardware module instruction translation method and related device

Abstract

The application discloses a multi-interface compatible SM3 / SM4 algorithm hardware module instruction translation method and related devices, including a host end, a translation chip end and a hardware algorithm end, wherein the host end and the translation chip end interact information, and the translation chip end and the hardware algorithm end interact information, the method and related devices have the characteristics of strong hardware form compatibility, high interface protocol adaptability and low calling complexity.

Description

Technical Field

[0001] This invention belongs to the field of network information security and relates to a method and related apparatus for translating instructions for hardware modules of the national cryptographic SM3 / SM4 algorithm that is compatible with multiple interfaces. Background Technology

[0002] The SM3 hash algorithm (used for data integrity verification) and the SM4 block cipher algorithm (used for data encryption) have become core security foundations. With the increasing prevalence of big data transmission and high-concurrency scenarios, the demand for algorithm processing speed continues to rise. The efficiency of pure software implementations is often insufficient for daily needs, and their hardware implementation has expanded from early programmable hardware (such as FPGAs) to application-specific integrated circuits (ASICs, often integrated into SoC chips), which are widely used in embedded devices (such as IoT gateways), industrial control terminals, high-performance servers, and other scenarios.

[0003] With the diversification of hardware forms, the communication requirements between the host and the SM3 / SM4 national cryptographic hardware modules are becoming increasingly complex: embedded scenarios need to call the SoC's built-in ASIC through low-speed interfaces such as UART / I2C / SPI, industrial scenarios need to access on-chip hardware modules through the AMBA bus (AXI / AHB), and high-performance scenarios need to call external hardware acceleration cards through PCIe. However, existing technologies focus on algorithm optimization for single hardware forms, and the calling mechanism in heterogeneous processor modes has obvious shortcomings: the interface protocols are not unified (such as serial port, AMBA bus, PCIe, etc.), and the control of hardware modules depends on complex timing signal configurations, making it difficult for existing hardware modules to quickly adapt to different host scenarios and failing to fully realize the value of hardware acceleration. At the same time, different application scenarios such as wireless LANs, embedded devices, and high-performance servers have significantly different requirements for the communication interface, transmission rate, and reliability between the host and hardware modules, and existing solutions lack a unified instruction translation and interface adaptation mechanism, and do not clearly define the data return path after computation and the host-side adaptation logic.

[0004] Deficiencies and shortcomings of existing technologies 1. Poor hardware form factor compatibility Existing solutions have interface signal definitions and timing logic that are deeply tied to specific hardware (e.g., only compatible with a certain brand of FPGA or a certain model of SoC ASIC). When changing hardware form factors, the core control code needs to be redesigned. For example, the SM4 module adapted to Xilinx FPGAs has reset signal timing and data valid signal width that are completely incompatible with TSMC's 28nm ASIC. After changing the hardware, the above timing drive logic needs to be redesigned, resulting in extremely high hardware reuse costs.

[0005] 2. Insufficient interface protocol compatibility The system fails to cover mainstream interfaces across multiple scenarios: There is a lack of unified adaptation bridges for UART / I2C in embedded scenarios, AMBA bus in industrial scenarios, and PCIe interfaces in high-performance scenarios. For example, some industrial-grade SM3 hardware modules only support the AMBAAXI4 bus. If they are to be used in IoT terminals (UART interface), a separate interface conversion submodule needs to be developed, extending the development cycle by 3-4 weeks, and compatibility is difficult to guarantee.

[0006] 3. High call complexity The host computer needs to manually configure the timing signals of the hardware modules (such as data valid signal, packet end signal, ready signal, etc.), and the signal levels (FPGA commonly uses 3.3V, ASIC mostly uses 1.8V) and delay characteristics (ASIC has a single-cycle response, FPGA requires 2-3 cycles to stabilize) vary significantly among different hardware. Developers need to write separate drivers for each type of hardware, resulting in a high rate of timing conflicts during debugging and low development efficiency. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method and related apparatus for translating instructions of the national cryptographic SM3 / SM4 algorithm hardware module with multiple interfaces compatible. This method and related apparatus have the characteristics of strong hardware form compatibility, high interface protocol adaptability and low calling complexity.

[0008] To achieve the above objectives, this invention discloses a hardware module instruction translation system for the national cryptographic SM3 / SM4 algorithm that is compatible with multiple interfaces, including a host end, a translation chip end, and a hardware algorithm end. The host end and the translation chip end exchange information, and the translation chip end and the hardware algorithm end exchange information.

[0009] Furthermore, the translation chip includes a multi-interface protocol conversion layer, an instruction translation core module, a hardware form factor adaptation submodule, and a configuration exception handling module for exception detection and processing. The host terminal interacts with the instruction translation core module via the multi-interface protocol conversion layer, and the instruction translation core module interacts with the hardware algorithm terminal via the hardware form factor adaptation submodule.

[0010] Furthermore, the multi-interface protocol conversion layer unifies the host-side SPI / UART / I2C / AMBA / PCIe interface protocols, adapts to low-speed interfaces, on-chip bus interfaces, and high-speed interfaces, and achieves protocol unification, timing synchronization, and data buffering.

[0011] Furthermore, the instruction translation core module parses the instructions from the host side, generates general hardware control signals, manages the data transmission process, and simultaneously receives the hardware calculation results transmitted by the hardware form adaptation submodule, generates a standardized response frame of "result identifier + data length + calculation result", and transmits it to the multi-interface protocol conversion layer through the internal standard bus.

[0012] Furthermore, the hardware form factor adaptation submodule adjusts its interface signals and timing parameters to adapt to FPGA / ASIC, while converting the hardware calculation results into a standard internal data format and sending them synchronously to the instruction translation core module.

[0013] Furthermore, the configuration and exception handling module provides parameter configuration, exception detection and recovery functions.

[0014] Furthermore, the host side is responsible for sending instructions, receiving results, and writing data back.

[0015] This invention discloses a hardware module instruction translation method for the national cryptographic SM3 / SM4 algorithm that is compatible with multiple interfaces, including: The host sends command 0x7 to configure the translation chip registers; The host sends the 0x1 command to configure hardware parameters; The host sends the 0x2 command three times to set the encryption key; The host sends the 0x3 command to set the SM3 checksum mode; The host sends the 0x4 command to set the SM4 encryption / decryption mode; The host sends a 0x5 command to transmit the data to be processed. The hardware algorithm performs calculations based on the data to be processed, and after the calculations are completed, the results are sent back to the translation chip. The translation chip packages the calculation results and transmits them to the host.

[0016] This invention discloses a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the instruction translation method for the hardware module of the multi-interface compatible national cryptographic SM3 / SM4 algorithm.

[0017] This invention discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the instruction translation method for the hardware module of the multi-interface compatible national cryptographic SM3 / SM4 algorithm.

[0018] The present invention has the following beneficial effects: In specific operation, the multi-interface compatible SM3 / SM4 national cryptographic algorithm hardware module instruction translation method and related device of the present invention involves information interaction between the host end and the translation chip end, and information interaction between the translation chip end and the hardware algorithm end. The translation chip end includes a multi-interface protocol conversion layer, an instruction translation core module, a hardware form adaptation sub-module, and a configuration exception handling module for exception detection and processing. By covering multiple interfaces and multiple protocols through the multi-interface protocol conversion layer, it has the characteristics of strong hardware form compatibility, high interface protocol adaptability, and low calling complexity, making it highly practical. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a system block diagram of the present invention; Figure 2 This is an internal diagram of the multi-interface protocol conversion layer; Figure 3 This is a flowchart of the method of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] In the description of this invention, it should be understood that the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0023] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0024] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " in this invention generally indicates that the preceding and following objects have an "or" relationship.

[0025] It should be understood that although terms such as first, second, third, etc., may be used in the embodiments of the present invention to describe the preset range, these preset ranges should not be limited to these terms. These terms are only used to distinguish the preset ranges from one another. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0026] Depending on the context, the word "if" as used here can be interpreted as "when," "when," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if determination" or "if detection (of the stated condition or event)" can be interpreted as "when determination," "in response to determination," "when detection (of the stated condition or event)," or "in response to detection (of the stated condition or event)."

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0028] The accompanying drawings illustrate various structural schematic diagrams according to embodiments disclosed in this invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0029] Example 1 refer to Figure 1 and Figure 2 The multi-interface compatible national cryptographic SM3 / SM4 algorithm hardware module instruction translation system of the present invention includes a host end, a translation chip end and a hardware algorithm end; Host side: Includes the calling software layer (driver + application) and host interface controller, which is responsible for sending instructions, receiving results and writing data back.

[0030] Specifically, at the software layer: the driver is developed based on a standardized instruction set, without needing to distinguish hardware form. It achieves adaptation through configuration registers (0x01 interface type, 0x10 hardware form) and provides a unified API for applications to call. The application initiates encryption / verification requests according to business needs, receives the result data parsed by the driver, and writes the specified data back to the target (memory / TXT document / register).

[0031] Host interface controller: Supports UART / I2C / AMBA / PCIe interfaces, enabling bidirectional communication with the multi-interface protocol conversion layer in the translation chip and matching the corresponding interface protocol format.

[0032] Data write-back mechanism: By default, write-back is written back to a specified address in the host's physical memory (suitable for high-concurrency scenarios); supports writing to local TXT documents (suitable for log retention scenarios); key results can be written to a specified register on the host (suitable for on-chip collaborative processing scenarios), and the write-back target is configured by the application.

[0033] The translation chip includes a multi-interface protocol conversion layer, an instruction translation core module, a hardware form factor adaptation submodule, and a configuration exception handling module.

[0034] Multi-interface protocol conversion layer: used to unify the host-side SPI / UART / I2C / AMBA / PCIe interface protocols to adapt to different application scenarios.

[0035] Specifically: The multi-interface protocol conversion layer supports various interface types; It covers three mainstream scenarios and is not tied to hardware form factor: Low-speed interfaces: UART (baud rate 9600~115200bps, compatible with embedded SoC ASIC), I2C; On-chip bus interfaces: AMBA AXI4-Lite (control signal transmission), AMBA AHB (high-speed data transmission, adapted to SoC on-chip ASIC); High-speed interface: PCIe 3.0 / 4.0 (x1 lane, supports DMA, compatible with external FPGA / ASIC accelerator cards).

[0036] The core functions of the multi-interface protocol conversion layer are: Protocol unification: Convert the frame formats of different interfaces (UART start / stop bits, AXI burst transmission, PCIeTLP packets) into an internal standard bus protocol of "address + data + control signals" to eliminate interface differences; Timing synchronization: The asynchronous FIFO solves the problem of cross-clock domain between the host and hardware modules (100-250MHz). The FIFO depth is dynamically configured according to the interface type (1-8KB for high-speed interfaces and 128B for low-speed interfaces). The host can manually overwrite the configuration through the 0x0C register to avoid data loss. Data buffer: High-speed interfaces are configured with scalable FIFOs to balance the high throughput requirements of ASICs, while low-speed interfaces are configured with small-capacity buffers to reduce resource consumption and adapt to the transmission rate differences of different hardware. Easy configuration: The host selects the interface type (00=UART, 11=I2C, 01=AXI4-Lite, 10=PCIe) through bits [1:0] of the 0x01 address register without modifying the core code, and the configuration response takes ≤1 clock cycle.

[0037] The instruction translation core module is used to parse instructions from the host side, generate general hardware control signals, and manage the data transmission process.

[0038] The design adopts a standardized instruction format of "4-bit opcode + 60-bit parameters," covering functions such as algorithm operation, hardware configuration, and exception recovery. It supports derivative algorithm extensions. The SM3 / SM4 instruction definitions are shown in Table 1. Table 1

[0039] The state machine of the instruction translation core module has been optimized as follows: Initial state: waiting for commands (receiving all instructions, regardless of hardware configuration); Hardware configuration status: After receiving the 0x01 instruction, load the timing parameters of the corresponding hardware, such as ASIC 1 cycle delay and FPGA 2 cycle delay; Abnormal state: Compatible with ASIC fault signals and FPGA configuration error signals, locking data transmission; Timing adaptation: The state transition delay is configured through register 0x06 to avoid timing conflicts caused by hardware differences; Parallel processing: Data reception (interface layer) and hardware transmission (adaptation layer) are pipelined in parallel to adapt to the high throughput requirements of ASICs and the flexible scheduling requirements of FPGAs.

[0040] The result processing function of the instruction translation core module is as follows: It receives the calculation results transmitted by the hardware form adaptation submodule, generates a standardized response frame of "result identifier + data length + calculation result", and transmits it to the multi-interface protocol conversion layer through the internal standard bus.

[0041] Hardware form factor adaptation submodule: used to dynamically adjust interface signals and timing parameters, compatible with FPGA / ASIC.

[0042] The core functions of the hardware form factor adaptation submodule are: decoupling instruction translation logic from hardware characteristics, which is achieved through register configuration without modifying the core code; adjusting interface signals and timing parameters in the downlink direction to adapt to FPGA / ASIC; and converting hardware calculation results into standard internal data format in the uplink direction and sending them synchronously to the instruction translation core module.

[0043] The configurable parameters (register addresses 0x10~0x1F) of the hardware form factor adaptation submodule include hardware form factor identifiers, signal level adaptation parameters, and data format conversion rules to cover bidirectional transmission adaptation requirements.

[0044] Table 2

[0045] The configuration and exception handling module provides parameter configuration, exception detection and recovery functions to ensure cross-morphological stability.

[0046] The general configuration register group (addresses 0x00~0x0F) contains parameters such as module enable, interface type selection, timeout threshold configuration, status transition delay configuration, and data write-back target selection.

[0047] Table 3

[0048] The general exception handling mechanism is as follows: Exception types and codes: 0x01: Instruction invalid (instruction code undefined); 0x02: Abnormal data length (e.g., SM4 key is less than 128 bits); 0x03: Transmission timeout (exceeded the 0x03 register configuration threshold); 0x04: Hardware failure (ASIC fault, FPGA configuration error); 0x05: FIFO overflow / empty read (rate mismatch); 0x06: Abnormal key format (SM4 key is 128 bits but the reserved bits are not 0, or the format does not conform to the national cryptographic standard). 0x07: Interface protocol format error (the received interface frame format is invalid); 0x08: Write-back target unavailable (write-back TXT has no file system or register address out of bounds); Anomaly response process: Detect an anomaly → Enter "abnormal state" → Lock data transmission to prevent the error from spreading; Return an "exception code + hardware form factor" to the host (to facilitate hardware problem location), with a response time of ≤2 clock cycles; Recovery method: The host sends a "reset" command, or automatically resets after a timeout (threshold is configurable).

[0049] Example 2 refer to Figure 2 The multi-interface compatible Chinese cryptographic SM3 / SM4 algorithm hardware module instruction translation method of the present invention includes the following steps: 1) Host configuration: The SoC processor sends the 0x7 command to write to the register through the AXI interface, 0x00=1 (module enable), 0x01=01 (interface type = AXI4-Lite), 0x10=0 (hardware form = ASIC), 0x11=1 (reset signal = active low), 0x03=00 (data write-back target = memory); 2) Hardware configuration: The host sends 0x01 (hardware configuration instruction) + 0x000001 (ASIC timing identifier) ​​to load ASIC parameters (status delay of 1 cycle, valid signal is always valid). 3) Key configuration: The host sends 0x05 (key instruction) + 128-bit key in 3 parts (52 bits each time, padded to the last time), the chip caches the key and triggers the ASIC initialization signal (which remains valid). 4) Encrypted startup: The host sends 0x04 (encryption command) + 0x01 (CBC encryption mode) + 0x01 (PKCS#7 padding) to set the chip to encryption mode; 5) Data transmission and processing: The host sends 0x11 (packet instruction) + 128 bits of plaintext, and the chip sends the plaintext to the ASIC block port, triggering a processing signal; 6) Result feedback: After the ASIC completes the calculation, it outputs a completion signal and transmits the encrypted data to the hardware form factor adaptation submodule. After format adaptation, it is sent to the instruction translation core module to generate a standardized response frame. The frame is then converted into an AXI burst packet through the multi-interface protocol conversion layer and transmitted to the host interface controller. 7) Data write-back: The host calls the software to parse the response frame and write the ciphertext to the preset memory address; 8) Abnormal recovery: If the ASIC triggers a fault (abnormal 0x04), the chip returns "0x04+0x00" (abnormal code + hardware identifier), and the host sends 0x00 (reset command) to recover.

[0050] This invention has the following characteristics: Multi-form compatibility and significantly reduced reuse costs: By adapting the hardware form factor to the sub-module, it can be compatible with the SoC's built-in ASIC and external FPGA without modifying the core code. The hardware reuse cost is almost zero, and the chip can be directly adapted to different hardware scenarios.

[0051] Multi-interface full coverage, greatly expanding the application scope: Supports UART / AMBA / PCIe three types of interfaces, which can be seamlessly deployed in embedded (SoC ASIC), industrial (on-chip bus), and high-performance (PCIe accelerator card) scenarios without the need for additional development of conversion sub-modules, greatly shortening the development cycle.

[0052] Improved ease of use and lower development threshold: The host only needs to send standardized instructions, without needing to pay attention to hardware form differences (reset level, timing delay); the unified host-side software calling and data write-back mechanism reduces the workload of driver development and adaptation, and greatly improves debugging efficiency.

[0053] End-to-end connectivity ensures efficient and reliable data transmission: a clearly defined data return path, symmetrically designed with the downlink transmission link, guarantees that calculation results are delivered to the host quickly and accurately; coverage of 5 common anomalies ensures business continuity and avoids interruptions in data transmission and processing.

[0054] Highly flexible and adaptable, supporting technology upgrades: Configurable parameters adapt to different needs. ASICs improve throughput by "always enabling clock", while FPGAs save resources by "enabling clock during data transmission". The data write-back target can be selected as needed. Reserved expansion space, supporting derivative algorithms such as SM3-HMAC and SM4-CTR. Adding new hardware forms only requires expanding the 0x08-0x0F register configuration, without refactoring the core.

[0055] Fully unleash performance and maximize hardware potential: Optimize bidirectional transmission logic for hardware characteristics, use asynchronous FIFO dynamic configuration and pipelined parallel processing to improve ASIC transmission efficiency, reduce FPGA scheduling latency, and increase speed by 20%-60%.

[0056] Example 3 A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of a hardware module instruction translation method for the multi-interface compatible national cryptographic SM3 / SM4 algorithm. For example, the steps include: the host sending a 0x7 command to configure the translation chip register; the host sending a 0x1 command to configure hardware parameters; the host sending three 0x2 commands to set the encryption key; the host sending a 0x3 command to set the SM3 verification mode or a 0x4 command to set the SM4 encryption / decryption mode; the host sending a 0x5 command to transmit data to be processed; the hardware algorithm performing calculations based on the data to be processed, and after completion, sending the calculation result back to the translation chip; and the translation chip packaging the calculation result and transmitting it to the host. The memory may include main memory, such as high-speed random access memory, or it may also include non-volatile memory, such as at least one disk storage device. The processor, network interface, and memory are interconnected via an internal bus, which can be an industry standard architecture bus, a peripheral component interconnection standard bus, an extended industry standard architecture bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory is used to store programs; specifically, the program may include program code, which includes computer operation instructions. The memory may include main memory and non-volatile memory, and provides instructions and data to the processor.

[0057] Example 4 A computer-readable storage medium stores a computer program. When executed by a processor, the computer program implements the steps of a hardware module instruction translation method for a multi-interface compatible national cryptographic SM3 / SM4 algorithm. For example, the steps include: the host sending a 0x7 command to configure the translation chip register; the host sending a 0x1 command to configure hardware parameters; the host sending three 0x2 commands to set the encryption key; the host sending a 0x3 command to set the SM3 verification mode or a 0x4 command to set the SM4 encryption / decryption mode; the host sending a 0x5 command to transmit data to be processed; the hardware algorithm performing calculations based on the data to be processed, and after completion, sending the calculation result back to the translation chip; and the translation chip packaging the calculation result and transmitting it to the host. Specifically, the computer-readable storage medium includes, but is not limited to, volatile memory and / or non-volatile memory. The volatile memory may include random access memory (RAM) and / or cache memory, etc. The non-volatile memory may include read-only memory (ROM), hard disk, flash memory, optical disk, magnetic disk, etc.

[0058] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0059] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0060] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0061] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0062] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and disclosure of the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.

[0063] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is limited only by the appended claims.

[0064] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the present invention. Any simple modifications, alterations, or equivalent structural changes made to the above embodiments based on the technical essence of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A hardware module instruction translation system for the national cryptographic SM3 / SM4 algorithm with multiple interfaces compatible, characterized in that, It includes a host, a translation chip, and a hardware algorithm. The host and the translation chip interact with each other, and the translation chip interacts with the hardware algorithm.

2. The multi-interface compatible SM3 / SM4 national cryptographic algorithm hardware module instruction translation system according to claim 1, characterized in that, The translation chip includes a multi-interface protocol conversion layer, an instruction translation core module, a hardware form factor adaptation submodule, and a configuration exception handling module for exception detection and processing. The host terminal interacts with the instruction translation core module through the multi-interface protocol conversion layer, and the instruction translation core module interacts with the hardware algorithm terminal through the hardware form factor adaptation submodule.

3. The multi-interface compatible SM3 / SM4 national cryptographic algorithm hardware module instruction translation system according to claim 2, characterized in that, The multi-interface protocol conversion layer unifies the host-side SPI / UART / I2C / AMBA / PCIe interface protocols, adapts to low-speed interfaces, on-chip bus interfaces and high-speed interfaces, and achieves protocol unification, timing synchronization and data buffering.

4. The multi-interface compatible SM3 / SM4 national cryptographic algorithm hardware module instruction translation system according to claim 2, characterized in that, The instruction translation core module parses the instructions from the host side, generates general hardware control signals, manages the data transmission process, and simultaneously receives the hardware calculation results transmitted by the hardware form adaptation submodule. It generates a standardized response frame consisting of "result identifier + data length + calculation result" and transmits it to the multi-interface protocol conversion layer via the internal standard bus.

5. The multi-interface compatible SM3 / SM4 national cryptographic algorithm hardware module instruction translation system according to claim 2, characterized in that, The hardware form factor adaptation submodule automatically adjusts the interface signals and timing parameters to adapt to FPGA / ASIC, and at the same time converts the hardware calculation results into a standard internal data format and sends them synchronously to the instruction translation core module.

6. The multi-interface compatible SM3 / SM4 national cryptographic algorithm hardware module instruction translation system according to claim 2, characterized in that, The configuration and exception handling module provides parameter configuration, exception detection and recovery functions.

7. The multi-interface compatible SM3 / SM4 national cryptographic algorithm hardware module instruction translation system according to claim 2, characterized in that, The host is responsible for sending commands, receiving results, and writing data back.

8. A method for translating instructions for a hardware module of the national cryptographic SM3 / SM4 algorithm that is compatible with multiple interfaces, characterized in that, include: The host sends command 0x7 to configure the translation chip registers; The host sends the 0x1 command to configure hardware parameters; The host sends the 0x2 command three times to set the encryption key; The host sends the 0x3 command to set the SM3 checksum mode; The host sends the 0x4 command to set the SM4 encryption / decryption mode; The host sends a 0x5 command to transmit the data to be processed. The hardware algorithm performs calculations based on the data to be processed, and after the calculations are completed, the results are sent back to the translation chip. The translation chip packages the calculation results and transmits them to the host.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the instruction translation method for the hardware module of the multi-interface compatible national cryptographic SM3 / SM4 algorithm as described in claim 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the instruction translation method for the hardware module of the multi-interface compatible national cryptographic SM3 / SM4 algorithm as described in claim 8.

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