Integration process method of heterojunction bipolar transistor and logic device
By depositing an unetched second sidewall material layer on the logic device to protect the logic device, and simultaneously defining the outer base region of the heterojunction bipolar transistor and the sidewall structure of the logic device in a single photolithography process, the problems of logic device damage and high mask cost are solved, and a highly efficient and simplified integration process is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HUA HONG SEMICON WUXI LTD
- Filing Date
- 2026-02-12
- Publication Date
- 2026-06-09
AI Technical Summary
In existing integration processes, the integration of heterojunction bipolar transistors and logic devices presents problems such as damage to logic devices from subsequent processes, high process complexity, and high mask costs.
By depositing a second sidewall material layer after the logic device is initially formed and protecting the logic device without etching, the outer base region of the heterojunction bipolar transistor and the sidewall structure of the logic device are defined simultaneously using a single photolithography process, simplifying the process flow and reducing mask costs.
It effectively protects logic devices from damage during subsequent processes, simplifies the integration process, reduces mask costs, and improves manufacturing efficiency.
Smart Images
Figure CN122180133A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to an integration process method for heterojunction bipolar transistors and logic devices. Background Technology
[0002] In the design and manufacturing of semiconductor integrated circuits, heterojunction bipolar transistors (HBTs) are widely used due to their excellent high-frequency performance. For example, silicon germanium heterojunction bipolar transistors (SiGe HBTs) utilize the band difference between the emitter and base to increase the base doping concentration while maintaining current amplification, thereby increasing the device's maximum oscillation frequency (fmax).
[0003] In traditional integrated circuit design, to minimize the impact of logic processes on HBT devices, the process steps for HBT modules are typically scheduled as late as possible. However, this approach has significant drawbacks: firstly, after the sidewall structure is formed, the gate region and active region of the logic device are continuously exposed to subsequent complex HBT-related processes (such as sacrificial layer deposition, base polysilicon deposition, and multiple etching processes), making them highly susceptible to physical damage or performance degradation; secondly, in existing processes, defining the outer base region of the HBT and forming the sidewall structure of the logic device usually requires two separate photomasks and corresponding etching processes, increasing manufacturing costs and process complexity.
[0004] Therefore, how to provide an integrated solution that is more compatible with logic device processes, reduces mutual interference, and does not increase mask costs is an urgent problem to be solved in this field. Summary of the Invention
[0005] The problem this application aims to solve is how to effectively protect logic devices from damage in subsequent processes and simplify the integration process of heterojunction bipolar transistors and logic devices while reducing mask costs.
[0006] To achieve the above and other related objectives, the present invention provides an integration process method for heterojunction bipolar transistors and logic devices, comprising the following steps:
[0007] Step 1: Provide a substrate and form the well region, gate structure, first sidewall structure, and low-doped drain injection region of the logic device on the substrate;
[0008] Step 2: Deposit a second sidewall material layer in the area where the logic device is located. Use the second sidewall material layer to cover and protect the area where the logic device is located, and do not perform an etching process on the second sidewall material layer at this time.
[0009] Step 3: Form a sacrificial material layer on the second sidewall material layer;
[0010] Step 4: Perform the first photolithography process to form a photoresist pattern, and use it as a mask to sequentially etch away the sacrificial material layer and the second sidewall material layer in the heterojunction bipolar transistor region to expose the active region of the heterojunction bipolar transistor region.
[0011] Step 5: Form a base material layer with a continuous capping layer on the active region and other surrounding substrate regions, and form an emitter structure on the base material layer;
[0012] Step 6: Perform a second photolithography process to form a photoresist pattern. Use the photoresist pattern to sequentially etch the base material layer, sacrificial material layer, and second sidewall material layer to simultaneously form the outer base structure of the heterojunction bipolar transistor and the second sidewall structure of the logic device.
[0013] Preferably, in step one, the substrate includes a shallow trench isolation structure for isolating the region where the logic device is located from the region where the heterojunction bipolar transistor is located.
[0014] Preferably, in step one, the gate structure includes a gate insulating dielectric layer and a gate polysilicon layer located on the gate insulating dielectric layer.
[0015] Preferably, in step two, the heterojunction bipolar transistor is a germanium-silicon heterojunction bipolar transistor.
[0016] Preferably, in step two, the second sidewall material layer is specifically a stacked structure composed of a silicon oxide layer and a silicon nitride layer.
[0017] Preferably, in step three, the sacrificial material layer is specifically a sacrificial oxide layer formed by deposition growth.
[0018] Preferably, in step five, the base material layer is a germanium-silicon epitaxial layer formed by a non-selective epitaxial process.
[0019] Preferably, in step five, the base region material layer includes an inner base region germanium-silicon epitaxial layer located on the active region, and an outer base region polycrystalline silicon layer covering other regions outside the active region.
[0020] Preferably, in step five, the polycrystalline silicon layer in the outer base region is specifically a polycrystalline silicon layer formed during epitaxial growth.
[0021] Preferably, in step five, before forming the emitter structure, the method further includes depositing an etch stop layer and a dielectric layer sequentially from bottom to top on the base material layer.
[0022] Preferably, in step five, both the etching stop layer and the dielectric layer are made of silicon oxide.
[0023] Preferably, in step five, forming the emitter structure further includes forming an emitter sidewall structure on the sidewall of the dielectric layer.
[0024] Preferably, in step five, the emitter structure is specifically composed of epitaxial emitter polycrystalline silicon that fills the emitter sidewall structure and is located on the dielectric layer.
[0025] Preferably, in step five, forming the emitter structure further includes a selective etching process for defining the shape of the emitter structure.
[0026] Preferably, in step six, etching the base region material layer specifically involves etching the polysilicon layer to define the outer base region of the heterojunction bipolar transistor.
[0027] Preferably, in step six, when etching the second sidewall material layer, a silicon nitride layer is used as a protective layer to prevent the etching process from damaging the logic device.
[0028] Preferably, after step six, the process further includes performing a source / drain heavy doping implantation process and a thermal activation process on the logic device.
[0029] As described above, the integration process method for heterojunction bipolar transistors and logic devices of the present invention has the following beneficial effects:
[0030] By depositing a second sidewall material layer after the initial formation of the logic device but not immediately etching it, the logic device remains physically shielded throughout the subsequent complex epitaxial growth, cleaning, and etching processes of the heterojunction bipolar transistor. This effectively avoids damage to the logic gate and active region caused by the process environment, ensuring the stability of the logic device's electrical parameters. Simultaneously, the core of this invention lies in utilizing the etching mask for the outer base region of the heterojunction transistor. In a single photolithography process, multi-stage in-situ etching simultaneously defines the base region shape and forms the logic region sidewalls, achieving highly efficient integration without increasing the cost of additional photomasks. This self-aligned synchronous definition scheme not only eliminates the cumulative registration error between different masks but also simplifies the manufacturing process. Attached Figure Description
[0031] Figure 1 The diagram shows a schematic flow of the integration process of heterojunction bipolar transistors and logic devices according to the present invention.
[0032] Figure 2 The diagram shown is a structural schematic of the present invention after the formation of the second sidewall material layer;
[0033] Figure 3 The diagram shows the structure of the present invention after forming a heterojunction bipolar transistor window.
[0034] Figure 4 The diagram shown is a schematic representation of the structure of the heterojunction bipolar transistor of the present invention after the formation of the heterojunction bipolar transistor structure.
[0035] Figure 5The diagram shown is a schematic representation of the structure after the simultaneous formation of the outer base region structure and the second sidewall of the logic device according to the present invention. Detailed Implementation
[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0037] refer to Figure 1 The integration process of heterojunction bipolar transistors and logic devices includes steps one through six.
[0038] Step 1: Provide a substrate 100, and form a well region, gate structure, first sidewall structure 106, and low-doped drain implantation region of a logic device on the substrate 100, forming a structure as follows: Figure 2 The structure is shown. First, a base substrate 100 is prepared, and the logic device region and the heterojunction bipolar transistor region are defined.
[0039] In some embodiments, a shallow trench isolation structure 101 is provided on the substrate 100 to achieve isolation between the logic device region and the heterojunction bipolar transistor region. The substrate 100 includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.
[0040] The shallow trench isolation structure 101 is made of silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass, or a low-dielectric-constant dielectric material. The formation method includes performing plasma anisotropic etching on the substrate 100 to form shallow trenches of a determined depth, followed by filling the dielectric material using high-density plasma chemical vapor deposition, tape chemical vapor deposition, or subatmospheric pressure chemical vapor deposition. After filling, chemical mechanical planarization is used to flatten the surface and align it with the top of the substrate 100. The shallow trench isolation structure 101 enables electrical independence between the logic region and the heterojunction region, suppressing parasitic interference and minority carrier injection between different functional modules.
[0041] In some embodiments, the gate structure includes a gate insulating dielectric layer 104 and a gate polysilicon layer 105 located on the gate insulating dielectric layer 104. The gate insulating dielectric layer 104 is prepared by thermal oxidation, in-situ vapor growth, atomic layer deposition, or chemical vapor deposition. The material can be selected from silicon dioxide, silicon oxynitride, silicon nitride, or high-dielectric-constant dielectrics such as metal oxides, metal silicates, and metal oxynitrides containing hafnium, zirconium, aluminum, lanthanum, or yttrium. In addition to polysilicon materials, the gate layer can contain metal gate materials composed of titanium, tantalum, aluminum, tungsten, ruthenium, cobalt, or their nitrides in replacement effect gate processes or metal gate structures. Using a high-dielectric-constant dielectric can effectively increase the gate coupling capability, and the threshold voltage of the logic device can be precisely adjusted by controlling the work function of the gate layer 105.
[0042] The first sidewall structure 106 is formed by depositing a conformal thin film on the gate sidewall and performing an etch-back process. The material can be selected from silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, or silicon carbonitride. The low-doped drain implantation region is implanted with phosphorus, arsenic, antimony, boron, or boron difluoride ions according to the device polarity. This region can smooth the active region electric field gradient at the gate edge, mitigating the reliability degradation risk caused by hot carriers.
[0043] Step 2: Deposit a second sidewall material layer 107 in the area where the logic device is located. The second sidewall material layer 107 covers and protects the area where the logic device is located. At this stage, no etching process is performed on the second sidewall material layer 107, forming a layer as shown in the image. Figure 2 The structure shown is such that the deposited second sidewall material layer 107 covers the logic gate 105, the first sidewall structure 106, and the surface of the logic active region in the form of a conformal interconnect film.
[0044] In some embodiments, the heterojunction bipolar transistor is specifically a germanium-silicon heterojunction bipolar transistor. By introducing germanium components into the base region material, the germanium-silicon heterojunction transistor can improve carrier injection efficiency, thereby significantly increasing the device's cutoff frequency. Furthermore, depending on different process integration requirements, the semiconductor material system used to fabricate the heterojunction bipolar transistor can also be selected from III-V compound semiconductors (e.g., gallium arsenide GaAs, indium phosphide InP, indium gallium arsenide InGaAs, or gallium nitride GaN) or IV-IV compounds (e.g., silicon carbide SiC) to utilize the high electron mobility or high breakdown voltage characteristics of these wide-bandgap materials to meet the performance requirements of millimeter-wave, radio frequency power amplification, or high-voltage applications.
[0045] In some embodiments, the second sidewall material layer 107 includes a protective layer material that has etching selectivity with the sacrificial material layer 401.
[0046] In some embodiments, the second sidewall material layer 107 is specifically a stack composed of a silicon oxide layer 107-1 and a silicon nitride layer 107-2 as a protective layer material. This layer is formed by low-pressure chemical vapor deposition or atomic layer deposition. Besides the silicon nitride layer 107-2, the protective layer material can also be replaced with low-stress silicon carbonitride, silicon carbonitride oxycarbonate, nitrogen boride, or a metal nitride layer containing titanium or aluminum. The specific deposition thickness range is to be determined. Utilizing the unetched second sidewall material layer 107 as a protective barrier ensures that the logic device is protected during subsequent complex heterojunction region windowing and epitaxial growth environments, guaranteeing that the critical layer morphology of the logic device is not damaged by subsequent chemical cleaning or physical impact.
[0047] Step 3: A sacrificial material layer 401 is formed on the second sidewall material layer 107. The sacrificial material layer 401 extends laterally and completely covers the logic device area.
[0048] In some embodiments, the sacrificial material layer 401 is specifically composed of sacrificial silicon oxide. The sacrificial material layer 401 is deposited using plasma-enhanced chemical vapor deposition, atmospheric pressure chemical vapor deposition, or spin-coating of an insulating dielectric. Besides silicon oxide, the sacrificial material layer 401 can also be an oxide layer made of tetraethoxysilane, phosphosilicate glass, carbon-doped silicon oxide, or spin-coated organic polymers. The sacrificial material layer 401 increases the physical coverage thickness above the logic device region, providing a buffer for subsequent multi-step etching and ensuring that the gate 105 of the logic device is not bombarded by plasma.
[0049] Step 4: Perform the first photolithography process to form a photoresist pattern 501, and use it as a mask to sequentially etch and remove the sacrificial material layer 401 and the second sidewall material layer 107 in the heterojunction bipolar transistor region, so as to expose the active region of the heterojunction bipolar transistor region, forming as shown in the image. Figure 3The structure shown is an example of this process. This process precisely defines the formation window for the heterojunction transistor, provided the logic region is fully protected by the sacrificial material layer 401. By adjusting the etch selectivity, precise shutdown of the substrate 100 surface is achieved, ensuring that the exposed active region surface has low lattice defects and minimal impurity contamination, providing superior interface conditions for subsequent high-quality epitaxial growth.
[0050] Step 5: A base material layer 403 is formed on the active region and other surrounding substrate regions, and an emitter structure 408 is formed on the base material layer 403, forming a structure as shown in the figure. Figure 4 The structure shown.
[0051] In some embodiments, the base material layer 403 is specifically a germanium-silicon epitaxial layer formed by an epitaxial process. It is grown using ultra-high vacuum chemical vapor deposition or reduced pressure vapor deposition techniques.
[0052] In some embodiments, the base region material layer 403 includes an inner base region germanium-silicon epitaxial layer 403-1 located on the active region, and an outer base region polycrystalline silicon layer 403-2 that extends continuously and covers other regions outside the active region.
[0053] In some embodiments, the outer base region polycrystalline silicon layer 403-2 is specifically a polycrystalline silicon layer formed during epitaxial growth. Since the crystal formed on the exposed monocrystalline silicon surface by the non-selective epitaxial process is a monocrystalline structure, thus constituting the inner base region 403-1, while the crystal formed on the amorphous surface such as the sacrificial layer 401 is a polycrystalline structure, thus constituting the outer base region 403-2.
[0054] In some embodiments, before forming the emitter structure 408, the method further includes depositing an etch stop layer 404 and a dielectric layer 406 sequentially from bottom to top on the base material layer 403.
[0055] In some embodiments, the etching stop layer 404 and the dielectric layer 406 are both made of silicon oxide.
[0056] In some embodiments, forming the emitter structure 408 further includes forming an emitter sidewall structure 407 on the sidewall of the dielectric layer 406. The sidewall material may be selected from silicon nitride, silicon carbonitride, or silicon oxide.
[0057] In some embodiments, the emitter structure 408 is specifically composed of epitaxial polycrystalline silicon material. This layer achieves carrier transport through in-situ doping with phosphorus or arsenic. The emitter material can also be formed as carbon-containing polycrystalline silicon in a metal-organic vapor phase epitaxy.
[0058] In some embodiments, forming the emitter structure 408 further includes a selective etching process that defines the shape of the emitter structure 408. This step can define the lateral physical dimensions of the emitter, thereby optimizing the cutoff frequency and power gain.
[0059] Step Six: Perform a second photolithography process to form a photoresist pattern 502. Using the photoresist pattern 502, sequentially etch the base material layer 403, the sacrificial material layer 401, and the second sidewall material layer 107 to simultaneously form the outer base region structure of the heterojunction bipolar transistor and the second sidewall structure of the logic device, forming a structure as shown below. Figure 5 The structure shown.
[0060] In some embodiments, etching the base region material layer 403 specifically involves etching the polysilicon layer 403-2 to form an outer base region structure.
[0061] In some embodiments, when etching the second sidewall material layer 107, a protective layer material is used to prevent damage to the logic devices during the etching process. The core technical solution of this process is to use the same mask used for etching the base region to form a photoresist pattern 502. After etching the polysilicon layer 403-2 of the base region, without changing the mask, the pattern 502 is directly used to continue in-situ etching of the lower sacrificial material layer 401 and the second sidewall material layer 107. This process reuses the mask, simultaneously defining the shape of the heterojunction outer base region and forming the second sidewall structure (107-1 and 107-2) of the logic devices in a single photolithography step. This simultaneous definition scheme achieves the production goal of not increasing the cost of additional masking and eliminates the cumulative overlay error between different device masks. Since the second sidewall material layer 107 has remained completely covered in all previous heterojunction high-temperature processes until this step, it is only etched and shaped, effectively preventing the process environment from eroding the logic gate 105 and greatly improving the chip manufacturing efficiency.
[0062] In some embodiments, after step six, the process further includes: performing a source / drain heavy doping implantation process on the logic device; and performing a thermal activation process after the source / drain heavy doping implantation. High doses of phosphorus or boron impurities are implanted according to the device polarity. The thermal activation process employs rapid thermal annealing, laser annealing, or spike annealing. Because the main thermal processing steps are arranged after the heterojunction module is formed, the distribution gradient of germanium concentration in the base region can be effectively controlled, preventing excessive diffusion of impurity atoms. This integration timing can achieve high-performance activation of the logic device while maintaining the superior high-frequency transconductance characteristics of the heterojunction transistor.
[0063] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A method for integrating heterojunction bipolar transistors and logic devices, characterized in that, At least including: Step 1: Provide a substrate (100) and form a well region, gate structure (104, 105), first sidewall structure (106), and low-doped drain implantation region of a logic device on the substrate (100); Step 2: Deposit a second sidewall material layer (107) in the area where the logic device is located, and use the second sidewall material layer (107) to cover and protect the area where the logic device is located, without performing an etching process on the second sidewall material layer (107); Step 3: Form a sacrificial material layer (401) on the second sidewall material layer (107); Step 4: Perform the first photolithography process to form a photoresist pattern (501), and use it as a mask to sequentially etch away the sacrificial material layer (401) and the second sidewall material layer (107) in the heterojunction bipolar transistor region to expose the active region of the heterojunction bipolar transistor region. Step 5: Form a base material layer (403) on the active region and other surrounding substrate regions, and form an emitter structure (408) on the base material layer (403); Step 6: Perform a second photolithography process to form a photoresist pattern (502). Use the photoresist pattern (502) to sequentially etch the base material layer (403), the sacrificial material layer (401), and the second sidewall material layer (107) to simultaneously form the outer base structure of the heterojunction bipolar transistor and the second sidewall structure of the logic device.
2. The integration process method for heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step one, a shallow trench isolation structure (101) is provided on the substrate (100) to achieve isolation between the logic device region and the heterojunction bipolar transistor region.
3. The integration process method for heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step one, the gate structure includes a stacked structure consisting of a gate insulating dielectric layer (104) and a gate polysilicon layer (105) located on the gate insulating dielectric layer (104).
4. The integration process method for heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step two, the specific type of the heterojunction bipolar transistor is a germanium-silicon heterojunction bipolar transistor.
5. The integration process method for heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step two, the second sidewall material layer (107) includes a protective layer material that has etching selectivity with the sacrificial material layer (401).
6. The integration process method for heterojunction bipolar transistors and logic devices according to claim 5, characterized in that: In step two, the second sidewall material layer (107) is specifically a stack composed of a silicon oxide layer (107-1) and a silicon nitride layer (107-2) as the protective layer material.
7. The integration process method for heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step three, the sacrificial material layer (401) is specifically composed of sacrificial silicon oxide material.
8. The integration process method of heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step five, the base material layer (403) is specifically a germanium-silicon epitaxial layer formed by an epitaxial process.
9. The integration process method for heterojunction bipolar transistors and logic devices according to claim 8, characterized in that: In step five, the base region material layer (403) includes an inner base region germanium-silicon epitaxial layer (403-1) located on the active region, and an outer base region polycrystalline silicon layer (403-2) that extends continuously and covers other regions outside the active region.
10. The integration process method of heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step five, before forming the emitter structure (408), the method further includes: sequentially forming an etch stop layer (404) and a dielectric layer (406) on the base material layer (403).
11. The integration process method of heterojunction bipolar transistors and logic devices according to claim 10, characterized in that: In step five, the etching stop layer (404) and the dielectric layer (406) are both made of silicon oxide.
12. The integration process method of heterojunction bipolar transistors and logic devices according to claim 10, characterized in that: In step five, forming the emitter structure (408) further includes forming an emitter sidewall structure (407) on the sidewall of the dielectric layer (406).
13. The integration process method of heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: In step five, the emitter structure (408) is specifically made of epitaxial polycrystalline silicon material.
14. The integration process method of heterojunction bipolar transistors and logic devices according to claim 12, characterized in that: Step five also includes selectively etching the shape of the emitter structure (408) before the photoresist pattern (502) is defined according to the second photolithography process.
15. The integration process method of heterojunction bipolar transistors and logic devices according to claim 9, characterized in that: In step six, etching the base region material layer (403) specifically involves etching the outer base region polysilicon layer (403-2) to form the outer base region structure.
16. The integration process method of heterojunction bipolar transistors and logic devices according to claim 5 or 6, characterized in that, In step six, when etching the second sidewall material layer (107), the protective layer material is used to prevent the logic device from being damaged during the etching process.
17. The integration process method of heterojunction bipolar transistors and logic devices according to claim 1, characterized in that: After step six, the process further includes: performing a source / drain heavy doping implantation process on the logic device; and performing a thermal activation process after the source / drain heavy doping implantation.