Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: a bottom device structure including a first device and a first dielectric layer, the first device including a first gate structure and first source / drain regions located on both sides of the first gate structure; forming a first conductive plug within the bottom device structure, the first conductive plug penetrating the first dielectric layer along a first direction and located on the surface of the first source / drain regions, the first direction being perpendicular to the surface of the bottom device structure; forming two mutually discrete source / drain interconnect layers on the first dielectric layer, one source / drain interconnect layer located on the surface of the first conductive plug on one side; forming a second device on the first dielectric layer, the second device being stacked with the first device along the first direction, the second device including a second gate structure and second source / drain regions located on both sides of the second gate structure, one second source / drain region located on a source / drain interconnect layer, electrically connected to the first source / drain region of the lower layer, further improving the density advantage of CFET devices.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As semiconductor process nodes continue to push towards their physical limits, traditional two-dimensional planar miniaturization technology can no longer meet the development demands of high-performance, high-density integrated circuits. The industry is focusing on three-dimensional integration, further increasing integration density and improving device performance through three-dimensional stacking. Existing three-dimensional transistor structures include FinFETs and gate-all-around (GAA) transistors.

[0003] As chip area shrinks further, the need for even smaller cell heights necessitates smaller spacing between nFETs and pFETs within a standard cell. However, for fin field-effect devices and gate-all-around devices, process limitations restrict the spacing between these n and p devices. Complementary FETs (CFETs) vertically stack nFETs and pFETs, significantly reducing chip area and achieving integration. CFETs represent a potential technological trend following FinFETs and GAA devices.

[0004] However, the performance of existing CFET devices still needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure, comprising: a bottom device structure, the bottom device structure including a first device and a first dielectric layer located on the first device, the first device including a first gate structure and first source / drain regions located on both sides of the first gate structure, the first gate structure including a first gate; a first conductive plug located within the bottom device structure, the first conductive plug penetrating the first dielectric layer along a first direction and located on the surface of the first source / drain regions, the first direction being perpendicular to the surface of the bottom device structure; two mutually independent source / drain interconnect layers located on the first dielectric layer, one of the source / drain interconnect layers being located on one side of the surface of the first conductive plug; a second device located on the first dielectric layer, the second device being stacked with the first device along the first direction, the second device including a second gate structure and second source / drain regions located on both sides of the second gate structure, the second gate structure including a second gate, one of the second source / drain regions being located on one of the source / drain interconnect layers, so as to electrically connect it to the first source / drain region of the lower layer.

[0007] Optionally, it further includes: a second conductive plug located within the underlying device structure, the second conductive plug penetrating the first dielectric layer along the first direction and located on the first gate surface; the source-drain interconnect layer exposing the surface of the second conductive plug; the second gate structure further includes a second gate dielectric layer having a gate dielectric opening, the bottom of the gate dielectric opening exposing the surface of the second conductive plug, and the second gate located on the surface of the second gate dielectric layer and within the gate dielectric opening.

[0008] Optionally, it further includes: a second dielectric layer located on the surface of the underlying device structure and the second source / drain region, the second dielectric layer having a gate opening; the second gate dielectric layer being located on the sidewall and bottom surface of the gate opening.

[0009] Optionally, the second source / drain region is flush with the sidewall of the source / drain interconnect layer.

[0010] Optionally, the second device further includes a channel region extending along a second direction, a second gate crossing the channel region along a third direction, the second direction and the third direction being parallel to the surface of the underlying device structure and perpendicular to each other, and the second source / drain regions being located at opposite ends of the channel region in the second direction.

[0011] Optionally, the second device is a GAA device; the channel region is multilayered, including a plurality of channel layers stacked along the first direction, with a gate groove between two adjacent channel layers, and the second gate is also located in the gate groove.

[0012] Optionally, the second device is a FinFET device; the channel region is a single layer.

[0013] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a bottom device structure, the bottom device structure including a first device and a first dielectric layer on the first device, the first device including a first gate structure and first source / drain regions located on both sides of the first gate structure, the first gate structure including a first gate; forming a first conductive plug in the bottom device structure, the first conductive plug penetrating the first dielectric layer along a first direction and located on the surface of the first source / drain regions, the first direction being perpendicular to the surface of the bottom device structure; forming two mutually discrete source / drain interconnect layers on the first dielectric layer, one of the source / drain interconnect layers being located on one side of the surface of the first conductive plug; forming a second device on the first dielectric layer, the second device being stacked with the first device along the first direction, the second device including a second gate structure and second source / drain regions located on both sides of the second gate structure, the second gate structure including a second gate, one of the second source / drain regions being located on one of the source / drain interconnect layers, so as to electrically connect it to the first source / drain region of the lower layer.

[0014] Optionally, the method for forming the second device and the source-drain interconnect layer includes: forming an initial source-drain interconnect layer and a channel structure located on the surface of the first dielectric layer and the first conductive plug, the initial source-drain interconnect layer and the channel structure extending along a second direction; forming a dummy gate structure spanning the initial source-drain interconnect layer and the channel structure, the dummy gate structure including a dummy gate extending along a third direction, the second direction and the third direction being parallel to the surface of the underlying device structure and perpendicular to each other; forming a second source-drain region within the channel structure on both sides of the dummy gate structure; forming a second dielectric layer on the surface of the first dielectric layer and the second source-drain region, the second dielectric layer being located on the sidewall of the dummy gate structure and exposing the top surface of the dummy gate; removing the dummy gate to form an initial gate opening within the second dielectric layer; removing a portion of the initial source-drain interconnect layer exposed by the initial gate opening to form a gate opening, and forming two source-drain interconnect layers with the initial source-drain interconnect layer; forming a second gate within the gate opening.

[0015] Optionally, the channel structure is in the shape of an "I" and includes a first region and a second region. The second region is located on both sides of the first region in the second direction. Along the third direction, the width of the second region is greater than the width of the first region; the dummy gate spans the first region.

[0016] Optionally, the method for forming the second source / drain region includes: using the pseudo-gate structure as a mask, injecting doped ions into the channel structure, and using the channel structures on both sides of the pseudo-gate structure as the second source / drain region.

[0017] Optionally, the method for forming the second source / drain region includes: using the pseudo-gate structure as a mask, etching the channel structure to form a source / drain groove within the channel structure; forming an epitaxial layer within the source / drain groove, the epitaxial layer containing doped ions, and forming the second source / drain layer using the epitaxial layer.

[0018] Optionally, the second device further includes the channel region extending along a second direction, the second gate crossing the channel region along the third direction, and the second source / drain regions located at opposite ends of the channel region in the second direction; the method further includes forming the channel region with the channel structure or a portion of the channel structure enclosed by the second gate.

[0019] Optionally, the method for forming the initial source-drain interconnect layer and the channel structure includes: forming a first source-drain interconnect material layer on the surface of the first dielectric layer and the first conductive plug; forming a top-level device substrate, the top-level device substrate including a second source-drain interconnect material layer and an initial channel structure located on the surface of the second source-drain interconnect material layer; aligning the second source-drain interconnect material layer toward the first source-drain interconnect material layer, thereby bonding the bottom-level device structure and the top-level device substrate; patterning the initial channel structure, the first source-drain interconnect material layer, and the second source-drain interconnect material layer, forming the channel structure with the initial channel structure, and forming the initial source-drain interconnect layer with the first source-drain interconnect material layer and the second source-drain interconnect material layer.

[0020] Optionally, the second device is a GAA device; the channel region is multilayered, including a plurality of channel layers stacked along the first direction, with a gate recess between adjacent channel layers, and the second gate is also located within the gate recess; the initial channel structure is multilayered, including a plurality of sacrificial material layers and a plurality of channel material layers stacked along the first direction, with each sacrificial material layer located between adjacent channel material layers; the method of forming the channel structure further includes: forming a sacrificial layer with the sacrificial material layers, forming a channel layer with the channel material layers, the channel structure including a plurality of sacrificial layers and a plurality of channel layers; after forming the initial gate opening, and before forming the gate opening, the method further includes: removing the sacrificial layer exposed by the initial gate opening, and forming the gate recess between adjacent channel layers; the second gate is also formed within the gate recess.

[0021] Optionally, the second device is a FinFET device; the channel region is a single layer; the initial channel structure is a single layer; and the channel structure is a single layer.

[0022] Optionally, the method further includes: forming a second conductive plug within the underlying device structure before forming the source-drain interconnect layer, the second conductive plug penetrating the first dielectric layer along the first direction and located on the first gate surface; the source-drain interconnect layer exposing the surface of the second conductive plug; the second gate structure further includes a second gate dielectric layer having a gate dielectric opening, the bottom of the gate dielectric opening exposing the surface of the second conductive plug, and the second gate located on the surface of the second gate dielectric layer and within the gate dielectric opening.

[0023] Optionally, the method for forming the gate structure further includes: forming a gate dielectric material layer on the surface of the second dielectric layer and inside the gate opening; etching a portion of the gate dielectric material layer at the bottom of the gate opening until the first dielectric layer is exposed, forming the gate dielectric opening; forming a second gate material layer on the surface of the gate dielectric material layer and inside the gate dielectric opening; planarizing the second gate material layer and the gate dielectric material layer until the surface of the second conductive plug is exposed, forming the gate dielectric layer with the gate dielectric material layer, and forming the second gate with the second gate material layer.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: In the semiconductor structure formation method provided by the present invention, the second source / drain region is electrically connected to the first source / drain region of the lower layer through the source / drain interconnect layer and the first conductive plug, thereby realizing the electrical connection between the source / drain regions of adjacent upper and lower layer devices. Since the second source / drain region, the source / drain interconnect layer, the first conductive plug and the first source / drain region are arranged vertically, they do not occupy additional chip planar area, thereby further improving the density advantage of CFET devices.

[0025] Furthermore, the second gate structure also includes a second gate dielectric layer, which has a gate dielectric opening. The bottom of the gate dielectric opening exposes the surface of the second conductive plug. The second gate is located on the surface of the second gate dielectric layer and within the gate dielectric opening. This allows the second gate to be electrically connected to the first gate through the second conductive plug, thereby achieving electrical connection between the gates of adjacent upper and lower layer devices. Since the second gate, the first gate, and the second conductive plug are arranged vertically, they do not occupy additional chip planar area, further improving the density advantage of CFET devices.

[0026] In the semiconductor structure provided by the present invention, the second source / drain region is electrically connected to the first source / drain region of the lower layer through the source / drain interconnect layer and the first conductive plug, thereby realizing the electrical connection between the source / drain regions of adjacent upper and lower layer devices. Since the second source / drain region, the source / drain interconnect layer, the first conductive plug and the first source / drain region are arranged vertically, they do not occupy additional chip planar area, thereby further improving the density advantage of CFET devices.

[0027] Furthermore, the second gate structure also includes a second gate dielectric layer, which has a gate dielectric opening. The bottom of the gate dielectric opening exposes the surface of the second conductive plug. The second gate is located on the surface of the second gate dielectric layer and within the gate dielectric opening. This allows the second gate to be electrically connected to the first gate through the second conductive plug, thereby achieving electrical connection between the gates of adjacent upper and lower layer devices. Since the second gate, the first gate, and the second conductive plug are arranged vertically, they do not occupy additional chip planar area, further improving the density advantage of CFET devices. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a CFET device. Figures 2 to 32 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0029] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0030] As described in the background section, the performance of existing CFET devices still needs further improvement. A CFET device will now be used as an example for explanation and analysis.

[0031] Figure 1 This is a schematic diagram of a CFET device.

[0032] Please refer to Figure 1 The CFET device includes: a substrate 100; a first device 11 located on the surface of the substrate 100, the first device 11 including a first gate structure 111 and first source / drain regions 112 located on both sides of the first gate structure 111; and a second device 12 stacked on the first device 11, the second device 12 including a second gate structure 121 and second source / drain regions 122 located on both sides of the second gate structure 121.

[0033] In the aforementioned CFET device, NMOS devices and PMOS devices, namely the first device 11 and the second device 12, are stacked and integrated in a direction perpendicular to the surface of the substrate 100. Theoretically, this can reduce the occupied area of ​​the standard cell to half that of the traditional two-dimensional structure, thereby achieving a doubling of transistor density.

[0034] However, in existing standard cells, such as transmission gates, inverters, and static random access memory (SRAM), it is necessary to interconnect the source / drain of upper and lower layers, which increases the planar area of ​​the chip. Specifically, in the existing CFET device fabrication method, to electrically connect the first source / drain region 112 and the second source / drain region 122, after forming the first device 11 and the second device 12, a first conductive plug 131 is formed on the first source / drain region 112, and a second conductive plug 132 is formed on the second source / drain region 122. Then, a top metal layer 133 is formed on the surface of the first conductive plug 131 and the second conductive plug 132, and the electrical connection is achieved through the top metal layer 133. In the above method, since the first conductive plug 131 and the second conductive plug 132 need to be staggered, additional chip planar area is inevitably occupied. Due to wiring congestion and design rule constraints, this area overhead significantly offsets the density advantage of CFET devices.

[0035] To address the aforementioned issues, the present invention provides a semiconductor structure and its formation method in which a second source / drain region is electrically connected to a first source / drain region in the lower layer via a source / drain interconnect layer and a first conductive plug, thereby achieving electrical connection between the source / drain regions of adjacent upper and lower layer devices. Since the second source / drain region, the source / drain interconnect layer, the first conductive plug, and the first source / drain region are arranged vertically, they do not occupy additional chip planar area, thus further improving the density advantage of CFET devices.

[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 32 This is a schematic diagram of the steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

[0038] Please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the three-dimensional structure. Figure 3 for Figure 2A cross-sectional structural schematic diagram along the EE1 direction is provided, showing a bottom device structure 20. The bottom device structure 20 includes a first device and a first dielectric layer 201 located on the first device. The first device includes a first gate structure 202 and first source / drain regions 203 located on both sides of the first gate structure 202. The first gate structure 202 includes a first gate 2021.

[0039] In this embodiment, the first gate structure 202 further includes a first sidewall 2022, which is located on the sidewall of the first gate 2021. The first sidewall 2022 can be a single layer or a multi-layer structure.

[0040] In this embodiment, the underlying device structure 20 further includes: a substrate structure 200 and an interlayer dielectric layer 204, wherein the interlayer dielectric layer 204 is located on the sidewall of the first device; and the first dielectric layer 201 is located on the top surface of the first gate structure 202 and the interlayer dielectric layer 204.

[0041] In this embodiment, the first device is a GAA device. The first device further includes a plurality of first channel layers (not shown in the figure) stacked along a first direction X, with a first gate recess (not shown in the figure) between adjacent two first channel layers. The first source / drain regions 203 are located at opposite ends of the plurality of first channel layers in a second direction Y. The first gate 2021 spans the plurality of first channel layers along a third direction Z and is located within the first gate recess. The first direction X is perpendicular to the surface of the underlying device structure 20, and the second direction Y and the third direction Z are parallel to the surface of the underlying device structure 20 and are perpendicular to each other.

[0042] In this embodiment, the substrate structure 200 includes a substrate (not shown in the figure), a fin (not shown in the figure) located on the surface of the substrate, and a shallow trench isolation structure. The shallow trench isolation structure is located on the sidewall of the fin (not shown in the figure), and a plurality of first channel layers and first source / drain regions 203 are located on the fin.

[0043] In other embodiments, the first device may also be a FinFET device.

[0044] In this embodiment, the first device is located at the bottom layer.

[0045] In other embodiments, the first device may not be limited to the bottom layer. That is, the technical solution of the present invention can be used to electrically connect the source and drain regions (i.e., the first source and drain region and the second source and drain region) of any two adjacent layers of devices.

[0046] The material of the first dielectric layer 201 is a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0047] For illustration purposes, the material of the first dielectric layer 201 is silicon oxide.

[0048] Please refer to Figures 4 to 6 , Figure 4 This is a schematic diagram of the three-dimensional structure. Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 6 for Figure 4 A cross-sectional view along the FF1 direction is shown in the diagram. A first conductive plug 205 is formed within the underlying device structure 20. The first conductive plug 205 penetrates the first dielectric layer 201 along the first direction X and is located on the surface of the first source / drain region 203.

[0049] In this embodiment, before the source-drain interconnect layer is subsequently formed, a second conductive plug 206 is also formed in the underlying device structure 20. The second conductive plug 206 penetrates the first dielectric layer 201 along the first direction X and is located on the surface of the first gate 2021.

[0050] The second conductive plug 206 is used to realize the electrical connection between the gates of two adjacent layers of devices (i.e., the first gate 2021 and the second gate).

[0051] In other embodiments, the second conductive plug may not be formed.

[0052] Subsequently, two independent source-drain interconnect layers are formed on the first dielectric layer 201, with one of the source-drain interconnect layers located on the surface of the first conductive plug 205 on one side; a second device is formed on the first dielectric layer 201, and the second device is stacked with the first device along the first direction X. The second device includes a second gate structure and second source-drain regions located on both sides of the second gate structure. The second gate structure includes a second gate, and one of the second source-drain regions is located on one of the source-drain interconnect layers, so that it is electrically connected to the first source-drain region 203 on the lower layer.

[0053] In this embodiment, please refer to the method for forming the second device and the source-drain interconnect layer. Figures 7 to 32 .

[0054] Specifically, an initial source-drain interconnect layer and a channel structure located on the surface of the first dielectric layer 201 and the first conductive plug 205 are formed, and the initial source-drain interconnect layer and the channel structure extend along the second direction Y.

[0055] In this embodiment, please refer to the method for forming the initial source-drain interconnect layer and the channel structure. Figures 7 to 10 .

[0056] Please refer to Figure 7 , Figure 7 The view direction is the same Figure 4 A first source-drain interconnect material layer 208 is formed on the surface of the first dielectric layer 201 and the first conductive plug 205.

[0057] In this embodiment, the material of the first source-drain interconnect material layer 208 is metal.

[0058] In this embodiment, the first source-drain interconnect material layer 208 is also formed on the surface of the second conductive plug 206.

[0059] Please refer to Figure 8 , Figure 8 The view direction is the same Figure 7 A top-level device substrate 21 is formed, the top-level device substrate 21 including a second source-drain interconnect material layer 211 and an initial channel structure 212 located on the surface of the second source-drain interconnect material layer 211.

[0060] In this embodiment, the material of the second source-drain interconnect material layer 211 is metal.

[0061] Here, the first source-drain interconnect material layer 208 and the second source-drain interconnect material layer 211 are used to form a source-drain interconnect layer to realize the electrical connection between the source-drain regions of different layers. The selection of low-resistance metal materials (such as titanium nitride, tungsten, etc.) helps to reduce the parasitic capacitance caused by the interconnect.

[0062] In this embodiment, the method for forming the top device substrate 21 includes: providing a silicon-on-insulator substrate (not shown in the figure), the silicon-on-insulator substrate including a substrate, an insulating layer and a silicon layer, the insulating layer being located between the substrate and the silicon layer; using an epitaxial process to form the initial channel structure 212 on the surface of the silicon-on-insulator substrate; forming a second source-drain interconnect material layer 211 on the surface of the initial channel structure 212 to form the top device substrate 21 on the surface of the silicon-on-insulator substrate; and peeling the top device substrate 21 from the silicon-on-insulator substrate by the insulating layer.

[0063] In this embodiment, the second device used to form is a GAA device; the initial channel structure 212 is multilayered, which includes a plurality of sacrificial material layers 2121 and a plurality of channel material layers 2122 stacked along the first direction X, and each of the sacrificial material layers 2121 is located between two adjacent channel material layers 2122.

[0064] The material of the sacrificial material layer 2121 is different from the material of the channel material layer 2122.

[0065] In this embodiment, the material of the sacrificial material layer 2121 is germanium silicon (Ge), and the material of the channel material layer 2122 is silicon (Si).

[0066] In other embodiments, the channel material layer 2122 may be made of Ge or GeSi, and the sacrificial material layer 2121 may be made of ZnS, ZnSe, BeS, or GaP, etc.

[0067] In another embodiment, the second device used to form is a FinFET device, and the initial channel structure is a single layer.

[0068] Please refer to Figure 9 , Figure 9 The view direction is the same Figure 8 The second source-drain interconnect material layer 211 is oriented toward the first source-drain interconnect material layer 208, so that the bottom device structure 20 and the top device substrate 21 are bonded.

[0069] In this embodiment, the bonding is performed after the top-layer device substrate 21 is peeled off from the surface of the silicon-on-insulator substrate.

[0070] In another embodiment, the top-layer device substrate 21 may be peeled off from the surface of the silicon-on-insulator substrate after the bonding is completed.

[0071] In this embodiment, the process of bonding the bottom device structure 20 and the top device substrate 21 is a metal bonding process.

[0072] Please refer to Figure 10 , Figure 10 The view direction is the same Figure 9 The initial channel structure 212, the first source-drain interconnect material layer 208 and the second source-drain interconnect material layer 211 are graphically represented. The initial channel structure 212 is used to form the channel structure 213, and the first source-drain interconnect material layer 208 and the second source-drain interconnect material layer 211 are used to form the initial source-drain interconnect layer 214.

[0073] The method for patterning the initial channel structure 212, the first source-drain interconnect material layer 208, and the second source-drain interconnect material layer 211 includes: forming a patterned mask layer on the surface of the initial channel structure 212, the first source-drain interconnect material layer 208, and the second source-drain interconnect material layer 211, and etching the initial channel structure 212, the first source-drain interconnect material layer 208, and the second source-drain interconnect material layer 211 using the patterned mask layer as a mask.

[0074] The initial source-drain interconnect layer 214 is used to form the source-drain interconnect layer. The initial source-drain interconnect layer 214 and the channel structure 213 are formed in the same photolithography process, so that the initial source-drain interconnect layer 214 and the channel structure 213 have self-alignment, which is beneficial to improve the alignment accuracy between the subsequently formed source-drain interconnect layer and the second source-drain region.

[0075] In this embodiment, the channel structure 213 is in the shape of an "I" and includes a first region I and a second region II. The second region II is located on both sides of the first region I in the second direction Y and along the third direction Z. The width of the second region II is greater than the width of the first region I.

[0076] In another embodiment, the channel structure can be strip-shaped.

[0077] In this embodiment, the method of forming the channel structure 213 further includes: forming a sacrificial layer 2131 with the sacrificial material layer 2121, forming a channel layer 2132 with the channel material layer 2122, and the channel structure 213 includes a plurality of sacrificial layers 2131 and a plurality of channel layers 2132.

[0078] Please refer to Figures 11 to 14 , Figure 11 This is a schematic diagram of the three-dimensional structure. Figure 12 for Figure 11 A top-down structural diagram (the hard mask layer is omitted). Figure 13 for Figure 11 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 14 for Figure 11 A cross-sectional view along the FF1 direction shows a pseudo-gate structure spanning the initial source-drain interconnect layer 214 and the channel structure 213. The pseudo-gate structure includes a pseudo-gate 215 that extends along the third direction Z.

[0079] In this embodiment, the dummy gate 215 spans across the first region I.

[0080] The dummy gate 215 is used to occupy a position for the second gate in the metal gate replacement process.

[0081] In this embodiment, the dummy gate 215 is made of amorphous silicon.

[0082] In other embodiments, the material of the dummy gate may also be polycrystalline silicon or the like.

[0083] In this embodiment, the dummy gate structure further includes a sidewall 216 and a hard mask layer 217. The sidewall 216 is located on the sidewall of the dummy gate 215, and the hard mask layer 217 is located on the top surface of the dummy gate 215.

[0084] Please refer to Figures 15 to 16 , Figure 15 This is a schematic diagram of the three-dimensional structure. Figure 16 for Figure 15 A cross-sectional view along the EE1 direction shows that the second source / drain region 218 is formed within the channel structure 213 on both sides of the pseudo-gate structure.

[0085] In this embodiment, the method for forming the second source / drain region 218 includes: using the pseudo-gate structure as a mask, injecting doped ions into the channel structure 213, and using the channel structure 213 on both sides of the pseudo-gate structure as the second source / drain region 218.

[0086] Specifically, doped ions are injected into the second region II of the channel structure 213.

[0087] It should be noted that the channel structure 213 is designed in an "I" shape, which helps to increase the area of ​​the second source / drain region 218 formed.

[0088] In another embodiment, the method for forming the second source / drain region includes: using the pseudo-gate structure as a mask, etching the channel structure to form a source / drain groove within the channel structure; forming an epitaxial layer within the source / drain groove, the epitaxial layer containing doped ions, and forming the second source / drain layer using the epitaxial layer.

[0089] Please refer to Figures 17 to 19 , Figure 17 This is a schematic diagram of the three-dimensional structure. Figure 18 for Figure 17 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 19 for Figure 17 A cross-sectional view along the FF1 direction shows that a second dielectric layer 219 is formed on the surfaces of the first dielectric layer 201 and the second source / drain region 218. The second dielectric layer 219 is located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate 215.

[0090] In this embodiment, the method for forming the second dielectric layer 219 includes: forming a second dielectric material layer (not shown in the figure) on the surface of the first dielectric layer 201 and the surface of the second source / drain region 218, wherein the top surface of the second dielectric material layer is higher than the top surface of the dummy gate structure; planarizing the second dielectric material layer and the hard mask layer 217 until the top surface of the dummy gate 215 is exposed.

[0091] The material of the second dielectric layer 219 is a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0092] The second dielectric layer 219 is made of a different material than the first dielectric layer 201. For illustration, the material of the second dielectric layer 219 is silicon nitride.

[0093] Please refer to Figures 20 to 22 , Figure 20 This is a schematic diagram of the three-dimensional structure. Figure 21 for Figure 20 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 22 for Figure 20 A cross-sectional view along the FF1 direction is shown, in which the dummy gate 215 is removed and an initial gate opening 220 is formed in the second dielectric layer 219.

[0094] The process for removing the dummy gate 215 includes one or a combination of dry etching and wet etching processes.

[0095] In this embodiment, a wet etching process is used to remove the dummy gate 215.

[0096] Next, a portion of the initial source-drain interconnect layer 214 exposed by the initial gate opening 220 is removed to form a gate opening, and two source-drain interconnect layers are formed with the initial source-drain interconnect layer 214.

[0097] In this embodiment, the second device formed is a GAA device. Therefore, after forming the initial gate opening 220 and before forming the gate opening, please refer to... Figure 23 and Figure 24 .

[0098] Please refer to Figure 23 and Figure 24 , Figure 23 This is a schematic diagram of the three-dimensional structure. Figure 24 for Figure 23 A cross-sectional view along the EE1 direction (red dashed box to indicate the location of the gate groove) shows the removal of the sacrificial layer 2131 exposed by the initial gate opening 220, forming a gate groove 222 between two adjacent channel layers 2132.

[0099] The process for removing the sacrificial layer 2131 exposed by the initial gate opening 220 includes one or a combination of dry etching and wet etching. In this embodiment, a wet etching process is used to remove the sacrificial layer 2131 exposed by the initial gate opening 220.

[0100] Please refer to Figure 25 and Figure 26 , Figure 25 This is a schematic diagram of the three-dimensional structure. Figure 26 for Figure 25 The cross-sectional structure diagram along the EE1 direction shows that the portion of the initial source-drain interconnect layer 214 exposed by the initial gate opening 220 is removed to form the gate opening 223, and two source-drain interconnect layers 224 are formed from the initial source-drain interconnect layer 214.

[0101] Thus, through the source-drain interconnect layer 224 and the first conductive plug 205, the second source-drain region 218 is electrically connected to the first source-drain region 203 in the lower layer, thereby realizing the electrical connection between the source-drain regions of adjacent upper and lower layer devices. Since the second source-drain region 218, the source-drain interconnect layer 224, the first conductive plug 205 and the first source-drain region 203 are arranged vertically, they do not occupy additional chip planar area, thereby further improving the density advantage of CFET devices.

[0102] In addition, of the two second source-drain regions 218 of the second device, one is used as the source region and the other is used as the drain region. By removing the portion of the initial source-drain interconnect layer 214 exposed by the initial gate opening 220, and forming two mutually independent source-drain interconnect layers 224 with the initial source-drain interconnect layer 214, the short-circuit anomaly between the source region and the drain region of the second device 12 can be effectively reduced.

[0103] In this embodiment, the source-drain interconnect layer 224 exposes the surface of the second conductive plug 206.

[0104] Subsequently, a second gate is formed within the gate opening 223.

[0105] In this embodiment, the second gate structure further includes a second gate dielectric layer, which has a gate dielectric opening. The bottom of the gate dielectric opening exposes the surface of the second conductive plug 224. The second gate is located on the surface of the second gate dielectric layer and within the gate dielectric opening.

[0106] In this embodiment, the method for forming the second gate structure is also referred to. Figures 27 to 32 .

[0107] Please refer to Figures 27 to 29 , Figure 27 This is a schematic diagram of the three-dimensional structure. Figure 28 for Figure 27 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 29 for Figure 27A cross-sectional view along the FF1 direction shows that a gate dielectric material layer 225 is formed on the surface of the second dielectric layer 219 and inside the gate opening 223; a portion of the gate dielectric material layer 225 at the bottom of the gate opening 223 is etched until the surface of the second conductive plug 206 is exposed, forming the gate dielectric opening 226.

[0108] In this embodiment, the gate dielectric material layer 225 is a high-k dielectric material. The purpose of forming the gate dielectric opening 226 is to electrically connect the subsequently formed second gate to the lower first gate.

[0109] In this embodiment, the gate dielectric material layer 225 is also formed within the gate groove 222.

[0110] Please refer to Figures 30 to 32 , Figure 30 This is a schematic diagram of the three-dimensional structure. Figure 31 for Figure 30 A schematic diagram of the cross-sectional structure along the EE1 direction. Figure 32 for Figure 30 A cross-sectional view along the FF1 direction is shown in the figure. A second gate material layer (not shown) is formed on the surface of the gate dielectric material layer 225 and within the gate dielectric opening 226. The second gate material layer and the gate dielectric material layer 225 are planarized until the second dielectric layer 219 is exposed. The gate dielectric layer 227 is formed with the gate dielectric material layer 225, and the second gate 228 is formed with the second gate material layer.

[0111] Here, the gate dielectric opening 226 is formed in the second gate dielectric layer 227 at the bottom of the gate opening 223. The bottom of the gate dielectric opening 226 exposes the surface of the second conductive plug 224, which allows the second gate 228 to be electrically connected to the first gate 2021 through the second conductive plug 24, thereby realizing the electrical connection between the gates of adjacent upper and lower layer devices. Since the second gate 228, the first gate 2021 and the second conductive plug 24 are arranged vertically, they do not occupy additional chip planar area, further improving the density advantage of CFET devices.

[0112] In this embodiment, the second gate structure further includes a sidewall 216, which is located on the sidewall of the second gate 228.

[0113] In this embodiment, the second device further includes a channel region extending along a second direction Y, a second gate 228 crossing the channel region along a third direction Z, and a second source / drain region 218 located at opposite ends of the channel region in the second direction Y.

[0114] The channel structure 213 enclosed by the second gate 228 (as shown) Figure 10 The channel region is formed by the channel structure 213 (as shown in the figure) or part of the channel structure 213.

[0115] In this embodiment, the second device is a GAA device, and the channel region is formed by the portion of the channel structure 213 enclosed by the second gate 228.

[0116] Specifically, the channel region is multi-layered, including a plurality of channel layers 2132 stacked along the first direction X, with a grid groove 222 between adjacent channel layers 2132.

[0117] In this embodiment, the second device is a GAA device, and the second gate 228 is also formed in the gate recess 222.

[0118] In another embodiment, the second device is a FinFET device, the channel structure is a single layer, the channel region is formed by the channel structure wrapped by the second gate, and the second gate is formed in the gate opening.

[0119] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figures 30 to 32 The device includes: a bottom device structure 20, which includes a first device and a first dielectric layer 201 on the first device. The first device includes a first gate structure 202 and first source / drain regions 203 on both sides of the first gate structure 202. The first gate structure 202 includes a first gate 2021. A first conductive plug 205 is located within the bottom device structure 20. The first conductive plug 205 penetrates the first dielectric layer 201 along a first direction X and is located on the surface of the first source / drain regions 203. The first direction X is perpendicular to the surface of the bottom device structure 20. Two source-drain interconnect layers 224 are located on the first dielectric layer 201, and one of the source-drain interconnect layers 224 is located on the surface of the first conductive plug 205 on one side. A second device is located on the first dielectric layer 201, and the second device is stacked with the first device along the first direction X. The second device includes a second gate structure and second source-drain regions 218 located on both sides of the second gate structure. The second gate structure includes a second gate 228. One of the second source-drain regions 218 is located on one of the source-drain interconnect layers 224, so that it is electrically connected to the first source-drain region 203 on the lower layer.

[0120] Thus, through the source-drain interconnect layer 224 and the first conductive plug 205, the second source-drain region 218 is electrically connected to the first source-drain region 203 in the lower layer, thereby realizing the electrical connection between the source-drain regions of adjacent upper and lower layer devices. Since the second source-drain region 218, the source-drain interconnect layer 224, the first conductive plug 205 and the first source-drain region 203 are arranged vertically, they do not occupy additional chip planar area, thereby further improving the density advantage of CFET devices.

[0121] In this embodiment, the semiconductor structure further includes: a second conductive plug 206 located within the underlying device structure 20, the second conductive plug 206 penetrating the first dielectric layer 201 along the first direction X and located on the surface of the first gate 2022; the source-drain interconnect layer 224 exposes the surface of the second conductive plug 206.

[0122] In this embodiment, the second gate structure further includes: a second gate dielectric layer 227, wherein the second gate dielectric layer 227 has a gate dielectric opening 226 (e.g., Figure 29 As shown), the bottom of the gate dielectric opening 226 exposes the surface of the second conductive plug 206, and the second gate 228 is located on the surface of the second gate dielectric layer 227 and within the gate dielectric opening 226.

[0123] Here, since the second gate dielectric layer 227 has a gate dielectric opening 226, the bottom of the gate dielectric opening 226 exposes the surface of the second conductive plug 224, which allows the second gate 228 to be electrically connected to the first gate 2021 through the second conductive plug 24, thereby realizing the electrical connection between the gates of adjacent upper and lower layer devices. Since the second gate 228, the first gate 2021 and the second conductive plug 24 are arranged vertically, they do not occupy additional chip planar area, further improving the density advantage of CFET devices.

[0124] In this embodiment, the semiconductor structure further includes: a second dielectric layer 219 located on the surface of the underlying device structure 20 and the second source / drain region 218, the second dielectric layer 219 having a gate opening 223 (e.g., Figures 27 to 29 (as shown); the second gate dielectric layer 227 is located on the sidewall and bottom surface of the gate opening 223.

[0125] In this embodiment, the second source / drain region 218 and the sidewall of the source / drain interconnect layer 224 are flush.

[0126] In this embodiment, the second device further includes: a channel region extending along a second direction Y, a second gate 228 spanning the channel region along a third direction Z, the second direction Y and the third direction Z being parallel to the surface of the underlying device structure 20 and perpendicular to each other, and the second source / drain region 218 being located at opposite ends of the channel region in the second direction Y.

[0127] In this embodiment, the second device is a GAA device; the channel region is multi-layered, including a plurality of channel layers 2132 stacked along the first direction X, and a gate recess 222 (e.g., between adjacent channel layers 2132) is provided. Figure 26 As shown), the second gate 228 is also located within the gate recess 222.

[0128] In another embodiment, the second device is a FinFET device; the channel region is a single layer.

[0129] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The underlying device structure includes a first device and a first dielectric layer on the first device. The first device includes a first gate structure and first source / drain regions located on both sides of the first gate structure. The first gate structure includes a first gate. A first conductive plug is located within the underlying device structure. The first conductive plug penetrates the first dielectric layer along a first direction and is located on the surface of the first source / drain region. The first direction is perpendicular to the surface of the underlying device structure. Two source-drain interconnect layers are located on the first dielectric layer and are separated from each other, with one of the source-drain interconnect layers located on the surface of the first conductive plug on one side; A second device is located on the first dielectric layer, and the second device is stacked with the first device along the first direction. The second device includes a second gate structure and second source / drain regions located on both sides of the second gate structure. The second gate structure includes a second gate. A second source / drain region is located on a source / drain interconnect layer, so that it is electrically connected to the first source / drain region on the lower layer.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second conductive plug is located within the underlying device structure, the second conductive plug penetrates the first dielectric layer along the first direction, and is located on the first gate surface; The source-drain interconnect layer exposes the surface of the second conductive plug; the second gate structure further includes a second gate dielectric layer having a gate dielectric opening, the bottom of the gate dielectric opening exposing the surface of the second conductive plug, and the second gate being located on the surface of the second gate dielectric layer and within the gate dielectric opening.

3. The semiconductor structure as described in claim 2, characterized in that, Also includes: A second dielectric layer is located on the surface of the underlying device structure and the second source / drain region, and the second dielectric layer has a gate opening; the second gate dielectric layer is located on the sidewall and bottom surface of the gate opening.

4. The semiconductor structure as described in claim 1, characterized in that, The second source / drain region is flush with the sidewall of the source / drain interconnect layer.

5. The semiconductor structure as described in claim 1, characterized in that, The second device further includes a channel region extending along a second direction, a second gate crossing the channel region along a third direction, the second direction and the third direction being parallel to the surface of the underlying device structure and perpendicular to each other, and the second source / drain regions being located at opposite ends of the channel region in the second direction.

6. The semiconductor structure as described in claim 5, characterized in that, The second device is a GAA device; the channel region is multilayered, including a plurality of channel layers stacked along the first direction, with a gate groove between two adjacent channel layers, and the second gate is also located in the gate groove.

7. The semiconductor structure as described in claim 5, characterized in that, The second device is a FinFET device; the channel region is a single layer.

8. A method for forming a semiconductor structure, characterized in that, include: A bottom-level device structure is provided, the bottom-level device structure including a first device and a first dielectric layer located on the first device, the first device including a first gate structure and first source / drain regions located on both sides of the first gate structure, the first gate structure including a first gate; A first conductive plug is formed within the underlying device structure. The first conductive plug penetrates the first dielectric layer along a first direction and is located on the surface of the first source / drain region. The first direction is perpendicular to the surface of the underlying device structure. Two mutually independent source-drain interconnect layers are formed on the first dielectric layer, with one of the source-drain interconnect layers located on one side of the surface of the first conductive plug. A second device is formed on the first dielectric layer, and the second device is stacked with the first device along the first direction. The second device includes a second gate structure and second source / drain regions located on both sides of the second gate structure. The second gate structure includes a second gate, and a second source / drain region is located on a source / drain interconnect layer, so that it is electrically connected to the first source / drain region on the lower layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The method of forming the second device and the source-drain interconnect layer includes: forming an initial source-drain interconnect layer and a channel structure located on the surface of the first dielectric layer and the first conductive plug, the initial source-drain interconnect layer and the channel structure extending along a second direction; forming a dummy gate structure spanning the initial source-drain interconnect layer and the channel structure, the dummy gate structure including a dummy gate extending along a third direction, the second direction and the third direction being parallel to the surface of the underlying device structure and perpendicular to each other; forming a second source-drain region within the channel structure on both sides of the dummy gate structure; forming a second dielectric layer on the surface of the first dielectric layer and the second source-drain region, the second dielectric layer being located on the sidewall of the dummy gate structure and exposing the top surface of the dummy gate; removing the dummy gate to form an initial gate opening within the second dielectric layer; removing a portion of the initial source-drain interconnect layer exposed by the initial gate opening to form a gate opening, and forming two source-drain interconnect layers with the initial source-drain interconnect layer; forming a second gate within the gate opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The channel structure is in the shape of an "I" and includes a first region and a second region. The second region is located on both sides of the first region in the second direction. Along the third direction, the width of the second region is greater than the width of the first region. The dummy gate spans the first region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The method for forming the second source / drain region includes: using the pseudo-gate structure as a mask, injecting doped ions into the channel structure, and using the channel structures on both sides of the pseudo-gate structure as the second source / drain region.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the second source / drain region includes: using the pseudo-gate structure as a mask, etching the channel structure to form a source / drain groove in the channel structure; forming an epitaxial layer in the source / drain groove, the epitaxial layer containing doped ions, and forming the second source / drain layer with the epitaxial layer.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The second device further includes the channel region extending along a second direction, the second gate crossing the channel region along the third direction, and the second source / drain regions located at opposite ends of the channel region in the second direction; the method further includes forming the channel region with the channel structure or a portion of the channel structure enclosed by the second gate.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The method for forming the initial source-drain interconnect layer and the channel structure includes: forming a first source-drain interconnect material layer on the surface of the first dielectric layer and the first conductive plug; forming a top device substrate, the top device substrate including a second source-drain interconnect material layer and an initial channel structure located on the surface of the second source-drain interconnect material layer; aligning the second source-drain interconnect material layer toward the first source-drain interconnect material layer, thereby bonding the bottom device structure and the top device substrate; patterning the initial channel structure, the first source-drain interconnect material layer, and the second source-drain interconnect material layer, forming the channel structure with the initial channel structure, and forming the initial source-drain interconnect layer with the first source-drain interconnect material layer and the second source-drain interconnect material layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The second device is a GAA device; the channel region is multilayered, including a plurality of channel layers stacked along the first direction, with a gate recess between adjacent channel layers, and the second gate is also located within the gate recess; the initial channel structure is multilayered, including a plurality of sacrificial material layers and a plurality of channel material layers stacked along the first direction, with each sacrificial material layer located between adjacent channel material layers; the method of forming the channel structure further includes: forming a sacrificial layer with the sacrificial material layers, forming a channel layer with the channel material layers, the channel structure including a plurality of sacrificial layers and a plurality of channel layers; after forming the initial gate opening and before forming the gate opening, the method further includes: removing the sacrificial layer exposed by the initial gate opening, and forming the gate recess between adjacent channel layers; the second gate is also formed within the gate recess.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The second device is a FinFET device; the channel region is a single layer; the initial channel structure is a single layer; the channel structure is a single layer.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method further includes: before forming the source-drain interconnect layer, forming a second conductive plug within the underlying device structure, the second conductive plug penetrating the first dielectric layer along the first direction and located on the first gate surface; the source-drain interconnect layer exposing the surface of the second conductive plug; the second gate structure further includes a second gate dielectric layer having a gate dielectric opening, the bottom of the gate dielectric opening exposing the surface of the second conductive plug, and the second gate located on the surface of the second gate dielectric layer and within the gate dielectric opening.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The method for forming the gate structure further includes: forming a gate dielectric material layer on the surface of the second dielectric layer and inside the gate opening; etching a portion of the gate dielectric material layer at the bottom of the gate opening until the first dielectric layer is exposed, forming the gate dielectric opening; forming a second gate material layer on the surface of the gate dielectric material layer and inside the gate dielectric opening; planarizing the second gate material layer and the gate dielectric material layer until the surface of the second conductive plug is exposed, forming the gate dielectric layer with the gate dielectric material layer, and forming the second gate with the second gate material layer.

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