Semiconductor structure and method of manufacturing the same, image sensor

Abstract

This disclosure provides a semiconductor structure and its fabrication method, as well as an image sensor, relating to the field of image sensor technology, to improve the performance of image sensors. The semiconductor structure includes a substrate and a photoelectric conversion unit disposed on the substrate. The photoelectric conversion unit includes a first sub-section, a second sub-section, and at least one third sub-section. The first sub-section is doped with a first ion. The second sub-section is disposed on the side of the first sub-section close to the substrate and is doped with a second ion. Both the first and second ions are either P-type or N-type ions, and the concentration of the first ion in the first sub-section is greater than the concentration of the second ion in the second sub-section. The third sub-section is located within the second sub-section and is doped with a third ion, which is either a P-type or N-type ion. This semiconductor structure is used in an image sensor.

Description

Technical Field

[0001] This disclosure relates to the field of image sensor technology, and in particular to a semiconductor structure and its fabrication method, and an image sensor. Background Technology

[0002] Image sensors are a crucial component of digital cameras. Based on their components, image sensors can be broadly classified into two categories: CCD (Charge Coupled Device) and CMOS (Complementary Metal-Oxide Semiconductor). CMOS image sensors, with their advantages of small size and low power consumption, are gradually replacing CCD image sensors as the mainstream in the market.

[0003] The basic unit of a CMOS image sensor is the pixel region, which includes a photoelectric conversion unit. The full-well capacity of the photoelectric conversion unit is an important parameter for evaluating CMOS image sensors. Currently, with the increasing market demand for smaller pixels in CMOS image sensors, the quantum efficiency and full-well capacity of the photoelectric conversion unit are decreasing, leading to a decline in the performance of CMOS image sensors. Summary of the Invention

[0004] This disclosure provides a semiconductor structure and its fabrication method, as well as an image sensor, to improve the performance of the image sensor.

[0005] On one hand, a semiconductor structure is provided, including a substrate and a photoelectric conversion unit disposed on the substrate. The photoelectric conversion unit includes a first sub-unit, a second sub-unit, and at least one third sub-unit. The first sub-unit is doped with a first ion, and the second sub-unit is disposed on the side of the first sub-unit close to the substrate, and the second sub-unit is doped with a second ion. The first ion and the second ion are both either p-type or n-type ions, and the concentration of the first ion doped in the first sub-unit is greater than the concentration of the second ion doped in the second sub-unit. The third sub-unit is located within the second sub-unit, and the third sub-unit is doped with a third ion, which is either a p-type or n-type ion.

[0006] In this configuration, the increased depth of the photoelectric conversion unit by the first and second sub-sub ...

[0007] Furthermore, the third sub-section and the second sub-section form a built-in electric field, ensuring complete depletion of charge in the central region between the first and second sub-sections. This reduces reset noise, prevents charge residue from the previous frame's exposure from affecting the next frame, improves image trailing, and further enhances the image sensor's performance. Simultaneously, the third sub-section lowers the potential of the second sub-section while maintaining the same potential in the first sub-section. This increases the potential difference between the first and second sub-sections, accelerating the transfer of charge from the depletion region to the photoelectric conversion unit, further improving the image sensor's performance.

[0008] In some embodiments, the photoelectric conversion unit includes a plurality of the third sub-units, which are spaced apart.

[0009] In some embodiments, the planes on which the surfaces of the plurality of third sub-parts are located near or away from the substrate are located on the same reference plane, which is parallel to the surface of the substrate away from the photoelectric conversion part.

[0010] In some embodiments, the reference surface is a first surface where the second sub-parts are located away from the substrate, and the plane containing the surfaces of the plurality of third sub-parts away from the substrate is located on the first surface.

[0011] In some embodiments, the reference surface is a second surface where the second sub-part is located near the substrate, and the plane containing the surfaces of the plurality of third sub-parts near the substrate is located on the second surface.

[0012] In some embodiments, the photoelectric conversion unit further includes a fourth sub-unit, which is disposed on the side of the first sub-unit away from the second sub-unit; the fourth sub-unit is doped with a fourth ion, which is of the same type as the third ion.

[0013] In some embodiments, the semiconductor structure further includes a floating diffusion portion, a channel portion, a gate layer, and a gate semiconductor layer. The floating diffusion portion is disposed on one side of the photoelectric conversion portion, the channel portion is disposed between the floating diffusion portion and the photoelectric conversion portion, and both ends of the channel portion are respectively connected to the floating diffusion portion and the photoelectric conversion portion. The gate layer is disposed on the side of the channel portion away from the substrate, and the gate semiconductor layer is disposed between the channel portion and the gate layer.

[0014] On the other hand, an image sensor is provided, including a first semiconductor structure and a second semiconductor structure. The first semiconductor structure is the semiconductor structure described in the above embodiments, and the second semiconductor structure is coupled to the side of the first semiconductor structure away from the substrate along the thickness direction of the first semiconductor structure.

[0015] Furthermore, a method for fabricating a semiconductor structure is provided, comprising:

[0016] A photoelectric conversion section is formed on a substrate, the photoelectric conversion section including a first sub-section, a second sub-section, and at least one third sub-section. The first sub-section is doped with a first ion, the second sub-section is disposed on the side of the first sub-section close to the substrate, and the second sub-section is doped with a second ion. Both the first ion and the second ion are either P-type or N-type ions, and the concentration of the first ion doped in the first sub-section is greater than the concentration of the second ion doped in the second sub-section. The third sub-section is located within the second sub-section, and the third sub-section is doped with a third ion, which is either a P-type or N-type ion.

[0017] In some embodiments, forming the photoelectric conversion portion on the substrate includes:

[0018] A substrate is obtained, the substrate comprising a substrate and a semiconductor layer disposed on the substrate.

[0019] On the side of the semiconductor layer away from the substrate, a second ion is doped into the semiconductor layer to form a second sub-section.

[0020] The second sub-part is doped with a third ion to form at least one third sub-part.

[0021] The portion of the semiconductor layer located on the second sub-section is doped with first ions to form the first sub-section.

[0022] In some embodiments, the doping dose of the first ion in the first sub-part is 1.8 × 10⁻⁶. 12 cm -2 ~2.2×

[0023] 10 12 cm-2 The doping dose of the second ion in the second sub-part is 1.8 × 10⁻⁶. 11 cm -2 ~2.2×10 11 cm -2 The doping dose of the third ion in the third sub-part is 3.8 × 10⁻⁶. 11 cm -2 ~4.2×10 11 cm -2 .

[0024] And / or, the doping energy of the first ion in the first sub-part is 55 KeV to 75 KeV; the doping energy of the second ion in the second sub-part is 190 KeV to 210 KeV; and the doping energy of the third ion in the third sub-part is 140 KeV to 160 KeV.

[0025] In some embodiments, the third ion doping of the second sub-part to form at least one third sub-part includes:

[0026] A mask layer is formed on the substrate, the mask layer having multiple openings.

[0027] Using the mask layer as a mask, the second sub-part is subjected to third ion doping within the opening to form a plurality of third sub-parts; the plurality of third sub-parts are spaced apart.

[0028] Remove the mask layer.

[0029] In some embodiments, the preparation method further includes:

[0030] After the photoelectric conversion section is formed on the substrate, a fourth sub-section is formed on the side of the first sub-section away from the second sub-section. The fourth sub-section is doped with a fourth ion of the same type as the third ion.

[0031] The image sensor described above has the same structure and beneficial technical effects as the semiconductor structure provided in the first aspect, and will not be described in detail here.

[0032] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0034] Figure 1 This is a structural diagram of an image sensor according to some embodiments;

[0035] Figure 2 for Figure 1 A sectional view along section line AA;

[0036] Figure 3 for Figure 1 Another sectional view along section line AA;

[0037] Figure 4 for Figure 1 Another sectional view along section line AA;

[0038] Figure 5 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0039] Figure 6 This is a flowchart of a method for fabricating another semiconductor structure according to some embodiments;

[0040] Figure 7 This is a flowchart of a method for fabricating another semiconductor structure according to some embodiments;

[0041] Figure 8 This is a flowchart of another method for fabricating a semiconductor structure according to some embodiments. Detailed Implementation

[0042] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0043] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0044] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0045] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.

[0046] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0047] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0048] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0049] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0050] like Figure 1 and Figure 2 As shown, some embodiments of this disclosure provide an image sensor 1000, including a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 includes a substrate 10 and an isolation structure 20. The isolation structure 20 is disposed on the substrate 10 and isolates at least one photosensitive area PX on the substrate 10.

[0051] The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds. In this embodiment, the substrate 10 is made of silicon. However, the use of silicon as the substrate 10 in this embodiment is for the convenience of those skilled in the art to understand the subsequent formation method and does not constitute a limitation.

[0052] It is understood that multiple photosensitive areas PX can be disposed on the substrate 10, and each photosensitive area PX may include at least one pixel area. A pixel area can be understood as the smallest photosensitive unit in the image sensor 1000. The multiple pixel areas are arranged in multiple rows and columns, with each row including at least two pixel areas arranged along the second direction X, and each column including at least two pixel areas arranged along the third direction Y.

[0053] It should be noted that the second direction X is the row direction of the arrangement of multiple pixel areas, and the third direction Y is the column direction of the arrangement of multiple pixel areas. The second direction X and the third direction Y intersect; for example, the second direction X and the third direction Y are perpendicular.

[0054] In addition, such as Figure 1 and Figure 2 As shown, the first semiconductor structure 100 further includes a photoelectric conversion section PD, a floating diffusion section FD, and a channel section GD. The photoelectric conversion section PD is disposed on the substrate 10 and located in the photosensitive region PX. The floating diffusion section FD is disposed on one side of the photoelectric conversion section PD, and the channel section GD is disposed between the floating diffusion section FD and the photoelectric conversion section PD, with both ends of the channel section GD connected to the floating diffusion section FD and the photoelectric conversion section PD, respectively.

[0055] The photoelectric conversion element formed by the photoelectric conversion unit PD and the substrate 10 is the core component of the image sensor 1000. Its main principle is that the incident light excites the photoelectric conversion unit PD with photons, causing the charges in the substrate 10 to transition, thereby realizing photoelectric conversion. The charges generated by the photoelectric conversion unit PD are transferred to the floating diffuser FD through the channel unit GD. In the floating diffuser FD, these charges are converted into voltage signals and then output.

[0056] In some embodiments, such as Figure 1 and Figure 2 As shown, the first semiconductor structure 100 further includes a gate layer TG and a gate dielectric layer GI. The gate layer TG is disposed on the side of the channel portion GD away from the substrate 10, and the gate dielectric layer GI is disposed between the channel portion GD and the gate layer TG. It can be understood that by applying a voltage to the gate TG, a channel for charge carriers is formed in the portion of the channel portion GD near the gate layer TG, thereby controlling the conduction of the channel portion GD.

[0057] It should be noted that the material of the gate layer TG includes polysilicon containing doped ions, and the material of the gate dielectric layer GI includes silicon dioxide.

[0058] In some embodiments, such as Figure 1 and Figure 2As shown, along the thickness direction of the first semiconductor structure 100, the second semiconductor structure 200 is coupled to the side of the first semiconductor structure 100 away from the substrate 10. The second semiconductor structure 200 includes a plurality of transistors, such as a first transistor MOS1, a second transistor MOS2, and a third transistor MOS3.

[0059] It should be noted that the second semiconductor structure 200 may also be disposed on the same side of the substrate 10 as the first semiconductor structure 100, and this disclosure does not specifically limit the embodiments. The following describes some embodiments of this disclosure by taking as an example that the second semiconductor structure 200 is coupled to the side of the first semiconductor structure 100 away from the substrate 10 along the thickness direction of the first semiconductor structure 100.

[0060] In some examples, such as Figure 1 and Figure 2 As shown, the first transistor MOS1 can be a reset transistor RX. The reset transistor RX periodically resets the potential of the floating diffuser FD to the reference voltage VDD, clearing residual charge from the previous signal transmission and preventing interference with new signal transmissions. The second transistor MOS2 can be a source follower transistor DX. The source follower transistor DX amplifies the potential changes in the floating diffuser FD and outputs the amplified potential changes to other external circuits Vout. The third transistor MOS3 can be a select transistor SX, used to control the signal output switch. The select transistor SX is turned on during the selection phase, allowing the signal to be transmitted from pixel area P to the external circuit, ensuring that the signal is output at the correct time and avoiding signal interference between different pixel areas P.

[0061] In some embodiments, such as Figure 2 As shown, the image sensor 1000 also includes a lens unit 300, which is disposed on the side of the first semiconductor structure 100 away from the second semiconductor structure 200 and corresponds to the photosensitive area PX. The lens unit 300 can cover the photoelectric conversion unit PD in the first semiconductor structure 100, so that light from the external environment is focused onto the photoelectric conversion unit PD, which can further increase the amount of light entering the image sensor 1000, thereby improving the image quality of the image sensor 1000.

[0062] Currently, with the increasing demand for integrated image sensors, the size of the pixel area is constantly decreasing. This means that the size of the photoelectric conversion unit is also constantly shrinking, thereby reducing the quantum efficiency of the photoelectric conversion element, reducing the full-well capacity of the photoelectric conversion unit, and ultimately leading to a decline in the performance of the image sensor.

[0063] It should be noted that quantum efficiency and full-well capacity are important indicators for measuring the performance of image sensors. Quantum efficiency refers to the ratio of the amount of photogenerated charge to the number of incident photons, while full-well capacity refers to the maximum amount of charge that a pixel area can collect and store.

[0064] Based on this, such as Figure 2 As shown, some embodiments of this disclosure provide a semiconductor structure, including the first semiconductor structure 100 of any of the above embodiments. The photoelectric conversion unit PD includes a first sub-unit 31, a second sub-unit 32, and at least one third sub-unit 33. The first sub-unit 31 is doped with a first ion, and the second sub-unit 32 is disposed on the side of the first sub-unit 31 near the substrate 10, and the second sub-unit 32 is doped with a second ion. Both the first and second ions are either P-type or N-type ions, for example, both the first and second ions are N-type ions. Furthermore, the concentration of the first ion doped in the first sub-unit 31 is greater than the concentration of the second ion doped in the second sub-unit 32.

[0065] In this configuration, the first sub-section 31 and the second sub-section 32 increase the depth of the photoelectric conversion unit (PD), widening its depletion region and improving quantum efficiency and full-well capacity. This results in an increase in the number of photogenerated electrons produced by the PD under the same illumination conditions, thereby enhancing the sensitivity of the image sensor 1000. Simultaneously, the image sensor 1000 can capture more light under weaker illumination conditions, generating brighter and clearer images and improving its contrast. Furthermore, the concentration of the first ion doped in the first sub-section 31 is greater than the concentration of the second ion doped in the second sub-section 32, creating a potential gradient between them. This promotes efficient charge transfer and prevents image trailing.

[0066] In some embodiments, such as Figure 2 As shown, the third sub-section 33 is located within the second sub-section 32. The third sub-section 33 is doped with a third ion, which is either a P-type ion or an N-type ion, for example, a P-type ion. In this case, the third sub-section 33 and the second sub-section 32 form a built-in electric field, which completely depletes the charge in the central region between the first sub-section 31 and the second sub-section 32. This reduces reset noise, prevents charge residue from the previous frame's exposure from affecting the next frame, improves image trailing, and further enhances the performance of the image sensor 1000. Simultaneously, the third sub-section 33 lowers the potential of the second sub-section 32 while keeping the potential of the first sub-section 31 unchanged. This increases the potential difference between the first sub-section 31 and the second sub-section 32, increasing the speed of charge transfer from the depletion region to the photoelectric conversion unit (PD), further improving the performance of the image sensor 1000.

[0067] In some examples, P-type ions include group III element ions, such as boron and gallium ions. N-type ions include group V element ions, such as phosphorus and arsenic ions.

[0068] It should be noted that the third sub-section 33 is also doped with N-type ions. In the third sub-section 33, the concentration of P-type ions is greater than that of N-type ions, making the third sub-section 33 a P-type semiconductor structure.

[0069] In some embodiments, such as Figure 2 and Figure 3 As shown, the photoelectric conversion unit PD includes a plurality of third sub-units 33. The plurality of third sub-units 33 are spaced apart, which can minimize the occupation of the second sub-unit 32 by the third sub-unit 33 while exhausting the charge in the central region between the first sub-unit 31 and the second sub-unit 32, thereby increasing the area ratio of the second sub-unit 32 in the photosensitive region PX of the first semiconductor structure 100 and increasing the full-well capacity.

[0070] For example, such as Figure 2 and Figure 3 As shown, there is a gap between two adjacent third sub-parts 33, and the gaps are equal, which can accelerate the depletion rate of the charge in the central region between the first sub-part 31 and the second sub-part 32, so that the charge in the central region between the first sub-part 31 and the second sub-part 32 is depleted more thoroughly.

[0071] In some embodiments, such as Figure 2 , Figure 3 and Figure 4 As shown, the planes on which the surfaces of the multiple third sub-parts 33 are close to or far from the substrate 10 are located on the same reference plane, which is parallel to the surface of the substrate 10 far from the photoelectric conversion part PD. At this time, the multiple third sub-parts 33 and the second sub-parts 32 form a uniformly distributed built-in electric field, which is beneficial to the formation of a potential gradient and improves the effective charge transfer efficiency.

[0072] In some examples, such as Figure 2 As shown, the reference surface is the first surface where the second sub-part 32 is located away from the substrate 10, and the plane where the surfaces of the plurality of third sub-parts 33 are located away from the substrate 10 is located on the first surface.

[0073] In some examples, such as Figure 3 As shown, the reference surface is the second surface where the second sub-part 32 is located near the substrate 10, and the plane where the surfaces of the plurality of third sub-parts 33 are located near the substrate 10 is located on the second surface.

[0074] In some examples, such as Figure 4As shown, the reference surface is parallel to the third surface where the second sub-part 32 is located near the substrate 10. The third surface is located between the surface where the second sub-part 32 is located near the substrate 10 and the surface where the second sub-part 32 is located away from the substrate 10. The planes containing the surfaces of the plurality of third sub-parts 33 near or away from the substrate 10 are located on the third surface.

[0075] In some embodiments, the photoelectric conversion unit PD includes two to four third sub-parts 33. For example, the photoelectric conversion unit PD includes any one of two, three, and four third sub-parts 33. Furthermore, along the plane containing the reference surface 321, the ratio of the contact area between the third sub-part 33 and the second sub-part 32 to the area of ​​the second sub-part 32 is 57% to 86%. For example, the ratio of the contact area between the third sub-part 33 and the second sub-part 32 to the area of ​​the second sub-part 32 is any one of 57%, 71%, and 86%.

[0076] For example, the radial length of the orthographic projection of the third sub-part 33 onto the substrate 10 is 100 nm to 140 nm, such as any one of 100 nm, 110 nm, 120 nm, 130 nm, and 140 nm. The radial distance refers to the length of any line segment passing through the geometric center of the third sub-part 33.

[0077] In some embodiments, such as Figure 2 As shown, the photoelectric conversion unit PD also includes a fourth sub-unit 34, which is disposed on the side of the first sub-unit 31 away from the second sub-unit 32. The fourth sub-unit 34 is doped with a fourth ion, which is of the same type as the third ion, for example, a p-type ion. In this case, the fourth sub-unit 34 can form a PN junction with the first sub-unit 31. This structure is beneficial for controlling carrier movement during the photoelectric conversion process, reducing dark current generated by thermal excitation under low light conditions, thereby improving the performance of the image sensor 1000, especially under low light conditions.

[0078] Some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, such as... Figure 5 As shown, the preparation method includes S100.

[0079] S100: A photoelectric conversion unit (PD) is formed on the substrate 10.

[0080] In the above steps, the photoelectric conversion unit (PD) includes a first sub-unit 31, a second sub-unit 32, and at least one third sub-unit 33. The first sub-unit 31 is doped with a first ion. The second sub-unit 32 is disposed on the side of the first sub-unit 31 closest to the substrate 10 and is doped with a second ion. Both the first and second ions are either P-type or N-type ions. Furthermore, the concentration of the first ion doped in the first sub-unit 31 is greater than the concentration of the second ion doped in the second sub-unit 32. The third sub-unit 33 is located within the second sub-unit 32 and is doped with a third ion, which is either a P-type or N-type ion.

[0081] In some embodiments, such as Figure 6 As shown, in S100, the above preparation method may further include S110 to S140.

[0082] S110: Obtain the substrate.

[0083] In the above steps, the substrate includes a substrate 10 and a semiconductor layer disposed on the substrate 10. The substrate may also include an isolation structure 20 disposed on the substrate 10.

[0084] S110 may specifically include: etching the side of the semiconductor layer away from the substrate to form a groove, and sequentially depositing an insulating layer and an isolation structure 20 within the groove. The isolation structure 20 encloses at least one photosensitive region PX.

[0085] S120: A second ion is doped into the semiconductor layer on the side of the semiconductor layer away from the substrate 10 to form a second sub-section 32.

[0086] In the above steps, the doping ion type is N-type ion, and the doping dose is 1.8 × 10⁻⁶. 11 cm -2 ~2.2×10 11 cm -2 The doping energy is 190 KeV to 210 KeV, and the doping depth is 100 nm to 300 nm.

[0087] It should be noted that the doping depth refers to the distance between the plane of the substrate 10 away from the photoelectric conversion part PD and the plane of the edge where the doped ions diffuse in the semiconductor layer.

[0088] S130: The second sub-part 32 is doped with a third ion to form at least one third sub-part 33.

[0089] In the above steps, the doping ion type is p-type ion, and the doping dose is 3.8 × 10⁻⁶. 11 cm -2 ~4.2×10 11 cm -2The doping energy is 140 KeV to 160 KeV, and the doping depth is 100 nm to 300 nm.

[0090] It should be noted that the third sub-section 33 is also doped with N-type ions. In the third sub-section 33, the concentration of P-type ions is greater than that of N-type ions, making the third sub-section 33 a P-type semiconductor structure.

[0091] S140: The semiconductor layer located on the second sub-section 32 is doped with first ions to form the first sub-section 31.

[0092] In the above steps, the doping ion type is N-type ion, and the doping dose is 1.8 × 10⁻⁶. 12 cm -2 ~2.2×10 12 cm -2 The doping energy is 55 KeV to 75 KeV, and the doping depth is 300 nm to 350 nm.

[0093] In some embodiments, such as Figure 7 As shown, in S130, the above preparation method may further include S131 to S133.

[0094] S131: A mask layer is formed on the substrate 10, the mask layer having multiple openings.

[0095] In the above steps, the mask layer is, for example, a photoresist layer, and the aperture size of the photoresist layer is, for example, 100nm to 140nm.

[0096] S132: Using the mask layer as a mask, the second sub-part 32 is doped with a third ion inside the opening to form multiple third sub-parts 33.

[0097] In the above steps, multiple third sub-parts 33 are spaced apart.

[0098] S133: Remove the mask layer.

[0099] In the above steps, the mask layer is, for example, a photoresist layer, which is removed by oxygen ion ashing.

[0100] In some embodiments, such as Figure 8 As shown, after S100, the above preparation method may also include S200.

[0101] S200: A fourth sub-part 34 is formed on the side of the first sub-part 31 away from the second sub-part 32.

[0102] In the above steps, the fourth sub-part 34 is doped with a fourth ion, which is of the same type as the third ion, for example, the fourth ion is a P-type ion.

[0103] S200 may specifically include: doping a portion of the semiconductor layer located on the first sub-part with a fourth ion to form a fourth sub-part 34.

[0104] In some embodiments, after S200, the above preparation method may further include the following steps: forming a floating diffusion portion FD, a channel portion GD, a gate layer TG, and a gate dielectric layer GI on the substrate 10.

[0105] In the above steps, the floating diffusion section FD is disposed on one side of the photoelectric conversion section PD, and the channel section GD is disposed between the floating diffusion section FD and the photoelectric conversion section PD, with both ends of the channel section GD connected to the floating diffusion section FD and the photoelectric conversion section PD, respectively. The gate layer TG is disposed on the side of the channel section GD away from the substrate 10, and the gate dielectric layer GI is disposed between the channel section GD and the gate layer TG.

[0106] The gate layer TG is made of polysilicon containing doped ions, and the gate dielectric layer GI is made of silicon dioxide.

[0107] Specifically, one side of the photoelectric conversion section PD on the substrate 10 is ion-doped to form a floating diffusion section FD. Ion doping is performed between the photoelectric conversion section PD and the floating diffusion section FD to form a channel section GD. A gate dielectric layer GI and a gate layer TG are sequentially formed on the photoelectric conversion section PD by chemical vapor deposition.

[0108] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0109] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; A photoelectric conversion unit is disposed on the substrate; the photoelectric conversion unit includes: The first subunit is doped with the first ion; The second sub-part is disposed on the side of the first sub-part closer to the substrate; the second sub-part is doped with a second ion, and both the first ion and the second ion are either P-type ions or N-type ions; and the concentration of the first ion doped in the first sub-part is greater than the concentration of the second ion doped in the second sub-part. At least one third sub-section is located within the second sub-section; the third sub-section is doped with a third ion, which is either a P-type ion or an N-type ion.

2. The semiconductor structure according to claim 1, characterized in that, The photoelectric conversion unit includes a plurality of third sub-units, which are spaced apart.

3. The semiconductor structure according to claim 2, characterized in that, The planes containing the surfaces of the plurality of third sub-parts that are near or far from the substrate are located on the same reference plane, which is parallel to the surface of the substrate that is far from the photoelectric conversion part.

4. The semiconductor structure according to claim 3, characterized in that, The reference surface is the first surface where the second sub-part is located away from the substrate, and the plane containing the surfaces of the plurality of third sub-parts away from the substrate is located on the first surface.

5. The semiconductor structure according to claim 3, characterized in that, The reference surface is the second surface of the second sub-part near the substrate, and the plane containing the surfaces of the plurality of third sub-parts near the substrate is located on the second surface.

6. The semiconductor structure according to claim 1, characterized in that, The photoelectric conversion unit further includes a fourth sub-unit, which is disposed on the side of the first sub-unit away from the second sub-unit; the fourth sub-unit is doped with a fourth ion, which is of the same type as the third ion.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that, The semiconductor structure also includes: A floating diffuser is disposed on one side of the photoelectric conversion unit; A channel portion is disposed between the floating diffusion portion and the photoelectric conversion portion, and both ends of the channel portion are respectively connected to the floating diffusion portion and the photoelectric conversion portion; A gate layer is disposed on the side of the channel portion away from the substrate; A gate dielectric layer is disposed between the channel portion and the gate layer.

8. An image sensor, characterized in that, include: A first semiconductor structure, wherein the first semiconductor structure is the semiconductor structure as described in any one of claims 1 to 7; A second semiconductor structure is coupled along the thickness direction of the first semiconductor structure to the side of the first semiconductor structure away from the substrate.

9. A method for fabricating a semiconductor structure, characterized in that, For preparing the semiconductor structure as described in any one of claims 1 to 7, comprising: A photoelectric conversion section is formed on a substrate; the photoelectric conversion section includes a first sub-section, a second sub-section, and at least one third sub-section; the first sub-section is doped with a first ion; the second sub-section is disposed on the side of the first sub-section close to the substrate; the second sub-section is doped with a second ion, wherein the first ion and the second ion are both P-type ions or N-type ions; and the concentration of the first ion doped in the first sub-section is greater than the concentration of the second ion doped in the second sub-section; the third sub-section is located within the second sub-section; the third sub-section is doped with a third ion, wherein the third ion is another P-type ion or N-type ion.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The process of forming the photoelectric conversion unit on the substrate includes: Obtain a substrate, the substrate comprising a substrate and a semiconductor layer disposed on the substrate; On the side of the semiconductor layer away from the substrate, a second ion is doped into the semiconductor layer to form a second sub-section; The second sub-part is doped with a third ion to form at least one third sub-part; The portion of the semiconductor layer located on the second sub-section is doped with first ions to form the first sub-section.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The doping dose of the first ion in the first sub-part is 1.8 × 10⁻⁶. 12 cm -2 ~2.2×10 12 cm -2 The doping dose of the second ion in the second sub-part is 1.8 × 10⁻⁶. 11 cm -2 ~2.2×10 11 cm -2 The doping dose of the third ion in the third sub-part is 3.8 × 10⁻⁶. 10 11 cm -2 ~4.2×10 11 cm -2 ; And / or, the doping energy of the first ion in the first sub-part is 55 KeV to 75 KeV; the doping energy of the second ion in the second sub-part is 190 KeV to 210 KeV; and the doping energy of the third ion in the third sub-part is 140 KeV to 160 KeV.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that, The doping of the second sub-part with a third ion to form at least one third sub-part includes: A mask layer is formed on the substrate, the mask layer having a plurality of openings; Using the mask layer as a mask, the second sub-part is doped with third ions within the opening to form a plurality of third sub-parts; the plurality of third sub-parts are spaced apart. Remove the mask layer.

13. The method for preparing a semiconductor structure according to claim 9, characterized in that, The preparation method further includes: After the photoelectric conversion section is formed on the substrate, a fourth sub-section is formed on the side of the first sub-section away from the second sub-section; the fourth sub-section is doped with a fourth ion, which is of the same type as the third ion.

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