Display panel, preparation method thereof and electronic device

Abstract

The application provides a display panel, a preparation method thereof and an electronic device, and relates to the technical field of display. The technical scheme provided by the application sets a packaging monitoring area in communication with a clearance area at the outer edge of a transistor array layer to achieve the purpose of setting an organic packaging monitoring point on the display panel. Specifically, when the organic packaging layer is prepared in the display panel, whether the side surface of the blocking wall relative to the packaging monitoring area is covered by the organic packaging material is monitored to determine whether the organic packaging layer prepared in the display panel meets the expectation, thereby solving the problem that the quality monitoring of the organic packaging layer is difficult in the prior art. Moreover, the organic packaging layer quality monitoring method provided by the embodiments of the application is simple and time-saving, and the preparation efficiency of the display panel is effectively improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing the same, and an electronic device. Background Technology

[0002] With the development of display technology, display panels are becoming increasingly common and have gradually become an indispensable component of electronic devices. Common display panels include LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode). Among them, OLED display panels are the mainstream development trend in the display field due to their lighter and thinner profile, wider viewing angles, and significant power savings. OLED display panels require at least an organic encapsulation layer to isolate the materials and circuitry within the OLED panel from the external environment's moisture and oxygen. However, in the current manufacturing process of OLED display panels, quality monitoring of the organic encapsulation layer is difficult, reducing the panel's manufacturing efficiency. Summary of the Invention

[0003] In view of this, this application provides a display panel, a method for manufacturing the same, and an electronic device, which effectively solves the technical problems existing in the prior art, reduces the difficulty of quality monitoring of organic encapsulation layers, and not only improves the debugging efficiency of printing equipment, but also improves the manufacturing efficiency of display panels.

[0004] To achieve the above objectives, the technical solution provided in this application is as follows:

[0005] A display panel, comprising:

[0006] substrate;

[0007] A transistor array layer and a barrier wall are located on one side surface of the substrate. The barrier wall surrounds the transistor array layer. The transistor array layer includes an outer edge facing the barrier wall, and a clearance area is provided between the barrier wall and the outer edge of the transistor array layer. At least one packaging monitoring area is provided at the outer edge of the transistor array layer, and the packaging monitoring area is connected to the clearance area.

[0008] An organic encapsulation layer is located on the side of the transistor array layer facing away from the substrate. The organic encapsulation layer is located within the area surrounded by the barrier. The organic encapsulation layer covers the transistor array layer, the package monitoring area, and at least a portion of the clearance area. The organic encapsulation layer extends to contact the side of the barrier facing the transistor array layer and opposite at least one of the package monitoring areas.

[0009] Optionally, the display panel includes a display stack layer, the display stack layer including the transistor array layer, and,

[0010] A planarization layer located on the side of the transistor array layer opposite to the substrate;

[0011] A light-emitting structure layer located on the side of the planarization layer opposite to the substrate, wherein at least a portion of the sub-stacked layer of the transistor array layer, the planarization layer, and the light-emitting structure layer are hollowed out at the location corresponding to the packaging monitoring area.

[0012] Optionally, the display panel further includes:

[0013] A first inorganic encapsulation layer is located between the organic encapsulation layer and the transistor array layer, and the first inorganic encapsulation layer extends to cover the barrier.

[0014] Wherein, at the stacked structure of the barrier and the first inorganic encapsulation layer, the organic encapsulation layer extends to contact the side of the stacked structure facing the transistor array layer and relative to the encapsulation monitoring area.

[0015] Optionally, the display panel further includes:

[0016] The second inorganic encapsulation layer is located on the side of the organic encapsulation layer opposite to the substrate, and the second inorganic encapsulation layer extends to cover the barrier.

[0017] Optionally, the outer edge of the transistor array layer includes at least two package monitoring regions, and the at least two package monitoring regions are respectively located on opposite sides of the transistor array layer.

[0018] Optionally, in the orthographic projection of the transistor array layer onto the surface of the substrate, the outer edge of the transistor array layer includes at least one bend, and at least one of the bends includes at least one of the package monitoring regions.

[0019] Optionally, in the orthographic projection of the transistor array layer onto the surface of the substrate, the transistor array layer includes two edge lines disposed opposite each other in a first direction and two edge lines disposed opposite each other in a second direction, and at least two of the edge lines intersecting in the extension direction are connected by a bend line to form the bend portion, wherein the first direction and the second direction intersect.

[0020] Optionally, the bend line includes an arc, and at least two edge lines that intersect in the extension direction are connected by the arc to form an R-angle.

[0021] Optionally, at at least one of the bending portions, a packaging monitoring area is provided at the junction of the bending line and at least one of the edge lines.

[0022] Optionally, in the orthographic projection of the transistor array layer onto the surface of the substrate, the transistor array layer includes four bends distributed in a clockwise direction;

[0023] At each of the bending portions, a packaging monitoring area is provided at the junction of the bending line and the two edge lines.

[0024] Optionally, at the connection between the bend line and the edge line, there is a break between the endpoint of the bend line and the endpoint of the edge line, and the endpoint of the bend line and the endpoint of the edge line are connected by a break line, and the endpoint of the bend line is located on the side of the edge line facing the center of the display stacked layer.

[0025] The encapsulation monitoring area is located at the junction of the break line and the bend line.

[0026] Based on the same inventive concept, this application also provides a method for manufacturing a display panel, used to manufacture the above-mentioned display panel, the method comprising:

[0027] A1. Adjust the parameters of the printing equipment for organic encapsulation materials. The adjustment methods include:

[0028] A11. A semi-finished display panel without organic encapsulation is provided, the semi-finished display panel including a substrate; a transistor array layer and a barrier wall located on one side surface of the substrate, the barrier wall surrounding the transistor array layer, the transistor array layer including an outer edge facing the barrier wall, and a clearance area is provided between the barrier wall and the outer edge of the transistor array layer, wherein at least one encapsulation monitoring area is provided at the outer edge of the transistor array layer, and the encapsulation monitoring area is connected to the clearance area;

[0029] A12. The printing equipment is used to print the semi-finished display panel to form an organic encapsulation layer, wherein the printing area of ​​the printing equipment is the corresponding area of ​​the transistor array layer;

[0030] A13. Monitor whether the organic encapsulation layer extends to contact the side of the barrier facing the transistor array layer and relative to at least one of the encapsulation monitoring areas. If yes, determine that the current parameters of the printing device are normal and proceed to step S2. If no, adjust the parameters of the printing device and repeat steps A11 to A13 until the parameters of the printing device are determined to be normal and proceed to step A2.

[0031] A2. Based on the debugged printing equipment, perform organic encapsulation on the display panel to be organically encapsulated.

[0032] Optionally, monitoring whether the organic encapsulation layer extends to contact the side of the barrier facing the transistor array layer and relative to the encapsulation monitoring area includes:

[0033] Optical electronic instruments are used to monitor the reflectivity of the barrier wall on the side facing the transistor array layer and relative to the package monitoring area. If the reflectivity is not greater than a set value, it is determined that the organic package layer extends into contact with the barrier wall on the side facing the transistor array layer and relative to the package monitoring area; if the reflectivity is greater than the set value, it is determined that the organic package layer does not extend into contact with the barrier wall on the side facing the transistor array layer and relative to the package monitoring area.

[0034] Optionally, the semi-finished display panel further includes a first inorganic encapsulation layer, which is located on the side of the transistor array layer facing away from the substrate, and extends to cover the barrier; step S13 is:

[0035] At the stacked structure of the barrier and the first inorganic encapsulation layer, it is monitored whether the organic encapsulation layer extends into contact with the side of the transistor array layer relative to the encapsulation monitoring area.

[0036] Based on the same inventive concept, this application also provides an electronic device, which includes the above-described display panel.

[0037] Compared with existing technologies, the technical solution provided in this application has at least the following advantages:

[0038] This application provides a display panel, a method for fabricating the same, and an electronic device thereof. The display panel includes: a substrate; a transistor array layer and a barrier wall located on one side surface of the substrate, the barrier wall surrounding the transistor array layer, the transistor array layer including an outer edge facing the barrier wall, and a clearance area between the barrier wall and the outer edge of the transistor array layer, wherein at least one packaging monitoring area is provided at the outer edge of the transistor array layer, and the packaging monitoring area is connected to the clearance area; an organic encapsulation layer located on the side of the transistor array layer facing away from the substrate, the organic encapsulation layer being located within the area surrounded by the barrier wall, the organic encapsulation layer covering the transistor array layer, the packaging monitoring area, and at least a portion of the clearance area, and the organic encapsulation layer extending to contact the side of the barrier wall facing the transistor array layer and opposite at least one of the packaging monitoring areas.

[0039] As described above, the technical solution provided in this application achieves the purpose of setting organic encapsulation monitoring points on the display panel by setting an encapsulation monitoring area connected to the clearance area at the outer edge of the transistor array layer. Specifically, during the fabrication of the organic encapsulation layer in the display panel, the organic encapsulation layer prepared in the display panel is judged to meet expectations by monitoring whether the side of the barrier relative to the encapsulation monitoring area is covered by organic encapsulation material, thereby solving the problem of difficult quality monitoring of organic encapsulation layers in the prior art. Furthermore, the organic encapsulation layer quality monitoring method provided in this application is simple and time-saving, effectively improving the fabrication efficiency of the display panel. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0041] Figure 1 This is a partial structural diagram of a display panel provided in an embodiment of this application;

[0042] Figure 2 This application provides a partial overlay diagram of a display panel according to an embodiment of the present application;

[0043] Figure 3 This is a partial overlay diagram of another display panel provided in an embodiment of this application;

[0044] Figure 4 This is a partial overlay diagram of another display panel provided in an embodiment of this application;

[0045] Figure 5 This is a partial overlay diagram of another display panel provided in an embodiment of this application;

[0046] Figure 6 This is a partial overlay diagram of another display panel provided in an embodiment of this application;

[0047] Figure 7 This is a partial overlay diagram of another display panel provided in an embodiment of this application;

[0048] Figure 8 This is a partial overlay diagram of another display panel provided in an embodiment of this application;

[0049] Figure 9 This is a partial overlay diagram of another display panel provided in an embodiment of this application;

[0050] Figure 10This is a partial structural diagram of another display panel provided in an embodiment of this application;

[0051] Figure 11 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0052] Figure 12 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0053] Figure 13 This is a partial structural diagram of a bent portion provided in an embodiment of this application;

[0054] Figure 14 This is a partial structural schematic diagram of another display panel provided in an embodiment of this application;

[0055] Figure 15 A flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application;

[0056] Figure 16 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0057] Figure label:

[0058] 10-Display panel; 100-Substrate; 200-Display stacked layer; 210-Transistor array layer; 2011-Bending line; 2012-Break line; 211-Semiconductor layer; 212-Gate insulating layer; 213-Gate metal layer; 214-Interlayer insulating layer; 215-Source / drain metal layer; 220-Planarization layer; 230-Light-emitting structure layer; 231-Anode layer; 232-Pixel definition layer; 233-Light-emitting layer; 234 - Cathode layer; 201 - Encapsulation monitoring area; 310 - Barrier wall; 320 - Auxiliary barrier wall; 410 - Organic encapsulation layer; 421 - First inorganic encapsulation layer; 422 - Second inorganic encapsulation layer; NA - Clearance area; TFT - Transistor; S1 - Bending section; S11 - First bending section; S12 - Second bending section; S13 - Third bending section; S14 - Fourth bending section; First direction X; Second direction Y; 1000 - Electronic device. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0060] As described in the background section, with the development of display technology, display panels are becoming increasingly common and have gradually become an indispensable component of electronic devices. Common display panels include LCD and OLED. Among them, OLED display panels have become the mainstream development trend in the display field due to their lighter and thinner profile, wider viewing angles, and significant power savings. OLED display panels require at least an organic encapsulation layer to isolate the materials and circuitry within the OLED display panel from the external environment's water and oxygen. However, in the manufacturing of existing OLED display panels, quality monitoring of the organic encapsulation layer is difficult, reducing the panel's manufacturing efficiency.

[0061] Based on this, the embodiments of this application provide a display panel, a method for manufacturing the same, and an electronic device, which effectively solves the technical problems existing in the prior art, reduces the difficulty of quality monitoring of organic encapsulation layers, and not only improves the debugging efficiency of printing equipment, but also improves the manufacturing efficiency of display panels.

[0062] To achieve the above objectives, the technical solutions provided in this application are as follows, in specific combination with... Figures 1 to 16 The technical solutions provided in the embodiments of this application will be described in detail.

[0063] Combination Figure 1 As shown and Figure 2 As shown, Figure 1 This is a partial structural diagram of a display panel from a top view, provided in an embodiment of this application. Figure 2 A partial overlay diagram of a display panel provided in an embodiment of this application (e.g.) Figure 1 (Partial superimposed diagram along the AA' section direction). The display panel 10 provided in this application embodiment includes: a substrate 100; a transistor array layer 210 and a barrier 310 located on one side surface of the substrate 100, the barrier 310 surrounding the transistor array layer 210, the transistor array layer 210 including an outer edge facing the barrier 310, and a clearance area NA disposed between the barrier 310 and the outer edge of the transistor array layer 210, wherein at least one packaging monitoring area 201 is disposed at the outer edge of the transistor array layer 210, and the packaging monitoring area 201 is connected to the clearance area NA; an organic encapsulation layer 410 located on the side of the transistor array layer 210 away from the substrate 100, the organic encapsulation layer 410 being located within the surrounding area of ​​the barrier 310, the organic encapsulation layer 410 covering the transistor array layer 210, the packaging monitoring area 201 and at least a portion of the clearance area NA, and the organic encapsulation layer 410 extending to contact the side of the barrier 310 facing the transistor array layer 210 and opposite to at least one of the packaging monitoring areas 201.

[0064] At the outer edge of the transistor array layer 210 provided in this embodiment, the transistor array layer 210 has at least one recessed area that faces the central region of the transistor array layer 210. This recessed area may not have any circuit structure of the transistor array layer 210, or it may have a partial insulating structure of the transistor array layer 210, or a partial metal circuit of the transistor array layer 210, or a combination of a partial insulating structure and a partial metal circuit of the transistor array layer 210, so that the recessed area has the same structure as the clearance area NA, and this recessed area is defined as the encapsulation monitoring area 201. The organic encapsulation material is a flowable material. The organic encapsulation material is printed onto the printing area of ​​the display panel 10 using a printing device, and then flows outwards to complete the encapsulation, resulting in the organic encapsulation layer 410. Generally, during the organic encapsulation process of the display panel 10, the area where the transistor array layer 210 is located is the printing area, and the organic device prints the organic encapsulation material in this printing area. When preparing the organic encapsulation layer 410 in the display panel 10, organic encapsulation material needs to be printed in the corresponding area of ​​the transistor array layer 210. Then, the organic encapsulation material flows to the clearance area NA and at least part of the organic encapsulation material flows to the inner wall surface of the barrier 310 surrounding the transistor array layer 210 to complete the preparation of the organic encapsulation layer 410.

[0065] Currently, when monitoring the quality of the organic encapsulation layer 410, it is necessary to determine whether the side of the barrier 310 at the monitoring point is covered by the organic encapsulation layer 410. If not, the quality of the organic encapsulation layer 410 is determined to be unsatisfactory. However, in reality, the organic encapsulation layer 410 may cover the side of the barrier 310 in areas other than the monitoring point. Although the monitoring point may not detect any coverage of the side of the barrier 310 by the organic encapsulation layer 410, the organic encapsulation layer 410 is still considered to be satisfactory and qualified. Therefore, the existing technology cannot perform more accurate monitoring of the organic encapsulation layer 410, which is not only inefficient but also prone to misjudgment. Especially with the trend of narrow bezels in the display panel 10, the area of ​​the clearance area NA is being compressed smaller and smaller, making the quality monitoring of the organic encapsulation layer 410 even more difficult. In this embodiment, a recessed encapsulation monitoring region 201 is provided at the outer edge of the transistor array layer 210. The encapsulation monitoring region 201 is located within the printing area, and its structure is the same as that of the clearance area NA. The encapsulation monitoring region 201 can be regarded as an extension of the clearance area NA in the transistor array layer 210, thus connecting the encapsulation monitoring region 201 with the clearance area NA. Therefore, when printing organic encapsulation material in the corresponding printing area of ​​the transistor array layer 210, the organic encapsulation material can preferentially flow into the clearance area NA through the encapsulation monitoring region 201, allowing the organic encapsulation material in this area to flow and cover the side of the barrier 310 preferentially compared to other areas. Therefore, by monitoring whether the side of the barrier 310 relative to the encapsulation monitoring region 201 is covered by organic encapsulation material, it is possible to effectively determine whether the organic encapsulation layer 410 meets expectations.

[0066] It is understood that the technical solution provided in this application provides an organic encapsulation monitoring point on the display panel 10 by setting an encapsulation monitoring area 201 connected to the clearance area NA at the outer edge of the transistor array layer 210. Specifically, during the fabrication of the organic encapsulation layer on the transistor array layer 210, the organic encapsulation layer 410 fabricated in the display panel 10 is judged to meet expectations by monitoring whether the side of the barrier 310 relative to the encapsulation monitoring area 201 is covered by organic encapsulation material, thereby solving the problem of difficult quality monitoring of the organic encapsulation layer 410 in the prior art. Furthermore, the organic encapsulation layer 410 quality monitoring method provided in this application is simple and time-saving, effectively improving the fabrication efficiency of the display panel 10.

[0067] In some embodiments, the transistor array layer 210 provided in this application, on the side facing away from the substrate 100, further includes some planar structures and light-emitting structures, and the transistor array layer 210, the planar structures, and the light-emitting structures are all within the coverage area of ​​the organic encapsulation layer 410, so as to achieve the encapsulation effect of the display panel 10. See details. Figure 3The diagram shown is a partial overlay diagram of another display panel provided in an embodiment of this application. The display panel 10 provided in this embodiment includes a display overlay layer 200, an organic encapsulation layer 410 covering the display overlay layer 200, the display overlay layer 200 including the transistor array layer 210; a planarization layer 220 located on the side of the transistor array layer 210 facing away from the substrate 100; and a light-emitting structure layer 230 located on the side of the planarization layer 220 facing away from the substrate. At least a portion of the sub-overlay layer of the transistor array layer 210, the planarization layer 220, and the light-emitting structure layer 230 are hollowed out at the encapsulation monitoring area 201. In other words, at the outer edge of the display stacked layer 200 provided in this embodiment, the display stacked layer 200 has at least one recessed area facing the central region of the display stacked layer 200. The recessed area may not have any circuit structures of the transistor array layer 210, planarization layer 220, and light-emitting structure layer 230, or it may only have a partial insulating structure of the transistor array layer 210, making the recessed area structurally identical to the clearance area NA, and defining this recessed area as the encapsulation monitoring area 201. Based on the display panel 10 including the display stacked layer 200, the area where the display stacked layer 200 is located is the printing area, and the surface of the display stacked layer 200 facing away from the substrate 100 is the printing surface, which is the surface on which the printing equipment prints the organic encapsulation material. During the preparation of the organic encapsulation layer 410 in the display panel 10, organic encapsulation material needs to be printed on the surface of the display stacked layer 200 facing away from the substrate 100, and then the organic encapsulation material flows outwards to the clearance area NA.

[0068] The transistor TFTs included in the transistor array layer 210 provided in this embodiment can be top-gate transistors. See details... Figure 4 The diagram shown is a partial stacked view of another display panel provided in an embodiment of this application. The transistor array layer 210 provided in this embodiment includes: a semiconductor layer 211 located on a substrate 100, the semiconductor layer 211 including an active region forming a transistor TFT; a gate insulating layer 212 located on the side of the semiconductor layer 211 facing away from the substrate 100; a gate metal layer 213 located on the side of the gate insulating layer 212 facing away from the substrate 100, the gate metal layer 213 including a gate for forming a transistor TFT; an interlayer insulating layer 214 located on the side of the gate metal layer 213 facing away from the substrate 100; and a source / drain metal layer 215 located on the side of the interlayer insulating layer 214 facing away from the substrate 100, the source / drain metal layer 215 including a source and a drain for forming a transistor TFT, the source and drain being connected to the active layer through an insulating material.

[0069] Alternatively, the transistor TFTs included in the transistor array layer 210 provided in this embodiment can also be bottom-gate transistors. (See reference...) Figure 5The diagram shown is a partial stacked view of another display panel provided in an embodiment of this application. The transistor array layer 210 provided in this embodiment includes: a gate metal layer 213 located on a substrate 100, the gate metal layer 213 including a gate for forming a transistor TFT; a gate insulating layer 212 located on the side of the gate metal layer 213 facing away from the substrate 100; a semiconductor layer 211 located on the side of the gate insulating layer 212 facing away from the substrate 100, the semiconductor layer 211 including an active region for forming a transistor TFT; an interlayer insulating layer 214 located on the side of the semiconductor layer 211 facing away from the substrate 100; and a source / drain metal layer 215 located on the side of the interlayer insulating layer 214 facing away from the substrate 100, the source / drain metal layer 215 including a source and a drain for forming a transistor TFT, the source and drain being connected to the active layer through an insulating material.

[0070] It should be noted that the transistor array layer 210 provided in this application embodiment may further include a passivation layer located on the side of the source / drain metal layer 215 facing away from the substrate 100, and the side of the passivation layer facing away from the substrate 100 is a planarization layer 220; or, the side of the source / drain metal layer 215 of the transistor array layer 210 provided in this application embodiment is directly a planarization layer 220, which is the same as the prior art, so this application will not elaborate further. Figure 4 As shown, in the display stack layer 200 provided in this embodiment, the transistor array layer 210, planarization layer 220, and light-emitting structure layer 230 are all hollowed out at the corresponding packaging monitoring area 201, exposing the substrate 100 at the packaging monitoring area 201. The substrate 100 is also exposed at the corresponding clearance area NA, thus connecting the packaging monitoring area 201 and the clearance area NA. Alternatively, as... Figure 5As shown, in the display stack layer 200 provided in this embodiment, the planarization layer 220 and the light-emitting structure layer 230 are hollowed out at the corresponding packaging monitoring area 201. In the transistor array layer 210, the conductive layers such as the semiconductor layer 211, the gate metal layer 213, and the source / drain metal layer 215 are all hollowed out at the corresponding packaging monitoring area 201. At least one of the insulating layers such as the gate insulating layer 212 and the interlayer insulating layer 214 retains an insulating layer at the corresponding packaging monitoring area 201. Similarly, the insulating layer retained at the packaging monitoring area 201 extends to the clearance area NA to connect the packaging monitoring area 201 and the clearance area NA. This embodiment does not specifically limit whether the substrate 100 is exposed at the corresponding packaging monitoring area 201 and the clearance area NA, or whether at least part of the insulating layer is retained at the corresponding packaging monitoring area 201 and the clearance area NA. Specific design is required based on the actual application. Alternatively, in the display stack layer 200 provided in this application embodiment, the planarization layer 220 and the light-emitting structure layer 230 are hollowed out at the corresponding package monitoring area 201, while in the transistor array layer 210, at least a portion of the lines of the conductive layers such as the semiconductor layer 211, the gate metal layer 213, and the source / drain metal layer 215 are present at the corresponding package monitoring area 201, and at least one of the insulating layers such as the gate insulating layer 212 and the interlayer insulating layer 214 retains an insulating layer at the corresponding package monitoring area 201; similarly, the metal lines of the corresponding conductive layers and the corresponding insulating layers also extend to the clearance area NA (such as the cathode power line PVEE, etc., which are not specifically limited) to connect the package monitoring area 201 and the clearance area NA.

[0071] Furthermore, the light-emitting structure layer 230 provided in this embodiment can be an organic light-emitting structure layer. (See reference...) Figure 6 The diagram shown is a partial overlay diagram of another display panel provided in this application embodiment. The light-emitting structure layer 230 provided in this application embodiment includes: an anode layer 231 located on the side of the planarization layer 220 facing away from the substrate 100, the anode layer 231 including multiple anode blocks; a pixel definition layer 232 located on the side of the anode layer 231 facing away from the substrate 100, the pixel definition layer 232 including multiple pixel definition holes, each pixel definition hole corresponding to an anode block; a light-emitting layer 233 located in the pixel definition holes; and a cathode layer 234 located on the side of the light-emitting layer 233 facing away from the substrate 100. The cathode layer 234 can be a single cathode or a structure of multiple cathode blocks connected together; this application does not impose specific limitations on this. In this application embodiment, the anode layer 231, pixel definition layer 232, light-emitting layer 233, and cathode layer 234 are hollowed out at the corresponding encapsulation monitoring area 201.

[0072] In some embodiments, the encapsulation structure provided in this application may include inorganic encapsulation films in addition to the organic encapsulation layer 410, thereby improving the encapsulation effect. See details. Figure 7The diagram shown is a partial stacked structure of another display panel provided in this application embodiment. The display panel 10 provided in this application embodiment further includes: a first inorganic encapsulation layer 421, which is located between the organic encapsulation layer 410 and the transistor array layer 210, and extends to cover the barrier 310; wherein, at the stacked structure of the barrier 310 and the first inorganic encapsulation layer 421, the organic encapsulation layer 410 extends to contact the side of the stacked structure facing the transistor array layer 210 and opposite to the encapsulation monitoring area 201. The first inorganic encapsulation layer 421 is disposed between the organic encapsulation layer 410 and the transistor array layer 210, thereby improving the protective effect of the encapsulation structure and further reducing the problem of moisture erosion of the internal circuitry of the display panel 10. In some embodiments, when the display panel 10 provided in this application embodiment includes a display stacked layer 200, the first inorganic encapsulation layer 421 is located between the display stacked layer 200 and the organic encapsulation layer 410. The first inorganic encapsulation layer 421 provided in this application embodiment may only cover the side of the barrier 310 facing the transistor array layer 210; or the first inorganic encapsulation layer 421 may also extend to cover the surface of the barrier 310 away from the substrate 100; or the first inorganic encapsulation layer 421 may also extend to cover the side of the barrier 310 away from the transistor array layer 210, or even continue to extend to the surface area of ​​the substrate 100. By designing the extension coverage of the first inorganic encapsulation layer 421, the encapsulation structure can meet expectations, and this application does not impose specific limitations on this.

[0073] refer to Figure 8The diagram shown is a partial stacked view of another display panel provided in this application embodiment. The display panel 10 provided in this application embodiment further includes a second inorganic encapsulation layer 422, which is located on the side of the organic encapsulation layer 410 away from the substrate 100, and extends to cover the barrier 310. After the organic encapsulation layer 410 is prepared, the second inorganic encapsulation layer 422 is prepared again on the organic encapsulation layer 410, thereby improving the protective effect of the encapsulation structure and further reducing the problem of moisture erosion of the internal circuitry of the display panel 10. The second inorganic encapsulation layer 422 provided in this application embodiment can cover the side of the barrier 310 away from the substrate 100; or the second inorganic encapsulation layer 422 can also extend to cover the side of the barrier 310 away from the transistor array layer 210, or even continue to extend to the corresponding area on the surface of the substrate 100. By designing the extension coverage range of the second inorganic encapsulation layer 422, the encapsulation structure meets expectations, and this application does not impose specific limitations on this. Furthermore, the display panel 10 provided in this application embodiment may include only the first inorganic encapsulation layer 421 or only the second inorganic encapsulation layer 422; or, the display panel 10 provided in this application embodiment may also include both the first inorganic encapsulation layer 421 and the second inorganic encapsulation layer 422, so that the protection effect of the encapsulation structure is higher. The specific selection needs to be made according to the actual application.

[0074] Furthermore, the display panel 10 provided in this embodiment may also include more barrier structures. (See reference...) Figure 9 The diagram shown is a partial overlay of another display panel provided in this application embodiment. The display panel 10 provided in this application embodiment may further include an auxiliary barrier 320 surrounding the barrier 310. When the display panel 10 includes a first inorganic encapsulation layer 421 and a second inorganic encapsulation layer 422, at least one of the first inorganic encapsulation layer 421 and the second inorganic encapsulation layer 422 may extend to cover the area between the auxiliary barrier 320 and the barrier 310, and may even extend to the side of the auxiliary barrier 320 facing the barrier 310. This application does not impose specific limitations on this.

[0075] The stacked structure of the encapsulation monitoring area 201 in the sectional direction provided in the embodiments of this application has been described above. The distribution of the encapsulation monitoring area 201 in the display panel 10 provided in the embodiments of this application will be described in more detail below with reference to the accompanying drawings.

[0076] like Figure 1As shown, the display panel 10 provided in this embodiment may include only one encapsulation monitoring area 201. The manufacturing quality of the organic encapsulation layer 410 can be monitored by judging whether the organic encapsulation layer 410 at the encapsulation monitoring area 201 covers the side of the barrier wall 310. Alternatively, the display panel 10 provided in this embodiment may also have more encapsulation monitoring areas 201. The manufacturing quality of the organic encapsulation layer 410 can be monitored by judging whether the organic encapsulation layer 410 at all encapsulation monitoring areas 201 covers the side of the barrier wall 310. When the display panel 10 has more encapsulation monitoring areas 201, it can be set that when only one encapsulation monitoring area 201 has the organic encapsulation layer 410 covering the side of the barrier wall 310, it can be determined that the quality of the organic encapsulation layer 410 meets expectations. Alternatively, it can be set that when a preset number of encapsulation monitoring areas 201 have the organic encapsulation layer 410 covering the side of the barrier wall 310, it can be determined that the quality of the organic encapsulation layer 410 meets expectations. This application does not impose specific limitations on this.

[0077] For details, please refer to the following: Figure 10 The diagram shown is a partial top view of another display panel provided in this embodiment. The transistor array layer 210 provided in this embodiment includes at least two encapsulation monitoring areas 201 at its outer edge, and these at least two encapsulation monitoring areas 201 are respectively located on opposite sides of the transistor array layer 210. By setting different encapsulation monitoring areas 201, the coverage of the organic encapsulation layer 410 on the side of the barrier 310 in different areas is monitored, thereby improving the monitoring effect of the organic encapsulation layer 410 fabrication quality. Furthermore, by setting the encapsulation monitoring areas 201 on opposite sides of the transistor array layer 210, the distance span between different encapsulation monitoring areas 201 is increased, further improving the monitoring effect of the organic encapsulation layer 410 fabrication quality, ensuring higher fabrication quality of the organic encapsulation layer 410, and improving the encapsulation effect. Similarly, when the display panel 10 provided in this embodiment includes a display stack layer 200, at least two of the encapsulation monitoring areas 201 in the display panel 10 can be respectively located on opposite sides of the display stack layer 200.

[0078] In some embodiments, the encapsulation monitoring area 201 provided in this application is preferably located in an area of ​​the display panel 10 with a low wiring density, thereby avoiding the impact of the encapsulation monitoring area 201 on the panel wiring and ensuring a larger effective wiring area for the display panel 10. For example... Figure 11The diagram shown is a partial top view of another display panel provided in this application embodiment. In the orthographic projection of the transistor array layer 210 on the surface of the substrate 100, the outer edge of the transistor array layer 210 includes at least one bent portion S1, and at least one of the bent portions S1 includes at least one of the encapsulation monitoring areas 201. Similarly, when the transistor array layer 210 of the display panel 10 includes a planarization layer 220 and a light-emitting structure layer 230, the display stack layer 200 formed by stacking the transistor array layer 210, the planarization layer 220, and the light-emitting structure layer 230 has the same shape in the orthographic projection on the surface of the substrate 100 as the transistor array layer 210 in the orthographic projection on the surface of the substrate 100; the display stack layer 200 has a bent portion S1 at the same position as the transistor array layer 210, and at least one bent portion S1 includes at least one encapsulation monitoring area 201.

[0079] Optionally, the bending portion S1 provided in this embodiment can be an irregularly shaped structure formed on the edge extension path of the transistor array layer 210. Alternatively, the bending portion S1 can also be the area where two adjacent edge lines of the transistor array layer 210 intersect; this application does not specifically limit this. (Continue to refer to...) Figure 11 As shown, in the orthographic projection of the transistor array layer 210 provided in this embodiment of the application onto the surface of the substrate 100, the transistor array layer 210 includes two edge lines disposed opposite each other in the first direction X, and two edge lines disposed opposite each other in the second direction Y. At least two of the edge lines intersecting in the extension direction are connected by a bending line 2011 to form the bending portion S1 where the first direction X and the second direction Y intersect (the first direction X and the second direction Y may be perpendicular). There are fewer lines at the bending portion S1, which facilitates the setting of the encapsulation monitoring area 201. That is to say, in the orthographic projection of the transistor array layer 210 provided in this embodiment of the application onto the surface of the substrate 100, the shape of the transistor array layer 210 can be a quadrilateral shape formed by the intersection of the two edge lines disposed opposite each other in the first direction X and the two edge lines disposed opposite each other in the second direction Y, such as a rectangular shape; all the encapsulation monitoring areas 201 of the display panel 10 can be concentrated at the same bending portion S1. Alternatively, in the display panel 10 provided in this application embodiment, at least one encapsulation monitoring area 201 can be provided at each bend S1; see details below. Figure 12The diagram shown is a partial structural schematic from a top view of another display panel provided in this application embodiment. In the orthographic projection of the transistor array layer 210 provided in this application embodiment onto the surface of the substrate 100, the outer edge of the transistor array layer 210 includes four bends S1 located at the four vertices, respectively defined as the first bend S11, the second bend S12, the third bend S13, and the fourth bend S14. At least one encapsulation monitoring area 201 is provided at any one of the first bend S11, the second bend S12, the third bend S13, and the fourth bend S14, thereby monitoring the situation of the organic encapsulation layer 410 covering the side of the barrier 310 in at least four regions during the preparation of the organic encapsulation layer 410, thereby improving the monitoring effect.

[0080] In some embodiments, the bend line 2011 connecting two intersecting edge lines provided in this application can be a right-angle bend line, an obtuse-angle bend line, or an acute-angle bend line. Furthermore, the bend line 2011 can also be an arc shape; this application does not impose specific limitations on this. (See reference...) Figure 13 The diagram shown is a partial top-view structural schematic of another display panel provided in this application embodiment. The bending line 2011 provided in this application embodiment includes an arc line, and at least two intersecting edge lines in the extension direction are connected by the arc line to form an R-angle. The encapsulation monitoring area 201 provided in this application embodiment can be set in the central area of ​​the bending line 2011. Since the central area of ​​the bending line 2011 and the bend of the baffle 310 have a large direct distance, when the organic encapsulation layer 410 is detected to cover the side of the encapsulation monitoring area 201 facing the baffle 310, it can be determined that most of the remaining areas of the transistor array layer 210 with a small direct distance from the side of the baffle 310 are covered by the organic encapsulation layer 410, resulting in higher quality of the organic encapsulation layer 410.

[0081] The encapsulation monitoring area 201 provided in this embodiment can also be located at the junction of the bend line 2011 and the edge line. (See reference...) Figure 13 The diagram shown is a partial structural diagram of a bent portion according to an embodiment of this application. At at least one bent portion S1, an encapsulation monitoring area 201 is provided at the connection point of the bending line 2011 and at least one edge line. Because the distance between the connection point of the bending line 2011 and the edge line and the retaining wall 310 is smaller, it is easier to monitor the situation where the organic encapsulation layer 410 covers the side of the retaining wall 310, reducing monitoring difficulty and improving monitoring efficiency, thereby improving the panel manufacturing efficiency. Continuing as... Figure 13As shown, at the connection between the bend line 2011 and the edge line, there is a break h between the endpoint of the bend line 2011 and the endpoint of the edge line. The endpoint of the bend line 2011 and the endpoint of the edge line are connected by a break line 2012. The endpoint of the bend line 2011 is located on the side of the edge line facing the center of the transistor array layer 210. The package monitoring area 201 is located at the connection between the break line 2012 and the bend line 2011. Thus, by setting the package monitoring area 201 at the connection between the bend line 2011 and the edge line, and by optimizing the shape of the connection between the bend line 2011 and the edge line, the overall bending shape of the bending portion S1 can be maintained.

[0082] In some embodiments, in all the bent portions S1 of the display panel 10 provided in this application embodiment, a sealing monitoring area 201 is provided at the connection point between the bending line 2011 and the two connected edge lines. (See reference) Figure 14 The diagram shown is a partial structural schematic from a top view of another display panel provided in this application embodiment. In the orthographic projection of the transistor array layer 210 provided in this application embodiment onto the surface of the substrate 100, the transistor array layer 210 includes four bent portions S1 distributed in a clockwise direction, which are respectively defined as the first bent portion S11, the second bent portion S12, the third bent portion S13, and the fourth bent portion S14; at each of the bent portions S1, a packaging monitoring area 201 is respectively provided at the connection between the bending line 2011 and the two edge lines. In particular, at the first bend S11, the second bend S12, the third bend S13 and the fourth bend S14, two encapsulation monitoring areas 201 are respectively provided at each bend S1, so that there are a total of eight encapsulation monitoring areas 201 on the display panel 10. The eight encapsulation monitoring areas 201 are distributed at the four top corners of the transistor array layer 210, thereby enabling the monitoring of the organic encapsulation layer 410 covering the side of the barrier 310 in more areas, thereby improving the monitoring effect.

[0083] Based on the same inventive concept, this application also provides a method for manufacturing a display panel, used to manufacture the display panel 10 provided in any of the above embodiments. (Reference) Figure 15 The diagram shown is a flowchart of a method for manufacturing a display panel according to an embodiment of this application. The manufacturing method provided in this embodiment includes:

[0084] A1. Adjust the parameters of the printing equipment for organic encapsulation materials. The adjustment methods include:

[0085] A11. A semi-finished display panel without organic encapsulation is provided, the semi-finished display panel including a substrate; a transistor array layer and a barrier wall located on one side surface of the substrate, the barrier wall surrounding the transistor array layer, the transistor array layer including an outer edge facing the barrier wall, and a clearance area provided between the barrier wall and the outer edge of the transistor array layer, wherein at least one encapsulation monitoring area is provided at the outer edge of the transistor array layer, and the encapsulation monitoring area is connected to the clearance area.

[0086] A12. The printing equipment is used to print the semi-finished display panel to form an organic encapsulation layer, wherein the printing area of ​​the printing equipment is the corresponding area of ​​the transistor array layer.

[0087] A13. Monitor whether the organic encapsulation layer extends to contact the side of the barrier facing the transistor array layer and relative to at least one of the encapsulation monitoring areas. If yes, determine that the current parameters of the printing device are normal and proceed to step A2. If no, adjust the parameters of the printing device and repeat steps A11 to A13 until the parameters of the printing device are determined to be normal and proceed to step A2.

[0088] A2. Based on the debugged printing equipment, perform organic encapsulation on the display panel to be organically encapsulated.

[0089] It is understood that in the display panel fabrication method provided in this application embodiment, the provided semi-finished display panel includes an encapsulation monitoring area, thereby adjusting the parameters of the printing equipment based on the semi-finished display panel. Specifically, in the semi-finished display panel, an encapsulation monitoring area connected to the clearance area is set at the outer edge of the transistor array layer to achieve the purpose of setting organic encapsulation monitoring points on the semi-finished display panel. Furthermore, when fabricating the organic encapsulation layer on the transistor array layer, by monitoring whether the side of the barrier relative to the encapsulation monitoring area is covered by organic encapsulation material, it is determined whether the organic encapsulation layer fabricated in the semi-finished display panel meets expectations, thereby determining whether the parameters of the printing equipment for the organic encapsulation material meet expectations, thus completing the parameter debugging process of the printing equipment. The organic encapsulation layer quality monitoring method provided in this application embodiment is simple and time-saving, effectively improving the debugging efficiency of the printing equipment.

[0090] Meanwhile, the display panel to be organically encapsulated provided in this application embodiment is the display panel provided in any of the above embodiments (i.e., the panel before the organic encapsulation layer is prepared as illustrated in any of the above embodiments). When preparing the organic encapsulation layer on the transistor array layer, the organic encapsulation layer prepared in the display panel is judged to meet expectations by monitoring whether the side of the barrier relative to the encapsulation monitoring area is covered by organic encapsulation material, thereby solving the problem of difficult quality monitoring of organic encapsulation layers in the prior art. Furthermore, the organic encapsulation layer quality monitoring method provided in this application embodiment is simple and time-saving, effectively improving the preparation efficiency of the display panel.

[0091] In some embodiments, the method provided in this application for monitoring whether the organic encapsulation layer extends into contact with the side of the barrier facing the transistor array layer and relative to the encapsulation monitoring area includes: using an optical electronic instrument to monitor the reflective brightness at the side of the barrier facing the transistor array layer and relative to the encapsulation monitoring area; if the reflective brightness is not greater than a set value, it is determined that the organic encapsulation layer extends into contact with the side of the barrier facing the transistor array layer and relative to the encapsulation monitoring area; if the reflective brightness is greater than the set value, it is determined that the organic encapsulation layer does not extend into contact with the side of the barrier facing the transistor array layer and relative to the encapsulation monitoring area. It is understood that when the organic encapsulation layer provided in this application covers the side of the barrier, the brightness of the side of the barrier monitored by the optical electronic instrument is actually the corresponding reflective brightness of the organic encapsulation material, which is lower than the reflective brightness of the barrier. Therefore, it is possible to determine whether the organic encapsulation layer extends into contact with the side of the barrier facing the transistor array layer and relative to the encapsulation monitoring area by monitoring the brightness at the side of the barrier using an optical electronic instrument.

[0092] In some embodiments, the semi-finished display panel provided in this application further includes a first inorganic encapsulation layer. The first inorganic encapsulation layer is located on the side of the transistor array layer opposite to the substrate, and the first inorganic encapsulation layer extends to cover the barrier. Therefore, the side of the barrier being monitored is actually the side of the first inorganic encapsulation layer being monitored. That is, step A13 provided in this application is: at the stacked structure of the barrier and the first inorganic encapsulation layer, monitoring whether the organic encapsulation layer extends to contact the side of the transistor array layer relative to the encapsulation monitoring area. In other words, when using optical electronic instruments to monitor the organic encapsulation layer, monitoring the side brightness of the barrier is actually monitoring the side brightness of the first inorganic encapsulation layer.

[0093] Based on the same inventive concept, this application also provides an electronic device, which includes the display panel 10 provided in any of the above embodiments. (Reference) Figure 16The diagram shown is a structural schematic of an electronic device provided in an embodiment of this application. The electronic device 1000 provided in this embodiment can be a display device. Optionally, the electronic device 1000 provided in this embodiment can specifically be a mobile terminal, laptop, tablet computer, computer, wearable device, in-vehicle display device, etc., and this application does not impose specific limitations on this.

[0094] In summary, this application provides a display panel, its fabrication method, and an electronic device. The display panel includes: a substrate; a transistor array layer and a barrier wall located on one side surface of the substrate, the barrier wall surrounding the transistor array layer, the transistor array layer including an outer edge facing the barrier wall, and a clearance area between the barrier wall and the outer edge of the transistor array layer, wherein at least one encapsulation monitoring area is provided at the outer edge of the transistor array layer and is connected to the clearance area; an organic encapsulation layer located on the side of the transistor array layer facing away from the substrate, the organic encapsulation layer being located within the area surrounded by the barrier wall, the organic encapsulation layer covering the transistor array layer, the encapsulation monitoring area, and at least a portion of the clearance area, and the organic encapsulation layer extending to contact the side of the barrier wall facing the transistor array layer and opposite at least one of the encapsulation monitoring areas. As can be seen from the above, the technical solution provided by this application achieves the purpose of setting organic encapsulation monitoring points on the display panel by providing an encapsulation monitoring area connected to the clearance area at the outer edge of the transistor array layer. Specifically, during the fabrication of the organic encapsulation layer in the display panel, the presence of organic encapsulation material on the side of the barrier relative to the encapsulation monitoring area is monitored to determine whether the organic encapsulation layer fabricated in the display panel meets expectations. This solves the problem of difficult quality monitoring of organic encapsulation layers in existing technologies. Furthermore, the organic encapsulation layer quality monitoring method provided in this application is simple and time-saving, effectively improving the fabrication efficiency of the display panel.

[0095] In the description of the embodiments of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and other terms indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0097] In the embodiments of this application, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0098] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0099] In the embodiments of this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0100] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display panel, characterized in that, include: substrate; A transistor array layer and a barrier wall are located on one side surface of the substrate. The barrier wall surrounds the transistor array layer. The transistor array layer includes an outer edge facing the barrier wall, and a clearance area is provided between the barrier wall and the outer edge of the transistor array layer. At least one packaging monitoring area is provided at the outer edge of the transistor array layer, and the packaging monitoring area is connected to the clearance area. An organic encapsulation layer is located on the side of the transistor array layer facing away from the substrate. The organic encapsulation layer is located within the area surrounded by the barrier. The organic encapsulation layer covers the transistor array layer, the package monitoring area, and at least a portion of the clearance area. The organic encapsulation layer extends to contact the side of the barrier facing the transistor array layer and opposite at least one of the package monitoring areas.

2. The display panel according to claim 1, characterized in that, The display panel includes a display stack layer, the display stack layer including the transistor array layer, and, A planarization layer located on the side of the transistor array layer opposite to the substrate; A light-emitting structure layer located on the side of the planarization layer opposite to the substrate, wherein at least a portion of the sub-stacked layer of the transistor array layer, the planarization layer, and the light-emitting structure layer are hollowed out at the location corresponding to the packaging monitoring area.

3. The display panel according to claim 1, characterized in that, The display panel also includes: A first inorganic encapsulation layer is located between the organic encapsulation layer and the transistor array layer, and the first inorganic encapsulation layer extends to cover the barrier. Wherein, at the stacked structure of the barrier and the first inorganic encapsulation layer, the organic encapsulation layer extends to contact the side of the stacked structure facing the transistor array layer and relative to the encapsulation monitoring area.

4. The display panel according to claim 1, characterized in that, The display panel also includes: The second inorganic encapsulation layer is located on the side of the organic encapsulation layer opposite to the substrate, and the second inorganic encapsulation layer extends to cover the barrier.

5. The display panel according to claim 1, characterized in that, The outer edge of the transistor array layer includes at least two package monitoring regions, and the at least two package monitoring regions are respectively located on opposite sides of the transistor array layer.

6. The display panel according to claim 1, characterized in that, In the orthographic projection of the transistor array layer onto the surface of the substrate, the outer edge of the transistor array layer includes at least one bend, and at least one of the bends includes at least one of the package monitoring regions.

7. The display panel according to claim 6, characterized in that, In the orthographic projection of the transistor array layer onto the surface of the substrate, the transistor array layer includes two edge lines disposed opposite each other in a first direction and two edge lines disposed opposite each other in a second direction. At least two edge lines intersecting in the extension direction are connected by a bend line to form the bend portion. The first direction and the second direction intersect.

8. The display panel according to claim 7, characterized in that, The bend line includes an arc, and at least two edge lines that intersect in the extension direction are connected by the arc to form an R-angle.

9. The display panel according to claim 7, characterized in that, At at least one of the bending portions, a packaging monitoring area is provided at the junction of the bending line and at least one of the edge lines.

10. The display panel according to claim 9, characterized in that, The transistor array layer, in its orthographic projection onto the surface of the substrate, includes four bends distributed in a clockwise direction. At each of the bending portions, a packaging monitoring area is provided at the junction of the bending line and the two edge lines.

11. The display panel according to claim 9, characterized in that, At the junction of the bend line and the edge line, there is a break between the endpoint of the bend line and the endpoint of the edge line. The endpoint of the bend line and the endpoint of the edge line are connected by a break line. The endpoint of the bend line is located on the side of the edge line facing the center of the display stacked layer. The encapsulation monitoring area is located at the junction of the break line and the bend line.

12. A method for manufacturing a display panel, characterized in that, The method for preparing the display panel according to any one of claims 1-11 includes: A1. Adjust the parameters of the printing equipment for organic encapsulation materials. The adjustment methods include: A11. A semi-finished display panel without organic encapsulation is provided, the semi-finished display panel including a substrate; a transistor array layer and a barrier wall located on one side surface of the substrate, the barrier wall surrounding the transistor array layer, the transistor array layer including an outer edge facing the barrier wall, and a clearance area is provided between the barrier wall and the outer edge of the transistor array layer, wherein at least one encapsulation monitoring area is provided at the outer edge of the transistor array layer, and the encapsulation monitoring area is connected to the clearance area; A12. The printing equipment is used to print the semi-finished display panel to form an organic encapsulation layer, wherein the printing area of ​​the printing equipment is the corresponding area of ​​the transistor array layer; A13. Monitor whether the organic encapsulation layer extends to contact the side of the barrier facing the transistor array layer and relative to at least one of the encapsulation monitoring areas. If yes, determine that the current parameters of the printing device are normal and proceed to step A2. If no, adjust the parameters of the printing device and repeat steps A11 to A13 until the parameters of the printing device are determined to be normal and proceed to step A2. A2. Based on the debugged printing equipment, perform organic encapsulation on the display panel to be organically encapsulated.

13. The method for manufacturing a display panel according to claim 12, characterized in that, Monitoring whether the organic encapsulation layer extends into contact with the side of the barrier facing the transistor array layer and relative to the encapsulation monitoring area includes: Optical electronic instruments are used to monitor the reflectivity of the barrier wall on the side facing the transistor array layer and relative to the package monitoring area. If the reflectivity is not greater than a set value, it is determined that the organic package layer extends into contact with the barrier wall on the side facing the transistor array layer and relative to the package monitoring area; if the reflectivity is greater than the set value, it is determined that the organic package layer does not extend into contact with the barrier wall on the side facing the transistor array layer and relative to the package monitoring area.

14. The method for manufacturing a display panel according to claim 12, characterized in that, The semi-finished display panel further includes a first inorganic encapsulation layer, which is located on the side of the transistor array layer away from the substrate, and extends to cover the barrier; step A13 is: At the stacked structure of the barrier and the first inorganic encapsulation layer, it is monitored whether the organic encapsulation layer extends into contact with the side of the transistor array layer relative to the encapsulation monitoring area.

15. An electronic device, characterized in that, The electronic device includes the display panel as described in any one of claims 1-11.

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