Method for manufacturing a semiconductor power device and semiconductor power device

Abstract

This invention relates to the field of semiconductor technology, specifically providing a method for fabricating a semiconductor power device and the semiconductor power device itself. The method for fabricating the semiconductor power device includes: providing a substrate layer, the substrate layer including an active region and a termination region surrounding the active region; forming a patterned mask on the surface of the substrate layer; the patterned mask covering at least a portion of the surface of the termination region; etching the area of ​​the substrate layer surface not covered by the patterned mask to make the thickness of at least a portion of the termination region greater than the thickness of the active region, and to achieve a target thickness for the active region; removing the patterned mask, wherein the surface of the active region of the substrate layer is lower than the surface of the termination region and forms a stepped structure with the surface of the termination region. While ensuring the conduction characteristics of the semiconductor power device are matched (i.e., the thickness of the active region is the target thickness), the thickness of the termination region is indirectly increased, thereby balancing the conduction characteristics and breakdown resistance of the semiconductor power device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor power device and the semiconductor power device itself. Background Technology

[0002] Higher conduction characteristics are required for new generations of semiconductor power devices, further compressing the space for silicon thickness in the active region. Various terminal protection structures, such as field limiting rings and metal field plates, can only achieve 90% of the withstand voltage of the PN junction due to the influence of the curvature radius of the edge electric field, which makes it necessary to further improve the breakdown resistance of the terminal protection structure.

[0003] In the prior art, although various terminal protection structures can improve the radius of curvature of the edge electric field, the silicon thickness of the active region of semiconductor power devices cannot be increased due to the requirement of matching conduction characteristics. This results in the breakdown voltage of semiconductor power devices under the same terminal protection structure design not being able to be further improved. Summary of the Invention

[0004] The purpose of this invention is to provide at least one method for fabricating a semiconductor power device and a semiconductor power device, which can at least achieve both the conduction characteristics and breakdown resistance of the semiconductor power device.

[0005] To address the aforementioned technical problems, the present invention provides a method for fabricating a semiconductor power device, comprising: providing a substrate layer, the substrate layer including an active region and a terminal region surrounding the active region; forming a patterned mask on the surface of the substrate layer; the patterned mask covering at least a portion of the surface of the terminal region; etching a region of the surface of the substrate layer not covered by the patterned mask to make the thickness of at least a portion of the terminal region greater than the thickness of the active region, and to give the active region a target thickness; and removing the patterned mask, wherein the surface of the active region of the substrate layer is lower than the surface of the terminal region and forms a stepped structure with the surface of the terminal region.

[0006] The method for fabricating a semiconductor power device provided by this invention involves forming a patterned mask on the surface of a substrate layer, the patterned mask covering at least a portion of the termination region; and etching the areas of the substrate layer surface not covered by the patterned mask to ensure that the thickness of at least a portion of the termination region is greater than the thickness of the active region, and that the active region achieves a target thickness. In other words, by adding an etching process to the active region of the substrate layer, the thickness of the termination region is indirectly increased while ensuring the conduction characteristics of the semiconductor power device are matched (i.e., the thickness of the active region is the target thickness), thereby balancing the conduction characteristics and breakdown resistance of the semiconductor power device. Furthermore, the above-described method for fabricating a semiconductor power device only requires adding one etching step to the areas of the substrate layer surface not covered by the patterned mask, resulting in low process costs.

[0007] Additionally, the substrate layer includes a front side and a back side disposed opposite to each other, and forming a patterned mask on the surface of the substrate layer includes forming a patterned mask on the front side and / or the back side of the substrate layer.

[0008] Additionally, it includes: performing an ion implantation process on the surface of the substrate layer to form an ion implantation region on the surface of the substrate layer; and forming a metal layer on the ion implantation region.

[0009] In addition, forming a patterned mask on the surface of the substrate layer includes: forming a patterned mask on the front side of the substrate layer; the method for fabricating a semiconductor power device further includes: after removing the patterned mask, forming an active ion implantation region on the front side of the active region; forming a front metal layer on the active ion implantation region; forming a terminal ion implantation region on the front side of the terminal region; forming a back ion implantation region on the back side; and forming a back metal layer on the back ion implantation region.

[0010] Additionally, forming a patterned mask on the surface of the substrate layer includes: forming a patterned mask on the back side of the substrate layer; the method for fabricating a semiconductor power device further includes: before forming a patterned mask on the back side, forming an active ion implantation region on the front side of the active region, forming a terminal ion implantation region on the front side of the terminal region; and forming a front metal layer on the active ion implantation region; after removing the patterned mask, forming a back ion implantation region on the back side; and forming a back metal layer on the back ion implantation region.

[0011] In addition, forming a patterned mask on the surface of the substrate layer includes forming a patterned photoresist mask on the surface of the substrate layer.

[0012] In addition, forming a patterned mask on the surface of the substrate layer further includes: forming a hard mask layer on the surface of the substrate layer before forming a patterned photoresist mask on the surface of the substrate layer; and etching the hard mask layer using the patterned photoresist mask as a mask to form a patterned hard mask layer.

[0013] The present invention also provides a semiconductor power device, comprising: a substrate layer, the substrate layer including an active region and a terminal region surrounding the active region; wherein at least a portion of the thickness of the terminal region is greater than the thickness of the active region, and the active region has a target thickness; the surface of the substrate layer is stepped.

[0014] Additionally, the substrate layer includes a front side and a back side disposed opposite to each other, wherein the front side of at least a portion of the terminal region is higher than the front side of the active region, and / or, the back side of at least a portion of the terminal region is lower than the back side of the active region.

[0015] Additionally, it includes: an active ion implantation region located on the front side of the active region; a terminal ion implantation region located on the front side of the terminal region; and a back ion implantation region located on the back side; a front metal layer located on the active ion implantation region; and a back metal layer located on the back ion implantation region. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 A schematic flowchart illustrating the fabrication method of a semiconductor power device provided in an embodiment of the present invention; Figure 2 A schematic diagram of a semiconductor power device provided in an embodiment of the present invention; Figure 3 This is another schematic diagram of a semiconductor power device provided in an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand the present invention. However, the technical solutions claimed in the present invention can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0019] refer to Figure 1This invention provides a method for fabricating a semiconductor power device, comprising: S1: Provides a base layer, which includes an active region and a terminal region surrounding the active region; S2: A patterned mask is formed on the surface of the base layer; the patterned mask covers at least a portion of the surface of the terminal region; S3: Etch the area of ​​the base layer surface that is not covered by the patterned mask so that the thickness of at least part of the terminal region is greater than the thickness of the active region, and the active region obtains the target thickness. S4: Remove the patterned mask. The surface of the active region of the base layer is lower than the surface of the terminal region and has a stepped structure with respect to the surface of the terminal region.

[0020] In this embodiment, a patterned mask is formed on the surface of the substrate layer, covering at least a portion of the termination region. The areas of the substrate layer not covered by the patterned mask are etched to ensure that the thickness of at least a portion of the termination region is greater than the thickness of the active region, and that the active region achieves the target thickness. In other words, by adding an etching process to the active region of the substrate layer, the thickness of the termination region is indirectly increased while ensuring the conduction characteristics of the semiconductor power device are matched (i.e., the thickness of the active region is the target thickness), thereby balancing the conduction characteristics and breakdown resistance of the semiconductor power device. Furthermore, the above-described semiconductor power device fabrication method only requires adding an etching step to the areas of the substrate layer not covered by the patterned mask, resulting in low process costs.

[0021] Specifically, in conjunction with reference Figure 2 and Figure 3 The target thickness H is the thickness required to ensure the semiconductor power device meets its conduction characteristics. The active region A is the core area in the semiconductor power device that directly participates in carrier transport, conductance modulation, and current control. Meeting the target thickness H is a key design parameter for achieving low resistance, low loss, high efficiency, and reliability when the semiconductor power device is on. Its thickness setting requires comprehensive consideration of material properties, device structure, operating voltage and current, heat dissipation requirements, and process feasibility. Therefore, the target thickness of the active region A is set based on the requirements of those skilled in the art regarding the conduction characteristics of the semiconductor power device.

[0022] It is understood that in this embodiment, the overall thickness of the substrate layer is greater than the target thickness of the active region.

[0023] In this embodiment, the substrate 1 includes a silicon wafer.

[0024] In one embodiment, the semiconductor power device includes, but is not limited to, an insulated gate bipolar transistor (IGBT), a bipolar transistor (BJT), or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0025] In one embodiment, the patterned mask (not shown) covering at least a portion of the terminal region B can be either a patterned mask covering the surface of a portion of the terminal region B or a patterned mask covering the entire surface of the terminal region B. In this embodiment, it is preferred that the patterned mask covers the entire surface of the terminal region B, and the area of ​​the substrate layer 1 not covered by the patterned mask is etched, i.e., the entire surface of the active region A is etched, so that the surface of the active region A is lower than the surface of the terminal region B, and the thickness of the entire terminal region B is greater than the thickness of the active region A, further improving the breakdown resistance of the semiconductor power device; and optimizing the conduction characteristics of the semiconductor power device.

[0026] In other embodiments, the patterned mask covers the surface of the terminal region and extends to cover the surface of a portion of the active region. The area of ​​the substrate surface not covered by the patterned mask is etched, i.e., the surface of a portion of the active region is etched.

[0027] In one embodiment, forming a patterned mask on the surface of the substrate layer 1 includes forming a patterned photoresist mask on the surface of the substrate layer 1. Specifically, the step of forming a patterned photoresist mask on the surface of the substrate layer 1 includes forming a photoresist layer (not shown) on the surface of the substrate layer 1, and sequentially exposing and developing the photoresist layer to form a patterned photoresist mask. The patterned photoresist mask covers at least a portion of the surface of the terminal region B, and the surface of the active region A is etched using the patterned photoresist mask as a mask.

[0028] In one embodiment, forming a patterned mask on the surface of the substrate layer 1 further includes: forming a hard mask layer (not shown) on the surface of the substrate layer 1 before forming a patterned photoresist mask; and etching the hard mask layer using the patterned photoresist mask as a mask to form a patterned hard mask layer. Both the patterned photoresist mask and the patterned hard mask layer cover at least a portion of the surface of the terminal region B, and the surface of the active region A is etched using the patterned hard mask layer as a mask. The hard mask layer acts as an intermediate medium, transferring the pattern from the photoresist layer to the hard mask layer and then precisely transferring it to the substrate layer, thereby improving the etching accuracy of the surface of the active region A.

[0029] In one embodiment, the etching process for the area of ​​the substrate 1 not covered by the patterned mask includes a wet etching process or a dry etching process. The dry etching process uses gases such as carbon tetrafluoride (CF4) or sulfur hexafluoride (SF6).

[0030] In one embodiment, the method for fabricating a semiconductor power device further includes: performing an ion implantation process on the surface of a substrate layer 1 to form an ion implantation region on the surface of the substrate layer 1; and forming a metal layer on the ion implantation region.

[0031] In one embodiment, the step of providing substrate 1 includes: thinning an initial substrate layer to form a substrate layer. This facilitates enhanced integration of subsequent structures formed on substrate 1. It is known that the thickness of the initial substrate layer is much greater than the thickness of substrate 1; therefore, thinning the initial substrate layer can achieve the advantages of both lightweight design and high integration.

[0032] In this embodiment, the base layer 1 includes a front side and a back side disposed opposite to each other, and forming a patterned mask on the surface of the base layer 1 includes forming a patterned mask on the front side and / or the back side of the base layer 1.

[0033] In one embodiment, forming a patterned mask on the surface of the substrate layer 1 includes: forming a patterned mask on the front side of the substrate layer 1; (Refer to...) Figure 2 The method for fabricating a semiconductor power device further includes: after removing the patterned mask, forming an active ion implantation region 2 on the front side of the active region A; forming a front metal layer 3 on the active ion implantation region 2; forming a terminal ion implantation region 4 on the front side of the terminal region B; forming a back ion implantation region (not shown) on the back side; and forming a back metal layer (not shown) on the back ion implantation region.

[0034] Specifically, forming a patterned mask on the surface of the substrate layer 1 includes: forming a patterned mask on the front side of the substrate layer 1, i.e., the patterned mask covers at least a portion of the front side of the terminal region B; and etching the areas of the front side of the substrate layer 1 not covered by the patterned mask, i.e., etching the front side of the active region A. The patterned mask covering at least a portion of the front side of the terminal region B can be either covering only a portion of the front side of the terminal region B or covering the entire front side of the terminal region B. Preferably, the patterned mask covers the entire front side of the terminal region B, and etching the areas of the surface of the substrate layer 1 not covered by the patterned mask, i.e., etching the entire front side of the active region A.

[0035] refer to Figure 2 After etching, the front side of the active region A is lower than the front side of the terminal region B, and the front side of the substrate 1 forms a stepped structure.

[0036] Forming the terminal ion implantation region 4 on the front side of the terminal region B can be done before forming the patterned mask on the front side of the substrate layer 1; or, after removing the patterned mask, the terminal ion implantation region 4 can be formed on the front side of the terminal region B. After removing the patterned mask, forming the active ion implantation region 2 on the front side of the active region A and forming the terminal ion implantation region 4 on the front side of the terminal region B can be done in the same process or in different processes. The order in which the active ion implantation region 2 is formed on the front side of the active region A and the terminal ion implantation region 4 is formed on the front side of the terminal region B is not restricted. Forming the back ion implantation region on the back side can be done before forming the patterned mask on the front side of the substrate layer 1; or, after removing the patterned mask, the back ion implantation region can be formed on the back side.

[0037] In one embodiment, before forming the back ion implantation region on the back side, the method further includes thinning the back side. In other embodiments, thinning may not be performed.

[0038] In one embodiment, the terminal ion implantation region 4 includes a P-type terminal ion implantation region; the terminal ion implantation region 4 is the terminal structure of the semiconductor power device, such as a field limiting ring, junction termination extension, floating field ring, etc., which serves to suppress electric field concentration and improve the voltage withstand capability of the semiconductor power device.

[0039] The ion type and concentration in the active ion implantation region 2 are selected according to the type of semiconductor power device, and are not limited in this embodiment.

[0040] In one embodiment, the front metal layer 3 includes a front electrode layer and a front pad layer; the back metal layer includes a back electrode layer. The front and back metal layers are common knowledge in the art and can be configured by those skilled in the art according to actual needs.

[0041] In another embodiment, forming a patterned mask on the surface of the substrate layer 1 includes: forming a patterned mask on the back side of the substrate layer 1; the method for fabricating a semiconductor power device further includes: forming an active ion implantation region 2 on the front side of the active region A and a terminal ion implantation region 4 on the front side of the terminal region B before forming the patterned mask on the back side; forming a front metal layer 3 on the active ion implantation region 2; forming a back ion implantation region on the back side after removing the patterned mask; and forming a back metal layer on the back ion implantation region.

[0042] Specifically, forming a patterned mask on the surface of the substrate layer 1 includes: forming a patterned mask on the back side of the substrate layer 1, i.e., the patterned mask covers at least a portion of the back side of the terminal region B; and etching the areas on the back side of the substrate layer 1 not covered by the patterned mask, i.e., etching at least the back side of the active region A. The patterned mask covering at least a portion of the back side of the terminal region B can be either covering only a portion of the back side of the terminal region B or covering the entire back side of the terminal region B. Preferably, the patterned mask covers the entire back side of the terminal region B, and etching the areas on the surface of the substrate layer 1 not covered by the patterned mask, i.e., etching the entire back side of the active region A.

[0043] refer to Figure 3 After etching, the back surface of the active region A is lower than the back surface of the terminal region B, and a stepped structure is formed on the back surface of the substrate 1.

[0044] In one embodiment, forming the active ion implantation region 2 on the front side of the active region A and forming the terminal ion implantation region 4 on the front side of the terminal region B can be performed in the same process or in different processes. The order in which the active ion implantation region 2 is formed on the front side of the active region A and the terminal ion implantation region 4 is formed on the front side of the terminal region B is not restricted.

[0045] In one embodiment, before forming the patterned mask on the back side, the method further includes thinning the back side. The thinning process can be performed using a masking process. In other embodiments, the back side may not be thinned; instead, the patterned mask can be formed directly on the back side of the substrate layer.

[0046] The formation of the patterned mask, the type of terminal ion implantation region 4, the ion type and concentration of the active ion implantation region 2, and the descriptions of the front metal layer 3 and the back metal layer are as described above and will not be repeated here.

[0047] In other embodiments, forming a patterned mask on the surface of the substrate layer includes forming patterned masks on the front and back sides of the substrate layer, respectively. After the etching process, the front side of the active region is lower than the front side of the terminal region, and the back side of the active region is lower than the back side of the terminal region, with both the front and back sides of the substrate layer forming a stepped structure.

[0048] After removing the patterned mask, an active ion implantation region is formed on the front side of the active region; a front metal layer is formed on the active ion implantation region; a terminal ion implantation region is formed on the front side of the terminal region; a back ion implantation region is formed on the back side; and a back metal layer is formed on the back ion implantation region.

[0049] The content that is the same as that in other embodiments and the foregoing embodiments will not be repeated here.

[0050] Reference Figure 2 and Figure 3 This embodiment also provides a semiconductor power device, including: a substrate layer 1, the substrate layer 1 including an active region A and a terminal region B surrounding the active region A; wherein, at least a portion of the thickness of the terminal region B is greater than the thickness of the active region A, and the active region A has a target thickness; the surface of the substrate layer 1 is stepped.

[0051] The thickness of at least a portion of the terminal region B is greater than the thickness of the active region A. This can be either a partial thickness of the terminal region B being greater than the thickness of the active region A, or the thickness of all the terminal regions B being greater than the thickness of the active region A. In this embodiment, it is preferred that the thickness of all the terminal regions B is greater than the thickness of the active region A. This further improves the breakdown resistance of the semiconductor power device and further balances the requirements of both the conduction characteristics and breakdown resistance of the semiconductor power device.

[0052] The description of the target thickness of the active region A is given in the description of the foregoing embodiments.

[0053] In one embodiment, the base layer 1 includes a front side and a back side disposed opposite to each other, wherein at least a portion of the front side of the terminal region B is higher than the front side of the active region A, and / or, at least a portion of the back side of the terminal region B is lower than the back side of the active region A.

[0054] At least a portion of the front side of the terminal region B is higher than the front side of the active region A, the front side of the base layer 1 is stepped, and the back side of the base layer 1 is planar; at least a portion of the back side of the terminal region B is lower than the back side of the active region A, the back side of the base layer 1 is stepped, and the front side of the base layer 1 is planar; at least a portion of the front side of the terminal region B is higher than the front side of the active region A and at least a portion of the back side of the terminal region B is lower than the back side of the active region A, the front side of the base layer 1 is stepped, and the back side of the base layer 1 is stepped.

[0055] In one embodiment, the semiconductor power device further includes: an active ion implantation region 2 located on the front side of the active region A; a terminal ion implantation region 4 located on the front side of the terminal region B; and a back ion implantation region located on the back side; a front metal layer 3 located on the active ion implantation region 2; and a back metal layer located on the back ion implantation region.

[0056] For the descriptions of the type of terminal ion implantation region 4, the ion type and concentration of active ion implantation region 2, the front metal layer 3, and the back metal layer, please refer to the previous descriptions and they will not be repeated here.

[0057] It should be understood that the terms "mechanism," "device," "component," etc., used in this application are merely one method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0058] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention. In practical applications, the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A method for fabricating a semiconductor power device, characterized in that, include: A base layer is provided, the base layer including an active region and a terminal region surrounding the active region; A patterned mask is formed on the surface of the base layer; The patterned mask covers at least a portion of the surface of the terminal area; The area of ​​the surface of the base layer not covered by the patterned mask is etched to make the thickness of at least a portion of the terminal region greater than the thickness of the active region, and to make the active region achieve the target thickness; Remove the patterned mask, and the surface of the active region of the base layer is lower than the surface of the terminal region and has a stepped structure with the surface of the terminal region.

2. The method for fabricating a semiconductor power device according to claim 1, characterized in that, The base layer includes a front side and a back side disposed opposite to each other, and forming a patterned mask on the surface of the base layer includes forming a patterned mask on the front side and / or the back side of the base layer.

3. The method for fabricating a semiconductor power device according to claim 1, characterized in that, Also includes: An ion implantation process is performed on the surface of the substrate layer to form an ion implantation region on the surface of the substrate layer. And a metal layer is formed on the ion implantation region.

4. The method for fabricating a semiconductor power device according to claim 2, characterized in that, Forming a patterned mask on the surface of the substrate layer includes: forming a patterned mask on the front side of the substrate layer; The method for fabricating a semiconductor power device further includes: after removing the patterned mask, forming an active ion implantation region on the front side of the active region; and forming a front metal layer on the active ion implantation region; A terminal ion implantation region is formed on the front side of the terminal region; a back ion implantation region is formed on the back side; and a back metal layer is formed on the back ion implantation region.

5. The method for fabricating a semiconductor power device according to claim 2, characterized in that, Forming a patterned mask on the surface of the substrate layer includes: forming a patterned mask on the back side of the substrate layer; The method for fabricating a semiconductor power device further includes: forming an active ion implantation region on the front side of the active region and a terminal ion implantation region on the front side of the terminal region before forming a patterned mask on the back side; and forming a front metal layer on the active ion implantation region. After removing the patterned mask, a back ion implantation region is formed on the back side; and a back metal layer is formed on the back ion implantation region.

6. The method for fabricating a semiconductor power device according to claim 1, characterized in that, Forming a patterned mask on the surface of the substrate layer includes: forming a patterned photoresist mask on the surface of the substrate layer.

7. The method for fabricating a semiconductor power device according to claim 6, characterized in that, The process of forming a patterned mask on the surface of the substrate layer further includes: forming a hard mask layer on the surface of the substrate layer before forming a patterned photoresist mask on the surface of the substrate layer; and etching the hard mask layer using the patterned photoresist mask as a mask to form a patterned hard mask layer.

8. A semiconductor power device, characterized in that, include: A substrate layer includes an active region and a terminal region surrounding the active region; wherein at least a portion of the terminal region has a thickness greater than the thickness of the active region, and the active region has a target thickness; the surface of the substrate layer is stepped.

9. The semiconductor power device according to claim 8, characterized in that, The substrate layer includes a front side and a back side disposed opposite to each other, wherein the front side of at least a portion of the terminal region is higher than the front side of the active region, and / or, the back side of at least a portion of the terminal region is lower than the back side of the active region.

10. The semiconductor power device according to claim 9, characterized in that, It also includes: an active ion implantation region located on the front of the active region; a terminal ion implantation region located on the front of the terminal region; and a back ion implantation region located on the back side; A front metal layer is located on the active ion implantation region; a back metal layer is located on the back ion implantation region.

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