High voltage charge diode structure and method of manufacturing the same

Abstract

This invention provides a high-voltage charging diode structure and its manufacturing method. The structure includes a semiconductor substrate of a second conductivity type, an epitaxial layer of a first conductivity type, and a field dielectric structure. The field dielectric structure includes a first field dielectric layer and a second field dielectric layer, the second field dielectric layer being thicker than the first field dielectric layer and disposed near the substrate electrode. By setting an asymmetric thickness field dielectric layer, this invention effectively suppresses leakage current flowing to the substrate in forward charging mode, thereby improving charging efficiency; in reverse breakdown mode, the thickened dielectric layer compresses the underlying doped region, promoting the depletion of that region, thus significantly improving the reverse breakdown voltage of the device. This solution can achieve simultaneous growth in charging current and breakdown voltage performance without increasing process complexity, and is suitable for kilovolt-level high-voltage applications.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a high-voltage charging diode structure and its manufacturing method. Background Technology

[0002] In power electronics applications, high-voltage integrated circuits typically require internal high-voltage diodes to charge capacitors and block high voltage.

[0003] Traditional high-voltage diode structures typically employ a lateral structure based on a silicon substrate, utilizing a lightly doped epitaxial layer as the drift region, and optimizing the surface electric field distribution through a field oxide (LOCOS) layer and a metal field plate. During forward charging, current flows from the source region to the drain region; during reverse breakdown, the depletion region extends into the drift region to maintain a high voltage.

[0004] However, existing high-voltage diode structures face challenges in simultaneously improving charging current and breakdown voltage. First, during forward charging, some current flows out through the substrate (bulk) terminal, forming leakage current and reducing the effective current flowing to the charging terminal, thus decreasing charging efficiency. Second, in high-voltage applications (e.g., above 1000V), the distribution of impurities in the drift region and the oxide layer structure significantly affect the degree of depletion. If the semiconductor region under the oxide layer is not sufficiently depleted, premature breakdown is highly likely, limiting the device's breakdown voltage reliability.

[0005] Therefore, how to design a high-voltage diode structure that can suppress substrate leakage current while improving breakdown voltage and charging current is a problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a high-voltage charging diode structure and its manufacturing method, so as to solve the problems of low charging efficiency due to large substrate leakage current when the existing diode structure is working in the forward direction, and the difficulty in further improving the breakdown voltage due to insufficient depletion of the drift region under reverse high voltage environment.

[0007] To solve the above technical problems, the present invention provides a high-voltage charging diode structure, comprising:

[0008] Second conductivity type semiconductor substrate;

[0009] A first conductivity type epitaxial layer is disposed on a second conductivity type semiconductor substrate;

[0010] A field dielectric structure is disposed in the first conductivity type epitaxial layer. The field dielectric structure includes a first field dielectric layer and a second field dielectric layer. The thickness of the second field dielectric layer is greater than the thickness of the first field dielectric layer, and the second field dielectric layer is disposed near the substrate electrode position of the high voltage charging diode structure.

[0011] Preferably, the second field dielectric layer is configured to suppress leakage current flowing to the substrate electrodes under positive operating conditions.

[0012] Preferably, the second conductivity type region beneath the second field dielectric layer is compressed by the second field dielectric layer to increase the depletion degree of the high-voltage charging diode structure in the reverse operating state.

[0013] Preferably, in the forward charging operating state, the substrate electrode terminal and the substrate gate terminal are connected to zero potential, and the source electrode lead-out terminal is connected to a forward voltage, so that the PN junction between the source electrode lead-out terminal and the voltage connection terminal is connected.

[0014] Preferably, the high-voltage charging diode structure charges the external capacitor through the voltage terminal.

[0015] Preferably, the high-voltage charging diode structure is configured to withstand a voltage of 1000V or more in reverse.

[0016] Preferably, the first conductivity type epitaxial layer is provided with a first conductivity type buried layer and a second conductivity type buried layer.

[0017] Preferably, a well region of a second conductivity type is provided in the epitaxial layer of the first conductivity type.

[0018] Preferably, a second conductivity type injection region is provided in the first conductivity type epitaxial layer.

[0019] Preferably, the first conductivity type epitaxial layer is provided with a first conductivity type heavily doped region and a second conductivity type heavily doped region.

[0020] Preferably, a polycrystalline silicon layer is disposed above the epitaxial layer of the first conductivity type.

[0021] The present invention also provides a method for manufacturing a high-voltage charging diode structure as described above, comprising:

[0022] Step 1: Form a buried layer structure on a semiconductor substrate of the second conductivity type;

[0023] Step 2: Form an epitaxial layer of the first conductivity type on a semiconductor substrate of the second conductivity type;

[0024] Step 3: Form a field dielectric structure in the first conductivity type epitaxial layer, wherein the in-plane region of a local module is thickened to form a second field dielectric layer, and the remaining part forms the first field dielectric layer;

[0025] Step 4: Form a doped region in the epitaxial layer of the first conductivity type;

[0026] Step 5: Form a polycrystalline silicon layer on the surface of the epitaxial layer of the first conductivity type;

[0027] Step 6: Form a heavily doped region in the epitaxial layer of the first conductivity type;

[0028] Step 7: Form a metal layer.

[0029] Preferably, in step one, the buried layer structure includes a first conductive type buried layer and a second conductive type buried layer spaced apart from each other.

[0030] Preferably, in step three, the second field dielectric layer is formed near the bottom electrode to reduce substrate leakage current.

[0031] Preferably, in step four, the doped region includes a well region of the second conductivity type and an implantation region of the second conductivity type.

[0032] Preferably, in step four, the region of the second conductivity type injection area corresponding to the area below the second field dielectric layer is compressed by the second field dielectric layer to improve the reverse withstand voltage depletion.

[0033] Preferably, in step six, the heavily doped region includes a first conductivity type heavily doped region and a second conductivity type heavily doped region.

[0034] Preferably, in step seven, each electrode and metal layer is configured to enable the high-voltage charging diode structure to be forward charged and to withstand a high voltage of over 1000V in reverse.

[0035] As described above, the high-voltage charging diode structure and its manufacturing method of the present invention have the following beneficial effects:

[0036] By incorporating a thickened second field dielectric layer near the substrate electrode, the increased dielectric thickness enhances the potential barrier perpendicular to the substrate. This effectively suppresses leakage current flowing to the substrate during forward charging, improving the effective current and charging efficiency of the charging path. Simultaneously, the thickened second field dielectric layer compresses the underlying second conductivity type region during manufacturing, allowing this region to be depleted more easily and fully under reverse high-voltage applications, thus optimizing the electric field distribution. Through this asymmetric field dielectric design, this invention can simultaneously improve the forward charging current and reverse breakdown voltage of the device without adding an additional photolithography mask, enhancing the reliability and stability of high-voltage integrated circuits. Attached Figure Description

[0037] Figure 1 The diagram shown is a flowchart illustrating a manufacturing method for a high-voltage charging diode structure according to the present invention.

[0038] Figure 2 The diagram shows a cross-sectional view of a high-voltage charging diode structure of the present invention after the formation of the buried layer structure.

[0039] Figure 3 The diagram shows a cross-sectional view of a high-voltage charging diode structure of the present invention after the formation of the epitaxial layer;

[0040] Figure 4 The diagram shows a cross-sectional view of a high-voltage charging diode structure of the present invention after the formation of a field dielectric structure.

[0041] Figure 5 The diagram shows a cross-sectional view of a high-voltage charging diode structure of the present invention after the formation of the well region and the injection region;

[0042] Figure 6 The diagram shows a cross-sectional view of a high-voltage charging diode structure of the present invention after the formation of a polycrystalline silicon layer.

[0043] Figure 7 The diagram shows a cross-sectional view of a high-voltage charging diode structure of the present invention after the formation of a heavily doped region.

[0044] Figure 8 The diagram shown is a cross-sectional view of a high-voltage charging diode structure of the present invention after the metal layer and terminal electrodes are formed. Detailed Implementation

[0045] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0046] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the manufacturing process for this high-voltage charging diode structure.

[0047] This high-voltage charging diode structure includes a second conductivity type semiconductor substrate 101.

[0048] In some embodiments, the second conductivity type semiconductor substrate 101 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer of the SOI substrate. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0049] A first conductivity type epitaxial layer 103 is disposed on a second conductivity type semiconductor substrate 101.

[0050] In some embodiments, the first conductivity type epitaxial layer 103 can be fabricated using an epitaxial growth apparatus. This epitaxial growth process may include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), or metal-organic chemical vapor deposition (MOCVD). A precursor gas containing a silicon source (such as silane, silane, dichlorosilane, or trichlorosilane) is decomposed in a high-temperature reactor, and impurity gases such as phosphine (PH3) or arsine (AsH3) are introduced. The epitaxial layer 103 serves as the main voltage support region in reverse operating mode, and its thickness and impurity distribution gradient determine the uniformity of the longitudinal electric field. By introducing gradient doping technology, the epitaxial layer 103 can have specific concentration transitions at the interface near the substrate 101, thereby reducing the forward conduction resistance while maintaining high breakdown voltage.

[0051] The field dielectric structure is disposed in the first conductivity type epitaxial layer 103. The field dielectric structure includes a first field dielectric layer 104 and a second field dielectric layer 104B (thickness greater than 700 Å). The thickness of the second field dielectric layer 104B is greater than the thickness of the first field dielectric layer 104, and the second field dielectric layer 104B is disposed near the substrate electrode Bulk position of the high voltage charging diode structure.

[0052] In some embodiments, the first field dielectric layer 104 and the second field dielectric layer 104B may be composed of silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. For example, the thickness of the first field dielectric layer 104 may be 700 Å, while the thickness of the second field dielectric layer 104B may be increased from 700 Å to 1000 Å. This locally thickened asymmetric morphology not only alters the physical profile of the semiconductor surface but also achieves physical modulation of the interface-side potential extension through the difference in the dielectric constant of the materials.

[0053] The second dielectric layer 104B is configured to suppress leakage current flowing to the substrate electrode Bulk under positive operating conditions.

[0054] In some embodiments, during forward conduction of the device, the thickened second field dielectric layer 104B increases the impedance along the vertical path. This thickened structure physically acts as an electric field blocking wall, effectively altering the diffusion distribution of minority carriers.

[0055] The second conductivity type region beneath the second field dielectric layer 104B is compressed by the second field dielectric layer 104B to increase the depletion of the high-voltage charging diode structure in the reverse operating state.

[0056] In some embodiments, the longitudinal thickness of the underlying second conductivity type well region 107 is physically reduced as the second dielectric layer 104B consumes a portion of the underlying silicon material during thermal oxidation growth. This volumetric compression reduces the total amount of acceptor impurities per unit area, causing a shift in the charge balance point of this region under an applied reverse bias. Compared to the unthickened region, the doped layer here can be completely depleted by the depletion layer at a lower critical potential, thereby eliminating potential electric field spikes. This structural evolution significantly smooths the equipotential line distribution at the substrate electrode edges, thereby increasing the breakdown voltage from 1494V to 1534V, an improvement of approximately 3%, providing a higher safety voltage margin for the high-voltage pump circuit.

[0057] In the forward charging state, the substrate electrode Bulk and the substrate gate BG are connected to zero potential, and the source electrode lead BS is connected to a forward voltage, so that the PN junction between the source electrode lead BS and the voltage connection VB is turned on.

[0058] In some embodiments, the substrate electrode Bulk can be led out through a heavily p-doped region and used as a potential stabilization reference during charging. This multi-terminal co-biasing mode utilizes the forced ground potential of the substrate to stabilize the potential energy at the bottom of the epitaxial layer 103, preventing local latch-up effects or potential drift caused by large current flows.

[0059] The high-voltage charging diode structure charges the external capacitor through the voltage terminal VB.

[0060] In some embodiments, the external capacitor can be an integrated metal-insulator-metal (MIM) capacitor or an off-chip discrete capacitor. The charging path flows from the conducting anode region through the epitaxial drift region to the cathode region. Due to the current-conducting effect of the thickened field dielectric layer, the charging current is increased from 1.78 × 10^-2 to 1.84 × 10^-2, an increase of approximately 3%, which improves the dynamic response characteristics of the diode under high current pulses.

[0061] The high-voltage charging diode is configured to withstand voltages of over 1000V in reverse.

[0062] In some embodiments, the combined optimization of RESURF (Reduced Surface Electric Field) technology and a thickened field dielectric layer enables the device to operate for extended periods under ultra-high voltage conditions without avalanche breakdown. This withstand voltage capability allows the device to be widely used in industrial frequency converters, brushless DC motor drives, and high-performance display backlight control systems.

[0063] The first conductivity type epitaxial layer 103 is provided with a first conductivity type buried layer 102 and a second conductivity type buried layer 105.

[0064] In some embodiments, these buried layers may be formed using an ion implantation combined with a high-temperature propulsion process. The implanted elements may include phosphorus, arsenic, and antimony as a first conductivity type, or boron, aluminum, and gallium as a second conductivity type.

[0065] A second conductivity type well region 107 is provided in the first conductivity type epitaxial layer 103.

[0066] In some embodiments, the second conductivity type well region 107 serves as the body region for accommodating the source region.

[0067] A second conductivity type injection region 106 is provided in the first conductivity type epitaxial layer 103.

[0068] In some embodiments, the second conductivity type injection region 106 is configured as an auxiliary depletion region at the top of the drift region. Specifically, a portion of the second conductivity type injection region 106 is disposed below the first field dielectric layer 104. Furthermore, another portion of the second conductivity type injection region 106 is disposed above the second conductivity type buried layer 105. This vertical distribution characteristic allows the second conductivity type injection region 106 to establish an electrical connection with the deep buried layer structure in the longitudinal direction. By accurately compensating for the charge amount of the epitaxial layer 103, the internal electric field of the device tends to be balanced under reverse bias, thereby avoiding the local electric field from reaching the breakdown limit too quickly and significantly improving the dynamic reliability of the device under a 1000V high-voltage environment.

[0069] Furthermore, in some embodiments, the second conductivity type well region 107 extends vertically above the second conductivity type implantation region 106 near the Bulk end, and makes electrical contact with or partially overlaps with the second conductivity type implantation region 106. The second conductivity type heavily doped region 110 located in this region serves as the lead-out terminal of the substrate electrode Bulk, used to transfer the external zero potential to the inner layer of the device via the second conductivity type well region 107 and the second conductivity type implantation region 106, thereby ensuring the stability of the substrate potential in the forward charging mode. Through this vertically stacked doping distribution design, the second conductivity type well region 107 not only defines the source region boundary but also constructs a low-impedance ohmic path from the metal junction to the deep implantation region. Combined with the thickened second field dielectric layer 104B, the initial morphology of the depletion region on the substrate side can be more precisely controlled.

[0070] The first conductivity type epitaxial layer 103 is provided with a first conductivity type heavily doped region 109 and a second conductivity type heavily doped region 110.

[0071] A polycrystalline silicon layer 108 is disposed above the first conductivity type epitaxial layer 103.

[0072] In some embodiments, the polysilicon layer 108 can serve as a control gate or field plate. The material can be undoped or in-situ doped polysilicon, or even polycrystalline material formed by laser annealing and recrystallization of amorphous silicon. The thickness and particle size of the polysilicon layer 108 are optimized by controlling the deposition temperature and gas flow ratio to reduce the gate depletion effect. Furthermore, the conductivity of the electrode can be improved by depositing a refractory metal on the surface of the polysilicon and heat-treating it to form silicides.

[0073] In some embodiments, the first conductivity type mentioned herein is N-type, and the doping impurities can be group V elements such as phosphorus (P), arsenic (As), or antimony (Sb); correspondingly, the second conductivity type mentioned herein is P-type, and the doping impurities can be group III elements such as boron (B), boron fluoride (BF2), indium (In), or gallium (Ga). By introducing N-type impurities into the first conductivity type epitaxial layer 103, and combining this with the introduction of P-type impurities into the second conductivity type semiconductor substrate 101, the second conductivity type well region 107, and the second conductivity type implantation region 106, a PN junction electric field distribution capable of supporting high voltages is constructed. By using impurity atoms with different ionic radii for compensation, not only can the stress state of the silicon lattice be adjusted, but the movement rate of the depletion layer boundary can also be precisely fine-tuned to meet the high voltage carrying requirements of devices above 1000V, thereby maintaining extremely low parasitic charge storage effects in complex level shifting circuits.

[0074] The manufacturing methods for high-voltage charging diode structures include:

[0075] Step 1: Form a buried layer structure on the second conductivity type semiconductor substrate 101.

[0076] like Figure 2 As shown, in some embodiments, in step one, the buried layer structure includes a first conductive type buried layer 102 and a second conductive type buried layer 105 spaced apart from each other. The specific formation method may include firstly depositing a silicon dioxide hard mask on the surface of the substrate 101 using plasma-enhanced chemical vapor deposition (PECVD). Subsequently, the first mask layer is exposed using a photolithography machine, and windows are etched using a fluorine-based gas dry etching process. An ion implanter then implants dopant atoms. To prevent ion channeling effects, the implantation beam can be tilted at a specific angle to the substrate normal. After implantation, a high-temperature diffusion furnace is used to drive the implantation, stabilizing the impurities and achieving a preset diffusion junction depth.

[0077] Step 2: Form an epitaxial layer 103 of the first conductivity type on the semiconductor substrate 101 of the second conductivity type.

[0078] like Figure 3 As shown, in some embodiments, the formation method includes performing epitaxy in an epitaxial furnace tube. The initial growth stage may employ in-situ cleaning techniques to remove the native oxide layer, followed by the simultaneous introduction of dichlorosilane and a gas containing impurities. The thickness of the growth is precisely controlled according to the final withstand voltage level (e.g., 1000V).

[0079] Step 3: Form a field dielectric structure in the first conductivity type epitaxial layer 103, wherein the in-plane region of a local module is thickened to form a second field dielectric layer 104B, and the remaining part forms the first field dielectric layer 104.

[0080] like Figure 4 As shown, in some embodiments, in step three, the second field dielectric layer 104B is formed near the bottom electrode Bulk to reduce substrate leakage current. Specific formation processes may include first depositing a silicon nitride pad layer in the active region and defining the field dielectric region using photolithography. Alternatively, shallow trench isolation (STI) combined with high-density plasma (HDP) filling may be used. In this embodiment, a local oxidation process (LOCOS) is employed, utilizing a two-step oxidation method. The first step involves conventional oxidation to obtain a first field dielectric layer 104 with a thickness of 700 Å; subsequently, a second mask is used to protect other areas, and supplementary oxidation is performed on the left Bulk end region to grow the thickness to 1000 Å, forming the second field dielectric layer 104B.

[0081] Step 4: Form a doped region in the first conductivity type epitaxial layer 103.

[0082] like Figure 5As shown, in some embodiments, in step four, the doped region includes a second conductivity type well region 107 and a second conductivity type implantation region 106.

[0083] In some embodiments, in step four, the region of the second conductivity type well region 107 corresponding to the area below the second field dielectric layer 104B is compressed by the second field dielectric layer 104B to improve the reverse breakdown voltage depletion. Because the second field dielectric layer 104B is relatively thick, the kinetic energy of the implanted impurities before entering the silicon surface is significantly consumed, or the silicon is vertically consumed by the oxidation growth process, resulting in a thinner or shallower morphology for the well region 107 ultimately remaining below the oxide layer. This asymmetric doping profile formed based on the difference in physical dielectric layer thickness produces an excellent lateral electric field shaping effect, which is key to the simultaneous improvement of BV and charging current performance.

[0084] Step 5: Form a polycrystalline silicon layer 108 on the surface of the first conductivity type epitaxial layer 103.

[0085] like Figure 6 As shown, in some embodiments, the formation process includes depositing a polycrystalline silicon thin film using low-pressure chemical vapor deposition (LPCVD). It can then exhibit N-type or P-type conductivity via ion implantation or in-situ diffusion. Excess material is subsequently removed using anisotropic inductively coupled plasma etching (ICP) to form a polycrystalline silicon gate or field plate structure with specific sidewall angles.

[0086] Step 6: Form a heavily doped region in the first conductivity type epitaxial layer 103.

[0087] like Figure 7 As shown, in some embodiments, in step six, the heavily doped region includes a first conductivity type heavily doped region 109 (defining the drain terminal D and the voltage terminal VB) and a second conductivity type heavily doped region 110 (defining the source terminal BS and the substrate lead-out region). To prevent short-channel effects or excessively high contact resistance, a lightly doped drain (LDD) structure can be formed before heavy doping. This is followed by a rapid thermal annealing process lasting several seconds to activate the doped atoms and repair point defects caused by implantation, thereby improving carrier mobility.

[0088] Step 7: Forming the metal layer 111.

[0089] like Figure 8As shown, in some embodiments, the process of forming the metal layer 111 in step seven may include first depositing a pre-metal dielectric layer (PMD) on the device surface. In addition to BPSG, the dielectric material may alternatively be phosphosilicate glass (PSG), undoped silicate glass (USG), fluorine-doped silicate glass (FSG), or silicon oxide formed by the decomposition of silane. Besides APCVD, plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDPCVD), or flowable chemical vapor deposition (FCVD) may be used to ensure conformal coverage of the polycrystalline silicon layer 108 and the sidewall regions of the field dielectric structure. When performing the CMP process, a polishing slurry with a high selectivity ratio can be used to achieve nanoscale flatness on the dielectric layer surface.

[0090] During the patterning of contact holes, dry etching is performed using plasma containing oxygen and fluorine-based gases. The barrier layer material formed inside the contact holes can alternatively be a titanium / titanium nitride stack, a tantalum / tantalum nitride stack, cobalt (Co), or ruthenium (Ru). In addition to ALD, metal-organic chemical vapor deposition (MOCVD) can also be used for its formation. When a large aspect ratio contact structure is required, ALD is preferred, and pulsed precursor injection ensures the uniformity of the barrier layer on the hole walls.

[0091] In addition to aluminum-copper alloys, conductive filler materials can be transition metals with lower resistivity. For example, tungsten plugs can be formed first, followed by CMP removal of redundant metal outside the vias. The main interconnect metal layer 111 may comprise aluminum, copper, titanium, or multilayer composite films of these materials, such as an electric field-tuned stack composed of titanium / aluminum / titanium / titanium nitride. Furthermore, if process requirements permit, the metal layer 111 may also be formed using a copper damask process, which includes electroplating filler processes and subsequent metal mechanical polishing.

[0092] The specific pattern formed by the metal layer 111 not only serves as wiring for the Bulk, BS, BG, D, and VB terminals, but also performs field plate adjustment functions. The metal layer 111 achieves good ohmic contact with the heavily doped region 110 of the second conductivity type through contact holes, thereby stably feeding back the zero potential of the Bulk terminal to the well region 107 and the implantation region 106 of the second conductivity type. In the upper region near the second field dielectric layer 104B, the metal layer 111 extends outward as a field plate, assisting in adjusting the longitudinal capacitance distribution at the confined well region 107 and the implantation region 106 under reverse voltage. This layout further coordinates with the physical variations in the field dielectric thickness, allowing the potential difference to smoothly cross the epitaxial layer 103. After completing the metal patterning, a passivation layer composed of silicon nitride, silicon oxide, or polyimide can be applied to shield against external environmental interference. This systematic back-end connection network, combined with the optimized asymmetric active region structure at the bottom layer, ensures high-voltage reliability while providing superior forward conduction efficiency for high-performance charging circuits.

[0093] In some embodiments, the first conductivity type mentioned herein is N-type, and the doping impurities can be group V elements such as phosphorus (P), arsenic (As), or antimony (Sb); correspondingly, the second conductivity type mentioned herein is P-type, and the doping impurities can be group III elements such as boron (B), boron fluoride (BF2), indium (In), or gallium (Ga). By introducing N-type impurities into the first conductivity type epitaxial layer 103, and combining this with the introduction of P-type impurities into the second conductivity type semiconductor substrate 101, the second conductivity type well region 107, and the second conductivity type implantation region 106, a PN junction electric field distribution capable of supporting high voltages is constructed. By using impurity atoms with different ionic radii for compensation, not only can the stress state of the silicon lattice be adjusted, but the movement rate of the depletion layer boundary can also be precisely fine-tuned to meet the high voltage carrying requirements of devices above 1000V, thereby maintaining extremely low parasitic charge storage effects in complex level shifting circuits.

[0094] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A high-voltage charging diode structure, characterized in that, include: Second conductivity type semiconductor substrate; A first conductivity type epitaxial layer is disposed on a second conductivity type semiconductor substrate; A field dielectric structure is disposed in the first conductivity type epitaxial layer. The field dielectric structure includes a first field dielectric layer and a second field dielectric layer. The thickness of the second field dielectric layer is greater than the thickness of the first field dielectric layer, and the second field dielectric layer is disposed near the substrate electrode position of the high voltage charging diode structure.

2. The high-voltage charging diode structure according to claim 1, characterized in that: The second field dielectric layer is configured to suppress leakage current flowing to the substrate electrodes under positive operating conditions.

3. The high-voltage charging diode structure according to claim 1, characterized in that: The second conductivity type region beneath the second field dielectric layer is compressed by the second field dielectric layer to increase the depletion degree of the high-voltage charging diode structure in the reverse operating state.

4. The high-voltage charging diode structure according to claim 1, characterized in that: In the forward charging state, the substrate electrode terminals and the substrate gate terminal are connected to zero potential, and the source electrode lead-out terminal is connected to a forward voltage, so that the PN junction between the source electrode lead-out terminal and the voltage connection terminal is connected.

5. The high-voltage charging diode structure according to claim 4, characterized in that: The high-voltage charging diode structure charges the external capacitor through the voltage terminal.

6. The high-voltage charging diode structure according to claim 1, characterized in that: The high-voltage charging diode structure is configured to withstand voltages of 1000V or more in reverse.

7. The high-voltage charging diode structure according to claim 1, characterized in that: The first conductivity type epitaxial layer is provided with a first conductivity type buried layer and a second conductivity type buried layer.

8. The high-voltage charging diode structure according to claim 1, characterized in that: A second conductivity type well region is provided in the first conductivity type epitaxial layer.

9. The high-voltage charging diode structure according to claim 1, characterized in that: The first conductivity type epitaxial layer is provided with a second conductivity type injection region.

10. The high-voltage charging diode structure according to claim 1, characterized in that: The first conductivity type epitaxial layer is provided with a first conductivity type heavily doped region and a second conductivity type heavily doped region.

11. The high-voltage charging diode structure according to claim 1, characterized in that: A polycrystalline silicon layer is disposed above the first conductivity type epitaxial layer.

12. A method for manufacturing a high-voltage charging diode structure as described in any one of claims 1 to 11, characterized in that, include: Step 1: Form a buried layer structure on a semiconductor substrate of the second conductivity type; Step 2: Form an epitaxial layer of the first conductivity type on the second conductivity type semiconductor substrate; Step 3: Form a field dielectric structure in the first conductivity type epitaxial layer, wherein the in-plane region of a local module is thickened to form a second field dielectric layer, and the remaining part forms a first field dielectric layer; Step 4: Form a doped region in the epitaxial layer of the first conductivity type; Step 5: Form a polycrystalline silicon layer on the surface of the first conductivity type epitaxial layer; Step 6: Form a heavily doped region in the epitaxial layer of the first conductivity type; Step 7: Form a metal layer.

13. The method for manufacturing the high-voltage charging diode structure according to claim 12, characterized in that: In step one, the buried layer structure includes a first conductive type buried layer and a second conductive type buried layer spaced apart from each other.

14. The method for manufacturing the high-voltage charging diode structure according to claim 12, characterized in that: In step three, the second field oxide layer is grown near the bottom electrode to reduce substrate leakage current.

15. The method for manufacturing the high-voltage charging diode structure according to claim 12, characterized in that: In step four, the doped region includes a second conductivity type well region and a second conductivity type implantation region formed by ion implantation.

16. The method for manufacturing the high-voltage charging diode structure according to claim 12, characterized in that: In step four, the region below the second field oxide layer corresponding to the second conductivity type injection region is compressed by the second field oxide layer to improve the reverse breakdown voltage depletion.

17. The method for manufacturing the high-voltage charging diode structure according to claim 12, characterized in that: In step six, the heavily doped region includes a first conductivity type heavily doped region and a second conductivity type heavily doped region.

18. The method for manufacturing the high-voltage charging diode structure according to claim 12, characterized in that: In step seven, each electrode and the metal layer are configured to enable the high-voltage charging diode structure to be forward charged and to withstand a high voltage of over 1000V in reverse.

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