Substrate wiring packaging method and substrate wiring packaging structure

Abstract

This invention provides a substrate wiring packaging method and structure, relating to the field of chip packaging technology. First, a barrier layer is formed on a carrier. Then, adjacent regions on the barrier layer are respectively covered with mutually bonded photoresist positive and negative layers. Next, the photoresist positive and negative layers are patterned and grooved to form wiring metal layers. Then, the photoresist positive and negative layers are removed, and a wiring dielectric layer is applied. The fabrication process of each wiring metal layer is repeated to form a wiring assembly layer. Compared to existing technologies, this invention can achieve zoned exposure, meeting the requirements for larger pattern area sizes. It can also expand the wiring area, reduce aperture density, and mitigate diffraction / scattering phenomena caused by optical properties during the exposure process, improving the resolution of the transferred pattern. Furthermore, it can ensure exposure accuracy.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically, to a substrate wiring packaging method and a substrate wiring packaging structure. Background Technology

[0002] Existing 2.5D packaging technology integrates multiple small chips together as a multi-chip packaging solution to connect the pad lines of adjacent chips within a single package, thereby improving its package integration. During fabrication, multiple flip chips are typically mounted on a substrate wiring layer structure, and an underfill colloid is used as a protective layer to protect the solder joints of the flip chips.

[0003] As multi-chip packaging technology increases its integration density, it requires larger pattern area sizes to meet the demands of this increased integration. However, due to mask size limitations, a single mask cannot meet the requirements for larger pattern area sizes. Furthermore, the increased wiring density of high-density wiring layers means that finer wiring needs to be designed within a limited pattern area, leading to increased mask aperture density and smaller size. During the exposure process, diffraction / scattering phenomena occur due to optical properties, which in turn affects the resolution of the transferred pattern.

[0004] Furthermore, due to the increased aperture density and reduced size of the mask, extremely high exposure energy is required, which can easily cause the imaging lens to expand due to the heating effect, leading to a decrease in alignment accuracy and affecting the resolution of the transferred pattern. Summary of the Invention

[0005] The purpose of this invention is to provide a substrate wiring packaging method and a substrate wiring packaging structure that can mitigate the diffraction / scattering phenomenon caused by optical properties during the exposure process, improve the resolution of the transferred pattern, and ensure exposure accuracy.

[0006] In a first aspect, the present invention provides a substrate wiring packaging method, comprising: A barrier layer is formed on the surface of the vehicle; A positive photoresist layer and a negative photoresist layer are respectively covered in adjacent regions on the barrier layer, wherein the positive photoresist layer and the negative photoresist layer are bonded together; The positive photoresist layer and the negative photoresist layer are respectively patterned and grooved to form a wiring metal layer; Remove any remaining photoresist positive layer and photoresist negative layer; A wiring dielectric layer is formed on the absorbing protective layer, and the wiring dielectric layer covers the wiring metal layer; Repeat the above steps to form a cabling composite layer, wherein the cabling composite layer includes multiple cabling dielectric layers and multiple cabling metal layers; A first protective dielectric layer is formed on the wiring combination layer; A first connection pad is formed in the first protective dielectric layer; Multiple stacked chips are mounted on the first connection pad, wherein the stacked chips are electrically connected to the wiring combination layer through the first connection pad; A molding compound layer is formed on the first protective dielectric layer to encapsulate the stacked chips; Remove the vehicle and the barrier layer in sequence.

[0007] In an optional embodiment, the step of covering adjacent different regions on the barrier layer with a positive photoresist layer and a negative photoresist layer respectively includes: The preset area of ​​the barrier layer is divided into adjacent positive adhesive area and negative adhesive area; A photolithographic positive resist layer is applied over the positive resist area; A photolithographic negative resist layer is applied within the negative resist area.

[0008] In an optional embodiment, the step of patterning and slotting the photoresist positive layer and the photoresist negative layer to form a wiring metal layer includes: The photoresist layer is exposed and developed using a first photomask to form a first pattern window on the photoresist layer, and a first notch is formed on the edge of the photoresist layer near the photoresist layer, wherein the photoresist layer blocks and covers the negative resist area. The photoresist layer is exposed and developed using a second photomask to form a second pattern window on the photoresist layer, and a second notch is formed at the edge of the photoresist layer near the photoresist layer, wherein the first notch and the second notch are spliced ​​together to form a positioning opening. A wiring metal layer is formed by electroplating in the first pattern window and the second pattern window, and a positioning metal layer is formed by electroplating in the positioning opening.

[0009] In an optional embodiment, the projections of the multiple stacked chips onto the barrier layer fall into the preset area, and both the positive adhesive area and the negative adhesive area are rectangular, with the multiple positive adhesive areas and the multiple negative adhesive areas distributed in an array.

[0010] In an optional embodiment, the projections of the stacked chips onto the barrier layer fall into the preset area, where both the positive adhesive area and the negative adhesive area are right-angled triangles, and the hypotenuse side edge of the positive adhesive area is joined to the hypotenuse side edge of the negative adhesive area.

[0011] In an optional embodiment, the projection of some of the stacked chips onto the barrier layer falls into the preset area, both the positive adhesive area and the negative adhesive area are rectangular, a plurality of the positive adhesive areas and a plurality of the negative adhesive areas are distributed in an array, and the bonding edges of the positive adhesive areas and the negative adhesive areas are misaligned with the plurality of stacked chips.

[0012] In an optional implementation, the positioning opening is circular, rhomboid, or rectangular.

[0013] In an optional embodiment, before the step of respectively covering adjacent different regions on the barrier layer with a positive photoresist layer and a negative photoresist layer, the method further includes: A base metal layer is formed on the barrier layer; An absorbing protective layer is formed on the blocking layer, wherein the absorbing protective layer covers the substrate metal layer and has openings to expose the substrate metal layer; The microwave absorbing protective layer is used to absorb exposure energy and protect the substrate metal layer.

[0014] In an optional implementation, after the step of sequentially removing the vehicle and the barrier layer, the method further includes: A second protective dielectric layer is formed on the surface of the wiring assembly layer away from the first protective dielectric layer; A second connection pad is formed in the second protective dielectric layer, wherein the second connection pad is electrically connected to the base metal layer; Solder balls are formed on the second connection pad.

[0015] In an optional implementation, the step of sequentially removing the vehicle and the barrier layer includes: The carrier is peeled off using a debonding process; The barrier layer is removed by micro-etching or grinding processes.

[0016] In a second aspect, the present invention provides a substrate wiring packaging structure, which is fabricated using the substrate wiring packaging method described in the foregoing embodiments, comprising: The cabling combination layer includes multiple cabling dielectric layers and multiple cabling metal layers, wherein the multiple cabling metal layers are respectively disposed in the multiple cabling dielectric layers; A first protective dielectric layer is disposed on one side of the wiring assembly layer, and a first connection pad is formed in the first protective dielectric layer; Multiple stacked chips are disposed on one side of the wiring combination layer and electrically connected to the wiring combination layer via the first connection pad; A molding compound is disposed on the first protective dielectric layer and covers the stacked chips.

[0017] In an optional embodiment, the substrate wiring package structure further includes an absorbing protective layer and a base metal layer. The absorbing protective layer is located on the other side of the wiring assembly layer and covers the base metal layer. The base metal layer is electrically connected to the wiring assembly layer.

[0018] In an optional embodiment, the substrate wiring package structure further includes a second protective dielectric layer, which is disposed on the side of the microwave absorbing protective layer away from the first protective dielectric layer. The second protective dielectric layer has a second connection pad, which is electrically connected to the substrate metal layer and has solder balls.

[0019] In an optional embodiment, the substrate wiring package structure further includes an insulating layer surrounding the periphery of the wiring assembly layer and at least covering the sidewalls of the wiring assembly layer.

[0020] In an optional embodiment, the insulating layer further covers one side of the wiring assembly layer, and a conductive post is provided in the insulating layer. One end of the conductive post is connected to the first connection pad, and the other end protrudes from the insulating layer. A plurality of the stacked chips are mounted on the conductive post.

[0021] The beneficial effects of the embodiments of the present invention include: The substrate wiring packaging method and structure provided in this invention first form a barrier layer on a carrier. Then, adjacent regions on the barrier layer are respectively covered with mutually bonded photoresist positive and negative layers. Next, the photoresist positive and negative layers are patterned and grooved to form wiring metal layers. Then, the photoresist positive and negative layers are removed, and a wiring dielectric layer is applied. The fabrication process of each wiring metal layer is repeated to form a wiring assembly layer. Then, a first protective dielectric layer is formed on the wiring assembly layer, and a first connection pad is formed in the first protective dielectric layer. Finally, the die-packing and molding compound are fabricated, and the carrier and barrier layer are removed.

[0022] Compared to existing technologies, this invention employs photolithographic positive and negative resist layers to cover different areas, and exposes the positive and negative resists separately. This allows for zoned exposure, meeting the requirements for larger pattern areas. Furthermore, it expands the wiring area, reduces aperture density, and mitigates diffraction / scattering phenomena caused by optical properties during the exposure process, improving the resolution of the transferred pattern. Additionally, it reduces exposure energy, preventing the imaging lens from expanding due to heat and ensuring exposure accuracy. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a process step diagram of the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the structure corresponding to step S1 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the structure corresponding to step S2 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S3 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 5 This is a schematic diagram of the structure corresponding to step S4 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 6 This is a schematic diagram of the structure corresponding to step S5 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 7 This is a schematic diagram of the structure corresponding to step S6 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 8 This is a schematic diagram of the structure corresponding to step S7 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 9 This is a schematic diagram of the structure corresponding to step S8 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 10 This is a schematic diagram of the structure corresponding to step S9 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 11 This is a schematic diagram of the structure corresponding to step S10 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 12 This is a schematic diagram of the structure corresponding to step S11 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 13 This is a schematic diagram of the structure corresponding to step S12 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 14 This is a schematic diagram of the structure corresponding to step S13 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 15 This is a schematic diagram of the structure corresponding to step S14 in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figures 16 to 21 This is a top view of different division methods of the positive adhesive area and the negative adhesive area in the substrate wiring and packaging method provided in the first embodiment of the present invention; Figure 22 This is a schematic diagram of the substrate wiring packaging structure provided in the first embodiment of the present invention; Figure 23 This is a schematic diagram of the substrate wiring packaging structure provided in the second embodiment of the present invention; Figure 24 This is a schematic diagram of the substrate wiring package structure provided in the third embodiment of the present invention.

[0025] Icons: 100 - Substrate wiring package structure; 110 - Wiring assembly layer; 111 - Wiring dielectric layer; 112 - Wiring metal layer; 113 - Positioning metal layer; 120 - First protective dielectric layer; 121 - First connection pad; 130 - Stacked chips; 131 - First chip; 132 - Second chip; 140 - Molding layer; 150 - Absorbing protective layer; 160 - Substrate metal layer; 170 - Second protective dielectric layer; 171 - Second connecting pad; 172-Solder ball; 180-Insulating layer; 181-Conductive pillar; 200-Carrier; 210-Barrier layer; 220-Photolithography positive resist layer; 221-Positive resist area; 222-First photomask; 223-First pattern window; 224-First notch; 230-Photolithography negative resist layer; 231-Negative resist area; 232-Second photomask; 233-Second pattern window; 234-Second notch; 240-Correction opening. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0029] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0030] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0031] In existing technologies, as multi-chip packaging technology increases integration, it requires larger pattern area sizes to meet the demands of this increased integration. However, due to mask size limitations, a single mask cannot meet the requirements for larger pattern areas. Furthermore, the increased wiring density of high-density wiring layers means that finer wiring needs to be designed within a limited pattern area, leading to increased mask aperture density and smaller size. During the exposure process, diffraction / scattering phenomena occur due to optical properties, affecting the resolution of the transferred pattern. Moreover, the increased mask aperture density and smaller size require extremely high exposure energy, which can easily cause the imaging lens to expand due to heat, leading to decreased alignment accuracy and affecting the resolution of the transferred pattern.

[0032] Furthermore, existing technologies have also introduced a partitioned exposure scheme, which uses a mask to pattern different areas and then forms a metal layer together. However, in order to ensure the continuity of the patterned areas, partitioned exposure inevitably affects the photoresist layers in adjacent areas. That is, during the exposure process, diffraction / scattering phenomena occur due to the influence of optical properties, which in turn affects the resolution of the transferred pattern.

[0033] To address the aforementioned problems, embodiments of the present invention provide a novel substrate wiring packaging method and substrate wiring packaging structure. It should be noted that, unless otherwise specified, the features in the embodiments of the present invention can be combined with each other.

[0034] First Embodiment The substrate wiring packaging method provided in this embodiment of the invention can mitigate the diffraction / scattering phenomenon caused by optical properties during the exposure process, improve the resolution of the transferred pattern, and ensure exposure accuracy.

[0035] See Figure 1 The substrate wiring packaging method provided in this embodiment of the invention is used to prepare a substrate wiring packaging structure 100. The substrate wiring packaging method includes the following steps: S1: A barrier layer 210 is formed on the surface of the vehicle 200.

[0036] See also Figure 2 Specifically, a carrier 200 is first taken, and a liquid adhesive material is coated onto the surface of the carrier 200 using a spin coating process. Then, it is soft-baked on a hot plate to form a film, creating an adhesive layer. This adhesive layer can be a bonding adhesive, which is separated by UV light irradiation. The material of the adhesive layer can include epoxy resin, polyimide, benzocyclobutene, and other polymer composite materials. Then, a barrier layer 210 is formed using LPCVD (Low Pressure Chemical Vapor Deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition). The barrier layer 210 is made of at least one of Ti, Cu, and Al, serving as a light-blocking material to prevent the underlying adhesive layer from being affected during subsequent exposures.

[0037] S2: Photolithographic positive resist layer 220 and photolithographic negative resist layer 230 are respectively covered on adjacent different regions of the barrier layer 210.

[0038] See also Figure 3 The photoresist layer 220 and the photoresist layer 230 are bonded together. Specifically, before covering the photoresist, a base metal layer 160 can be formed on the barrier layer 210, and then an absorbing protective layer 150 can be formed on the barrier layer 210. The absorbing protective layer 150 is a dielectric material, covering the base metal layer 160 and exposing the base metal layer 160 through openings. In actual fabrication, photoresist can be spin-coated first, then exposed and developed to form openings, then electroplated to form the base metal layer 160, then the photoresist can be removed, and then a dielectric material can be spin-coated, cured, and the openings exposed to expose the base metal layer 160. Here, the base metal layer 160 serves as the base electrical connection pad, and its layout is regular, so the mask pattern is simple and can be directly formed by zoned exposure and development. Of course, in other preferred embodiments of the present invention, the fabrication of the base metal layer 160 and the absorbing protective layer 150 can be omitted, and wiring processes can be performed directly on the barrier layer 210.

[0039] It should be noted that a substrate metal layer 160 and a microwave absorbing protective layer 150 are fabricated here. The microwave absorbing protective layer 150 can absorb the exposure energy in the subsequent exposure process, further preventing the exposure process from affecting the adhesive layer of the carrier 200, and further preventing diffraction / scattering phenomena due to optical properties during the exposure process. At the same time, the microwave absorbing protective layer 150 can also protect the substrate metal layer 160 in the subsequent resist removal process.

[0040] After the absorbing protective layer 150 is prepared, the wiring process can be carried out. First, the preset area of ​​the blocking layer 210 is divided into adjacent positive resist area 221 and negative resist area 231. Then, the photolithographic positive resist layer 220 is covered in the positive resist area 221 and the photolithographic negative resist layer 230 is covered in the negative resist area 231 using the spin coating process.

[0041] It should be noted that both the positive photoresist layer 220 and the negative photoresist layer 230 are photoresists, but their solubility after exposure to light is opposite. After exposure, the exposed areas of the positive photoresist layer 220 dissolve in the developer, while the unexposed areas remain intact. Conversely, the negative photoresist layer 230 undergoes a cross-linking reaction after exposure and remains insoluble in the developer, while the unexposed areas do dissolve.

[0042] It is worth noting that the preset area of ​​the barrier layer 210 is divided into different positive resist areas 221 and negative resist areas 231. This preset area is the area where wiring needs to be performed. The positive resist areas 221 and negative resist areas 231 are adjacent to each other, so that the photoresist completely covers the entire preset area.

[0043] It should also be noted that the absorbing protective layer 150 is pre-drilled to expose the base metal layer 160. Compared with using photoresist to drill holes, pre-drilling can ensure drilling accuracy and make the window position of the base metal layer 160 more precise.

[0044] S3: Pattern and groove the photolithographic positive resist layer 220 and the photolithographic negative resist layer 230 respectively to form a wiring metal layer 112.

[0045] See Figure 4Specifically, the positive photoresist layer 220 is first exposed and developed using a first photomask 222 to form a first pattern window 223 on the positive photoresist layer 220, and a first notch 224 is formed on the edge of the positive photoresist layer 220 near the negative photoresist layer 230. At this time, the negative photoresist layer 230 blocks and covers the negative photoresist area, which can protect the bottom substrate metal layer 160 and the microwave absorbing protective layer 150. Then, the negative photoresist layer 230 is exposed and developed using a second photomask 232 to form a second pattern window 233 on the negative photoresist layer 230, and a second notch 234 is formed on the edge of the negative photoresist layer 230 near the positive photoresist layer 220. The first notch 224 and the second notch 234 are spliced ​​together to form a positioning opening. Finally, a wiring metal layer 112 is electroplated in the first pattern window 223 and the second pattern window 233, and a positioning metal layer 113 is electroplated in the positioning opening. Both the wiring metal layer 112 and the positioning metal layer 113 can be copper layers. The positioning metal layer 113 can determine the accuracy of adjacent pattern layers and improve the bonding force at the splicing interface between the positive adhesive area 221 and the negative adhesive area 231. The positioning opening here can be circular, rhomboid, or rectangular, so that the positioning metal layer 113 is circular, rhomboid, or rectangular, which is more conducive to using the positioning metal layer 113 as a positioning mark during subsequent layer stacking.

[0046] It should be noted that the size of the metal pads in the positioning metal layer 113 can be detected here, and the measured value can be compared with the design value of the pattern. When the measured value is within the standard design error, it indicates that there is no abnormality in the pattern splicing. In actual inspection, it can be achieved through automated optical inspection (AOI), which utilizes the difference in reflectivity between the dielectric and the underlying metal, as well as the interference effect of the dielectric thin film, to quickly identify / measure the morphology / size of the metal layer inside the opening through differences in reflected light intensity, color difference, and grayscale distribution.

[0047] It should be noted that the wiring metal layer 112 here has a complex wiring structure, so it can be divided into a positive photoresist area 221 and a negative photoresist area 231 during exposure. The patterns of the first photomask 222 and the second photomask 232 are different and can be set according to actual needs. The size of the first photomask 222 can be adapted to the size of the positive photoresist area 221, and the size of the second photomask 232 can be adapted to the size of the negative photoresist area 231. By using the first photomask 222 and the second photomask 232 for separate exposure and development, zoned exposure is achieved. Furthermore, the use of positive and negative photoresist design can avoid mutual interference between pattern layers, reduce diffraction / scattering phenomena caused by optical properties in adjacent areas during the exposure process, improve the resolution of the transferred pattern, and ensure exposure accuracy.

[0048] S4: Remove the residual photolithography positive resist layer 220 and photolithography negative resist layer 230.

[0049] See Figure 5 Specifically, the photoresist layer is removed by a cleaning solution, thereby retaining the wiring metal layer 112 and the positioning metal layer 113, and the wiring metal layer 112 can make electrical contact with the substrate metal layer 160.

[0050] It should be noted that, due to the presence of the microwave absorbing protective layer 150, which acts as a dielectric material, it can protect the underlying base metal layer 160 during the adhesive removal process, preventing adhesive removal cleaning fluid residue and excessive corrosion.

[0051] S5: A wiring medium layer 111 is formed on the barrier layer 210.

[0052] See Figure 6 The wiring dielectric layer 111 covers the wiring metal layer 112. Specifically, a dielectric material can be spin-coated onto the absorbing protective layer 150 and cured to form the wiring dielectric layer 111, wherein the wiring dielectric layer 111 can cover the wiring metal.

[0053] S6: Repeat the above steps to form wiring combination layer 110.

[0054] See Figure 7 The wiring combination layer 110 includes a multi-layer wiring dielectric layer 111 and a multi-layer wiring metal layer 112. Specifically, steps S2 to S5 can be repeated to form a multi-layer wiring dielectric layer 111 or a multi-layer wiring metal layer 112. For example, both the wiring dielectric layer 111 and the wiring metal layer 112 can be two layers. When redividing the positive adhesive area 221 and the negative adhesive area 231, the already shaped previous positioning metal layer 113 can be used as a positioning marker, and the positioning metal layer 113 expands layer by layer, which facilitates more accurate division of areas and wiring, and improves the accuracy of subsequent overlay patterns.

[0055] S7: A first protective dielectric layer 120 is formed on the wiring combination layer 110.

[0056] See Figure 8 Specifically, a dielectric material can be spin-coated onto the top layer of the wiring dielectric layer 111 and cured to form a first protective dielectric layer 120, which can completely cover the underlying wiring combination layer 110.

[0057] S8: A first connection pad 121 is formed in the first protective dielectric layer 120.

[0058] See Figure 9 Specifically, the first protective dielectric layer 120 is opened by an exposure and development process, and metal and conductive protrusions are electroplated to form the first connecting pad 121, which improves the solderability of the solder ball 172.

[0059] S9: Multiple stacked chips 130 are mounted on the first connection pad 121.

[0060] See Figure 10 The stacked chip 130 is electrically connected to the wiring combination layer 110 via the first connection pad 121. Specifically, multiple stacked chips 130 can be mounted on the first connection pad 121 using a chip mounting process. All stacked chips 130 are flip chips and are fixed to the first connection pad 121 using a reflow soldering process. The multiple stacked chips 130 include a first chip 131 and a second chip 132. The first chip 131 is located at the center, and the second chip 132 is located around the first chip 131. The first chip 131 can be a graphics processing unit (GPU) chip or a logic chip, etc., and the second chip 132 can be a random access memory (DDR) chip or a high-bandwidth memory (HBM) chip, etc., and the second chip 132 can be a multilayer chip.

[0061] S10: A molding compound 140 is formed on the first protective dielectric layer 120 to cover a plurality of stacked chips 130.

[0062] See Figure 11 Specifically, a molding layer 140 can be formed by selective molding using printing or pressure injection molding processes to protect multiple stacked chips 130.

[0063] In some preferred embodiments, the molding compound 140 can also be polished to expose the back side of at least one stacked chip 130, thereby reducing the package height while improving the chip's heat dissipation efficiency.

[0064] S11: Remove vehicle 200 and barrier layer 210 in sequence.

[0065] See Figure 12 Specifically, the carrier 200 can be first stripped by debonding, and then the barrier layer 210 can be removed by micro-etching. In actual fabrication, the carrier 200 can be removed by irradiating with UV light to expose the barrier layer 210, and then the barrier layer 210 can be removed by etching or chemical polishing to expose the substrate metal layer 160 and the microwave absorbing protective layer 150.

[0066] S12: A second protective dielectric layer 170 is formed on the surface of the wiring combination layer 110 away from the first protective dielectric layer 120.

[0067] See Figure 13 Specifically, a second protective medium layer 170 can be formed by spin-coating a medium material onto the surface of the base metal layer 160 and the microwave absorbing protective layer 150 and then curing it.

[0068] S13: A second connection pad 171 is formed in the second protective dielectric layer 170.

[0069] See Figure 14 The second connection pad 171 is electrically connected to the base metal layer 160. Specifically, referring to the preparation process of the first connection pad 121, an opening is made in the second protective dielectric layer 170 to expose the base metal layer 160, and then a metal layer is electroplated to form the second connection pad 171.

[0070] S14: Form solder balls 172 on the second connection pad 171.

[0071] See connection Figure 15 Specifically, solder balls 172 are formed on the second connecting pad 171 through a ball-planting process, and then cut to form a single product. During the cutting process, the positioning metal layer 113 can be removed.

[0072] See Figure 16 It should be noted that in this embodiment, the preset areas are all rectangular areas. When performing step S2, the area division can be based on the mounting area of ​​the subsequent stacked chips 130. For example, the first division pattern allows the projections of multiple stacked chips 130 on the barrier layer 210 to fall into the preset area. Both the positive adhesive area 221 and the negative adhesive area 231 are rectangular, and multiple positive adhesive areas 221 and multiple negative adhesive areas 231 are distributed in an array. By evenly distributing them, the size of the exposure area can be reduced, making it easier to perform zoned exposure. For example, a 5-inch standard mask can be used to limit the size of the chip wiring area.

[0073] It is worth noting that the edges of the rectangular positive adhesive area 221 and negative adhesive area 231 are respectively designed with a first notch 224 and a second notch 234, thus forming a positioning opening at the joint. A positioning opening is necessarily present at the intersection of the rectangles, with multiple positioning openings distributed along different intersection edges. Since the adjacent edges of the rectangular positive adhesive area 221 or negative adhesive area 231 are perpendicular, positioning openings are provided on adjacent intersection edges. Referring to the previous text, when detecting the positioning metal layers 113 on adjacent edges (e.g., three positioning metal layers 113 located on adjacent right-angled sides), their deflection angle can also be detected, thereby detecting the deflection angle of the positive adhesive area 221 or negative adhesive area 231. When the deflection angle exceeds a limit value, it indicates that the defined area of ​​the positive adhesive area 221 or negative adhesive area 231 is incorrect and needs correction.

[0074] See Figure 17In other preferred embodiments of the present invention, a second patterning method can also be used: the projections of multiple stacked chips 130 onto the barrier layer 210 fall into a predetermined area, with both the positive adhesive area 221 and the negative adhesive area 231 forming right-angled triangles, and the hypotenuse side edge of the positive adhesive area 221 joining the hypotenuse side edge of the negative adhesive area 231. This allows for mirroring during the layering patterning process, thereby reducing warpage of the stacked dielectric layer and absorbing stress.

[0075] It is worth noting that when repeating step S2 here, either the first type of partitioning pattern can be used consistently, or the second type of partitioning pattern can be used consistently. Or, as follows: Figure 18 When performing step S2 at different layers, a scheme of alternating between the first and second partitioning patterns can be adopted, that is, rectangular partitioning is used when routing at the first layer, and right-angled triangle partitioning is used when routing at the second layer.

[0076] See Figure 19 In other preferred embodiments of the present invention, a third type of pattern can also be used: the projection of some stacked chips 130 on the barrier layer 210 falls into a preset area, the positive adhesive area 221 and the negative adhesive area 231 are both rectangular, the multiple positive adhesive areas 221 and the multiple negative adhesive areas 231 are arrayed, and the bonding edges of the positive adhesive areas 221 and the negative adhesive areas 231 are misaligned with the multiple stacked chips 130.

[0077] It is worth noting that the bonding edges of the positive adhesive area 221 and the negative adhesive area 231 are misaligned with the stacked chips, allowing the positioning openings and positioning metal layer 113 to be misaligned with the stacked chips 130. Specifically, the multiple stacked chips 130 are distributed in multiple modules, with each module having multiple stacked chips 130, and the bonding edges can be distributed along the gaps between adjacent modules. Furthermore, the rectangular distribution of the positive adhesive area 221 and the negative adhesive area 231 also enables the detection of the overall preset area offset. That is, by detecting the deflection angle of the multiple positioning openings and the positioning metal layer 113, the deflection angle of the positive adhesive area 221 or the negative adhesive area 231 can be detected. When the deflection angle exceeds the limit value, it indicates that the defined area of ​​the positive adhesive area 221 or the negative adhesive area 231 is incorrect and needs to be corrected.

[0078] See Figure 20 Furthermore, when creating the patterned opening, a correction opening 240 can be provided adjacent to the positioning opening. After electroplating metal, a correction pad can be formed in the correction opening 240. This correction pad can work with the positioning metal layer 113 to improve positioning accuracy, thereby preventing the offset of multiple patterned layers. In addition, the correction pad and the positioning metal layer 113 can also form a flow channel and improve structural strength, preventing warping and delamination.

[0079] See Figure 21In other preferred embodiments of the present invention, a fourth type of pattern division can also be adopted: the projection of part of the stacked chip 130 on the barrier layer 210 falls into a preset area, and the positive adhesive area 221 and the negative adhesive area 231 are both right-angled triangles.

[0080] It is worth noting that when repeating step S2, either the third or fourth partitioning pattern can be used consistently. Alternatively, when performing step S2 on different layers, the third and fourth partitioning patterns can be used alternately, i.e., rectangular partitioning is used for the first layer routing and right-angled triangle partitioning is used for the second layer routing. This allows for better utilization of the positioning metal layer 113 of each layer as a positioning representation, further improving the accuracy of the overlay pattern.

[0081] See Figure 22 This invention also provides a substrate wiring package structure 100, fabricated using the substrate wiring package method described in the foregoing embodiments. The substrate wiring package structure 100 includes a wiring assembly layer 110, a first protective dielectric layer 120, a plurality of stacked chips 130, and a molding compound layer 140. The wiring assembly layer 110 includes multilayer wiring dielectric layers 111 and multilayer wiring metal layers 112, with the multilayer wiring metal layers 112 respectively disposed within the multilayer wiring dielectric layers 111. The first protective dielectric layer 120 is disposed on one side of the wiring assembly layer 110, and a first connection pad 121 is formed in the first protective dielectric layer 120. The plurality of stacked chips 130 are disposed on one side of the wiring assembly layer 110 and electrically connected to the wiring assembly layer 110 via the first connection pad 121. The molding compound layer 140 is disposed on the first protective dielectric layer 120 and covers the plurality of stacked chips 130.

[0082] Furthermore, the substrate wiring package structure 100 also includes an absorbing protective layer 150, a base metal layer 160, and a second protective dielectric layer 170. The absorbing protective layer 150 is located on the other side of the wiring assembly layer 110 and covers the base metal layer 160. The base metal layer 160 is electrically connected to the wiring assembly layer 110. The second protective dielectric layer 170 is disposed on the side of the absorbing protective layer 150 away from the first protective dielectric layer 120. The second protective dielectric layer 170 has a second connection pad 171, which is electrically connected to the base metal layer 160 and has solder balls 172.

[0083] The multiple stacked chips 130 may include a first chip 131 and a second chip 132. The first chip 131 is located at the center, and the second chip 132 is located around the first chip 131. The first chip 131 may be a graphics processing unit (GPU) chip or a logic chip, etc., and the second chip 132 may be a random access memory (DDR) chip or a high bandwidth memory (HBM) chip, etc., and the second chip 132 may be a stacked chip.

[0084] In summary, the substrate wiring packaging method and substrate wiring packaging structure 100 provided in this embodiment of the invention first form a barrier layer 210 on a carrier 200. Then, adjacent regions on the barrier layer 210 are respectively covered with mutually bonded photoresist positive layers 220 and photoresist negative layers 230. Next, the photoresist positive layers 220 and photoresist negative layers 230 are patterned and grooved to form wiring metal layers 112. Then, the photoresist positive layers 220 and photoresist negative layers 230 are removed, and a wiring dielectric layer 111 is then covered. The fabrication process of each wiring metal layer 112 is repeated to form a wiring assembly layer 110. Then, a first protective dielectric layer 120 is formed on the wiring assembly layer 110, and a first connection pad 121 is formed in the first protective dielectric layer 120. Finally, the die stack and molding compound 140 are fabricated, and the carrier 200 and barrier layer 210 are removed. Compared to existing technologies, this invention employs a photolithographic positive resist layer 220 and a photolithographic negative resist layer 230 to cover different areas, and exposes the positive and negative resists separately. This allows for zoned exposure, meeting the requirements for larger pattern areas. Furthermore, it expands the wiring area, reduces aperture density, and mitigates diffraction / scattering phenomena caused by optical properties during the exposure process, improving the resolution of the transferred pattern. Additionally, it reduces exposure energy, preventing the imaging lens from expanding due to heat and ensuring exposure accuracy.

[0085] Second Embodiment See Figure 23 This embodiment of the invention provides a substrate wiring packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.

[0086] In this embodiment, the substrate wiring package structure 100 includes a wiring assembly layer 110, a first protective dielectric layer 120, a plurality of stacked chips 130, a molding compound layer 140, a microwave absorbing protective layer 150, a substrate metal layer 160, and a second protective dielectric layer 170. The wiring assembly layer 110 includes a multilayer wiring dielectric layer 111 and a multilayer wiring metal layer 112, with the multilayer wiring metal layer 112 respectively disposed in the multilayer wiring dielectric layer 111. The first protective dielectric layer 120 is disposed on one side of the wiring assembly layer 110, and a first connection pad 121 is formed in the first protective dielectric layer 120. The plurality of stacked chips 130 are disposed on one side of the wiring assembly layer 110 and are electrically connected to the wiring assembly layer 110 through the first connection pad 121. The molding compound layer 140 is disposed on the first protective dielectric layer 120 and covers the plurality of stacked chips 130. The absorbing protective layer 150 is located on the other side of the wiring assembly layer 110 and covers the base metal layer 160. The base metal layer 160 is electrically connected to the wiring assembly layer 110. The second protective dielectric layer 170 is disposed on the side of the absorbing protective layer 150 away from the first protective dielectric layer 120. The second protective dielectric layer 170 has a second connection pad 171, which is electrically connected to the base metal layer 160 and has solder balls 172.

[0087] In some preferred embodiments, the molding compound 140 can also be polished to expose the back side of at least one stacked chip 130, thereby reducing the package height while improving the chip's heat dissipation efficiency.

[0088] Furthermore, the substrate wiring package structure 100 also includes an insulating layer 180, which surrounds the periphery of the wiring assembly layer 110 and at least covers the sidewalls of the wiring assembly layer 110. Specifically, the insulating layer 180 can protect the wiring assembly layer 110, thereby preventing the wiring assembly layer 110 from warping. In addition, the insulating layer 180 can also cover the sidewalls of the microwave absorbing protective layer 150, the first protective dielectric layer 120, and the second protective dielectric layer 170, and is flush with the second protective dielectric layer 170. The material of the insulating layer 180 can be polyimide, benzocyclobutene, epoxy resin, etc.

[0089] Third Embodiment See Figure 24 This invention provides a substrate wiring packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first or second embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first or second embodiment.

[0090] The substrate wiring package structure 100 includes a wiring assembly layer 110, a first protective dielectric layer 120, multiple stacked chips 130, a molding compound layer 140, a microwave absorbing protective layer 150, a base metal layer 160, and a second protective dielectric layer 170. The wiring assembly layer 110 includes multiple wiring dielectric layers 111 and multiple wiring metal layers 112, with the multiple wiring metal layers 112 respectively disposed in the multiple wiring dielectric layers 111. The first protective dielectric layer 120 is disposed on one side of the wiring assembly layer 110, and a first connection pad 121 is formed in the first protective dielectric layer 120. The multiple stacked chips 130 are disposed on one side of the wiring assembly layer 110 and are electrically connected to the wiring assembly layer 110 through the first connection pad 121. The molding compound layer 140 is disposed on the first protective dielectric layer 120 and covers the multiple stacked chips 130. The microwave absorbing protective layer 150 is located on the other side of the wiring assembly layer 110 and covers the base metal layer 160, which is electrically connected to the wiring assembly layer 110. The second protective dielectric layer 170 is disposed on the side of the microwave absorbing protective layer 150 away from the first protective dielectric layer 120. The second protective dielectric layer 170 is provided with a second connecting pad 171, which is electrically connected to the base metal layer 160 and is provided with solder balls 172.

[0091] In some preferred embodiments, the molding compound 140 can also be polished to expose the back side of at least one stacked chip 130, thereby reducing the package height while improving the chip's heat dissipation efficiency.

[0092] Furthermore, the substrate wiring package structure 100 also includes an insulating layer 180, which surrounds the periphery of the wiring assembly layer 110 and at least covers the sidewalls of the wiring assembly layer 110. The insulating layer 180 also covers the side of the wiring assembly layer 110 near the stacked chips 130. Conductive pillars 181 are also provided in the insulating layer 180, with one end of the conductive pillar 181 connected to the first connection pad 121 and the other end protruding from the insulating layer 180. Multiple stacked chips 130 are mounted on the conductive pillars 181.

[0093] It should be noted that the insulating layer 180 also covers the first connection pad 121 and the wiring metal, and forms conductive pillars 181 on top to achieve the electrical connection between the stacked chip 130 and the first connection pad 121. According to the capacitance formula C=εS / d (C is the capacitance value, ε is the dielectric constant, S is the overlap area between the circuit layers, and d is the vertical distance between the circuit layers), the conductive pillars 181 can improve conductivity, thereby allowing higher current to pass through.

[0094] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A substrate wiring packaging method, characterized in that, include: A barrier layer is formed on the surface of the vehicle; A positive photoresist layer and a negative photoresist layer are respectively covered in adjacent regions on the barrier layer, wherein the positive photoresist layer and the negative photoresist layer are bonded together; The positive photoresist layer and the negative photoresist layer are respectively patterned and grooved to form a wiring metal layer; Remove any remaining photoresist positive layer and photoresist negative layer; A wiring dielectric layer is formed on the barrier layer, and the wiring dielectric layer covers the wiring metal layer; Repeat the above steps to form a cabling composite layer, wherein the cabling composite layer includes multiple cabling dielectric layers and multiple cabling metal layers; A first protective dielectric layer is formed on the wiring combination layer; A first connection pad is formed in the first protective dielectric layer; Multiple stacked chips are mounted on the first connection pad, wherein the stacked chips are electrically connected to the wiring combination layer through the first connection pad; A molding compound layer is formed on the first protective dielectric layer to encapsulate the stacked chips; Remove the vehicle and the barrier layer in sequence.

2. The substrate wiring and packaging method according to claim 1, characterized in that, The step of coating adjacent different regions on the barrier layer with a positive photoresist layer and a negative photoresist layer respectively includes: The preset area of ​​the barrier layer is divided into adjacent positive adhesive area and negative adhesive area; A photolithographic positive resist layer is applied over the positive resist area; A photolithographic negative resist layer is applied within the negative resist area.

3. The substrate wiring and packaging method according to claim 2, characterized in that, The steps of patterning and slotting the photoresist positive layer and the photoresist negative layer to form a wiring metal layer include: The positive photoresist layer is exposed and developed using a first photomask to form a first pattern window on the positive photoresist layer, and a first notch is formed on the edge of the positive photoresist layer near the negative photoresist layer, wherein the negative photoresist layer blocks and covers the negative photoresist area. The photoresist layer is exposed and developed using a second photomask to form a second pattern window on the photoresist layer, and a second notch is formed at the edge of the photoresist layer near the photoresist layer, wherein the first notch and the second notch are spliced ​​together to form a positioning opening. A wiring metal layer is formed by electroplating in the first pattern window and the second pattern window, and a positioning metal layer is formed by electroplating in the positioning opening.

4. The substrate wiring and packaging method according to claim 3, characterized in that, The projections of multiple stacked chips onto the barrier layer fall into the preset area, and both the positive adhesive area and the negative adhesive area are rectangular, with multiple positive adhesive areas and multiple negative adhesive areas distributed in an array.

5. The substrate wiring and packaging method according to claim 3, characterized in that, The projections of the stacked chips onto the barrier layer fall into the preset area, where both the positive adhesive area and the negative adhesive area are right-angled triangles, and the hypotenuse side edge of the positive adhesive area is joined to the hypotenuse side edge of the negative adhesive area.

6. The substrate wiring and packaging method according to claim 3, characterized in that, The projection of some of the stacked chips onto the barrier layer falls into the preset area. Both the positive adhesive area and the negative adhesive area are rectangular. Multiple positive adhesive areas and multiple negative adhesive areas are distributed in an array, and the bonding edges of the positive adhesive areas and the negative adhesive areas are misaligned with the multiple stacked chips.

7. The substrate wiring and packaging method according to claim 3, characterized in that, The positioning opening is circular, rhomboid, or rectangular.

8. The substrate wiring and packaging method according to claim 1, characterized in that, Before the step of respectively covering adjacent different regions on the barrier layer with a positive photoresist layer and a negative photoresist layer, the method further includes: A base metal layer is formed on the barrier layer; An absorbing protective layer is formed on the blocking layer, wherein the absorbing protective layer covers the substrate metal layer and has openings to expose the substrate metal layer; The microwave absorbing protective layer is used to absorb exposure energy and protect the substrate metal layer.

9. The substrate wiring and packaging method according to claim 8, characterized in that, After the steps of sequentially removing the vehicle and the barrier layer, the method further includes: A second protective dielectric layer is formed on the surface of the wiring assembly layer away from the first protective dielectric layer; A second connection pad is formed in the second protective dielectric layer, wherein the second connection pad is electrically connected to the base metal layer; Solder balls are formed on the second connection pad.

10. The substrate wiring and packaging method according to claim 1, characterized in that, The step of sequentially removing the vehicle and the barrier layer includes: The carrier is peeled off using a debonding process; The barrier layer is removed by micro-etching or grinding processes.

11. A substrate wiring packaging structure, fabricated using the substrate wiring packaging method as described in claim 1, characterized in that, include: The cabling combination layer includes multiple cabling dielectric layers and multiple cabling metal layers, wherein the multiple cabling metal layers are respectively disposed in the multiple cabling dielectric layers; A first protective dielectric layer is disposed on one side of the wiring assembly layer, and a first connection pad is formed in the first protective dielectric layer; Multiple stacked chips are disposed on one side of the wiring combination layer and electrically connected to the wiring combination layer via the first connection pad; A molding compound is disposed on the first protective dielectric layer and covers the stacked chips.

12. The substrate wiring packaging structure according to claim 11, characterized in that, The substrate wiring package structure further includes an absorbing protective layer and a base metal layer. The absorbing protective layer is located on the other side of the wiring assembly layer and covers the base metal layer. The base metal layer is electrically connected to the wiring assembly layer.

13. The substrate wiring packaging structure according to claim 12, characterized in that, The substrate wiring package structure further includes a second protective dielectric layer, which is disposed on the side of the microwave absorbing protective layer away from the first protective dielectric layer. The second protective dielectric layer has a second connection pad, which is electrically connected to the substrate metal layer and has solder balls.

14. The substrate wiring package structure according to any one of claims 11-13, characterized in that, The substrate wiring package structure further includes an insulating layer surrounding the periphery of the wiring assembly layer and at least covering the sidewalls of the wiring assembly layer.

15. The substrate wiring packaging structure according to claim 14, characterized in that, The insulating layer also covers one side of the wiring assembly layer, and a conductive post is provided in the insulating layer. One end of the conductive post is connected to the first connection pad, and the other end protrudes from the insulating layer. Multiple stacked chips are mounted on the conductive post.

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