Improved bipolar transistor reverse recovery
By introducing a parasitic PNP transistor structure and a deep trench isolation structure into the isolation trench region of a bipolar transistor, a low-impedance conductive path is formed, which solves the problem of long reverse recovery time and improves frequency response performance and surge current capacity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEXAS INSTRUMENTS INC
- Filing Date
- 2024-12-19
- Publication Date
- 2026-06-09
Smart Images
Figure CN122181201A_ABST
Abstract
Description
Background Technology
[0001] Bipolar transistors can be isolated in integrated circuits using junction implants or deep trench isolation structures. One characteristic of this type of transistor is its reverse recovery time, which can limit the transistor's frequency response. Summary of the Invention
[0002] In one aspect, an electronic device includes a semiconductor layer, a base region, an emitter region, and a first collector region and a second collector region. The semiconductor layer extends over a substrate and has a top surface and an isolation trench region extending from the top surface into the semiconductor layer. The base region has a first conductivity type and extends from the top surface into the isolation trench region, and the semiconductor layer has an opposite second conductivity type. The emitter region has the second conductivity type and extends from the top surface into the base region. The first collector region has the second conductivity type and extends from the top surface into the isolation trench region and is spaced apart from the base region. The second collector region has the first conductivity type and extends from the top surface into the isolation trench region, and is spaced apart from the base region and the collector region.
[0003] In another aspect, an integrated circuit includes: an epitaxial layer over a semiconductor substrate; an isolation structure surrounding an isolation trench region and including a portion of the epitaxial layer; a base well having a first conductivity type and extending into the isolation trench region, the epitaxial layer having an opposite second conductivity type; and a transistor terminal having the second conductivity type and extending into the base well. The integrated circuit further includes: a first well having the second conductivity type and extending into the isolation trench region and spaced apart from the base well; and a second well having the first conductivity type and extending into the isolation trench region and spaced apart from the base well, wherein the transistor terminal, the base well, the isolation trench region, and the first well form a first bipolar transistor having a first polarity type, and the base well, the isolation trench region, and the second well form a second bipolar transistor having a second polarity type.
[0004] In another aspect, a method of manufacturing an electronic device includes: forming a base region having a first conductivity type in an isolation trench region of the semiconductor layer above a substrate supporting the semiconductor layer, the semiconductor layer having a second conductivity type; forming an emitter region having the second conductivity type in the base region; forming a first collector region having the second conductivity type and spaced apart from the base region in the isolation trench region; and forming a second collector region having the first conductivity type and spaced apart from the base region and the collector region in the isolation trench region. Attached Figure Description
[0005] Figure 1This is a partial top view of an electronic device containing bipolar transistors in an isolation bay.
[0006] Figure 1A It is along Figure 1 A partial side front view of the electronic device taken from line 1A-1A.
[0007] Figure 1B yes Figure 1 and 1A Top perspective view of the electronic device.
[0008] Figure 2 This is a flowchart of a method for manufacturing electronic devices.
[0009] Figures 3 to 19 It is based on Figure 2 The method involves manufacturing processes Figures 1 to 1B A partial side front view of an electronic device.
[0010] Figure 20 This is a partial top view of another electronic device containing bipolar transistors in an isolation bay.
[0011] Figure 21 This is a partial top view of another electronic device containing bipolar transistors in an isolation bay.
[0012] Figure 22 and 23 It is a graph that shows the comparative reverse recovery performance. Detailed Implementation
[0013] In the drawings, the same element symbols refer to the same element throughout, and various features are not necessarily drawn to scale. Furthermore, the terms "couple" or "couples" encompass indirect or direct electrical connections or mechanical connections, or combinations thereof. For example, if a first device is coupled to or with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of function, which in some cases arises from the configuration and / or interconnection of various structures when the circuit system is powered and operated. In the following description and claims, the terms "including," "includes," "having," "has," "with," or variations thereof are inclusive in a manner similar to the term "comprising," and therefore mean "including, but not limited to."
[0014] Unless otherwise stated, "approximately," "roughly," or "substantially" preceding a value means + / - 10% of the stated value. The following describes one or more operating characteristics of various circuits, systems, and / or components in the context of functionality, which in some cases stems from the configuration and / or interconnection of various structures when the circuit system is powered and operated. The described examples include doped regions of various semiconductor structures, which may be characterized as p-doped and / or n-doped regions or portions, and include regions having a particular type of majority carrier dopant (e.g., n-type or p-type dopant), and these regions or portions having a conductivity type such as n-type or p-type. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc., may be referred to herein as first, second, third, etc., e.g., first and second terminals, first well, second and third well, etc., wherein these should not be construed as limiting with respect to the claims. The various structures and methods described in this specification can be advantageously applied to the manufacture of electronic devices such as integrated circuits. While such examples may provide various improvements, no particular result is required by this specification unless expressly stated in a particular claim.
[0015] This specification recognizes that the reverse recovery time of some bipolar transistors is determined in part by the time required to remove holes injected into the collector (for examples of NPN transistors) when the transistor is in a reverse bias state (e.g., negative base-emitter bias). Various examples can improve the performance of such transistors by providing parasitic PNP transistors that provide conductive paths to the device substrate for holes, thereby reducing the reverse recovery time. While these examples may be expected to improve device performance parameters such as maximum operating frequency, such specific results are not required unless expressly stated in the particular claims.
[0016] Figure 1 , Figure 1A and 1B An electronic device 100 is shown having a semiconductor die 101, the semiconductor die including a semiconductor substrate 102. Figure 1A The semiconductor substrate is or comprises silicon or other suitable semiconductor material and has a first conductivity type (e.g., comprising a first type of majority carrier dopant, such as p-type, in...). Figure 1A (The label is "substrate" in Chinese). Electronic device 100 includes components formed on... Figure 1A The bipolar NPN transistor in the isolation trench 103 described herein. Electronic device 100 is shown having a first direction X, a perpendicular (orthogonal) second direction Y. Figure 1 and 1B ) and a third direction Z perpendicular (or orthogonal) to the corresponding first direction X and second direction Y. Figure 1A and 1B In an exemplary three-dimensional space.
[0017] Semiconductor layer 104 (e.g., epitaxial silicon, which may be referred to as second semiconductor layer 104 or epitaxial layer 104) in Figure 1A The semiconductor substrate 102 shown extends above and has a first conductivity type (e.g., containing a first type of majority carrier dopant, such as p-type, in...) Figure 1A (labeled "PEI" in Chinese). It has the opposite second conductivity type (e.g., containing a second type of majority carrier dopant, such as n-type, in...). Figure 1A A buried layer 105 (labeled "NBL") extends from the epitaxial semiconductor layer 104. In the example described below, the first conductivity type is p-type and the second conductivity type is n-type. In other embodiments not explicitly shown, similar benefits and structures can be made by reversing the conductivity types of various structures, for example, where the first conductivity type may be n-type and the second conductivity type may be p-type.
[0018] like Figure 1A As shown, a semiconductor layer 106 (e.g., epitaxial silicon, which may be referred to as the first semiconductor layer 106 or epitaxial layer 106) extends over the substrate 102 from the epitaxial layer 104 and from the buried layer 105. The semiconductor layer 106 has a second conductivity type (e.g., containing n-type majority carriers) and... Figure 1A The semiconductor layer 106 is marked as "N EPI". The semiconductor layer 106 has a top surface extending in planes in the respective first direction X and second direction Y, and includes an isolation trench 103 extending from the top surface into the semiconductor layer 106 to the buried layer 105. The upper portion of the buried layer 105 extends into the lower portion of the semiconductor layer 106 in the illustrated example, for example, by diffusing an n-type dopant originally implanted in the epitaxial layer 104 into the lower portion of the semiconductor layer 106.
[0019] like Figure 1 and 1A As further shown, the deep trench isolation structure 107 extends from the top surface through the semiconductor layer 106 and into the substrate 102. The substrate 102 lies beneath the deep trench isolation structure 107, and the deep trench isolation structure 107 laterally surrounds the isolation trench 103 of the semiconductor layer 106. The buried layer 105 extends between the semiconductor layer 106 and the substrate 102 and is laterally demarcated by the deep trench isolation structure 107 that laterally surrounds the isolation trench 103, as shown below. Figure 1 and 1A As shown in the illustration. In the illustrated example, the embedded layer 105 does not extend laterally outward from the deep trench isolation structure 107. In another example, a portion of the embedded layer 105 extends laterally outward beyond a portion of the deep trench isolation structure 107 (e.g., in...). Figure 1A In the view along the first direction X). For example Figure 1AAs shown in the illustration, in one example, the deep trench isolation structure 107 includes a trench having a sidewall liner 108 (e.g., an oxide or other insulator) and doped polysilicon 109 on the sidewall liner 108, extending from the top surface of the epitaxial semiconductor layer 106 to the substrate 102.
[0020] like Figure 1 and 1A As shown, electronic device 100 includes a first bipolar transistor Q1 and a second bipolar transistor Q2 within an isolation trench 103. In the illustrated example, transistor Q1 is an NPN transistor and includes an n-type collector C1 implemented by a first collector region, also referred to as C1. The first collector region C1 includes an n-type well or region 110 (e.g., in...). Figure 1A The first collector region C1, labeled "N-well" and sometimes referred to as deep well 110 or n-well 110, has a dopant concentration of the second type of majority carriers that is greater than that of the n-type epitaxial layer 106. The first collector region C1 also includes a more heavily doped n-type region 112 (sometimes referred to as collector junction 112) extending into the top surface of the epitaxial semiconductor layer 106 within the deep implantation region 110. In one example, the shallow n-type implantation region 112 has a greater n-type dopant concentration than that of the deep implantation region 110, for example, through degenerate doping, and in… Figure 1A The n-well 110 and the collector contact 112 can both be formed by ion implantation and diffusion. The collector C1 is further realized by a semiconductor layer 106, which provides a conductive path between the n-well 110 and the p-type base B1.
[0021] Base B1 passes through p-type base region 114 (e.g., in...) Figure 1A (marked as "P") and the more heavily doped p-type base junction region 118 within the base region 114 (in Figure 1A The transistor Q1 is marked "P+" and is sometimes referred to as implantation region 118 or base contact 118, both of which can be formed by ion implantation. The transistor Q1 further comprises transistors having a second conductivity type (e.g., n-type, marked "N+" and...). Figure 1A The n-type emitter region (E1) is realized by a heavily doped region 116 containing majority carriers. The doped region 116 (sometimes referred to as implanted region 116, emitter region 116, or emitter junction region 116) can be formed by ion implantation and diffusion. In the illustrated example, a p-type base junction region 118 laterally surrounds the n-type emitter region 116 within a p-type base region 114. In one example, the n-type emitter region 116 has an n-type dopant concentration approximately the same as that of the n-type implanted region 112 of the collector C1, and in one example, implanted regions 112 and 116 extend to approximately the same depth along the third direction Z.
[0022] In this example, the second transistor Q2 is a parasitic PNP bipolar transistor Q2 in the isolation trench 103 of the semiconductor layer 106, having an n-type base B2 implemented by the n-type semiconductor layer 106 or the collector of transistor Q1. The second transistor Q2 has a p-type emitter E2 implemented by the p-type base B1 of the NPN bipolar transistor Q1 (including the base region 114 and the base contact region 118).
[0023] The second transistor Q2 also has a p-type collector C2, sometimes referred to as a second collector region. The p-type collector C2 is implemented through a p-type second collector region, which includes a p-type well region 120 having a majority carrier of the first type (e.g., in...). Figure 1A The p-type regions 120 and 122 are marked "P" and sometimes referred to as implantation region 120, and a more heavily doped shallow p-type implantation region 122 extending into the top surface of the epitaxial semiconductor layer 106 within the well region 120. In this example, the p-type regions 120 and 122 extend from the top side of a portion of the epitaxial semiconductor layer 106 in the isolation trench 103 and are laterally spaced from the p-type base B1 and the n-type collector C1 of the NPN bipolar transistor Q1 (containing the deep implantation region 110 and the collector contact 112). Figure 1A In the view along the first direction X). The epitaxial semiconductor layer 106 extends to the top surface between the p-type implantation region 120 and the base region 114 of the NPN transistor Q1.
[0024] In one example, the shallow n-type implantation region 122 has a higher p-type dopant concentration than the p-type dopant concentration in the implantation region 120, and in Figure 1A The p-type base region 114 and p-well 120 extend along the third direction Z in the epitaxial semiconductor layer 106 to approximately the same depth and have the same or similar p-type dopant concentration. In this or another example, more heavily doped (e.g., P+) p-type implantation regions 118 and 122 extend along the third direction Z in the epitaxial semiconductor layer 106 to approximately the same depth and have the same or similar p-type dopant concentration. In one example, p-type implantation region 124 provides an ohmic contact with the doped polysilicon 109 of the deep trench isolation structure 107, such as... Figure 1A As shown in the figure. The implantation region 124 may also be referred to as deep trench contact 124 or DT contact 124. In some instances, the doped polysilicon 119 is p-type and directly contacts the substrate 102, thereby providing a conductive path from the DT contact 124 and the substrate 102.
[0025] like Figure 1As further illustrated, the lateral sides of the p-type base region 114 and p-well 120 are laterally spaced apart from each other by a distance D1 along a first direction X. For example, this distance can be customized according to the breakdown voltage rating of a specific design for the NPN first emitter Q1. The second (PNP) transistor Q2 in this example is a parasitic transistor used to aid in the rapid reverse recovery of the NPN first transistor Q1. The inclusion of p-type regions 120, 122 facilitates the extraction of hole carriers from the n-type isolation trench 103 after reverse biasing of transistor Q1. One or more additional p-type implanted regions 120, 122 provide hole extraction paths to low-potential nodes, such as substrate 102, to facilitate rapid reverse recovery of transistor Q1. Specifically, additional p-type regions (e.g., a second collector region) 120, 122 can be connected to any low-potential node to facilitate enhanced reverse recovery.
[0026] In the illustrated example, electronic device 100 includes Figure 1A The metallization structure 130 shown is illustrated. The metallization structure 130 includes a first vertical metal interconnect 131 and a second vertical metal interconnect 132 (e.g., vias or contacts containing tungsten or other suitable conductive metals) in a metal front dielectric (PMD) layer 133, and metal trace features 134 in a first interlayer or interlayer dielectric (ILD) layer 135. Metal trace features 134 and other metal trace features may include aluminum or copper traces formed by any suitable process. In one example, the metallization structure 130 includes a third layer, such as a bonding pad, die pad, etc., with conductive metal terminals 136, which can provide terminal connections to interconnect the semiconductor die 101 and its transistor Q1, for example, by bonding wire connections or by soldering one or more terminals 136 to a substrate or lead frame (not shown) during the packaging of the electronic device 100. The contacts of the PMD layer (e.g., interconnects 131 and 132) extend downward along a third direction Z to provide electrical connection to a corresponding portion of the top side of the epitaxial semiconductor layer 106, and the connection may include conductive metal silicide (not shown).
[0027] In the illustrated example, a first metal interconnect 131 provides an electrical connection to a heavily doped p-type implanted region 122 (e.g., the second collector region C2 of a parasitic PNP bipolar second transistor Q2) within implanted region 120. The first metal interconnect 131 extends to and contacts a portion of a conductive metal trace feature 134 of a first ILD layer of the metallization structure 130. A second metal interconnect 132 of the PMD layer extends from another portion of the metal trace feature 134 down a third direction (Z) along a deep trench isolation structure 107 to a conductive doped polysilicon 109 (e.g., containing any heavily doped (e.g., P+) region 124 therein). This exemplary structure provides a conductive path from the p-type regions 120, 122 to facilitate hole extraction from the p-type regions through the metallization structures 131, 134, 132 and through the doped polysilicon 109 to the substrate 102. In another embodiment, the p-type regions 120, 122 may be electrically connected (e.g., through an associated feature of the metallization structure 130) to another low-potential node. The described instances and other implementation schemes (e.g., the following) Figure 20 and Figure 21 This provides a solution to slow down the reverse recovery operation of bipolar transistors in isolation trench 103 without forming Schottky diodes or other reverse recovery components, while realizing the space-saving benefits of deep trench-based bipolar transistor isolation.
[0028] The interconnection from the p-type region C2 (120, 122) to the low-potential node in electronic device 100 advantageously provides a low-impedance path to extract hole carriers from the n-type epitaxial silicon of the semiconductor layer 106 in isolation trench 103, thereby enhancing the surge current capacity of electronic device 100 to provide fast reverse recovery of NPN transistor Q1. In other embodiments (e.g., hereinafter) Figure 20 and Figure 21 The different structural relationships and arrangements of the NPN bipolar transistor Q1 and the additional second collector region C2 can be provided within an isolation trench 103 defined by an isolation structure (e.g., a deep trench isolation structure 107) to facilitate one or more low-impedance conductive paths or other conductive connections from the epitaxial semiconductor portion (e.g., n-type epitaxial silicon of the semiconductor layer 106 within the isolation trench 103) to the substrate 102 or other low-potential nodes (e.g., via the deep trench isolation structure 107 or other conductive connections) during the operation of the electronic device 100, so as to provide enhanced reverse recovery performance during the operation of the transistor Q1.
[0029] Also refer to Figure 1BIn one example, electronic device 100 is an integrated circuit having a semiconductor die 101 as described above, the semiconductor die being packaged with electrical connections formed between conductive terminals (e.g., terminal 136) and one or more conductive features of the start lead frame and / or package substrate (not shown). The package interconnects can be manufactured using any suitable structure and technique, including but not limited to wire bonding, flip-chip bonding of the terminals 136 of the semiconductor die 101, etc. Figure 1B An exemplary electronic device 100 has opposing bottom sides 141 and top sides 142 spaced apart from each other along a third direction Z, and laterally opposing third sides 143 and fourth sides 144, as well as laterally opposing ends 145 and 146. A semiconductor die 101 has one or more terminals electrically connected to corresponding conductive metal leads 147, such as conductive portions of a lead frame and / or a package substrate (not shown). In this example, the leads 147 and portions of the semiconductor die 101 are at least partially enclosed by a molded or ceramic package structure 148 defining sides 141 to 146. The leads 147 can be connected by suitable solder, soldered into a socket, or otherwise electrically connected to a host system (e.g., a printed circuit board or PCB, not shown).
[0030] Also refer to Figures 2 to 19 , Figure 2 A method 200 for manufacturing electronic devices is shown, and Figures 3 to 19 An exemplary electronic device 100 described above is shown, which undergoes a manufacturing process according to method 200. Method 200 begins at... Figure 2 At position 202, an epitaxial layer is formed on the substrate. Figure 3 An example is shown in which an epitaxial deposition (e.g., growth) process 300 is performed, which causes an epitaxial layer 104 to grow on the top side of a starting substrate 102 (e.g., during processing of multiple cell or die regions of a starting wafer containing substrate 102). In one example, the epitaxial deposition process 300 includes providing a process gas containing a p-type dopant (e.g., boron, etc.) to provide a p-type epitaxial layer 104 on substrate 102.
[0031] Method 200 in Figure 2 At position 204, the embedded layer 105 and the upper part of the p-type epitaxial layer 104 are implanted. Figure 4 An example is shown where an implantation process 400 is performed using an implantation mask 402. The implantation process 400 implants an n-type dopant (e.g., phosphorus, etc.) into an exposed portion on the top side of a p-type epitaxial semiconductor layer 104 to provide net n-type doping of a buried layer 105 portion of the epitaxial layer 104, wherein the buried layer 105 contains a second type (e.g., n-type) majority carrier.
[0032] Method 200 in Figure 2At position 206, an n-type epitaxial semiconductor layer 106 is formed on the p-type epitaxial layer 104. Figure 5 An example is shown in which an epitaxial deposition (e.g., growth) process 500 is performed, which deposits (e.g., grows) n-type doped epitaxial silicon to form an epitaxial semiconductor layer 106 on the top side of a p-type epitaxial semiconductor layer 104. In one example, the epitaxial deposition process 300 includes providing a process gas containing an n-type dopant (e.g., phosphorus, etc.) to provide an n-type doped first epitaxial silicon layer 106 on a p-doped second epitaxial silicon layer 104. In one example, the deposition process 500 causes a previously implanted lower shell and the n-type dopant (e.g., phosphorus) to diffuse slightly upward from the buried layer 105, and the dopant diffusion causes the buried layer 105 to extend into the lower portion of the deposited n-type epitaxial semiconductor layer 106, such as... Figure 5 As shown in the image.
[0033] Method 200 in Figure 2 The 208 places in the text continue to be implanted in conjunction with the above. Figure 1 and Figure 1A The described deep n-well 110. Figure 6 An example is shown where an implantation process 600 is performed via an implantation mask 602, which exposes a desired first collector portion of the top surface of an n-type epitaxial semiconductor layer 106 in a cell region of the processed wafer or a desired die region. Implantation process 600 implants an n-type dopant to form... Figure 6 The deep implantation region 110 shown in the figure contains, in one instance, an n-type dopant (e.g., phosphorus) with a dopant concentration higher than that of the n-type epitaxial semiconductor layer 106.
[0034] Method 200 in Figure 2 Continue at positions 210 to 216 to form the exemplary deep trench isolation structure 107 described above, thereby defining the above... Figure 1 and Figure 1A The lateral extent of the isolation groove 103. In another example, different isolation structures (e.g., interface implants, etc.) can be used to define the isolation groove area. The illustrated example uses... Figure 2 The trench etching begins at position 210. Figure 7 This example illustrates an etching process 700 performed using an etching mask 702 to etch trenches extending through a first (n-type) epitaxial semiconductor layer 106, a second (p-type) epitaxial semiconductor layer 104, and reaching a portion of the top side of the semiconductor substrate 102, as shown. Figure 7 As shown above. Figure 1 As illustrated, the illustrated example also includes a single trench that laterally surrounds the intended isolation trench 103 for each intended trench isolation NPN transistor Q1 in each cell or die region of the processed wafer.
[0035] exist Figure 2 At position 212, method 200 continues to form the groove lining. Figure 8 An example is shown where an oxidation process 800 is performed, which oxidizes the exposed trench sidewalls to form silicon dioxide, as the trench liner 108 extends along the trench sidewalls. Method 200 in Figure 2 Polysilicon deposition continues at position 214 to fill the trench. Figure 9 An example is shown in which a polysilicon deposition process 900 is performed to form a doped polysilicon 109 on a trench liner 108 in a trench, wherein the doped polysilicon 109 extends downward to form a conductive contact with an exposed portion of the substrate 102 at the bottom of the trench.
[0036] In one instance, method 200 is... Figure 2 At point 216, planarization continues to remove any excess polysilicon extending above the top side of the epitaxial semiconductor layer 106. Figure 10 An example is shown in which a chemical mechanical polishing (CMP) process 1000 is performed to planarize the top side of the epitaxial semiconductor layer 106. In one example, after trench isolation at 210 to 216, shallow trench isolation structures (not shown) may be formed, for example, between base region 114 and n-well 110 and between base region 114 and p-well 120.
[0037] Method 200 in Figure 2 218 sites were further implanted with p-type base region 114 and p-well 120 of the second collection region. Figure 11 An example is shown in which an implantation process 1100 is performed via an implantation mask 1102 to implant a p-type dopant (e.g., boron) into an exposed portion of the top side or top surface of an epitaxial semiconductor layer 106. In this example, the implantation process 1100 simultaneously forms a p-type base region 114 and a p-well 120, which in one example may extend along a third direction Z within the upper portion of the epitaxial semiconductor layer 106 to approximately the same depth and may have the same or similar p-type dopant concentration. In another embodiment, the base region 114 and the p-well 120 may be formed by a separate process.
[0038] Method 200 in Figure 2 At 220 locations, n-type source and drain electrodes are implanted (NSD implantation) to form the collector and emitter of the NPN transistor. Figure 12An example is shown in which an implantation process 1200 is performed using an implantation mask 1202 to implant an n-type dopant (e.g., phosphorus) into an exposed portion of the top surface of an epitaxial semiconductor layer 106. The implantation process 1200 in the illustrated example implants phosphorus or other n-type dopant simultaneously into the illustrated opening in the implantation mask 1202 to simultaneously form N+ implantation regions 112 and 116 for the collector C1 and emitter E1 of the respective NPN transistors. In this example, implantation regions 112 and 116 extend along a third direction Z to approximately the same depth and have the same or similar n-type dopant concentrations higher than those of implantation region 110. In another embodiment, implantation regions 112 and 116 can be formed by a separate process (not shown). In one embodiment, implantation process 1200 and mask 1202 can be used to simultaneously form n-type implanted source and drain regions (not shown) of one or more other transistors (e.g., field-effect transistors) in individual cell regions of a processed wafer.
[0039] Method 200 in Figure 2 At position 222, p-type source-drain implantation (PSD implantation) is continued to form the other part of the base B1 of the NPN transistor. Figure 13 An example is shown in which an implantation mask 1302 is used to perform an implantation process 1300 to implant boron or other p-type dopants to form a base contact region 118, a p-type region 122 of the second collector, and a deep trench contact 124. The illustrated example uses corresponding openings in the implantation mask 1302 to simultaneously form implantation regions 118, 122, and 124. In another embodiment, a separate implantation process can be used to individually form implantation regions 118, 122, and 124. In the illustrated example, implantation regions 118, 122, and 124 extend along a third direction Z to approximately the same depth, and implantation regions 118, 122, and 124 have approximately the same or similar concentrations of p-type dopants, wherein in one example, the dopant concentration of implantation regions 118, 122, and 124 is greater than the corresponding dopant concentration of the base region 114 and the p-well 120.
[0040] Method 200 in Figure 2 At 224 sites, further metallization is performed to form single or multilayer metallized structures. As previously combined... Figure 1A The described and illustrated examples include a multilayer metallized structure 130. Figure 14 An example is shown in which a multi-step metallization process 1400 is performed, forming a PMD layer and corresponding tungsten contacts 131 and 132, followed by the formation of an ILD layer and associated conductive metal features (e.g., traces) 134, and any final top-level device terminal conductive features. In the illustrated example, the metallization structure provides electrical connections between additional p-type regions 120, 122 in the deep trench isolation structure and conductive polysilicon 109, to the isolation trench 103 ( Figure 1AThe semiconductor layer 106 within the substrate 102 provides a conductive path between the n-type epitaxial silicon and the substrate 102.
[0041] Method 200 continues Figure 2 Die separation and packaging operations are performed at positions 226 to 234. Die separation is performed at position 226 to separate the individual processed semiconductor dies 101 from the processed substrate 102. Figure 15 and Figure 15 A illustrates an example where individual dies 101 of a wafer are separated along die separation process 1500. Figure 15 The lines 1502 shown are separated from each other. In one example, laser cutting is used, wherein a laser (not shown) translates along one side of the wafer (e.g., from the bottom or back side in one example) along the kerf between adjacent columns and rows of the die 101. Laser cutting creates cracks and fissures in the wafer, and the wafer is mounted on a carrier or tape structure. Then, through... Figure 16 The extended process 1600 shown in the figure radially stretches the strip to separate the individual processed semiconductor dies 101 from each other and from the starting wafer structure.
[0042] The separated semiconductor die 101 was then in Figure 2 Positions 228 to 234 are used as components in the packaging operation to create the packaged electronic device 100. In the illustrated example, the semiconductor die 101 is... Figure 2 At positions 228 and 230, flip-chips are attached (e.g., soldered) to the substrate. Figure 17 An example is shown in which a flip-chip die attachment process 1700 is performed, which attaches metal pillars of individual semiconductor dies 101 to corresponding top-side conductive metal features on an upper layer of a starting multilayer packaging substrate 170 in the form of a panel array having columns and rows of individual cell regions 1701 or dies. In one example, the die attachment process 1700 uses an automated pick-and-place device (not shown) to place the individual semiconductor dies 101 in the corresponding cell regions 1701 of the panel array.
[0043] Method 200 in Figure 2 At point 230, solder continues to be reflowed to form solder connections between die terminals and associated conductive features along the top side of the multilayer packaging substrate 170 in each unit region 1701 of the panel array structure. Figure 18 An example is shown in which a thermal reflow process 1800 is performed, in which solder is reflowed at a suitable temperature for a sufficient amount of time to establish solder joints that electrically and mechanically interconnect the semiconductor die 101 with the corresponding cell region 1701 of the multilayer package substrate 170.
[0044] exist Figure 2At position 232, method 200 continues the molding process, for example, to form a molded package structure 148 that encloses the semiconductor die 101 and extends to the exposed top side of the multilayer package substrate 170. In one embodiment, a single mold cavity can be used to form a monolithic molded structure 148 in all cell regions 1701 of the panel array structure prior to package separation. In another embodiment (not shown), multiple cavities can be used, each containing one or more of the cell regions 1701. Figure 2 At position 234, method 200 includes a package separation process to separate individual packaged electronic devices 100 from the panel array structure. Figure 19 An example is shown where a die separation process 1900 is performed, which separates individual packaged electronic devices along a line 1902 between adjacent cell regions 1701. In one example, the die separation process 1900 includes a dicing operation using any suitable technology and equipment (not shown), such as sawing, laser cutting, etching, etc., to produce the combination described above. Figures 1 to 1B Several examples of packaged electronic devices 100 described and illustrated.
[0045] Figure 20 A partial top view of another exemplary electronic device 2000 is shown, comprising a trench-isolated NPN transistor Q1 formed in an isolation trench 103 surrounded by a deep trench isolation structure 107 having various similarly numbered structures and features described above. In this example, the second collector region includes implanted p-type regions 2020 and 2222, similar to p-type regions 120 and 122, which generally extend in a second direction Y, for example, similar to p-type regions 120 and 122 along a first side of the isolation trench 103. A first additional p-type region 2031 extends from p-type regions 2020 and 2222 along a second side of the isolation trench 103 in a first direction X. A second additional p-type region 2032 extends from p-type regions 2020 and 2222 along a third side of the isolation trench 103 in a first direction X. In the illustrated example, p-type regions 2020 and 2022 are parallel to the top surface of the semiconductor layer 106. Figure 20 The base region 114 and the three sides of the base contact 118 shown extend to form a C-shaped structure, thereby enhancing the surface area available for hole extraction and reducing the impedance between the n-type epitaxial layer material 106 and the substrate within the isolation trench 103 to facilitate fast reverse bias recovery of the transistor Q1. In this case, the electronic device 100 also includes a corresponding contact, and the metallization feature 134 extends further within the substantially C-shaped structure for the reverse recovery transistor performance benefits described above.
[0046] Figure 21Another non-limiting example of electronic device 2100 is shown, comprising a trench-isolated NPN transistor Q1 formed in an isolation trench 103 surrounded by a deep trench isolation structure 107 having various similarly numbered structures and features described above. In this example, transistor Q1 has multiple examples of emitter regions 116, for example formed along a second direction Y in a stack of these regions, each containing an n-type dopant and extending from the top surface of semiconductor layer 106 into base region 114 and base contact 118. Furthermore, in this example, electronic device 2100 comprises a bilaterally symmetrical arrangement, wherein first and second examples of p-type regions 120 and 122 are spaced apart from each other along a first direction X in the isolation trench 103 of semiconductor layer 106. Additionally, electronic device 2100 in this example includes first and second examples of n-wells 110, which are spaced apart from each other along a second direction Y in the isolation trench 103 of semiconductor layer 106.
[0047] Also refer to Figures 22 to 23 Comparative performance graphs are provided to illustrate the benefits of improved reverse recovery performance achievable using the techniques and structures described above. These performance graphs are representative in nature and may have vertical and horizontal axes that are not plotted to the same scale. Figure 22 The graph 2200 is shown, where the first curve 2201 corresponds to the collector-emitter voltage of a baseline NPN transistor (e.g., similar to electronic device 100 without p-type regions 120 and 122), and the second curve 2202 corresponds to the input of a reference resistor connected to the base of the baseline NPN transistor, which switches from an initial level to approximately zero to disconnect the transistor. A reverse recovery time 2204 is generated between the falling edge of the control signal (curve 2202) and the time when the collector voltage (curve 2201) reaches the recovery threshold level.
[0048] Figure 23 Display curve 2300, where curve 2302 corresponds to... Figure 1 and Figure 1A The collector voltage of the exemplary device consistent with the NPN transistor Q1 described above in the isolation trench 103 shown is illustrated. Curve 2301 again represents the voltage at the input of the reference resistor connected to the base of transistor Q1. Taking into account the scaling difference of the horizontal axis, the resulting recovery time 2304 from the falling edge of curve 2302 to the recovery threshold of curve 2304 is approximately 60% of the recovery time 2204. The reduced recovery time indicates the following benefits: providing a second collector region including p-type regions 120 and 122 and a connection through the metallization structure 130 to the substrate 102 (or other low-potential nodes of the electronic device 100) to extract hole carriers from the isolation trench 103, thereby significantly reducing the reverse recovery time.
[0049] Modifications are possible in the described instances, and other instances are possible within the scope of the claims.
Claims
1. An electronic device comprising: A semiconductor layer located above a substrate has a top surface extending in a plane orthogonal to a first direction and a second direction and includes an isolation trench region extending from the top surface into the semiconductor layer. A base region having a first conductivity type, the base region extending from the top surface into the isolation trench region, and the semiconductor layer having the opposite second conductivity type; An emitter region having the second conductivity type, the emitter region extending from the top surface into the base region; A first collector region having the second conductivity type extends from the top surface into the isolation trench region and is spaced apart from the base region; as well as The second collector region has the first conductivity type, the second collector region extends from the top surface into the isolation trench region, and the second collector region is spaced apart from the base region and the first collector region.
2. The electronic device of claim 1, wherein the second collector region is electrically connected to the substrate.
3. The electronic device according to claim 1, further comprising: A deep trench isolation structure extends from the top surface through the semiconductor layer to the substrate below the deep trench isolation structure, the deep trench isolation structure laterally surrounding the isolation trench region of the semiconductor layer; as well as A metallized structure comprising a metal interconnect that electrically connects the second collector region to the substrate via the deep trench isolation structure.
4. The electronic device of claim 3, wherein the deep trench isolation structure comprises: a trench having a sidewall liner and doped polysilicon on the sidewall liner and extending from the top surface to the substrate.
5. The electronic device of claim 3, further comprising a buried layer having the second conductivity type, the buried layer being located between the semiconductor layer and the substrate and laterally delimited by the deep trench isolation structure.
6. The electronic device of claim 5, further comprising a second semiconductor layer having the first conductivity type and extending in a third direction between the semiconductor layer and the semiconductor substrate.
7. The electronic device of claim 1, further comprising a buried layer having the second conductivity type, the buried layer being between the semiconductor layer and the substrate and laterally delimited by an isolation structure surrounding the isolation trench region.
8. The electronic device of claim 1, wherein the second collector region extends along the top surface parallel to the two sides of the base region.
9. The electronic device of claim 8, wherein the second collector region extends along the top surface parallel to three sides of the base region.
10. The electronic device of claim 9, wherein the emitter region comprises a plurality of adjacent emitter regions having the second conductivity type and extending from the top surface into the base region.
11. The electronic device according to claim 1, comprising: A first example and a second example of the second collector regions spaced apart from each other along the first direction in the isolation trench region of the semiconductor layer; as well as First and second examples of the first collector regions spaced apart from each other along the second direction in the isolation trench region of the semiconductor layer.
12. The electronic device of claim 11, wherein the emitter region comprises a plurality of adjacent emitter region examples having the second conductivity type and extending from the top surface into the base region.
13. The electronic device according to claim 1, wherein the first conductivity type is p-type and the second conductivity type is n-type.
14. The electronic device of claim 1, wherein the emitter region comprises a plurality of adjacent emitter region examples having the second conductivity type and extending from the top surface into the base region.
15. An integrated circuit, comprising: An epitaxial layer, which is located above the semiconductor substrate; An isolation structure that surrounds the isolation trench region and includes a portion of the epitaxial layer; The base well has a first conductivity type and extends into the isolation trench region, and the epitaxial layer has the opposite second conductivity type; A transistor terminal having the second conductivity type and extending into the base well; A first well having the second conductivity type and extending into the isolation trench area and spaced apart from the base well; as well as The second well has the first conductivity type and extends into the isolation trench area and is spaced apart from the base well. in: The transistor terminal, the base well, the isolation trench region, and the first well form a first bipolar transistor having a first polarity type, and The base well, the isolation trench region, and the second well form a second bipolar transistor having a second polarity type.
16. A method of manufacturing an electronic device, the method comprising: A base region having a first conductivity type is formed in an isolation trench region of the semiconductor layer above a substrate supporting the semiconductor layer, and the semiconductor layer has a second conductivity type; An emitter region having the second conductivity type is formed in the base region; A first collector region having the second conductivity type and spaced apart from the base region is formed in the isolation trench region; as well as A second collector region having the first conductivity type and spaced apart from the base region and the first collector region is formed in the isolation trench region.
17. The method of claim 16, further comprising forming an isolation structure that laterally surrounds the isolation trench region and contacts the substrate.
18. The method of claim 16, further comprising forming a metallization structure that conductively connects the second collector region to the substrate by means of a deep trench isolation structure.
19. The method of claim 18, further comprising forming a buried layer having the second conductivity type between the semiconductor layer and the substrate.
20. The method of claim 16, wherein the second collector region extends along the top surface of the semiconductor layer parallel to the two sides of the base region.