System for testing defects of semiconductor devices and method for analyzing defects of semiconductor devices
By using a waveform generator and a semiconductor analyzer in a semiconductor device defect testing system, combined with impedance matching resistors and chokes, the problem of traditional testing methods being unable to detect small currents at the femtoampere level has been solved, achieving high-precision current detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-04-14
- Publication Date
- 2026-06-12
AI Technical Summary
With the miniaturization of semiconductor devices, traditional low-frequency testing methods are struggling to detect small currents at the femtoampere level.
The test system, which uses a waveform generator and a semiconductor analyzer, connects the semiconductor device under test through gate probes, source probes, drain probes and substrate probes. The ground terminals share a common ground terminal. Combined with impedance matching resistors and chokes, noise is suppressed to achieve high-precision current detection.
It improves the accuracy and stability of semiconductor analyzers in detecting source and drain currents and substrate currents, enabling precise detection of small currents at the femtoampere level.
Smart Images
Figure CN122193857A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of semiconductor testing, and more particularly to a testing system for semiconductor device defects and a method for analyzing semiconductor device defects. Background Technology
[0002] Charge pumping (CP) technology is a semiconductor device defect detection technique based on impedance-matched pulsed voltage driving the accumulation or release of charge carriers at the gate dielectric-semiconductor interface. Its core principle is to quantify the density and characteristics of interface defects by measuring the dynamic changes in substrate current when a periodic pulse is applied to the gate. When the gate pulse switches, minority and majority carriers in the interface traps recombine, generating a net substrate current whose direction is opposite to the reverse leakage current of the source / drain diode to the substrate. The amplitude of this current is proportional to the pulse frequency. During testing, the source / drain is grounded, an impedance-matched pulse is applied to the gate, and the substrate current signal is captured by an electrometer or high-precision current probe. The device state is then adjusted by combining parameters such as pulse amplitude and DC bias. This method is used in process monitoring to evaluate the interface quality between the gate dielectric and the device channel (e.g., interface state density analysis of HKMG devices), in reliability testing to monitor defect growth after accelerated aging, and by calculating the interface trap density. Its advantages lie in its non-destructive nature, high sensitivity, and dynamic charge transport resolution capabilities.
[0003] However, as device size shrinks, the charge pump current of the device becomes extremely small, making it difficult for traditional, unoptimized low-frequency testing methods to detect small currents at the femtoampere level. Summary of the Invention
[0004] This invention provides a testing system and analysis method for semiconductor device defects to solve the above-mentioned technical problems, so as to accurately detect the small current of a femtoampere charge pump.
[0005] According to a first aspect of the present invention, a testing system for defects in semiconductor devices is provided, comprising: A waveform generator, the output of which is connected to the gate of the semiconductor device under test via a gate probe, and the ground terminal of which is connected to a common ground terminal; A semiconductor analyzer, wherein the first input terminal of the semiconductor analyzer is connected to the source of the semiconductor device under test via a source probe, and the first input terminal is also connected to the drain of the semiconductor device under test via a drain probe; the second input terminal of the semiconductor analyzer is connected to the substrate of the semiconductor device under test via a substrate probe; and the ground terminal of the semiconductor analyzer is connected to the common ground terminal.
[0006] Optionally, it may also include an impedance matching resistor, one end of which is connected to the gate probe and the other end of which is connected to the common ground.
[0007] Optionally, the resistance value of the impedance matching resistor is equal to the output impedance of the waveform generator, and the frequency of the impedance matching resistor is between 18Hz and 40GHz.
[0008] Optionally, it may also include a choke coil, said choke coil on any one or more of the first, second, third and fourth conductors; The first wire is used to connect the output terminal of the waveform generator and the gate probe; the second wire is used to connect the first input terminal of the semiconductor analyzer and the source probe; the third wire is used to connect the first input terminal of the semiconductor analyzer and the drain probe; and the fourth wire is used to connect the second input terminal of the semiconductor analyzer and the substrate probe.
[0009] Optionally, the waveform generator may include at least the M8194A or AWG5200.
[0010] Optionally, the semiconductor analyzer may include at least the B1500A or 4200A-SCS model.
[0011] According to a second aspect of the present invention, a method for analyzing defects in a semiconductor device is provided, the method comprising: Connect the grounding terminals of both the waveform generator and the semiconductor analyzer to the common ground terminal. After connecting the ground terminals of both the waveform generator and the semiconductor analyzer to a common ground terminal, the waveform generator outputs a gate pulse of a preset frequency, which is transmitted to the gate of the semiconductor device under test through a gate probe. After the waveform generator outputs a gate pulse, the semiconductor analyzer detects the source and drain currents of the semiconductor device under test through source and drain probes. The semiconductor analyzer also detects the substrate current of the semiconductor device under test through a substrate probe. The interface defect density of the semiconductor device under test is obtained based on the source / drain current and the substrate current.
[0012] Optionally, before connecting the ground terminals of the waveform generator and the semiconductor analyzer to a common ground terminal, the method further includes welding an impedance matching resistor between the gate probe and the common ground terminal.
[0013] Optionally, the method by which the semiconductor analyzer detects the source-drain current and the substrate current includes: capacitance integration current detection.
[0014] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the semiconductor device defect testing system provided by the technical solution of the present invention, the output terminal of the waveform generator is connected to the gate of the semiconductor device under test through a gate probe, the first input terminal of the semiconductor analyzer is connected to the source of the semiconductor device under test through a source probe, the first input terminal is also connected to the drain of the semiconductor device under test through a drain probe, and the second input terminal of the semiconductor analyzer is connected to the substrate of the semiconductor device under test through a substrate probe, thereby constituting a semiconductor device defect testing system.
[0015] Since the grounding terminals of the waveform generator and the semiconductor analyzer are both connected to a common ground, noise introduced by connecting the waveform generator and the semiconductor analyzer to different ground terminals is avoided, thereby improving the accuracy of the semiconductor analyzer in detecting source leakage current and substrate current.
[0016] Furthermore, it also includes an impedance matching resistor, one end of which is connected to the gate probe and the other end of which is connected to the common ground terminal. Impedance matching is performed by the impedance matching resistor and the output impedance of the waveform generator, thereby greatly suppressing the reflection of the pulse applied to the gate and making the pulse effectively loaded on the gate.
[0017] Furthermore, it also includes a choke coil, which is connected to one or more of the first, second, third, and fourth wires. The first wire is used to connect the output terminal of the waveform generator and the gate probe; the second wire is used to connect the first input terminal of the semiconductor analyzer and the source probe; the third wire is used to connect the first input terminal of the semiconductor analyzer and the drain probe; and the fourth wire is used to connect the second input terminal of the semiconductor analyzer and the substrate probe. The choke coil effectively suppresses high-frequency noise on one or more of the first, second, third, and fourth wires, thereby further improving the accuracy of the semiconductor analyzer in detecting source / drain current and substrate current.
[0018] Furthermore, the method by which the semiconductor analyzer detects the source-drain current and the substrate current includes capacitance integration current detection, thereby improving the stability of the semiconductor analyzer in detecting the source-drain current and the substrate current. Attached Figure Description
[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0020] Figure 1 A schematic diagram of the system structure of a semiconductor device defect testing system provided in the first embodiment of the present invention; Figure 2 A three-dimensional perspective view of the impedance matching resistor provided for the first embodiment of the present invention; Figure 3 A flowchart of a semiconductor device defect analysis method provided in the second embodiment of the present invention.
[0021] 10-gate; 11-Source; 12-Drain; 13-Substrate; 20-Waveform generator; 21-Semiconductor Analyzer; GND - Common Ground; q1 - Gate probe; q2 - Source probe; q3 - Drain probe; q4 - Substrate probe; R1 - Impedance matching resistor; T1 - Choke. Detailed Implementation
[0022] As described in the background section, with the miniaturization of device dimensions, the charge pump current of semiconductor devices has become extremely small, making it difficult for traditional, unoptimized low-frequency testing schemes to detect small currents at the femtoampere level.
[0023] In view of this, the technical solution of the present invention provides a novel testing system for semiconductor device defects, including a waveform generator and a semiconductor analyzer. The output terminal of the waveform generator is connected to the gate of the semiconductor device under test via a gate probe. The first input terminal of the semiconductor analyzer is connected to the source of the semiconductor device under test via a source probe, and the first input terminal is also connected to the drain of the semiconductor device under test via a drain probe. The second input terminal of the semiconductor analyzer is connected to the substrate of the semiconductor device under test via a substrate probe. Since the ground terminals of the waveform generator and the semiconductor analyzer are both connected to a common ground terminal, noise introduced by the waveform generator and the semiconductor analyzer due to different ground terminals is avoided, thereby improving the accuracy of the semiconductor analyzer in detecting source-drain current and substrate current, and enabling the semiconductor analyzer to detect femtoampere-level small currents.
[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0025] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0026] The technical solution of the present invention will be described in detail below through specific embodiments. The embodiments described below can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.
[0027] [First Embodiment] This embodiment provides a testing system for defects in semiconductor devices, including a waveform generator 20 and a semiconductor analyzer 21.
[0028] Please refer to Figure 1The output terminal of the waveform generator 20 is connected to the gate 10 of the semiconductor device under test via the gate probe q1. The ground terminal of the waveform generator 20 is connected to the common ground GND.
[0029] The waveform generator 20 outputs a gate pulse of a preset frequency to the gate 10 of the semiconductor device under test through the gate probe q1.
[0030] It should be noted that any waveform generator 20 capable of outputting pulse signals is within the protection scope of this embodiment and is not limited thereto.
[0031] Furthermore, the waveform generator may include the M8194A or AWG5200.
[0032] Please continue to refer to this. Figure 1 The first input terminal of the semiconductor analyzer 21 is connected to the source 11 of the semiconductor device under test via the source probe q2. The first input terminal of the semiconductor analyzer 21 is also connected to the drain 12 of the semiconductor device under test via the drain probe q3. The second input terminal of the semiconductor analyzer 21 is connected to the substrate 13 of the semiconductor device under test via the substrate probe q4. The ground terminal of the semiconductor analyzer 21 is connected to the common ground terminal GND.
[0033] The semiconductor analyzer 21 detects the source and drain currents of the semiconductor device under test using source probe q2 and drain probe q3. The analyzer 21 also detects the substrate current of the semiconductor device under test using substrate probe q4. Both the substrate current and the source and drain currents are charge pump currents, and they are equal in magnitude and opposite in direction.
[0034] Furthermore, the model of the semiconductor analyzer may include B1500A or 4200A-SCS.
[0035] In this embodiment, the method by which the semiconductor analyzer 21 detects source-drain current and substrate current may include capacitor integration current detection, thereby improving the stability of the semiconductor analyzer 21 in detecting source-drain current and substrate current.
[0036] It should be noted that any semiconductor analyzer 21 with capacitance integration current detection function is within the protection scope of this embodiment and is not limited here.
[0037] Since this embodiment connects the ground terminal of the waveform generator 20 and the ground terminal of the semiconductor analyzer 21 to the same common ground terminal GND, it avoids the introduction of noise by connecting the waveform generator 20 and the semiconductor analyzer 21 to different ground terminals, thereby improving the accuracy of the semiconductor analyzer 21 in detecting source leakage current and substrate current.
[0038] Please refer to Figure 1 and Figure 2 In this embodiment, the test system further includes an impedance matching resistor R1. One end of the impedance matching resistor R1 is connected to the gate probe q1, and the second end of the impedance matching resistor R1 is connected to the common ground GND. Impedance matching is performed through the impedance matching resistor R1 and the gate probe q1, thereby avoiding reflection loss of the gate pulse output by the waveform generator 20 due to excessive frequency. That is, in high-frequency applications, the gate pulse is transmitted to the gate 10 of the semiconductor device under test with almost no loss.
[0039] Furthermore, since the impedance matching resistor is used for impedance matching with the output impedance of the waveform generator, the specific resistance value of the impedance matching resistor can include 5Ω, 10Ω, 20Ω, 50Ω, and 100Ω. It can be understood that as long as the resistance value of the impedance matching resistor is equal to the output impedance of the waveform generator, the resistance value of the impedance matching resistor is within the protection range of this embodiment and is not limited here. The frequency of the impedance matching resistor is between 18Hz and 40GHz.
[0040] The test system also includes a choke T1, which is disposed on any one or more of the first, second, third, and fourth conductors.
[0041] Please continue to refer to this. Figure 1 In this embodiment, four chokes T1 are provided, and the four chokes T1 are respectively provided on the first wire, the second wire, the third wire and the fourth wire.
[0042] Specifically, the first wire is used to connect the output terminal of the waveform generator 20 and the gate probe q1; the second wire is used to connect the first input terminal of the semiconductor analyzer 21 and the source probe q2; the third wire is used to connect the first input terminal of the semiconductor analyzer 21 and the drain probe q3; and the fourth wire is used to connect the second input terminal of the semiconductor analyzer 21 and the substrate probe q4.
[0043] By effectively suppressing high-frequency noise on the four wires through the choke T1 set on the four wires, the accuracy of the semiconductor analyzer 21 in detecting source leakage current and substrate current is further improved.
[0044] Please refer to Figure 1 and Figure 3 This embodiment also provides a method for analyzing defects in semiconductor devices, which includes the following specific steps: Step S1: Connect the ground terminals of both the waveform generator 20 and the semiconductor analyzer 21 to the common ground terminal GND.
[0045] Step S2: The waveform generator 20 outputs a gate pulse of a preset frequency and transmits it to the gate 10 of the semiconductor device under test through the gate probe q1.
[0046] Step S3: The semiconductor analyzer 21 detects the source and drain currents of the semiconductor device under test through the source probe q2 and the drain probe q3. The semiconductor analyzer 21 also detects the substrate current of the semiconductor device under test through the substrate probe q4.
[0047] Step S4: Obtain the interface defect density of the semiconductor device under test based on the source / drain current and the substrate current.
[0048] In this embodiment, the relationship between the charge pump current and the frequency of the gate pulse can be expressed by the following formula: I cp =f*A G *q*N it ; Among them, I cp is the charge pump current, which is equal to the absolute value of the source / drain current or the substrate current; f is the frequency of the gate pulse; A G is the gate area of the semiconductor device under test; q is the charge of a single electron; N it This represents the interface defect density of the semiconductor device under test.
[0049] Since the gate area, gate pulse frequency, and single electron charge of the semiconductor device under test are all known, the interface defect density of the semiconductor device under test can be obtained after detecting the source / drain current and the substrate current.
[0050] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A testing system for defects in semiconductor devices, characterized in that, include: A waveform generator, the output of which is connected to the gate of the semiconductor device under test via a gate probe, and the ground terminal of which is connected to a common ground terminal; A semiconductor analyzer, wherein the first input terminal of the semiconductor analyzer is connected to the source of the semiconductor device under test via a source probe, and the first input terminal is also connected to the drain of the semiconductor device under test via a drain probe; the second input terminal of the semiconductor analyzer is connected to the substrate of the semiconductor device under test via a substrate probe; and the ground terminal of the semiconductor analyzer is connected to the common ground terminal.
2. The semiconductor device defect testing system according to claim 1, characterized in that, It also includes an impedance matching resistor, one end of which is connected to the gate probe and the other end of which is connected to the common ground.
3. The semiconductor device defect testing system according to claim 2, characterized in that, The resistance value of the impedance matching resistor is equal to the output impedance of the waveform generator, and the frequency of the impedance matching resistor is between 18Hz and 40GHz.
4. The semiconductor device defect testing system according to claim 1, characterized in that, It also includes a choke coil, which is disposed on any one or more of the first conductor, the second conductor, the third conductor, and the fourth conductor; The first wire is used to connect the output terminal of the waveform generator and the gate probe; The second wire is used to connect the first input terminal of the semiconductor analyzer and the source probe; The third wire is used to connect the first input terminal of the semiconductor analyzer and the drain probe; The fourth wire is used to connect the second input terminal of the semiconductor analyzer and the substrate probe.
5. The semiconductor device defect testing system according to claim 1, characterized in that, The waveform generator model includes at least M8194A or AWG5200.
6. The semiconductor device defect testing system according to claim 1, characterized in that, The semiconductor analyzer model includes at least B1500A or 4200A-SCS.
7. A method for analyzing defects in semiconductor devices, characterized in that, Based on the semiconductor device defect testing system according to any one of claims 1 to 6, the method includes: Connect the grounding terminals of both the waveform generator and the semiconductor analyzer to the common ground terminal. After connecting the ground terminals of both the waveform generator and the semiconductor analyzer to a common ground terminal, the waveform generator outputs a gate pulse of a preset frequency, which is transmitted to the gate of the semiconductor device under test through a gate probe. After the waveform generator outputs a gate pulse, the semiconductor analyzer detects the source and drain currents of the semiconductor device under test through source and drain probes. The semiconductor analyzer also detects the substrate current of the semiconductor device under test through a substrate probe. The interface defect density of the semiconductor device under test is obtained based on the source / drain current and the substrate current.
8. The method for analyzing defects in semiconductor devices according to claim 7, characterized in that, Before connecting the ground terminals of the waveform generator and the semiconductor analyzer to the common ground terminal, the method further includes welding an impedance matching resistor between the gate probe and the common ground terminal.
9. The method for analyzing defects in semiconductor devices according to claim 7, characterized in that, The method for detecting the source / drain current and the substrate current using the semiconductor analyzer includes: capacitance integration current detection.