Wafer level chip, chip system, electronic device and communication method

Abstract

The application discloses a wafer-level chip, a chip system, an electronic device and a communication method, and relates to the technical field of integrated circuits. The wafer-level chip comprises a reconfigurable computing wafer, a cache storage wafer and an interconnection communication wafer which are stacked in sequence, and adjacent wafers are directly bonded wafer-to-wafer; the interconnection communication wafer comprises a photonic logic circuit, the cache storage wafer comprises an optical communication cache unit, and the optical communication cache unit is bonded with the photonic logic circuit; the optical communication cache unit caches data packets to be sent written by the reconfigurable computing wafer; the photonic logic circuit reads the data packets to be sent from the optical communication cache unit and converts the data packets to optical signals and sends out the optical signals; and / or the photonic logic circuit receives optical signals and converts the optical signals to electrical signals and writes the electrical signals into the optical communication cache unit; the optical communication cache unit caches the electrical signals and informs the reconfigurable computing wafer to read the electrical signals.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a wafer-level chip, chip system, electronic device, and communication method. Background Technology

[0002] Currently, AI (Artificial Intelligence) chips face bottlenecks related to "memory walls" and "power consumption walls." While 3D stacking (such as HBM (High Bandwidth Memory)) shortens the distance between memory cells and computing cells, off-chip communication still relies on electrical interconnects, which are limited in bandwidth and consume a lot of power. Although silicon photonic interconnects have the advantages of high bandwidth and low power consumption, existing solutions are mostly used for inter-chip or board-level interconnects, without deep collaboration with on-chip cache storage at the wafer level.

[0003] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0004] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a wafer-level chip, a chip system, an electronic device, and a communication method.

[0005] This application proposes a wafer-level chip, comprising reconfigurable computing wafers, cache storage wafers, and interconnect communication wafers stacked sequentially, with adjacent wafers directly bonded to each other; the interconnect communication wafers include photonic logic circuitry, and the cache storage wafers include optical communication cache units, which are bonded to the photonic logic circuitry; wherein... The optical communication buffer unit is configured to buffer the data packets to be transmitted written to the reconfigurable computing wafer; the photonic logic circuit is configured to read the data packets to be transmitted buffered in the optical communication buffer unit and convert the data packets to be transmitted into optical signals for transmission; and / or, The photonic logic circuit is configured to receive an optical signal and convert the received optical signal into an electrical signal and write it into the optical communication buffer unit; the optical communication buffer unit is configured to buffer the electrical signal written by the photonic logic circuit and notify the reconfigurable computing wafer to read the electrical signal.

[0006] In some embodiments, the photonic logic circuit includes an optical modulator, the optical communication buffer unit includes a first buffer unit, and the optical modulator and the first buffer unit are bonded together; The first cache unit is configured to cache the data packets to be transmitted written by the reconfigurable computing wafer; the optical modulator is configured to read the data packets to be transmitted cached in the first cache unit and convert the data packets to be transmitted into optical signals for transmission.

[0007] In some embodiments, the photonic logic circuit includes a photodetector, the optical communication buffer unit includes a second buffer unit, and the photodetector and the second buffer unit are bonded together; The photodetector is configured to receive an optical signal and convert the received optical signal into an electrical signal and write it into the second cache unit; the second cache unit is configured to cache the electrical signal written by the photodetector and notify the reconfigurable computing wafer to read the electrical signal.

[0008] In some embodiments, the optical communication cache unit is disposed on the top metal layer of the cache storage wafer, and the optical communication cache unit is located in a region perpendicular to the photonic logic circuit.

[0009] In some embodiments, the wafer-level chip is connected to an external chip via an electrical signaling line, and flow control signaling information is transmitted between the wafer-level chip and the external chip via the electrical signaling line.

[0010] In some embodiments, the interconnect communication wafer integrates a first credit counter, the initial value of which is equal to the depth of the storage space in the optical communication buffer unit used for receiving data packets; For each data packet received from the external chip, the count value of the first credit counter is decremented by 1. For each data packet successfully processed by the wafer-level chip, the count value of the first credit counter is incremented by 1, and a credit increment signal is sent to the external chip via the electrical signaling line.

[0011] In some embodiments, the reconfigurable computing wafer integrates a second credit counter, the initial value of which is equal to the depth of the storage space in the external chip used for receiving data packets, and the count value of the second credit counter is decremented by 1 for each data packet sent by the reconfigurable computing wafer. When the count value of the second credit counter is greater than 0 and a credit increase signal is received from the external chip, the reconfigurable computing wafer sends a data packet. When the count value of the second credit counter is 0, the reconfigurable computing wafer pauses sending data packets.

[0012] In some embodiments, the cache storage wafer includes an SRAM (Static Random Access Memory) wafer and / or a DRAM (Dynamic Random Access Memory) wafer.

[0013] In some embodiments, the cache storage wafer includes SRAM wafers and DRAM wafers; wherein, The SRAM wafers are stacked on the reconfigurable computing wafer; The DRAM wafers are stacked on the SRAM wafers; The interconnect communication wafers are stacked on the DRAM wafers.

[0014] In some embodiments, the DRAM wafers include a plurality of wafers stacked together, and adjacent DRAM wafers are vertically interconnected through through-silicon vias.

[0015] In some embodiments, the reconfigurable computing wafer includes an array of reconfigurable computing units interconnected via an on-chip network; The cache storage wafer includes a storage array, which includes multiple storage blocks. Each storage block is directly connected to a corresponding reconfigurable computing unit in the reconfigurable computing wafer via a vertical interconnect formed by hybrid bonding.

[0016] In some embodiments, the interconnect communication wafer further includes a DMA controller, and the photonic logic circuit includes an optical modulator, a photodetector, a grating coupler array, and a waveguide network; The DMA controller is configured to: package the cached data from the optical communication buffer unit and send it to the optical modulator, so that the optical modulator converts the packaged data into an optical signal; the waveguide network is configured to transmit the optical signal to the output of the grating coupler array; and / or The grating coupler array is configured to receive optical signals, and the waveguide network is configured to transmit the optical signals to the photodetector, such that the photodetector converts the optical signals into electrical signals and writes the electrical signals into the optical communication buffer unit.

[0017] In some embodiments, adjacent wafers are directly bonded to each other using a hybrid bonding technique; The optical communication buffer unit and the photonic logic circuit are bonded together using a hybrid bonding technique.

[0018] This application also provides a chip system comprising at least two wafer-level chips as described in any of the above embodiments, wherein the wafer-level chips achieve all-optical communication through edge optical interconnect.

[0019] This application also provides an electronic device, including at least one wafer-level chip as described in any of the above embodiments, or including a chip system as described in any of the above embodiments.

[0020] This application also provides a communication method applied to the wafer-level chip described in any of the above embodiments, the method comprising: The optical communication buffer unit buffers the data packets to be transmitted written to the reconfigurable computing wafer; the photonic logic circuit reads the data packets to be transmitted buffered in the optical communication buffer unit and converts the data packets to be transmitted into optical signals for transmission; and / or, The photonic logic circuit receives an optical signal and converts the received optical signal into an electrical signal, which is then written into the optical communication buffer unit. The optical communication buffer unit buffers the electrical signal written by the photonic logic circuit and notifies the reconfigurable computing wafer to read the electrical signal.

[0021] In some embodiments, the wafer-level chip is connected to an external chip via an electrical signaling line, and the interconnect communication wafer integrates a first credit counter, the initial value of which is equal to the depth of the storage space in the optical communication buffer unit used for receiving data packets; the method further includes: For each data packet received from the external chip, the count value of the first credit counter is decremented by 1. Each time the wafer-level chip successfully processes a data packet, the count value of the first credit counter is incremented by 1, and a credit increment signal is sent to the external chip via the electrical signaling line.

[0022] In some embodiments, the wafer-level chip is connected to an external chip via an electrical signaling line. The reconfigurable computing wafer integrates a second credit counter. The initial value of the second credit counter is equal to the depth of the storage space in the external chip used for receiving data packets. The count value of the second credit counter is decremented by 1 for each data packet sent by the reconfigurable computing wafer. When the count value of the second credit counter is greater than 0 and a credit increase signal is received from the external chip, the reconfigurable computing wafer sends a data packet. When the count value of the second credit counter is 0, the reconfigurable computing wafer pauses sending data packets.

[0023] This application also provides a wafer-level chip manufacturing method, including: Provides reconfigurable computing wafers; A cache storage wafer is stacked on top of the reconfigurable computing wafer, and the cache storage wafer and the reconfigurable computing wafer are bonded together using a bonding technology, wherein the cache storage wafer includes an optical communication cache unit; An interconnect communication wafer is stacked on top of the cache storage wafer, and the interconnect communication wafer and the cache storage wafer are bonded together using bonding technology. The photonic logic circuit integrated in the interconnect communication wafer is also bonded to the optical communication cache unit.

[0024] The wafer-level chip, chip system, electronic device, and communication method proposed in this application include a wafer-level chip comprising a reconfigurable computing wafer, a cache storage wafer, and an interconnect communication wafer stacked sequentially, with adjacent wafers directly bonded to each other. The interconnect communication wafer includes photonic logic circuitry, and the cache storage wafer includes an optical communication cache unit bonded to the photonic logic circuitry. The optical communication cache unit is configured to cache data packets to be transmitted written by the reconfigurable computing wafer. The photonic logic circuitry is configured to read the data packets to be transmitted cached in the optical communication cache unit and convert the data packets into optical signals for transmission. Alternatively, the photonic logic circuitry is configured to receive optical signals and convert the received optical signals into electrical signals, which are then written to the optical communication cache unit. The optical communication cache unit is configured to cache the electrical signals written by the photonic logic circuitry and notify the reconfigurable computing wafer to read the electrical signals. In this way, by setting up an optical communication buffer unit, optical-electric local caching is realized, significantly reducing communication latency and overcoming the problems of long data transport paths, high latency, high energy consumption, and occupation of valuable on-chip storage bandwidth in existing optical interconnect solutions. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of a wafer-level chip provided in an embodiment of this application.

[0026] Figure 2 This is a schematic diagram of the structure of a reconfigurable computing wafer provided in an embodiment of this application.

[0027] Figure 3 This is a schematic diagram of the structure of a wafer-level chip provided in an embodiment of this application.

[0028] Figure 4This is a schematic flowchart of a wafer-level chip manufacturing method provided in an embodiment of this application.

[0029] Figure 5 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0030] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0031] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0032] To better understand this application, the research background of this application will be explained in detail below.

[0033] Existing silicon photonic interconnect solutions are typically used as standalone modules or only for inter-chip communication, without direct integration with cache memory units at the wafer level. Data must traverse multiple storage levels before transmission (e.g., from the computing unit via SRAM main array, or even DRAM, to the optical interface), and the reverse process is required after reception. This results in high end-to-end communication latency, high power consumption during invalid data transport, and the occupation of valuable on-chip memory bandwidth. In other words, existing optical interconnect solutions lack deep integration with on-chip memory, leading to high communication latency and low energy efficiency.

[0034] To address the aforementioned technical problems, embodiments of this application provide a wafer-level chip, a chip system, an electronic device, and a communication method, which can solve at least one of the aforementioned problems existing in the prior art.

[0035] Figure 1 This is a schematic diagram of the structure of a wafer-level chip provided in an embodiment of this application, as shown below. Figure 1As shown, this application embodiment provides a wafer-level chip 100, including a reconfigurable computing wafer 1, a cache storage wafer 2, and an interconnect communication wafer 3 stacked sequentially, with adjacent wafers directly bonded to each other; the interconnect communication wafer 3 includes photonic logic circuitry, and the cache storage wafer 2 includes an optical communication cache unit, which is bonded to the photonic logic circuitry; wherein, The optical communication buffer unit is configured to buffer the data packets to be transmitted written by the reconfigurable computing wafer 1; the photonic logic circuit is configured to read the data packets to be transmitted buffered in the optical communication buffer unit and convert the data packets to be transmitted into optical signals for transmission; and / or, The photonic logic circuit is configured to receive an optical signal and convert the received optical signal into an electrical signal and write it into the optical communication buffer unit; the optical communication buffer unit is configured to buffer the electrical signal written by the photonic logic circuit and notify the reconfigurable computing wafer 1 to read the electrical signal.

[0036] The wafer-level chip 100 provided in this embodiment involves stacking wafers together, with adjacent wafers directly bonded to form a high-density vertical interconnect. The interconnect communication wafer 3 enables optical signal input / output at the wafer edge. Data collaborative processing is achieved between each wafer layer through a preset communication protocol. By establishing a dedicated high-speed buffer channel—an optical communication buffer unit directly connected to the photonic logic circuit—between the cache storage wafer 2 and the interconnect communication wafer 3, tight optical-electrical coupling is achieved, eliminating intermediate handling steps. Specifically: When sending data outward: The reconfigurable computing wafer 1 (specifically through the DMA (Direct Memory Access) controller) writes the data packet to be sent to the optical communication buffer unit at the specified address → the optical communication buffer unit sets the "ready" flag → triggers the photonic logic circuit to read the buffered data and convert it into an optical signal for transmission; When receiving external data: the photonic logic circuit converts the received optical signal into an electrical signal → directly writes it into the optical communication buffer unit → sets the interrupt flag to notify the reconfigurable computing wafer 1 to read the data.

[0037] As can be seen, by forming a local buffer pool with "tight optical-electrical coupling", congestion of the main cache storage unit array due to communication traffic can be avoided. This is a wafer-level deep integration feature that existing optical interconnect solutions do not possess, overcoming the problems of long data transport paths, high latency, high power consumption, and occupation of valuable on-chip storage bandwidth in existing optical interconnect solutions.

[0038] In some embodiments, the photonic logic circuit includes an optical modulator, the optical communication buffer unit includes a first buffer unit, and the optical modulator and the first buffer unit are bonded together; the first buffer unit is configured to buffer data packets to be transmitted written by the reconfigurable computing wafer 1; the optical modulator is configured to read the data packets to be transmitted buffered in the first buffer unit and convert the data packets to be transmitted into optical signals for transmission.

[0039] In some embodiments, the photonic logic circuit includes a photodetector, the optical communication cache unit includes a second cache unit, and the photodetector and the second cache unit are bonded together; the photodetector is configured to receive an optical signal and convert the received optical signal into an electrical signal and write it into the second cache unit; the second cache unit is configured to cache the electrical signal written by the photodetector and notify the reconfigurable computing wafer 1 to read the electrical signal.

[0040] In some embodiments, the photonic logic circuit includes the optical modulator and the photodetector, and correspondingly, the optical communication buffer unit includes the first buffer unit and the second buffer unit.

[0041] In some embodiments, the optical communication cache unit is disposed on the top metal layer of the cache storage wafer 2, and the optical communication cache unit is located in a region perpendicular to the photonic logic circuit.

[0042] Specifically, when the photonic logic circuit includes an optical modulator and the optical communication buffer unit includes a first buffer unit, the first buffer unit is located in a region perpendicular to the optical modulator. When the photonic logic circuit includes a photodetector and the optical communication buffer unit includes a second buffer unit, the second buffer unit is located in a region perpendicular to the photodetector.

[0043] like Figure 1 As shown, for example, the cache storage wafer 2 includes an SRAM wafer. On the top metal layer of the SRAM wafer, a separate SRAM sub-block is specifically designated for each area perpendicular to the optical modulator and photodetector, serving as an "optical communication cache unit." The capacity of the SRAM sub-block can be 64 to 512 bytes, composed of high-speed static memory cells. During the design phase of the interconnect communication wafer 3, the metal pads of the optical modulator input port and photodetector output port at its bottom are precisely positioned to match the optical communication cache unit pads on the SRAM wafer below.

[0044] During wafer stacking, Cu-Cu hybrid bonding technology can be used to directly and exclusively connect the electrical signal ports of the optical modulator / photodetector to the optical communication cache unit directly below it, bypassing the global data bus of the SRAM master array.

[0045] In some embodiments, the wafer-level chip 100 is connected to an external chip via an electrical signaling line, and flow control signaling information is transmitted between the wafer-level chip 100 and the external chip via the electrical signaling line.

[0046] Specifically, existing high-speed optical interconnect solutions between chips lack reliable flow control mechanisms, making it difficult to guarantee communication stability. Once an optical signal is transmitted, it cannot be canceled or retransmitted midway. When the buffer of the receiving chip is full, newly arriving optical data packets will be directly lost, failing to meet the deterministic, zero-packet-loss communication requirements of artificial intelligence / high-performance computing applications.

[0047] This application proposes that a portion of the low-speed electrical interconnects reserved in the hybrid bonding (e.g., one dedicated signaling line shared by every 8 to 16 optical channels) can be used to construct an independent electrical signaling channel between chips for transmitting flow control information, thereby realizing a reliable transmission mechanism of "authorization first, emission later" and ensuring the reliability of the high-speed optical link.

[0048] In some embodiments, the interconnect communication wafer 3 integrates a first credit counter, the initial value of which is equal to the depth of the storage space in the optical communication buffer unit used for receiving data packets ('depth' refers to the maximum number of data packets that the storage space used for receiving data packets can store); the interconnect communication wafer 3 decrements the value of the first credit counter by 1 for each data packet received from the external chip; the wafer-level chip 100 increments the value of the first credit counter by 1 for each data packet successfully processed, and sends a credit increment signal to the external chip through the electrical signaling line.

[0049] Specifically, when acting as a receiver, the interconnect communication wafer 3 of the wafer-level chip 100 maintains a credit counter. The initial value of this credit counter is equal to the depth of the storage space in the optical communication buffer unit used for receiving data packets (e.g., 8 packets). Each time a data packet is successfully received and processed, the credit counter is incremented by 1, and a credit increment signal (e.g., a "Credit+" pulse) is sent to the chip acting as the transmitter via an electrical signaling line. The credit counting and signaling generation at the receiver can be implemented by a small CMOS state machine circuit integrated within the interconnect communication wafer 3.

[0050] In some embodiments, the reconfigurable computing wafer 1 integrates a second credit counter. The initial value of the second credit counter is equal to the depth of the storage space in the external chip used for receiving data packets. The reconfigurable computing wafer 1 decrements the count value of the second credit counter by 1 for each data packet it sends. When the count value of the second credit counter is greater than 0 and a credit increment signal is received from the external chip, the reconfigurable computing wafer sends a data packet. When the count value of the second credit counter is 0, the reconfigurable computing wafer 1 pauses sending data packets.

[0051] Specifically, when acting as a transmitter, the reconfigurable computing wafer 1 maintains a credit counter. The initial value of this credit counter is equal to the depth of the storage space in the external chip acting as a receiver for receiving data packets. Each time the reconfigurable computing wafer 1 transmits a data packet, the credit counter value is decremented by 1. When the credit counter value is greater than 0 and a credit increment signal is received from the external chip, the reconfigurable computing wafer transmits the data packet. That is, the actual transmission of the optical data packet is triggered by the transmitter's local credit status and the received "Credit+" signal. When the count value is 0, transmission is paused. The credit management of the transmitter can be controlled by the DMA engine firmware or a dedicated hardware module in the reconfigurable computing wafer 1.

[0052] It is evident that by working together, the transmitting and receiving chips can achieve reliable optical communication with zero packet loss through credit counting and transmission flow control signaling, with extremely low signaling overhead (<1% of total bandwidth). This enables the introduction of an electronic flow control mechanism into the wafer-level optical interconnect system, solving the reliability problem of high-speed optical links and ensuring stable communication under high load.

[0053] The aforementioned dedicated opto-electric buffer structure and reliable optical interconnect protocol work in deep synergy, which greatly reduces the memory access distance and communication distance between chips, significantly improves computing energy efficiency, and realizes high bandwidth, low latency and high energy efficiency system integration.

[0054] In some embodiments, the cache memory wafer 2 includes SRAM wafers and / or DRAM wafers. Specifically, the cache memory wafer 2 may include only SRAM wafers, only DRAM wafers, or both SRAM and DRAM wafers. This application embodiment does not limit the composition of the cache memory wafer 2, nor does it limit the number of SRAM / DRAM wafers included in the cache memory wafer 2. When the cache memory wafer 2 includes multiple wafer layers, the wafer layers are stacked together.

[0055] like Figure 1As shown, in some embodiments, the cache storage wafer 2 includes an SRAM wafer and a DRAM wafer; wherein the SRAM wafer is stacked on the reconfigurable computing wafer 1; the DRAM wafer is stacked on the SRAM wafer; and the interconnect communication wafer 3 is stacked on the DRAM wafer.

[0056] like Figure 1 As shown, in the above embodiments, the DRAM wafers may include multiple DRAM wafers, which are stacked together, and adjacent DRAM wafers are vertically interconnected through through-silicon vias.

[0057] Specifically, a 3D stacked DRAM process can be used, stacking 1 to 4 DRAM wafers according to capacity requirements, and vertical interconnection between the DRAM wafers is achieved through TSVs (Through Silicon Vias). The capacity of a single DRAM wafer can be 16 to 32 GB. The DRAM wafer can integrate a cache controller to achieve efficient data exchange with the SRAM wafer; the DRAM wafer can adopt a wide I / O interface with a bandwidth >1TB / s.

[0058] like Figure 2 As shown, in some embodiments, the reconfigurable computing wafer 1 includes an array of reconfigurable computing units interconnected via an on-chip network.

[0059] Specifically, such as Figure 2 As shown, the reconfigurable computing wafer 1 contains an array of reconfigurable computing units. Each reconfigurable computing unit can support a dataflow architecture, integrate dedicated control logic and configuration memory, and is laid out in a grid structure. The computing units are interconnected through a network on-chip (NoC).

[0060] In some embodiments, the cache storage wafer 2 (e.g., an SRAM wafer) includes a storage array comprising a plurality of storage blocks, each of which is directly connected to a corresponding reconfigurable computing unit in the reconfigurable computing wafer 1 via a vertical interconnect formed by hybrid bonding.

[0061] Specifically, taking an SRAM wafer as an example, the structure of cache storage wafer 2 is described in detail: It employs a separately manufactured, monolithic SRAM wafer (embedded SRAM on a non-computing wafer), with an area perfectly matching that of reconfigurable computing wafer 1. The SRAM wafer's memory array is divided into memory tiles corresponding one-to-one with the underlying reconfigurable computing units. Each tile is directly connected to its corresponding computing unit via a submicron pitch vertical interconnect (<1μm pitch) formed by hybrid bonding. The capacity of a single SRAM wafer can range from 4 to 8 GB. The SRAM wafer can integrate a local data prefetch engine and compression and decompression units, dynamically adjusting data transfer strategies according to computing tasks to reduce unnecessary data transfers.

[0062] In this way, by decoupling SRAM from the logic process, better storage processes (such as dedicated processes for high-density 6T SRAM) can be used to improve energy efficiency and capacity density, while avoiding the limitation of SRAM area imposed by the logic process.

[0063] In some embodiments, the interconnect communication wafer further includes a DMA controller, and the photonic logic circuit includes an optical modulator, a photodetector, a grating coupler array, and a waveguide network; The DMA controller is configured to: package the cached data from the optical communication buffer unit and send it to the optical modulator, so that the optical modulator converts the packaged data into an optical signal; the waveguide network is configured to transmit the optical signal to the output of the grating coupler array; and / or The grating coupler array is configured to receive optical signals, and the waveguide network is configured to transmit the optical signals to the photodetector, such that the photodetector converts the optical signals into electrical signals and writes the electrical signals into the optical communication buffer unit.

[0064] Specifically, when sending data outward, the interconnect communication wafer 3 receives the aggregated data stream from the cache storage wafer 2 (DRAM wafer or SRAM wafer), which is then packaged by a dedicated DMA controller and sent to the optical modulator of the photonic logic circuit. The optical modulator converts the packaged data stream into an optical signal, which is then transmitted to the output of the grating coupler array through the waveguide network. When receiving external data, the received optical signal is converted by the photodetector of the photonic logic circuit and then directly written into the optical communication buffer unit, forming a hybrid communication paradigm of "optical input and output + electrical buffer", which significantly reduces end-to-end latency.

[0065] In some embodiments, the interconnect communication wafer 3 can be independently manufactured using a CMOS-compatible silicon photonics platform (such as an SOI wafer), and includes: a high-density grating coupler array located at the edge of the interconnect communication wafer 3 for interfacing with external optical fibers; a low-loss waveguide network covering the entire surface of the interconnect communication wafer 3, supporting optical routing between any two points; a high-speed micro-ring modulator or MZI modulator supporting a 100Gbps / channel rate, with integrated driving circuitry to achieve electro-optical conversion; and a wavelength division multiplexing (WDM) unit that allows multiple wavelengths to be transmitted on the same waveguide, improving single-link bandwidth.

[0066] like Figure 3 As shown, in some embodiments, adjacent wafers in the wafer-level chip 100 are directly bonded to each other using hybrid bonding technology; the optical communication cache unit and the photonic logic circuit are bonded together using hybrid bonding technology.

[0067] Specifically, hybrid bonding includes: metal-to-metal (e.g., Cu) direct bonding to form signal and power interconnects; and dielectric-to-dielectric bonding to provide insulation. Wafer-to-wafer interconnect density reaches 10,000 connections / mm² with a spacing of <1μm; signal interconnects can employ differential structures to improve anti-interference capabilities; and power / ground networks can utilize three-dimensional mesh structures to reduce IR drop.

[0068] For systems containing multiple wafer-level chips, all-optical communication is achieved between chips within the same system via edge optical interconnects. Inter-system communication: Connecting to other computing systems via external optical fibers to form larger-scale computing networks.

[0069] In some embodiments, the wafer-level chip can be applied to edge AI inference scenarios, such as for AI inference accelerators. The reconfigurable computing wafer can achieve 28,000 TOPS of INT8 computing power. The SRAM wafer layer stores model weights and activation values, while the DRAM wafer layer stores raw input data and intermediate results. Optical interconnects enable multi-chip collaborative inference, expanding computing power. In the ResNet-50 inference task, the energy efficiency ratio reaches 15 TOPS / W, which is 8 times higher than traditional GPU solutions.

[0070] In some embodiments, the wafer-level chip can be applied to high-performance computing scenarios: the reconfigurable computing wafer is configured as a double-precision floating-point computing array; the SRAM wafer layer implements high-speed caching to reduce DRAM access; multiple chips form a 256-node computing cluster through optical interconnection; in fluid dynamics simulation, the single-chip performance reaches 14000 TFLOPS, and the cluster communication bandwidth is >100TB / s.

[0071] Based on the same inventive concept, this application also provides a chip system, which includes at least two wafer-level chips as described in any of the above embodiments, and the wafer-level chips achieve all-optical communication through edge optical interconnect.

[0072] The chip system provided in this application embodiment includes the wafer-level chip, and therefore can achieve the same technical effects as the wafer-level chip, which will not be described in detail here.

[0073] Based on the same inventive concept, this application also provides an electronic device, which includes at least one wafer-level chip as described in any of the above embodiments, or includes a chip system as described in any of the above embodiments.

[0074] The electronic device provided in this application embodiment includes the wafer-level chip, and therefore can achieve the same technical effect as the wafer-level chip, which will not be described in detail here.

[0075] Based on the same inventive concept, embodiments of this application also provide a communication method applied to the wafer-level chip described in any of the above embodiments. The communication method provided in this application includes: The optical communication buffer unit buffers the data packets to be transmitted written to the reconfigurable computing wafer; the photonic logic circuit reads the data packets to be transmitted buffered in the optical communication buffer unit and converts the data packets to be transmitted into optical signals for transmission; and / or, The photonic logic circuit receives an optical signal and converts the received optical signal into an electrical signal, which is then written into the optical communication buffer unit. The optical communication buffer unit buffers the electrical signal written by the photonic logic circuit and notifies the reconfigurable computing wafer to read the electrical signal.

[0076] The communication method embodiments provided in this application are specifically the wafer-level chip communication methods in the above wafer-level chip embodiments. The specific implementation methods will not be repeated here, but can be referred to the detailed description of the above wafer-level chip embodiments.

[0077] In some embodiments, the wafer-level chip is connected to an external chip via an electrical signaling line, and the interconnect communication wafer integrates a first credit counter, the initial value of which is equal to the depth of the storage space in the optical communication buffer unit used for receiving data packets; the method further includes: For each data packet received from the external chip, the count value of the first credit counter is decremented by 1. Each time the wafer-level chip successfully processes a data packet, the count value of the first credit counter is incremented by 1, and a credit increment signal is sent to the external chip via the electrical signaling line.

[0078] In some embodiments, the wafer-level chip is connected to an external chip via an electrical signaling line. The reconfigurable computing wafer integrates a second credit counter. The initial value of the second credit counter is equal to the depth of the storage space in the external chip used for receiving data packets. The count value of the second credit counter is decremented by 1 for each data packet sent by the reconfigurable computing wafer. When the count value of the second credit counter is greater than 0 and a credit increase signal is received from the external chip, the reconfigurable computing wafer sends a data packet. When the count value of the second credit counter is 0, the reconfigurable computing wafer pauses sending data packets.

[0079] Based on the same inventive concept, this application also provides a wafer-level chip manufacturing method.

[0080] Figure 4This is a schematic flowchart of a wafer-level chip manufacturing method provided in an embodiment of this application. Figure 4 As shown in the embodiment of this application, a wafer-level chip manufacturing method includes: S1. Provides reconfigurable computing wafers; S2. Stack the cache storage wafer on top of the reconfigurable computing wafer, and bond the cache storage wafer to the reconfigurable computing wafer using bonding technology, wherein the cache storage wafer includes an optical communication cache unit; S3. Stack the interconnect communication wafer on top of the cache storage wafer, and use bonding technology to bond the interconnect communication wafer and the cache storage wafer together, and bond the photonic logic circuit integrated in the interconnect communication wafer to the optical communication cache unit.

[0081] Specifically, each wafer is manufactured independently: reconfigurable computing wafers, cache memory wafers (SRAM wafers and / or DRAM wafers), and interconnect communication wafers are manufactured on different process lines. Each wafer has reserved bonding areas and TSV openings.

[0082] Then, wafer-level testing and screening are performed: each wafer is fully tested using a probe card; defective areas are marked to generate a wafer-level mapping map; and good wafers are screened for stacking based on the mapping map.

[0083] Finally, wafer stacking and bonding are performed: cache storage wafers are bonded to reconfigurable computing wafers sequentially (e.g., SRAM wafers are bonded to reconfigurable computing wafers first, then DRAM wafers are bonded to SRAM wafers), and then interconnect communication wafers are bonded to cache storage wafers. Intermediate tests are performed after each bonding to verify interconnect integrity.

[0084] Figure 5 This is a block diagram of an electronic device provided in an embodiment of this application. For example, the electronic device 200 may be an AI server, an artificial intelligence server cluster, a training and promotion integrated machine, etc.

[0085] Reference Figure 5 The electronic device 200 may include one or more of the following components: an AI-accelerated computing module, a CPU module, a power supply module, a hard drive module, and a fan module. Each module works in conjunction with the bus system through a standardized hardware interface, with the specific architecture as follows: The AI-accelerated computing module comprises multiple AI accelerator cards deployed in parallel. Each AI accelerator card integrates at least one AI accelerator chip (or AI accelerator unit, such as an RPU chip, GPU chip, or CGRA chip). The AI ​​accelerator cards communicate with each other via a high-speed card-to-card (C2C) interconnect structure, supporting low-latency, high-bandwidth horizontal scaling. The AI ​​accelerator chip is dedicated to performing AI computing tasks such as high-density matrix operations, neural network model training, and / or inference, providing the main computing power support.

[0086] The CPU module includes at least one CPU board, which houses a central processing unit (CPU) chip and associated CPU memory (such as DDR4 / DDR5, RAM). The CPU chip serves as the system control center, responsible for task scheduling, resource allocation, I / O management, and coordinating the parallel computing of the AI ​​acceleration computing module, while also handling non-accelerated general-purpose computing tasks.

[0087] The power module is equipped with redundant power supply units to provide stable power distribution and management for the AI ​​acceleration computing module, CPU module and other modules.

[0088] The hard drive module integrates a high-speed solid-state drive (SSD) and / or a large-capacity hard disk drive (HDD), connected to the system bus via a backplane. The hard drive stores the operating system, AI training datasets, model parameters, and computation results, providing high-throughput data read / write channels and supporting data preprocessing and persistence.

[0089] The fan module uses a multi-zone independent speed-controlled fan array, which is configured in key heat source areas (such as AI accelerator cards and CPU heat dissipation areas) to achieve system heat dissipation through forced air cooling and ensure the stable operation of high-efficiency computing components.

[0090] The CPU module is connected to the AI ​​acceleration computing module via the PCIe bus to enable task distribution, result collection, and memory coordination.

[0091] The CPU module manages the data access of the hard drive module through SATA / SAS / NVMe interfaces.

[0092] The power module provides tiered power to all functional modules through the power distribution backplane.

[0093] The fan module adjusts the fan speed based on temperature monitoring signals from the CPU board and AI accelerator card.

[0094] This embodiment of the application provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer can perform the methods provided in the above-described method embodiments.

[0095] This embodiment provides a computer-readable storage medium storing a computer program that causes the computer to perform the methods provided in the above-described method embodiments.

[0096] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0097] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0098] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0099] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A wafer-level chip, characterized in that, The system comprises reconfigurable computing wafers, cache storage wafers, and interconnect communication wafers stacked sequentially, with adjacent wafers directly bonded to each other. The interconnect communication wafers include photonic logic circuitry, and the cache storage wafers include optical communication cache units, which are bonded to the photonic logic circuitry. The optical communication buffer unit is configured to buffer the data packets to be transmitted written to the reconfigurable computing wafer; the photonic logic circuit is configured to read the data packets to be transmitted buffered in the optical communication buffer unit and convert the data packets to be transmitted into optical signals for transmission; and / or, The photonic logic circuit is configured to receive an optical signal and convert the received optical signal into an electrical signal and write it into the optical communication buffer unit; the optical communication buffer unit is configured to buffer the electrical signal written by the photonic logic circuit and notify the reconfigurable computing wafer to read the electrical signal.

2. The wafer-level chip according to claim 1, characterized in that, The photonic logic circuit includes an optical modulator, and the optical communication buffer unit includes a first buffer unit, wherein the optical modulator and the first buffer unit are bonded together. The first cache unit is configured to cache the data packets to be sent written by the reconfigurable computing wafer; The optical modulator is configured to read the data packet to be transmitted cached in the first buffer unit and convert the data packet to be transmitted into an optical signal for transmission.

3. The wafer-level chip according to claim 1, characterized in that, The photonic logic circuit includes a photodetector, and the optical communication buffer unit includes a second buffer unit, wherein the photodetector and the second buffer unit are bonded together; The photodetector is configured to receive an optical signal and convert the received optical signal into an electrical signal and write it into the second cache unit; the second cache unit is configured to cache the electrical signal written by the photodetector and notify the reconfigurable computing wafer to read the electrical signal.

4. The wafer-level chip according to any one of claims 1 to 3, characterized in that, The optical communication cache unit is disposed on the top metal layer of the cache storage wafer, and the optical communication cache unit is located in a region perpendicular to the photonic logic circuit.

5. The wafer-level chip according to claim 1, characterized in that, The wafer-level chip is connected to an external chip via an electrical signaling line, and flow control signaling information is transmitted between the wafer-level chip and the external chip via the electrical signaling line.

6. The wafer-level chip according to claim 5, characterized in that, The interconnect communication wafer integrates a first credit counter, the initial value of which is equal to the depth of the storage space in the optical communication buffer unit used for receiving data packets. For each data packet received from the external chip, the count value of the first credit counter is decremented by 1. For each data packet successfully processed by the wafer-level chip, the count value of the first credit counter is incremented by 1, and a credit increment signal is sent to the external chip via the electrical signaling line.

7. The wafer-level chip according to claim 5, characterized in that, The reconfigurable computing wafer integrates a second credit counter. The initial value of the second credit counter is equal to the depth of the storage space in the external chip used to receive data packets. The count value of the second credit counter is decremented by 1 for each data packet sent by the reconfigurable computing wafer. When the count value of the second credit counter is greater than 0 and a credit increase signal is received from the external chip, the reconfigurable computing wafer sends a data packet. When the count value of the second credit counter is 0, the reconfigurable computing wafer pauses sending data packets.

8. The wafer-level chip according to claim 1, characterized in that, The cache storage wafer includes SRAM wafers and / or DRAM wafers.

9. The wafer-level chip according to claim 8, characterized in that, The cache storage wafer includes SRAM wafers and DRAM wafers; wherein... The SRAM wafers are stacked on the reconfigurable computing wafer; The DRAM wafers are stacked on the SRAM wafers; The interconnect communication wafers are stacked on the DRAM wafers.

10. The wafer-level chip according to claim 9, characterized in that, The DRAM wafers include multiple wafers, which are stacked together, and adjacent DRAM wafers are vertically interconnected through through-silicon vias.

11. The wafer-level chip according to claim 1, characterized in that, The reconfigurable computing wafer includes an array of reconfigurable computing units, which are interconnected via an on-chip network. The cache storage wafer includes a storage array, which includes multiple storage blocks. Each storage block is directly connected to a corresponding reconfigurable computing unit in the reconfigurable computing wafer via a vertical interconnect formed by hybrid bonding.

12. The wafer-level chip according to claim 1, characterized in that, The interconnect communication wafer also includes a DMA controller, and the photonic logic circuit includes an optical modulator, a photodetector, a grating coupler array, and a waveguide network; The DMA controller is configured to: package the cached data from the optical communication cache unit and send it to the optical modulator, so that the optical modulator converts the packaged data into an optical signal; the waveguide network is configured to transmit the optical signal to the output of the grating coupler array; and / or The grating coupler array is configured to receive optical signals, and the waveguide network is configured to transmit the optical signals to the photodetector, such that the photodetector converts the optical signals into electrical signals and writes the electrical signals into the optical communication buffer unit.

13. The wafer-level chip according to claim 1, characterized in that, Adjacent wafers are directly bonded to each other using a hybrid bonding technique; The optical communication buffer unit and the photonic logic circuit are bonded together using a hybrid bonding technique.

14. A chip system, characterized in that, It includes at least two wafer-level chips as described in any one of claims 1 to 13, wherein the wafer-level chips achieve all-optical communication through edge optical interconnect.

15. An electronic device, characterized in that, It includes at least one wafer-level chip as described in any one of claims 1 to 13, or it includes the chip system as described in claim 14.

16. A communication method, characterized in that, Applied to the wafer-level chip according to any one of claims 1 to 13, the method comprises: The optical communication buffer unit buffers the data packets to be transmitted written to the reconfigurable computing wafer; the photonic logic circuit reads the data packets to be transmitted buffered in the optical communication buffer unit and converts the data packets to be transmitted into optical signals for transmission; and / or, The photonic logic circuit receives an optical signal and converts the received optical signal into an electrical signal, which is then written into the optical communication buffer unit. The optical communication buffer unit buffers the electrical signal written by the photonic logic circuit and notifies the reconfigurable computing wafer to read the electrical signal.

17. The communication method according to claim 16, characterized in that, The wafer-level chip is connected to an external chip via an electrical signaling line. The interconnect communication wafer integrates a first credit counter, the initial value of which is equal to the depth of the storage space in the optical communication buffer unit used for receiving data packets. The method further includes: For each data packet received from the external chip, the count value of the first credit counter is decremented by 1. Each time the wafer-level chip successfully processes a data packet, the count value of the first credit counter is incremented by 1, and a credit increment signal is sent to the external chip via the electrical signaling line.

18. The communication method according to claim 16, characterized in that, The wafer-level chip is connected to an external chip via an electrical signaling line. The reconfigurable computing wafer integrates a second credit counter. The initial value of the second credit counter is equal to the depth of the storage space in the external chip used to receive data packets. The count value of the second credit counter is decremented by 1 for each data packet sent by the reconfigurable computing wafer. When the count value of the second credit counter is greater than 0 and a credit increase signal is received from the external chip, the reconfigurable computing wafer sends a data packet. When the count value of the second credit counter is 0, the reconfigurable computing wafer pauses sending data packets.

19. A wafer-level chip manufacturing method, characterized in that, include: Provides reconfigurable computing wafers; A cache storage wafer is stacked on top of the reconfigurable computing wafer, and the cache storage wafer and the reconfigurable computing wafer are bonded together using a bonding technology, wherein the cache storage wafer includes an optical communication cache unit; An interconnect communication wafer is stacked on top of the cache storage wafer, and the interconnect communication wafer and the cache storage wafer are bonded together using bonding technology. The photonic logic circuit integrated in the interconnect communication wafer is also bonded to the optical communication cache unit.

Images