Dynamic reconfigurable vector units, vector processors, chips and electronic devices

Abstract

The application discloses a dynamic reconfigurable vector unit, a vector processor, a chip and an electronic device, and relates to the technical field of reconfigurable computing circuits.The dynamic reconfigurable vector unit comprises a vector register file circuit, a physical total bit length of which is PLEN; a plurality of vector processing channel circuits, which are coupled with the vector register file circuit; a cross-channel switching network circuit, which is connected with the plurality of vector processing channel circuits; and a control logic circuit, which is used for performing the following operations: according to a received configuration value of a block length BLEN, dynamically dividing the plurality of vector processing channel circuits into one or more vector calculation blocks, a bit length of each vector calculation block being equal to BLEN, and a number of vector calculation blocks being equal to PLEN / BLEN; and according to the BLEN value and a calculation instruction, configuring a switching topology of the cross-channel switching network circuit.

Description

Technical Field

[0001] This application relates to the field of reconfigurable computing circuit technology, specifically to a dynamically reconfigurable vector unit, vector processor, chip, and electronic device. Background Technology

[0002] With the development of computer technology, vector processors have been widely used in scientific computing, artificial intelligence, image processing, and other fields due to their high efficiency in parallel computing. In vector processors, vector length (VLEN) is a key parameter that determines the amount of data a single vector instruction can process.

[0003] In the RISC-V Vector instruction set architecture, VLEN is defined as a fixed parameter in the hardware implementation; once the chip design is complete and manufactured, this parameter cannot be changed. Software can only obtain the VLEN value by reading the vlen register, but cannot modify it. This fixed design approach limits the flexibility and adaptability of vector processors in different application scenarios.

[0004] This section is intended to provide background or context for the embodiments of this application set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0005] In order to solve at least one of the above-mentioned problems in the prior art, embodiments of this application provide a dynamically reconfigurable vector unit, a vector processor, a chip, and an electronic device.

[0006] This application proposes a dynamically reconfigurable vector unit, including: The vector register file circuit has a physical total bit length of PLEN and is used to store vector data. Multiple vector processing channel circuits, each of which is coupled to the vector register file circuit, are used to perform vector operations on the vector data in the vector register file circuit and write back the results; A cross-channel switching network circuit, connecting the plurality of vector processing channel circuits, is used to exchange data between the plurality of vector processing channel circuits; A control logic circuit, coupled to the plurality of vector processing channel circuits and the cross-channel switching network circuit, is used to perform the following operations: Based on the configured value of the block length BLEN, the plurality of vector processing channel circuits are dynamically divided into one or more vector computation blocks. The bit length of each vector computation block is equal to the BLEN, and the number of vector computation blocks is equal to PLEN / BLEN, wherein the BLEN is less than or equal to the PLEN, and PLEN / BLEN is an integer; and Configure the switching topology of the cross-channel switching network circuit based on the BLEN value and calculation instructions.

[0007] In some embodiments, when BLEN is equal to PLEN, the control logic circuit divides all vector processing channel circuits into a single vector calculation block.

[0008] In some embodiments, when BLEN is smaller than PLEN, the control logic circuit divides the plurality of vector processing channel circuits into PLEN / BLEN vector calculation blocks, wherein the number of vector processing channel circuits contained in each vector calculation block is equal to BLEN divided by the bit width of each vector processing channel circuit.

[0009] In some embodiments, it also includes: The memory access unit circuit, coupled to the vector register file circuit, is used to perform the loading and storage operations of vector data between the vector register file circuit and the external memory; The memory access unit circuit supports the parallel execution of multiple vector memory access instructions to adapt to the division of the vector computation block.

[0010] In some embodiments, the control logic circuit further configures the read / write mode of the vector register file circuit according to the BLEN value, so that the vector register file circuit supports read / write at the granularity of processing channel circuits by a single vector, or supports read / write at the granularity of combining vector calculation blocks.

[0011] In some embodiments, the cross-channel switching network circuit includes multiple switching nodes, and the control logic circuit configures the switching topology by enabling or disabling at least some of the switching nodes based on the BLEN value and calculation instructions.

[0012] In some embodiments, the cross-channel switching network circuit further includes computing nodes connected to the switching node; when the number of computing nodes connected to a switching node exceeds two, the switching node divides the connected computing nodes into two groups of equal number and simultaneously exchanges data between the two groups of computing nodes.

[0013] In some embodiments, the system further includes: an instruction dispatch interface circuit for receiving vector instructions from an external instruction dispatch unit; the control logic circuit further configures the instruction dispatch interface circuit's instruction distribution method according to the BLEN value. When BLEN equals PLEN, the same vector instruction is distributed to all vector processing channel circuits. When BLEN is less than PLEN, it supports distributing different vector instructions to different vector computation blocks.

[0014] This application also proposes a dynamic configuration method for vector units, applied to the dynamically reconfigurable vector units described in any of the above embodiments. The method includes the following steps: The configuration value for the receive block length BLEN; Based on the BLEN value, the plurality of vector processing channel circuits are dynamically divided into one or more vector computation blocks, the bit length of each vector computation block is equal to the BLEN value, and the number of vector computation blocks is equal to PLEN / BLEN; and, based on the BLEN value and computation instructions, the switching topology of the cross-channel switching network circuit is configured.

[0015] This application also proposes a vector processor, including at least one dynamically reconfigurable vector unit as described in any of the above embodiments.

[0016] In some embodiments, it also includes: A vector calculation block length configuration register, coupled to the control logic circuit, is used to store the dynamically configurable block length BLEN; The vector physical bit length register, coupled to the control logic circuit, is used to store the physical bit length PLEN of the vector register file circuit in the dynamically reconfigurable vector unit.

[0017] This application also proposes a chip including at least one vector processor as described in any of the above embodiments.

[0018] This application also proposes an electronic device including the chip described in any of the above embodiments.

[0019] The dynamically reconfigurable vector unit, vector processor, chip, and electronic device proposed in this application first receive the configuration value of the block length BLEN through a control logic circuit. The control logic circuit then divides multiple vector processing channel circuits into several vector computation blocks based on the BLEN value, and configures a cross-channel switching network circuit based on the partitioning result and computation instructions. A vector register file circuit loads vector data from memory. Multiple vector processing channel circuits perform vector operations, exchanging data through the cross-channel switching network circuit when necessary. Finally, the computation result is written back to the vector register file circuit or memory. This dynamically reconfigurable design allows the vector unit to adapt to the needs of different application scenarios, improving the flexibility and efficiency of vector computation. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic diagram of the structure of a dynamically reconfigurable vector unit provided in an embodiment of this application.

[0021] Figure 2 This is a schematic diagram of a method for dividing a vector computation block according to an embodiment of this application.

[0022] Figure 3 This is a schematic diagram of the structure of a dynamically reconfigurable vector unit provided in an embodiment of this application.

[0023] Figure 4 This is a schematic diagram of the structure of a dynamically reconfigurable vector unit provided in an embodiment of this application.

[0024] Figure 5 This demonstrates the vector instruction dispatch methods under different vector computation block partitioning schemes.

[0025] Figure 6 This is a schematic diagram of a Cross Lane structure provided in an embodiment of this application.

[0026] Figure 7 This is a flowchart illustrating a dynamic configuration method for vector units provided in an embodiment of this application.

[0027] Figure 8 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0028] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0029] The term "coupled (or connected)" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. The terms "first," "second," etc., used throughout this specification (including the claims) are used to name components and are not intended to limit the upper or lower limit of the number of components, nor to limit the order of components. Furthermore, wherever possible, components / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same reference numerals or the same terms in different embodiments may be referred to mutually in the relevant descriptions.

[0030] To better understand this application, the research background of this application will be explained in detail below.

[0031] In hardware, the PLEN (Physical Total Bit Length) of a vector unit is fixed and set by the hardware; it cannot be modified by software. A vector unit consists of multiple blocks (VBs, vector computation blocks), all of which share the PLEN, and the block bit length (BLEN) of each VB is equal. Each VB consists of multiple vector lanes, and a lane is the basic unit of a vector unit.

[0032] In applications, sometimes it's necessary to process very long vectors. In these cases, a single-issue vector unit with a long VLEN (Vector Length) is more efficient. Conversely, sometimes fast multi-user response is required, in which case a short VLEN with multiple concurrent vector units is more efficient. Traditional hardware designs fix the number of VLENs and vector units per vector unit based on statistical analysis of historical applications.

[0033] In the RISC-V Vector instruction set, VLEN is a fixed parameter implemented in hardware. Typically, this parameter is fixed after chip implementation, and software can obtain the value of VLEN by reading the vlen register (vlen = VLEN / 8). In hardware, the register length of a vector unit is VLEN. To support high concurrency, multiple vector units need to be designed in hardware, all with the same VLEN, which wastes resources.

[0034] To address the aforementioned technical problems, embodiments of this application provide a dynamically reconfigurable vector unit, a vector processor, a chip, and an electronic device, which can solve at least one of the aforementioned problems existing in the prior art.

[0035] Figure 1 This is a schematic diagram of the structure of a dynamically reconfigurable vector unit provided in an embodiment of this application, such as... Figure 1 As shown, this application embodiment provides a dynamically reconfigurable vector unit 100, including a vector register file circuit 1, multiple vector processing channel circuits 2, a cross-channel switching network circuit 3, and a control logic circuit 4. Wherein, The vector register file circuit 1 has a physical total bit length of PLEN and is used to store vector data. This vector register file circuit 1 can contain multiple register units, each capable of storing data of a specific bit width. In this embodiment, the vector register file circuit 1 can be implemented using static random access memory (SRAM) and can have multiple read / write ports to support parallel access by multiple vector processing channel circuits 2.

[0036] Multiple vector processing lanes 2 are coupled to vector register file circuit 1, respectively, to perform vector operations on vector data in vector register file circuit 1 and write the results back to vector register file circuit 1. Each vector processing lane 2 may include one or more of the following: an arithmetic logic unit (ALU), a multiplier, a shifter, and a local control unit. The arithmetic logic unit is capable of performing at least one of the following basic operations: addition, subtraction, logical AND, logical OR, and logical XOR. The multiplier supports fixed-point and floating-point multiplication operations. The shifter is capable of performing logical shift and arithmetic shift operations. The local control unit is responsible for decoding instructions and controlling the timing of operations of each functional unit.

[0037] Cross Lane 3 connects multiple vector processing channel circuits 2 and is used to exchange data among them. This cross lane switching network circuit 3 can be implemented using a reconfigurable crossbar array, supporting various data exchange modes, including but not limited to adjacent channel switching, butterfly switching, and shuffle switching. The switching topology of the cross lane switching network circuit 3 can be dynamically adjusted via configuration registers to adapt to different vector computation requirements.

[0038] The control logic circuit 4 is coupled to multiple vector processing channel circuits 2 and cross-channel switching network circuit 3. Based on the configured value of the block length BLEN, the control logic circuit 4 dynamically divides the multiple vector processing channel circuits 2 into one or more vector computation blocks. The bit length of each vector computation block is equal to BLEN, and the number of vector computation blocks is equal to PLEN / BLEN, where BLEN is less than or equal to PLEN, and PLEN / BLEN is an integer. Based on the BLEN value and computation instructions, the control logic circuit 4 configures the switching topology of the cross-channel switching network circuit 3.

[0039] In this embodiment, the control logic circuit 4 may include an instruction decoding unit, a vector computation block partitioning unit, and a switching network configuration unit. The instruction decoding unit is responsible for parsing vector instructions and generating corresponding control signals. The vector computation block partitioning unit calculates the boundaries of the vector computation blocks based on the BLEN value and assigns a block identifier to each vector processing channel circuit 2. The switching network configuration unit generates configuration data for the cross-channel switching network circuit 3 based on the computation instructions according to the partitioning results of the vector computation blocks.

[0040] Therefore, the basic units of the dynamically reconfigurable vector unit 100 provided in this embodiment are also Vector Lane and Cross Lane. Unlike traditional vector units, multiple Lanes can be configured to form VB (vector computation block). The data bit length of each VB is BLEN, and the total data bit length of multiple VBs is PLEN. The Cross Lane adopts a hierarchical exchange and processing structure. In each layer, calculations (such as addition, comparison and other arithmetic operations) are performed first, and then data exchange is performed according to BLEN and calculation instructions.

[0041] In actual operation, the dynamically reconfigurable vector unit 100 first receives the configuration value of the block length BLEN through the control logic circuit 4. The control logic circuit 4 divides the multiple vector processing channel circuits 2 into several vector calculation blocks based on the BLEN value, and configures the cross-channel switching network circuit 3 based on the division results and calculation instructions. The vector register file circuit 1 loads vector data from memory. The multiple vector processing channel circuits 2 perform vector operations, exchanging data through the cross-channel switching network circuit 3 when necessary. Finally, the calculation results are written back to the vector register file circuit 1 or memory.

[0042] This dynamically reconfigurable design allows vector units to adapt to the needs of different application scenarios, improving the flexibility and efficiency of vector computation. It can smoothly transition between Single Instruction Multiple Data (SIMD) and Multiple Instruction Multiple Data (MIMD) modes, meeting computational requirements with different parallel granularities.

[0043] In some embodiments, when BLEN equals PLEN, the control logic circuit divides all vector processing channel circuits into a single vector calculation block. In this case, the vector unit operates in the same way as in a conventional structure.

[0044] In some embodiments, when BLEN is smaller than PLEN, the control logic circuit divides the plurality of vector processing channel circuits into PLEN / BLEN vector calculation blocks, wherein the number of vector processing channel circuits contained in each vector calculation block is equal to BLEN divided by the bit width of each vector processing channel circuit.

[0045] Specifically, when BLEN < PLEN, there are n = PLEN / BLEN vector units hardware - wise. The value range of BLEN: PLEN >= VLEN >= ELEN (element length, the number of bits occupied by one data), PLEN >= BLEN >= ELEN, and n must be an integer. There is no absolutely fixed ratio between VLEN and BLEN. Usually, the value of k = VLEN / BLEN is 0.5, 1, 2, etc.

[0046] The following takes the vector unit containing 4 Vector Lanes as an example to elaborate on the division method of the vector calculation block. As Figure 2 shown, when BLEN = PLEN, 4 Vector Lanes are divided into one vector calculation block; when BLEN = PLEN / 2, 4 Vector Lanes are divided into 2 vector calculation blocks; when BLEN = PLEN / 4, 4 Vector Lanes are divided into 4 vector calculation blocks.

[0047] As Figure 3 shown, in some embodiments, the dynamically reconfigurable vector unit 100 further includes: a memory access unit circuit 5, coupled to the vector register file circuit 1, for performing the loading and storing operations of vector data between the vector register file circuit 1 and an external memory; the memory access unit circuit 5 supports parallel execution of multiple vector memory access instructions to adapt to the division of the vector calculation block.

[0048] In some embodiments, the control logic circuit 4 also configures the reading and writing mode of the vector register file circuit 1 according to the BLEN value, such that the vector register file circuit 1 supports reading and writing at the granularity of a single vector processing channel circuit, or supports combined reading and writing at the granularity of a vector calculation block. To improve the memory access efficiency, the corresponding memory access unit supports parallel execution of multiple vector memory access instructions.

[0049] As Figure 4 shown, in some embodiments, the dynamically reconfigurable vector unit 100 further includes: an instruction issue interface circuit 6, for receiving vector instructions from an external instruction issue unit; the control logic circuit 4 also configures the instruction distribution mode of the instruction issue interface circuit 6 according to the BLEN value: When BLEN is equal to PLEN, the same vector instruction is distributed to all vector processing channel circuits 2; When BLEN is less than PLEN, it supports distributing different vector instructions to different vector calculation blocks.

[0050] Specifically, the following takes 4 Vector Lanes as an example to introduce the basic structure of Vector Lane (see Figure 5 ): When BLEN=PLEN, there is only one VB, and the instruction queue (Insn Queue) sends the same vector instruction to all Vector Lanes each time. When BLEN=PLEN / 2, there are two VBs, and the instruction queue can send different vector instructions to the two VBs at a time. With BLEN=PLEN / 4, there are 4 VBs. In this case, the instruction queue sends different vector instructions to all Vector Lanes each time. The instruction queue needs 4 issue ports (the hardware can also use fewer than 4, but the execution efficiency will be slightly reduced).

[0051] like Figure 6 As shown, in some embodiments, the cross-channel switching network circuit 3 includes multiple switching nodes; the control logic circuit 4 configures the switching topology by enabling or disabling at least some switching nodes according to the BLEN value and calculation instructions. Specifically, based on the data calculation method required by the calculation instructions, it selects which data to exchange to achieve data shifting. For example, if the calculation instructions require all data to be accumulated, then each layer of the switching network performs data exchange, so that all data is accumulated and calculated in the first column calculation unit. The core idea is to use a multi-layer switching network to achieve data shifting.

[0052] like Figure 6 As shown, in some embodiments, the cross-channel switching network circuit 3 further includes computing nodes connected to the switching node; when the number of computing nodes connected to a switching node exceeds two, the switching node divides the connected computing nodes into two groups of equal number and simultaneously exchanges data between the two groups of computing nodes.

[0053] Taking four vector lanes as an example, Figure 6 The structure of the corresponding Cross Lane is shown. Figure 6 In this system, each Node is a computing node, and each swapping node performs left and right swapping (when a swapping node has more than two signals (vector data) that need to be swapped, the signals are divided into two equal groups on the left and right with the middle point as the midpoint, and the two groups of signals are swapped at the same time). Figure 5 The example uses four Vector Lanes. If there are eight Vector Lanes, an additional layer of swapping nodes is needed. In other words, Cross Line is scalable.

[0054] Based on the same inventive concept, this application also provides a dynamic configuration method for vector units, which is applied to the dynamically reconfigurable vector units described in any of the above embodiments. Figure 7It is a schematic flowchart of a method for dynamically configuring a vector unit provided by an embodiment of the present application.

[0055] As Figure 7 shown, a method for dynamically configuring a vector unit provided by an embodiment of the present application includes the following steps: S1. Receive the configuration value of the block length BLEN; S2. According to the BLEN value, dynamically divide the multiple vector processing channel circuits into one or more vector calculation blocks, where the bit length of each vector calculation block is equal to the BLEN, and the number of vector calculation blocks is equal to PLEN / BLEN; and configure the switching topology of the cross-channel switching network circuit according to the BLEN value and calculation instructions.

[0056] Specifically, the execution subject of the above steps S1 to S2 is the dynamically reconfigurable vector unit. From the perspective of the software system and users, the process of the dynamic configuration method is as follows: Initialize the hardware: BLEN = PLEN The user software requests to modify the configuration: Send a request to configure the vector unit to the system, and the parameters are n: the number of parallelisms, and vlen: the minimum vector bit length.

[0057] The system modifies the configuration: The system obtains the value of PLEN and the parameters of the user software, and configures BLEN >= vlen. When PLEN < vlen, the system reports an error to the user, and the error type is a configuration error. After the configuration is successful, it returns to the user state. When the system configures the vector unit, other limiting conditions are consistent with the requirements of RVV.

[0058] The user executes vector operations: The user software reads vlenb, configures the application, and executes vector operations.

[0059] If the configuration is performed every time the user runs a vector calculation, it is obviously a waste of configuration time. A better scheduling method is to run in batches. For example, a group of similar user scenarios are centrally configured once in the system, and then the vector operations of these users are centrally executed, thereby saving configuration overhead.

[0060] The method embodiment provided by the embodiment of the present application is specifically the working method of the dynamically reconfigurable vector unit in the above-mentioned dynamically reconfigurable vector unit embodiment, and its specific implementation method will not be elaborated here and can be referred to the detailed description of the above-mentioned dynamically reconfigurable vector unit embodiment.

[0061] Based on the same inventive concept, an embodiment of the present application further provides a vector processor, and the vector processor includes at least one of the dynamically reconfigurable vector units described in the above embodiments.

[0062] The vector processor provided in this application embodiment includes the dynamically reconfigurable vector unit, and therefore can achieve the same technical effect as the dynamically reconfigurable vector unit, which will not be described in detail here.

[0063] In some embodiments, the vector processor further includes: A vector calculation block length configuration register, coupled to the control logic circuit, is used to store the dynamically configurable block length BLEN (WLRL). The vector physical bit length register, coupled to the control logic circuit, is used to store the physical bit length PLEN (WRRL) of the vector register file circuit in the dynamically reconfigurable vector unit.

[0064] Specifically, the vector compute block length configuration register (VLEN) interacts with the software, providing a dynamic configuration interface to obtain and store the configured block length (BLEN). When BLEN is configured, the value of the vlenb register (VLEN configuration register) also changes accordingly, thereby enabling dynamically configurable vector units with variable VLENs. It also supports high concurrency, allowing software to dynamically configure the hardware structure according to application characteristics to achieve optimal execution efficiency.

[0065] Based on the same inventive concept, this application also provides a chip, which includes at least one vector processor as described in any of the above embodiments.

[0066] Specifically, the chip may include a chip that implements RISC-V Vector, and based on the vector processor, the execution efficiency of the hardware can be effectively improved.

[0067] The chip provided in this application embodiment includes the vector processor, and therefore can achieve the same technical effect as the vector processor, which will not be described in detail here.

[0068] Based on the same inventive concept, embodiments of this application also provide an electronic device, which includes the chip described in any of the above embodiments.

[0069] The electronic device provided in this application embodiment includes the chip, and therefore can achieve the same technical effect as the chip, which will not be described in detail here.

[0070] Figure 8 This is a block diagram of an electronic device provided in an embodiment of this application. For example, the electronic device 200 may be an AI server, an artificial intelligence server cluster, a training and promotion integrated machine, etc.

[0071] Reference Figure 8The electronic device 200 may include one or more of the following components: an AI-accelerated computing module, a CPU module, a power supply module, a hard drive module, and a fan module. Each module works in conjunction with the bus system through a standardized hardware interface, with the specific architecture as follows: The AI-accelerated computing module comprises multiple AI accelerator cards deployed in parallel. Each AI accelerator card integrates at least one AI accelerator chip (or AI accelerator unit, such as an RPU chip, GPU chip, or CGRA chip). The AI ​​accelerator cards communicate with each other via a high-speed card-to-card (C2C) interconnect structure, supporting low-latency, high-bandwidth horizontal scaling. The AI ​​accelerator chip is dedicated to performing AI computing tasks such as high-density matrix operations, neural network model training, and / or inference, providing the main computing power support.

[0072] The CPU module includes at least one CPU board, which houses a central processing unit (CPU) chip and associated CPU memory (such as DDR4 / DDR5, RAM). The CPU chip serves as the system control center, responsible for task scheduling, resource allocation, I / O management, and coordinating the parallel computing of the AI ​​acceleration computing module, while also handling non-accelerated general-purpose computing tasks.

[0073] The power module is equipped with redundant power supply units to provide stable power distribution and management for the AI ​​acceleration computing module, CPU module and other modules.

[0074] The hard drive module integrates a high-speed solid-state drive (SSD) and / or a large-capacity hard disk drive (HDD), connected to the system bus via a backplane. The hard drive stores the operating system, AI training datasets, model parameters, and computation results, providing high-throughput data read / write channels and supporting data preprocessing and persistence.

[0075] The fan module uses a multi-zone independent speed-controlled fan array, which is configured in key heat source areas (such as AI accelerator cards and CPU heat dissipation areas) to achieve system heat dissipation through forced air cooling and ensure the stable operation of high-efficiency computing components.

[0076] The CPU module is connected to the AI ​​acceleration computing module via the PCIe bus to enable task distribution, result collection, and memory coordination.

[0077] The CPU module manages the data access of the hard drive module through SATA / SAS / NVMe interfaces.

[0078] The power module provides tiered power to all functional modules through the power distribution backplane.

[0079] The fan module adjusts the fan speed based on temperature monitoring signals from the CPU board and AI accelerator card.

[0080] This embodiment of the application provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions, and when the program instructions are executed by a computer, the computer is able to execute the methods provided in the above-described method embodiments.

[0081] This embodiment provides a computer-readable storage medium storing a computer program that causes the computer to execute the methods provided in the above-described method embodiments.

[0082] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0084] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0085] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above descriptions are merely specific embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A dynamically reconfigurable vector unit, characterized in that, include: The vector register file circuit has a physical total bit length of PLEN and is used to store vector data. Multiple vector processing channel circuits, each of which is coupled to the vector register file circuit, are used to perform vector operations on the vector data in the vector register file circuit and write back the results; A cross-channel switching network circuit, connecting the plurality of vector processing channel circuits, is used to exchange data between the plurality of vector processing channel circuits; A control logic circuit, coupled to the plurality of vector processing channel circuits and the cross-channel switching network circuit, is used to perform the following operations: Based on the configuration value of the block length BLEN, the multiple vector processing channel circuits are dynamically divided into one or more vector computing blocks. The bit length of each vector computing block is equal to the BLEN, and the number of vector computing blocks is equal to PLEN / BLEN. Wherein, the BLEN is less than or equal to the PLEN, and PLEN / BLEN is an integer. as well as Configure the switching topology of the cross-channel switching network circuit based on the BLEN value and calculation instructions.

2. The dynamically reconfigurable vector unit according to claim 1, characterized in that, When BLEN equals PLEN, the control logic circuit divides all vector processing channel circuits into a single vector calculation block.

3. The dynamically reconfigurable vector unit according to claim 1, characterized in that, When BLEN is less than PLEN, the control logic circuit divides the plurality of vector processing channel circuits into PLEN / BLEN vector calculation blocks. The number of vector processing channel circuits contained in each vector calculation block is equal to BLEN divided by the bit width of each vector processing channel circuit.

4. The dynamically reconfigurable vector unit according to claim 3, characterized in that, Also includes: The memory access unit circuit, coupled to the vector register file circuit, is used to perform the loading and storage operations of vector data between the vector register file circuit and the external memory; The memory access unit circuit supports the parallel execution of multiple vector memory access instructions to adapt to the division of the vector computation block.

5. The dynamically reconfigurable vector unit according to claim 1, characterized in that, The control logic circuit also configures the read / write mode of the vector register file circuit according to the BLEN value, so that the vector register file circuit supports read / write at the granularity of processing channel circuits by a single vector, or supports read / write at the granularity of combined vector calculation blocks.

6. The dynamically reconfigurable vector unit according to claim 1, characterized in that, The cross-channel switching network circuit includes multiple switching nodes, and the control logic circuit configures the switching topology by enabling or disabling at least some of the switching nodes according to the BLEN value and calculation instructions.

7. The dynamically reconfigurable vector unit according to claim 6, characterized in that, The cross-channel switching network circuit also includes computing nodes connected to the switching node; when the number of computing nodes connected to a switching node exceeds two, the switching node divides the connected computing nodes into two groups of equal number and simultaneously exchanges data between the two groups of computing nodes.

8. The dynamically reconfigurable vector unit according to claim 1, characterized in that, Also includes: The instruction dispatch interface circuit is used to receive vector instructions from an external instruction dispatch unit; the control logic circuit also configures the instruction dispatch mode of the instruction dispatch interface circuit according to the BLEN value. When BLEN equals PLEN, the same vector instruction is distributed to all vector processing channel circuits. When BLEN is less than PLEN, it supports distributing different vector instructions to different vector computation blocks.

9. A method for dynamically configuring vector units, characterized in that, Applied to the dynamically reconfigurable vector unit as described in any one of claims 1 to 8, the method comprises the following steps: The configuration value for the receive block length BLEN; Based on the BLEN value, the plurality of vector processing channel circuits are dynamically divided into one or more vector computation blocks, the bit length of each vector computation block is equal to the BLEN value, and the number of vector computation blocks is equal to PLEN / BLEN. Furthermore, the switching topology of the cross-channel switching network circuit is configured according to the BLEN value and calculation instructions.

10. A vector processor, characterized in that, It includes at least one dynamically reconfigurable vector unit as described in any one of claims 1 to 8.

11. The vector processor according to claim 10, characterized in that, Also includes: A vector calculation block length configuration register, coupled to the control logic circuit, is used to store the dynamically configurable block length BLEN; The vector physical bit length register, coupled to the control logic circuit, is used to store the physical bit length PLEN of the vector register file circuit in the dynamically reconfigurable vector unit.

12. A chip, characterized in that, It includes at least one vector processor as described in claim 10 or 11.

13. An electronic device, characterized in that, Including the chip as described in claim 12.

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