Hbf chip wafer level testability structure generation method and device

Abstract

The application relates to the field of chip structure optimization, in particular to an HBF chip wafer-level testability structure generation method and device. The method comprises the following steps: constructing a distribution topology based on an HBF chip demand design diagram, and constructing a first wafer test structure; performing limit working condition application analysis and working condition parameter collection based on the HBF chip demand design diagram, and constructing a limit test framework; performing dynamic running test on the first wafer test structure based on the limit test framework, and obtaining a standardized response data set; performing period parameter difference differential analysis according to the standardized response data set, and marking response difference test parameters; performing fault state analysis and topology structure layout optimization according to the response difference test parameters, and outputting test optimization results. The application improves the stability and quality of the HBF chip structure, and reduces the chip failure rate after production.

Description

Technical Field

[0001] This invention relates to the field of chip structure optimization, and in particular to a method and apparatus for generating wafer-level testability structures for HBF chips. Background Technology

[0002] With the rapid development of integrated circuit technology, HBF chips (High-bandwidth flash memory chips), as key components for next-generation high-speed, high-density storage and computing, have been widely used in fields such as artificial intelligence accelerators, data centers, and high-performance computing. HBF chips, with their extremely high bandwidth, low latency, and excellent energy efficiency, have become an important foundation for supporting large-scale parallel computing and massive data processing. However, with the widespread deployment of HBF chips in complex application scenarios, the reliability, testability, and performance optimization issues of their wafer-level structure are becoming increasingly prominent.

[0003] HBF (Hybrid Heat Transfer) chip wafers are susceptible to various factors under long-term operation and high-intensity load conditions, including interconnect delay, power concentration, thermal stress, and minor deviations in the manufacturing process. These factors can lead to local structural failures, abnormal electrical signal transmission, or functional performance degradation, thereby affecting the overall performance and reliability of the chip. Meanwhile, traditional wafer structure design is mostly based on static simulation or single-condition testing, which struggles to cover the various extreme loads and thermal, electrical, and stress coupling conditions that HBF chips may encounter under full operating conditions. This makes it difficult to identify and optimize potential failure modes in advance. Existing wafer structure optimization methods mainly rely on local parameter adjustments or empirical design rules, typically using a limited number of test points for structural verification. This approach has significant limitations: firstly, it cannot comprehensively capture faults and performance boundaries under all operating conditions, easily overlooking potential bottlenecks under extreme conditions; secondly, it lacks comprehensive analysis and optimization methods for wafer microstructure and electronic circuit layout, leading to potential global performance degradation due to local structural improvements. Traditional structural optimization relies heavily on manual analysis and iterative experiments, which is inefficient, costly, and difficult to achieve rapid feedback and adjustment, failing to meet the refined design requirements of HBF chips in high-bandwidth, low-latency, and high-reliability scenarios. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention proposes a method and apparatus for generating HBF chip wafer-level testability structures, thereby resolving at least one of the aforementioned technical problems.

[0005] To achieve the above objectives, the present invention provides a method for generating HBF chip wafer-level testability structures, comprising the following steps: Step S1: Based on the HBF chip requirement design, construct the distributed topology and build the first wafer test structure; Step S2: Based on the HBF chip requirement design drawing, perform extreme operating condition application analysis and set of operating condition parameters to build an extreme test framework; Step S3: Perform dynamic operation tests on the first wafer test structure under each working condition based on the extreme testing framework to obtain a standardized response dataset; Step S4: Perform periodic parameter difference analysis based on the standardized response dataset and label the response difference test parameters; Step S5: Perform fault state analysis and topology layout optimization based on response difference test parameters, and output the test optimization results.

[0006] This specification provides an apparatus for generating HBF chip wafer-level testability structures, used to perform the HBF chip wafer-level testability structure generation method described above, comprising: The test structure unit is used to construct the first wafer test structure based on the HBF chip requirement design drawing and to build a distributed topology. The extreme condition fitting unit is used to perform extreme condition application analysis and set of condition parameters based on the HBF chip requirement design drawing, and to build an extreme test framework. The test unit is used to perform dynamic operation tests on the first wafer test structure based on the extreme test framework to obtain a standardized response dataset. The periodic difference unit is used to perform periodic parameter difference analysis based on the standardized response dataset and to label the response difference test parameters. The structural optimization unit is used to perform fault state analysis and topology layout optimization based on response difference test parameters, and output the test optimization results.

[0007] The specific benefits of this invention are as follows: By constructing a distributed topology according to the requirements design diagram of the HBF chip, the test structure can accurately reflect the actual working environment and requirements of the chip. A reasonable layout can avoid deviations in later testing. Building the wafer test structure in the preliminary design stage allows for the simulation and anticipation of potential design problems or process bottlenecks, enabling adjustments to the structure to reduce repair costs and time when faults are discovered later. Considering the testing requirements of various subsequent operating conditions when constructing the initial test structure allows for better definition of test boundaries and methods. Extreme operating condition application analysis helps the team assess the chip's ability to operate in the most severe environments, such as high temperature, low temperature, and high voltage. This is a crucial step in understanding the chip's design potential and performance limits. Through a set of operating condition parameters, all possible operating environments can be comprehensively listed, thus covering all potential risk factors in testing and avoiding omissions of important operating conditions that may affect chip performance. Building an extreme testing framework helps ensure that all tests are conducted systematically, avoiding arbitrariness and inconsistency, and increasing the reliability of test data. Through dynamic testing of each operating condition, the chip's performance in actual operation can be comprehensively simulated. Dynamic testing not only observes the chip's behavior under different operating conditions but also tests its response time, stability, and durability. All test data is standardized, helping developers clearly understand the chip's response patterns in various environments, thus providing high-quality data support for subsequent analysis. Standardized response datasets quantify test results, facilitating comparison, analysis, and summarization, aiding in subsequent problem diagnosis and optimization suggestions. Through differential analysis of cycle parameters, response data under different operating conditions can be systematically compared to identify differences and trends in behavior. This helps analyze chip performance variations in different environments, providing a basis for design optimization. By comparing differences, abnormal situations or unexpected behaviors can be quickly identified, helping to locate potential fault points or performance bottlenecks. This step is crucial for fault diagnosis. Differential analysis reduces test redundancy by focusing on analyzing response data with significant differences, improving testing efficiency and effectiveness. Fault state analysis of test parameters with response differences helps engineers accurately pinpoint fault types, avoiding blind testing and adjustments. Based on fault states and difference analysis results, the chip's topology can be optimized, enabling the chip to operate more stably under extreme conditions. The optimized structure not only improves chip reliability but also reduces failure rates and errors during testing. By optimizing the structure, the chip's testability is enhanced, making subsequent testing more efficient and accurate, while reducing testing errors caused by structural design issues. The results of this stage of test optimization can be fed back into the chip design process for further design optimization, forming a continuously improving design-test-optimization closed loop. Attached Figure Description

[0008] Figure 1This is a schematic flowchart of the steps of the method for generating HBF chip wafer-level testability structure according to the present invention; Figure 2 This is a detailed flowchart illustrating the implementation steps of step S1. Figure 3 This is a flowchart illustrating the detailed implementation steps of step S2. Detailed Implementation

[0009] It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0010] This application provides a method and apparatus for generating HBF chip wafer-level testability structures. The execution entities of the HBF chip wafer-level testability structure generation method and apparatus include, but are not limited to, mechanical equipment, data processing platforms, cloud server nodes, network upload devices, etc., which can be considered as general computing nodes in this application. The data processing platform includes, but is not limited to, at least one of an audio / image management system, an information management system, and a cloud data management system.

[0011] Please see Figures 1 to 3 This invention provides a method for generating HBF chip wafer-level testability structures, comprising the following steps: Step S1: Based on the HBF chip requirement design, construct the distributed topology and build the first wafer test structure; Step S2: Based on the HBF chip requirement design drawing, perform extreme operating condition application analysis and set of operating condition parameters to build an extreme test framework; Step S3: Perform dynamic operation tests on the first wafer test structure under each working condition based on the extreme testing framework to obtain a standardized response dataset; Step S4: Perform periodic parameter difference analysis based on the standardized response dataset and label the response difference test parameters; Step S5: Perform fault state analysis and topology layout optimization based on response difference test parameters, and output the test optimization results.

[0012] In the embodiments of the present invention, see Figure 1 This is a schematic flowchart illustrating the steps of a method for generating an HBF chip wafer-level testability structure according to the present invention. In this example, the steps of the method for generating an HBF chip wafer-level testability structure include: Step S1: Based on the HBF chip requirement design, construct the distributed topology and build the first wafer test structure; In this embodiment, after obtaining the required design drawing of the HBF chip, the core functional units, interconnect network, and signal paths are first analyzed in a structural layered manner to clarify the logical and physical correspondence between different modules. The key objective of distributed topology construction is to form a first wafer test structure that can be used for testing and analysis based on the chip's multi-layered structure and physical constraints. This process uses functional blocks in the HBF architecture (such as cache arrays, interconnect network nodes, control units, and inter-chip interface modules) as basic units, mapping them to the wafer physical layer to establish the spatial distribution relationship of signal flow and power flow. During topology construction, factors such as metal interconnect density, power consumption distribution, and thermal conductivity paths need to be considered. For example, when the power consumption density of a certain computing area is higher than 0.8 W / mm², a heat diffusion layer should be added to the local area or the metal linewidth should be optimized to improve thermal conductivity. At the same time, to ensure the testability of subsequent fault simulation, test probe ports and monitoring channels are reserved at each major functional node to enable the acquisition of electrical signals, voltage, temperature, and stress response. The construction of the distributed topology also needs to meet parameter constraints (such as signal delay <200 ps, ​​current density <1.2×10). 6 (A / cm²) ensures electrical stability and structural reliability. The final first wafer test structure contains complete physical layout information, interconnect path topology, key parameter constraints, and monitoring node distribution, laying the structural foundation for subsequent extreme condition analysis and dynamic testing.

[0013] Step S2: Based on the HBF chip requirement design drawing, perform extreme operating condition application analysis and set of operating condition parameters to build an extreme test framework; In this embodiment, after determining the first wafer test structure, it is necessary to comprehensively evaluate the performance of the HBF chip under multiple extreme conditions, taking into account its application scenario and reliability objectives. The focus of extreme condition application analysis is to identify critical conditions that may lead to performance degradation or structural failure. Based on chip design characteristics, extreme conditions are divided into electrical limits (such as overvoltage 5.5 V, overcurrent 1.8 × rated value), thermal limits (… The operating conditions are categorized into four types: temperature range (40℃ to 150℃), mechanical limits (encapsulation stress > 150MPa), and timing limits (signal delay deviation > ±10%). By performing boundary fitting and ensemble processing on these operating parameters, a parameter interval matrix is ​​generated for each type of operating condition. For example, the temperature range is divided into... Three temperature ranges—40~0℃, 0~80℃, and 80~150℃—correspond to different material stress response curves. Based on these parameter sets, a multi-condition scenario model is constructed to serve as the input conditions for subsequent dynamic testing. Simultaneously, test resources and time allocation are planned according to the complexity and reliability requirements of the conditions. For example, the test duration is increased to 1800 seconds under high temperature and high current conditions to fully capture delayed failure characteristics. The final extreme testing framework includes a condition classification table, parameter boundary ranges, test time planning, and response variable sampling strategies, providing complete condition control logic and execution paths for the dynamic testing phase.

[0014] Step S3: Perform dynamic operation tests on the first wafer test structure under each working condition based on the extreme testing framework to obtain a standardized response dataset; In this embodiment, after the extreme testing framework is determined, a multi-condition dynamic operation test is performed on the first wafer test structure to obtain the response characteristics under real operating conditions. The test is executed sequentially in each operating scenario, applying corresponding electrical and thermal load signals for different types of stress factors. Taking high-temperature and high-pressure conditions as an example, a 5.0 V operating voltage and an ambient temperature of 130°C are applied, and current fluctuations, impedance change rate, and local temperature rise response curves are recorded; under low-temperature and high-frequency conditions, [further details are needed]. At 20℃ and a signal frequency of 2.5 GHz, parameters such as time delay drift and signal integrity were collected. During each operating condition, the collected response signals included multi-dimensional values ​​such as voltage, current, power density, junction temperature change, and structural micro-deformation. To ensure data consistency, all raw signals underwent normalization and standardization, uniformly converting them to dimensionless form (e.g., normalized voltage V_norm = V / V_max). Furthermore, to reduce noise and abrupt interference, a sliding window averaging and second-order filtering method were used to smooth the data, maintaining signal sampling stability at ±0.5%. After multi-condition testing and processing, a standardized response dataset was compiled. The data structure includes a time index, operating condition labels, response channel numbers, and a standardized response amplitude matrix. This dataset provides an accurate statistical basis for subsequent periodic difference analysis and fault analysis.

[0015] Step S4: Perform periodic parameter difference analysis based on the standardized response dataset and label the response difference test parameters; In this embodiment, after obtaining standardized response data, periodic decomposition and differential analysis are performed to reveal the parameter change trends at each stage of the test. First, based on the duration of the operating condition and the rules for dividing the test stages, the data sequence is divided into several adaptive periodic segments. For example, an operating condition with a total test duration of 1800 seconds can be divided into six 300-second periodic points. Core parameters such as current density, heat flux intensity, and impedance change are extracted within each period. Then, the difference between the first and last periods, ΔP = P_last, is calculated. P_first is used to calculate the ratio of change rate to amplitude (ΔP_rate = ΔP / t). When the amplitude of a parameter change exceeds a preset threshold (e.g., ΔR > 15%, ΔT > 10 K), it is identified as a response difference parameter and marked. The periodic difference method can effectively identify parameter drift phenomena under long-term stress, such as the slow increase in impedance caused by electromigration or the change in thermal diffusivity caused by interface stress concentration. The difference results are recorded in matrix form, including parameter name, amplitude of change, rate of change, period time index, and difference confidence index. To improve accuracy, statistical screening criteria are introduced, such as excluding outlier data points with a standard deviation of fluctuation exceeding 30% of the mean, ensuring that the difference parameters have true physical meaning. The final marked results of the response difference test parameters provide accurate input for fault type identification and topology optimization.

[0016] Step S5: Perform fault state analysis and topology layout optimization based on response difference test parameters, and output the test optimization results.

[0017] In this embodiment, after marking the differential parameters, the process proceeds to the fault state analysis and structural optimization stage. First, based on the differential parameter matrix, the variation patterns of each parameter and the corresponding potential fault types are analyzed. For example, when the resistance rise rate exceeds 0.02 Ω / s and is accompanied by a thermal drift greater than 8 K, interconnect aging or electromigration failure can be inferred; when current fluctuations exhibit periodic spikes and significant phase drift, it may indicate signal coupling interference or dielectric breakdown. By establishing a correspondence between differential parameters and a typical fault feature library, a similarity index is calculated, and the fault type and severity level (minor, moderate, severe) are determined. Subsequently, the fault location is mapped back to the wafer topology to locate high-risk areas. For these areas, topology optimization design is performed, including adjusting interconnect path lengths, redistributing current density, and optimizing the arrangement of heat dissipation channels and stress buffer layers. For example, shifting high-density interconnects 2.5 µm from the center to the periphery can reduce local temperature rise by approximately 12%; adding a high thermal conductivity metal island structure to the power distribution area can reduce the temperature gradient to 70% of its original value. After optimization, the overall performance indicators are checked to ensure that power consumption changes do not exceed ±5% and signal delay does not exceed 8% of the initial value. The final output test optimization result file includes a fault type distribution map, parameter change statistics table, optimized topology model, and comprehensive reliability improvement assessment, providing data basis and design closed loop for HBF chip wafer-level structure optimization and testability verification.

[0018] In this embodiment, see Figure 2 The diagram below illustrates the detailed implementation steps of step S1. In this embodiment, the detailed implementation steps of step S1 include: Based on the HBF chip requirement design diagram, we analyze the usage requirements and extract multiple requirement indicators. The multiple requirements indicators include performance indicators, power consumption constraints, application scenarios, and reliability targets; Design multiple structural layers based on multiple demand indicators to generate a multi-layered structure; Based on multiple demand indicators, wafer microstructure and electronic circuit layout analysis is performed to obtain wafer microstructure and electronic circuit layout data. Based on the wafer microstructure and electronic circuit layout data, a distributed topology of the multilayer structure is constructed to build the first wafer test structure.

[0019] In this embodiment, based on the HBF chip design diagram, the overall usage objectives are decomposed and summarized layer by layer. First, starting from the chip's functional framework, interconnect structure, core modules, and peripheral interfaces, the performance requirements, power consumption limitations, and environmental adaptability indicators of each part during operation are extracted. Through item-by-item analysis of the architecture diagram and design parameters, four main categories of requirement indicators are formed: performance indicators, power consumption constraints, application scenarios, and reliability targets. The performance aspect includes a clock frequency range between 2.5GHz and 3.2GHz, on-chip bandwidth of no less than 256GB / s, and signal transmission delay of less than 10ns; the power consumption aspect controls the overall chip power to below 80W, and the power density of a single module to no more than 1.2W / mm²; the application scenario is limited to operation under multi-task parallelism and AI accelerated computing conditions, with an ambient temperature range of [missing information]. The operating temperature range is 20℃ to 105℃. Reliability targets include a mean time between failures (MTBF) of at least 10^6 hours, wafer bonding strength greater than 45 MPa, and multilayer interconnect failure rate less than 0.1 ppm. Based on these indicators, the structural hierarchy, conductive paths, packaging heat dissipation, and material matching relationships are quantified item by item to ensure that each indicator is traceable and achievable in subsequent designs. The indicator matrix formed at this stage forms the basic framework for subsequent multilayer structure design and layout analysis. Functional modules are divided, including the computing layer, storage layer, and interconnect layer. The computing layer is responsible for data processing logic and adopts a high-density FinFET structure to improve switching speed; the storage layer adopts a high-bandwidth storage array design to maintain low-latency data exchange; the interconnect layer is configured with multilayer copper wiring and through-silicon vias (TSVs) to achieve vertical signal transmission. The silicon wafer thickness is controlled within the range of 50±3μm, the TSV diameter is approximately 2.5μm, and the spacing is no greater than 10μm to balance conductivity and structural strength. Interlayer metal interconnects employ a combination of copper redistribution layers (Cu-RDL) and low-dielectric-constant organic insulating materials to reduce parasitic capacitance and signal crosstalk. Thermal stress control is achieved by adjusting the metal layer thickness and the coefficient of thermal expansion of the dielectric material, keeping the overall peak thermal stress below 280 MPa, within the material tolerance limit. After completing the stacking design, the multilayer structure generates a complete geometric model with vertical interconnect and lateral distribution characteristics, providing structural boundaries and parameter constraints for subsequent microstructure layout analysis.

[0020] After determining the multilayer structure, a comprehensive analysis of the wafer's microstructure and circuit layout is required. This stage focuses on confirming the geometric proportions, electrical connection paths, and current distribution characteristics between each layer. Regarding the microstructure, the specific parameters of the doped regions, dielectric layers, and metal interconnect layers are determined: the doping concentration in the n-type region is approximately 5 × 10¹. 7 cm - ³, the p-type region is approximately 8 × 10¹ 6 cm - The silicon oxide layer thickness is controlled at approximately 80 nm, and the silicon nitride layer at 50 nm to maintain the electrical isolation performance and mechanical stability of the dielectric layer. The metal interconnect layer spacing is controlled at approximately 100 nm to balance conductivity and parasitic effect control. During the layout analysis, the length, impedance, and electromagnetic coupling of the signal path are evaluated to ensure that the signal propagation delay does not exceed 18 ps / mm and the coupling noise is less than 25 mV, thus meeting the high-frequency transmission requirements. A thermal balance analysis is performed on the overall power consumption distribution. When the power density reaches 0.8 W / mm², the local temperature rise remains below 12°C, meeting the thermal stability requirements. The reliability assessment is completed by comparing the thermal stress with the failure probability of the material interface. The interface failure probability remains below 0.05%. Through comprehensive analysis of the above parameters, complete wafer microstructure data and electronic circuit layout data are formed, providing accurate physical and electrical basis for topology construction. Based on the microstructure data and electronic circuit layout results, a topology framework that can be used for full fault simulation and structural verification is established. First, each functional module and interconnect node is abstracted into topology nodes and connection units, and a distributed structure is formed through hierarchical mapping. To improve the structural testability and local fault detection capability, detection units and monitoring nodes are embedded in key interconnect paths for online verification of signal integrity and interconnect status. The topology construction employs a constraint optimization approach, comprehensively considering signal propagation delay, path coverage, and redundant interconnect ratio. Topology design parameters include a path coverage of no less than 99.2%, a redundant connection rate of no more than 3%, and a signal hop count of no more than 4 layers. Through iterative optimization of structural mapping and path constraints, a consistent layout of electrical distribution and geometric topology is achieved. At the geometric distribution level, the connectivity of local heat dissipation channels and power distribution networks is ensured; at the electrical level, the observability and controllability of interconnect paths at each layer are ensured. The final first wafer test structure includes a continuity measurement unit, an interconnect integrity detection area, and a bond strength verification point, enabling full fault simulation analysis at the wafer level, providing a data foundation for subsequent structural improvements and reliability optimization.

[0021] In this embodiment, see Figure 3 The diagram below illustrates the detailed implementation steps of step S2. In this embodiment, the detailed implementation steps of step S2 include: Based on the HBF chip requirement design diagram, multi-extreme operating condition application analysis is performed to identify the chip's potential extreme operating conditions. The extreme working conditions are fitted with extreme working condition parameter boundaries to generate the parameter range for each working condition; Construct multiple extreme operating condition scenarios based on the parameter range; Based on the aforementioned multi-extreme operating conditions, the fault exposure time constant, reliability stress accumulation probability, and test resource constraints are determined, and the test time for each operating condition is planned. Based on the test time for each operating condition and the limits of the multiple extreme operating conditions, a comprehensive test architecture is generated to construct an extreme test framework.

[0022] In this embodiment, all functional modules, interconnect nodes, power domains, package geometry, and material parameters in the design drawing are systematically analyzed, and each item is mapped to possible operating conditions: temperature, supply voltage, clock frequency, power density, humidity, vibration and mechanical stress, thermal cycling amplitude and rate, EMI pulse amplitude, etc. Sensitivity indicators are extracted for each module; for example, high-frequency transceiver units are sensitive to voltage offset, bonding points are sensitive to thermal cycling, and RDLs are sensitive to mechanical stress. A hierarchical enumeration method and a causal tree method are used to form a candidate list of extreme operating conditions. Each candidate is labeled with triggering scenarios (such as startup transients, continuous high load, thermal shock, drop / vibration, live isolation anomalies, etc.) and possible failure modes (open circuit, short circuit, increased contact resistance, EMI-induced functional malfunction, thermal stress leading to interface fracture, etc.). To ensure coverage, a boundary expansion strategy is introduced: an initial limit range is defined by extending the normal operating boundary upwards and downwards by 10% to 30%. For example, the temperature dimension value starts from... The extreme operating conditions are expanded from 40℃ to +125℃, with the supply voltage within ±15% of the nominal Vdd (e.g., 1.0V ± 0.15V), the clock frequency from the nominal 2.8GHz to a peak of 3.5GHz, and the power density from the normal 0.8W / mm² to 1.5W / mm². A sensitivity weighting matrix is ​​used to prioritize each candidate extreme condition for subsequent fitting and priority verification. The output of this stage is a structured list of extreme conditions, including the triggering conditions, corresponding modules, priorities, and expected failure modes for each condition, serving as input for parameter boundary fitting. Historical data, previous data from similar packages / processes, material properties, and physical failure model outputs are summarized as fitting samples. For single dimensions (such as temperature, Vdd, and power density), extreme value theory and distribution fitting methods are used, such as the generalized extreme value distribution (GEV) or Gumbel distribution, to estimate the probability of extreme temperature occurrence; for lifetime or time-related failures, the shape and scale parameters are fitted using the Weibull distribution to obtain failure rate curves under different stress levels. If multidimensional parameters are correlated, such as high power density and local temperature rise, or Vdd offset and time window shrinkage, a joint distribution model is established using a Copula function or a multivariate log-normal distribution to obtain the joint boundary surface. To improve the robustness of the fit, Latin hypercube sampling or response surface methodology is used to generate sample points in the parameter space to obtain the model's local sensitivity and interaction effects. Parameter boundaries are given in the form of confidence intervals; for example, the temperature limit interval is expressed with a 95% confidence level as [-45℃, 130℃], the Vdd limit interval is [0.85V, 1.15V] (corresponding to nominal 1.0V ± 15%), and the power density interval is [0.5, 1.6] W / mm². Critical thresholds are given for time-dependent parameters (such as thermal shock frequency and cycle count): a thermal cycling amplitude of ±80℃ and a maximum cycle count of 1000 times are considered high-risk areas. This stage ultimately generates a clear parameter range, corresponding probability density function, and joint distribution model for each extreme working condition, and labels the boundary values ​​at different confidence levels as quantitative inputs for constructing multi-working-condition scenarios.

[0023] Stratified sampling and constrained sampling methods are employed: First, the operating conditions are divided into high, medium, and low priority categories. Then, within each category, Latin hypercube or Monte Carlo sampling combined with a joint distribution model is used to generate several scenario points, ensuring sample coverage across every parameter dimension and its interaction surface. Scenario classification includes common extreme scenarios (e.g., high temperature + high power density, low temperature + high voltage surge, thermal cycling + mechanical vibration superposition), rare joint extremes (e.g., voltage drop accompanied by EMI spikes under high-frequency operation), and progressive stress scenarios (e.g., long-term slight overvoltage leading to migration accumulation). Each scenario represents parameter values ​​(temperature, Vdd, frequency, power density, humidity, vibration spectrum, number of cycles, etc.) in vector form with generation probability weights. For example: Scenario A (thermally induced high load) = {T=110℃, Vdd=1.05V, f=3.2GHz, Pden=1.4W / mm², thermal cycling rate=2℃ / s, number of cycles=200}, weight 0.12; Scenario B (low temperature pulse) = {T= At 40℃, Vdd drops to 0.85V in a sudden burst lasting 10ms, f=2.5GHz, Pden=0.6W / mm², with a weight of 0.05. The expected failure induction probability is calculated for each scenario based on the previous joint distribution model and failure mechanism mapping function. The scenario set should meet coverage targets, such as covering more than 95% of the extreme failure probability quality, while controlling the number of scenarios within an executable range (e.g., 50-200 representative scenarios) to balance coverage and resource constraints. The output of this stage is a scenario library containing the parameter vector, occurrence probability, targeted failure modes, and priority labels for each scenario, providing a basis for test time planning and coverage test architecture design. Failure acceleration models and cumulative damage models (e.g., Miner linear cumulative model and nonlinear acceleration factor model) are used to map different stress histories to equivalent damage quantities. For transient faults (such as voltage pulse triggering), the estimated time τ is typically in the millisecond to second range. For cumulative faults such as thermal migration or interface fatigue, τ is usually measured in hours or cycles. For example, the equivalent exposure time can be obtained through Weibull scale parameter transformation: when the local temperature is 110°C and the power density is 1.4 W / mm², the equivalent lifetime reduction factor may be 10 to 100 times, corresponding to the need to run for hundreds to thousands of hours under accelerated conditions to cover conventional lifetime scenarios. Combining the probability and priority of scenario occurrence, time is allocated according to resource constraints (number of available test bays, number of parallel test channels, number of test points per wafer, and single-point measurement time overhead). For example, when there are 5 parallel test positions, each of which can run for 24 hours per day, it can be calculated that at least N complete exposures (e.g., N=3) must be guaranteed for high-priority scenarios within a limited period (e.g., 30 days) to achieve statistical confidence. The time planning also needs to incorporate a discovery curve model. Based on Monte Carlo simulations, the probability of discovering a fault at a given time is estimated, and the test duration is adjusted accordingly to ensure that the probability of fault discovery in a single scenario reaches the target threshold (e.g., ≥90%). Furthermore, resource redundancy and priority preemption strategies need to be implemented: if a high-severity defect is discovered in real time, resources can be dynamically reallocated to increase the runtime of that scenario. Finally, a timeline matrix is ​​formed, showing the total test duration, single exposure duration, number of repetitions, and resource allocation for each scenario, ensuring that the overall coverage and confidence level meet the design specifications under given resources.

[0024] By combining the aforementioned scenario library with time planning, a comprehensive test architecture is generated, aiming to achieve maximum fault detection coverage with minimal resources. The architecture design employs a layered coverage strategy: the first layer is a rapid scanning layer, performing short-term half-coverage on all scenarios to discover obvious failures; the second layer is a deep exposure layer, implementing long-term exposure on high-priority / high-risk scenarios to trigger cumulative failures; and the third layer is a cross-overlay layer, jointly exposing multi-condition interaction scenarios to reveal complex coupled failure modes. Coverage optimization algorithms, such as set cover and weighted coverage models, are used in architecture generation. The objective function is to maximize the weighted fault detection probability given the test time and channel resources. Constraints include the minimum exposure time required for each scenario, the upper limit of parallel testing equipment, and the limit on the number of testable points per wafer. The architecture output includes the test sequence (scenario execution order), the parallel allocation matrix (which test bit executes which scenario, and when to switch), and data acquisition and archiving specifications (sampling frequency, monitoring channels, and failure judgment thresholds). To improve efficiency, online discrimination logic is incorporated into the architecture: if abnormal signs are detected during operation in a certain scenario (such as sudden changes in interconnect impedance, sudden increases in current, or an increase in timing failure count), extended exposure is automatically triggered or a more granular diagnostic process is switched. The final extreme testing framework should provide traceable coverage proof: for coverage metrics (such as covering 99% of high-risk failure probability), a coverage matrix and confidence assessment results are output; for resource consumption, time cost estimates and parallel efficiency assessments are output. This framework provides an executable and quantifiable verification path for wafer-level full-failure simulation and subsequent structural optimization.

[0025] In this embodiment, step S3 includes the following steps: Based on the extreme testing framework, dynamic operation testing of the first wafer test structure was carried out under each working condition, and the test response signal under each working condition was extracted. The test response signal is used to identify the response parameter type and to label different response parameters; By comprehensively analyzing different response parameters, a test response dataset is obtained. Anomaly parameters were detected and outliers were removed from the test response dataset to obtain a standardized response dataset.

[0026] In this embodiment, the first wafer test structure is loaded one by one according to the previously generated extreme scenario library and the dynamic operation process is executed. Each operating condition is set and applied to the unit under test according to a predetermined parameter vector (e.g., temperature T, supply voltage Vdd, frequency f, power density Pden, vibration spectrum, etc.); example parameters: thermally induced high load condition T=110℃, Vdd=1.05V, f=3.2GHz, Pden=1.4W / mm², and the continuous exposure time is set to 1000 hours as planned (actually converted to 200 hours using an accelerated exposure strategy). During the execution of each operating condition, the response of key measurement points is continuously or intermittently collected, including current sampling (static leakage current, dynamic peak), voltage trajectory, interconnect impedance, timing offset, bit error rate, transmission jitter, and temperature distribution. The sampling frequency is set according to the response characteristics: high-frequency timing or jitter type is sampled at ≥1GS / s, current transient is sampled at ≥100MS / s, and slow thermal response is sampled at 1Hz or lower. To ensure signal integrity, front-end filtering and anti-aliasing processing are first applied. For example, bandpass filtering captures high-frequency oscillations, and low-pass filtering removes out-of-band interference from power supply noise. Differential measurements are performed on current and voltage signals to reduce common-mode noise. After each load condition is applied, several cycles of thermal equilibrium waiting are performed (e.g., waiting 5-30 minutes under accelerated thermal load to stabilize the local temperature). Subsequently, periodic functional excitation is initiated (e.g., pulse load with a 50% duty cycle or linear frequency sweep excitation), and the collected data is stored synchronously with timestamps and load condition identifiers. The final output is a set of raw response signals, including time-domain waveforms, event trigger records, and metadata (load condition parameters, sampling rate, measurement point number, calibration coefficients, etc.), providing a complete raw data foundation for subsequent parameter identification and statistical analysis. For the large number of raw waveforms collected, signal preprocessing and segmentation are performed first. Preprocessing includes DC bias removal, amplitude normalization, baseline drift removal, and windowing. High sampling rate data is first resampled or multi-resolution decomposition to adapt to subsequent analysis. Subsequently, parameter type identification is performed, with the workflow divided into three parallel categories: time-domain feature extraction, frequency-domain feature extraction, and joint time-frequency feature extraction. Time-domain features include peak value, mean voltage / current, root mean square (RMS), rise / fall time, pulse width, pulse count, and transient response time constant τ. An example threshold is set: if the peak current exceeds 5σ of the baseline mean, it is recorded as a sudden event. Frequency-domain features are extracted using Fast Fourier Transform (FFT) to obtain the dominant frequency component, spectral density distribution, and harmonic content; for signals sensitive to jitter and noise, power spectral density (PSD) and phase noise indices are also extracted. Joint time-frequency features employ wavelet decomposition or Short-Time Fourier Transform (STFT) to capture transient spectral changes and extract the energy envelope and transient band energy ratio. For interconnect impedance and RDL probe data, DC impedance, AC amplitude-frequency characteristics (e.g., amplitude and phase within the 20Hz~1MHz range), and the slope of the temperature-dependent admittance curve are extracted.Each extracted parameter is labeled according to a standardized namespace (e.g., CURR_PEAK, VDD_RMS, JITTER_RMS, IMP_AC_1KHz, etc.) and includes metadata: sampling rate, window start and end time, corresponding operating condition ID, and measurement point location. Furthermore, blind source separation (e.g., Independent Component Analysis (ICA)) or Principal Component Analysis (PCA) is used for complex waveforms to separate superimposed sources and identify potential coupled responses. The output of this stage is a labeled set containing multiple types of response parameters, each with its numerical value, unit, confidence interval estimate, and operating condition association information, facilitating subsequent statistical summarization and anomaly detection.

[0027] After parameter labeling, multidimensional statistical summarization is performed to construct a structured test response dataset. The summarization process includes data reshaping and aggregation using a three-dimensional index by operating condition, measurement point, and parameter type, and calculation of descriptive statistics: mean, standard deviation, skewness, kurtosis, minimum / maximum, interquartile range (IQR), and confidence intervals (e.g., 95% confidence interval). For time-series parameters, the autocorrelation function (ACF), power spectral density (PSD) mean curve, and cumulative energy over time curve are also calculated. The time label for each parameter is retained in the constructed dataset to trace the causes and consequences of sudden events. To facilitate subsequent modeling, parameter values ​​are standardized according to a predefined scale (e.g., z-score or min-max) while retaining the original dimensional fields. For cross-condition comparisons, a parameter comparison matrix is ​​generated between conditions, such as the rate of change and slope of CURR_LEAK at different temperature points, to measure thermal sensitivity. For example, when the temperature rises from 25℃ to 110℃, the median leakage current at a certain interconnect point increases from 2.1µA to 18.5µA, an increase of approximately 780%. Furthermore, parameter correlation analysis is performed, using the Pearson / Spearman correlation coefficient matrix and mutual information to assess the linear or nonlinear relationships between parameters, identifying strongly correlated pairs for subsequent dimensionality reduction or modeling. The final dataset format is as follows: each record includes a condition ID, measurement point ID, timestamp, parameter vector, standardized value, raw value, statistical label, and quality indicator (whether it passed the initial screening). This dataset is suitable for both diagnostic inspections and as an input data source for fault classification and lifespan prediction. The data cleaning process aims to ensure the reliability of subsequent analyses, and includes multi-layered detection and rejection strategies. The first layer is univariate outlier detection, using robust statistical indicators such as median absolute deviation (MAD) and interquartile range (IQR) to identify extreme values: when a parameter value exceeds the median ± 4MAD or falls below Q1... A value exceeding 1.5IQR (or Q3 + 1.5 * IQR) is initially identified as a potential outlier. The second layer is multivariate anomaly detection, considering parameter correlation and joint distribution, using both distance-based and density-based methods in parallel: Mahalanobis distance is used for Gaussian approximation scenarios; if the distance exceeds the corresponding chi-square distribution threshold (e.g., p < 0.001), an anomaly is identified; density bases (such as the Local Outlier Factor (LOF)) are used for non-Gaussian distributions, with thresholds adjusted based on historical false alarm rates. The third layer is sequence anomaly detection, using CUSUM or drift detection methods to identify sudden jumps or gradual drifts in time series parameters; if a measurement point experiences a sudden amplitude change within a short period accompanied by multiple parameter anomalies, its anomaly level is increased. To avoid mistakenly removing causal defects, a multi-evidence verification mechanism is incorporated: when a single criterion indicates an anomaly, the responses of neighboring test points and similar operating conditions are checked for the same pattern; if the neighborhood is also anomaly-prone, it is retained as a potential defect sample and marked "awaiting manual confirmation"; if only isolated points are anomaly-prone and lack neighborhood support, they are removed or repaired through interpolation. The repair strategy employs nearest-time interpolation or fills in missing values ​​based on regression models (e.g., locally weighted regression), and uncertainty is labeled after interpolation when necessary. A standardized response dataset is ultimately formed: after removing or labeling anomaly records, the remaining data undergoes uniform standardization (z-score or 0-1 scaling), and each data point is accompanied by a quality label and the reason for removal / retention. This standardized dataset can be directly used for fault mode identification, model training, and subsequent quantitative analysis of structural optimization, thereby improving the credibility and reproducibility of fault simulation and optimization results.

[0028] In this embodiment, step S4 includes the following steps: The adaptive duration is divided according to the test time of each working condition to obtain the adaptive cycle point; The standardized response dataset is dynamically decomposed based on adaptive period points to extract test response data from multiple periods. Extract the test response data of the first cycle and the test response data of the last cycle based on test response data from multiple cycles; Perform cycle parameter difference analysis on the test response data of the first cycle and the test response data of the last cycle, and mark the test parameters of response difference.

[0029] In this embodiment, the total test time for each operating condition and the pre-planned exposure strategy are used as inputs to generate time segments (cycle points) for that operating condition using an adaptive partitioning principle. The adaptive partitioning adopts a dual-criteria method based on energy density and failure accumulation rate: on the one hand, high-variability periods are identified based on the energy change rate of the response signal (e.g., the energy slope calculated with a short-term energy window of 1 second); on the other hand, the cumulative damage curve output by the failure acceleration model (e.g., based on the Weibull scaling factor or the Miner accumulation method) is used to determine the time interval requiring longer exposure. Specifically, the total duration is first pre-segmented according to the minimum segment length L_min and the maximum segment length L_max constraints (example values: L_min = 1 minute, L_max = 8 hours), and then the short-term energy slope, peak event rate, and predicted equivalent damage growth rate are calculated within each pre-segment. If the energy slope of a pre-segment exceeds a set threshold (e.g., short-term energy slope > 3σ of the baseline mean) or the equivalent damage growth rate is in the upper 10th percentile, the pre-segment is subdivided into shorter intervals until L_min is met or the slope drops. Conversely, if the pre-segment energy is low and the damage growth is negligible, adjacent segments are merged to reduce fragmentation until approaching L_max or the merged segments do not exceed the allowable decrease in failure detection sensitivity (e.g., a decrease in detection probability of no more than 5%). A balance function is used during the partitioning process to weigh coverage against test resources: the goal is to cover ≥95% of the cumulative failure probability quality with fewer cycles. The partitioning output is an ordered set of time points (cycle start and end points), with each cycle labeled with priority, suggested sampling rate, and expected exposure actions (e.g., peak sweep, duty cycle loading, etc.). For example, a high-load condition at 110℃, under a total equivalent of 200 hours, might be divided into 10 cycles: several short cycles (10-30 minutes each) during the initial rapid fluctuation period, several long cycles (6-8 hours each) during the middle stable load period, and a continuous exposure period (12 hours) at the end for accelerated judgment. This adaptive division ensures denser observations during high-sensitivity periods, conserves resources during low-variability periods, and retains the ability to capture cumulative failures. After obtaining the adaptive cycle point set, the standardized response data is segmented and dynamically decomposed to extract the response data for each cycle. First, the standardized data is mapped to the corresponding cycle interval by timestamp, and boundary alignment and resampling are performed: if the original sampling rate of a certain cycle is inconsistent with the target sampling rate, resampling is performed using least squares-based interpolation or local weighted regression to ensure data comparability within the cycle. To handle transient events that may exist within the cycle, a multi-resolution decomposition method (e.g., discrete wavelet transform) is used to divide the signal within each cycle into low-frequency trend components and high-frequency transient components, which are then saved as cycle feature subsets. Next, extract time domain, frequency domain and time-frequency joint features (such as mean, RMS, peak value, main peak of power spectrum, instantaneous energy envelope, waveform singularity count, etc.) for each period, and calculate the statistical description within the period (median, IQR, autocorrelation time constant).To address periodic drift, local baseline correction is introduced: using the first N% (e.g., the first 5%) of data within a period as a reference baseline, baseline fine-tuning is performed across the entire period to eliminate offsets caused by measurement probe drift or slow environmental changes. If a period contains missing segments or severe noise contamination (such as continuous packet loss or sampling anomalies), the period is discarded or improvised based on a missing threshold: if the missing percentage is <10%, trend imputation from adjacent periods is used and uncertainty is labeled; if the missing percentage is ≥10%, the period is labeled as low confidence and downweighted in subsequent analyses. The final output is a set of periodized response datasets: each period contains the original time-series waveform (resampled and baseline corrected), multi-resolution decomposed components, and a uniformly formatted periodic feature vector and quality label. This decomposition preserves transient fault information and provides a structured representation that can be directly used for periodic comparative analysis.

[0030] The first and last periods were determined from the periodic response dataset, and their complete features were extracted for differential comparison. The first period was defined as the first valid and quality-compliant period after the start of the operating condition (quality label: high confidence, missing percentage: less than 5%); the last period was defined as the last period that met the same quality conditions before the end of the operating condition or reached the set termination criteria in the continuous exposure period (e.g., cumulative damage reached a preset threshold or a continuous downward trend in key parameters was detected). The extraction process included strict alignment of the time reference, uniform sampling rate and amplitude scaling to ensure that the original waveforms during the two weeks could be directly compared point by point. To address the situation of different period lengths, the shorter period was first unified through time normalization (e.g., interpolation at 1000 points) and amplitude standardization (z-score), and then the two periods were aligned by dynamic time warping (DTW) to compensate for slow drift and phase deviation. During the extraction process, the statistical feature sets (mean, variance, skewness, kurtosis, peak value and frequency position of the energy spectrum, transient count, etc.) of the two periods are calculated and saved simultaneously, along with the confidence intervals of each feature (Bootstrap confidence intervals obtained based on sub-window resampling within the period). In addition, complete high-resolution transient waveform segments (e.g., ±10ms before and after triggering the peak) are additionally saved for key measurement points for high-precision comparison and fault location. If the first or last period is determined to have low confidence (e.g., noise contamination or sampling anomalies), it is rolled back to the next acceptable period, or, if necessary, marked as "uncomparable" and removed from subsequent analysis. The output of this step is two fully comparable and clearly quality-labeled periodic response data packages (first and last periods), containing waveform, time-frequency components, eigenvectors, and alignment mapping information, laying a solid data foundation for subsequent periodic difference analysis. After obtaining comparable data for the first and last periods, multi-level difference analysis is performed to identify parameters with significant response changes and label their severity and potential failure types. Difference analysis is divided into three main categories: direct difference test, statistical significance test, and multivariate distance assessment. The direct difference test calculates the absolute difference and relative rate of change for each feature. For example, if the median leakage current increases from 2.1µA to 18.5µA, the absolute difference is 17.4µA, representing a relative increase of approximately 828%. The same calculations are performed for peak jitter, interconnect impedance, etc., and compared with preset sensitivity thresholds (thresholds such as leakage current increase >200% or interconnect impedance change >10% trigger high concern). Statistical significance testing uses paired tests: when the feature data follows an approximately normal distribution, a paired t-test is used, providing the p-value and effect size (Cohen's d); for non-normal features or features containing outliers, a Wilcoxon paired sign test is used to obtain robust p-values. Confidence thresholds are set, for example, p < 0.01 and effect size > 0.8 is marked as "significant difference"; p between 0.01 and 0.05 and effect size moderate is marked as "suspicious difference".Multivariate distance assessment calculates the Mahalanobis distance or relative KL divergence of the eigenvectors of the first and last cycles to evaluate the overall behavioral shift. If the distance exceeds the chi-square distribution threshold (e.g., p < 0.001), it is labeled as "overall drift". Furthermore, to capture transient differences, the time-domain difference spectrum and frequency-domain power spectrum changes of key transient waveforms in the first and last cycles are compared, using short-time energy difference spectrum and dominant frequency shift as supplementary indicators. All labeled results include a causal chain: the characteristics of the change, the numerical difference, the confidence level, and the possible associated failure mechanisms (e.g., interface fracture leading to impedance surge or high-temperature migration leading to increased leakage current), and are categorized into three alarm levels (low / medium / high) based on severity. Finally, a differential report is generated, listing the labeled response difference test parameters and their quantitative indicators, recommended further diagnostic actions (e.g., extended exposure, probe local thermal stress increment testing, or electron microscopy interface inspection suggestions), and priority ranking, providing direct input for subsequent structural optimization and failure root cause localization.

[0031] In this embodiment, step S5 includes the following steps: Calculate the parameter difference value, change magnitude, change rate and change pattern of the response difference test parameters, and generate a difference parameter matrix; Fault state analysis is performed based on the limits of the difference parameter matrix to obtain the fault type and fault severity. Parameter drift gradient identification is performed based on the difference parameter matrix to generate parameter drift gradient directions; The fault location is determined by analyzing the direction of the parameter drift gradient. The fault type and fault severity are subjected to fault expansion evolution to generate a fault expansion range; The fault location and fault expansion range are analyzed, and the fault status is comprehensively quantified to generate test fault reports for various operating conditions. Based on the test fault report, local structural adjustments and overall topology optimization are performed at the fault location.

[0032] In this embodiment, four types of quantitative indicators are calculated for each of the labeled response difference test parameters: parameter difference value (Δ), magnitude of change (percentage or multiple), rate of change (rate of change per unit time), and change pattern (such as abrupt change, linear drift, exponential growth, or periodic fluctuation). The specific process is as follows: for each labeled parameter, the statistical representation of the first and last periods (such as median, mean, and peak value) is taken, and the absolute difference Δ is calculated as: Δ = (value - end) / (value - end). The value_first; and using the first period baseline as a reference, the relative change amplitude %Δ = Δ / |value_first| × 100%. The rate of change is obtained by dividing Δ by the equivalent exposure time between two periods, with units such as µA / hour, Ω / hour, or ps / hour. To identify change patterns, piecewise regression and model fitting are performed on the parameter time series throughout the exposure period: linear fitting, exponential fitting, piecewise linear fitting, and periodic component fitting are attempted, and the best model is determined using the fitting residuals and goodness of fit (e.g., R² or AIC). If the fit exhibits a step function and the residuals increase significantly before and after the step point, it is marked as "abrupt"; if the fit is a first-order polynomial and the fitting slope is significant, it is marked as "linear drift"; if the fit is exponential and the half-life / growth constant can be estimated, it is marked as "accelerated". In addition, the statistical changes in transient event counts and energy envelope are also used as inputs for pattern discrimination. For example, in the case of abnormal interconnect impedance, if multiple high-amplitude transition events are found to overlap in a short period of time, it is determined to be an "intermittent burst coupling" mode. All parameters are organized into four categories of indicators in matrix form: rows represent parameter IDs and measurement point locations, and columns represent Δ, %Δ, rate, mode identifier, and confidence level. Each matrix element simultaneously records the time base used for calculation, sample interval length, and confidence interval (e.g., 95%) for subsequent traceability analysis and threshold comparison. This difference parameter matrix provides direct numerical input for subsequent qualitative and quantitative fault identification. Using the difference parameter matrix as input, fault state analysis is performed to identify fault types (e.g., open circuit, short circuit, increased contact impedance, thermal migration, interface cracks, timing mismatch, etc.) and fault severity (mild, moderate, severe). The process includes multi-channel mapping rules and a discrimination tree: first, a mapping library from parameters to fault mechanisms is constructed. For example, a continuous increase in interconnect impedance accompanied by a local temperature rise and a decrease in current is mapped to "contact migration / interface passivation"; if leakage current rises sharply accompanied by frequent transient pulses and no significant temperature rise, it is mapped to "dielectric breakdown / local short circuit". A weight matrix is ​​set for each mapping, and the confidence score for each fault mechanism is calculated based on the magnitude and rate of parameter change. Next, Bayesian updates or weighted probability summation are used to normalize the scores of each mechanism to obtain the final fault probability distribution. The fault severity is determined by a multi-dimensional threshold rule: for example, if %Δ > 300% and the rate > threshold (e.g., leakage current > 10µA / hour) and the corresponding local temperature > 100℃, it is marked as "severe"; if %Δ is between 50% and 150% and accompanied by short-term reversible fluctuations, it is marked as "moderate"; below 50% and without a clear trend, it is marked as "mild". In addition, a multi-scale consistency check is introduced: if similar fault indications appear at adjacent measuring points or under similar operating conditions, the severity level is increased (because it may represent spatial scalability). The output includes the type, probability, severity rating, main supporting parameters and their contribution ratio for each fault candidate.This output is used to prioritize decisions (such as immediately stopping a certain type of exposure or switching to high-precision diagnostics) and provides causal clues for subsequent drift gradient identification and location.

[0033] Parameter drift gradient identification aims to identify the directionality and propagation trend of parameter changes from the perspective of spatial and electrical networks, providing a vector field for localization and extended analysis. The implementation consists of three steps: spatial interpolation field construction, gradient operator calculation, and mainstream vector extraction. First, spatial interpolation is performed on the difference parameter matrix based on the geometric coordinates of the measurement points (XY and hierarchical coordinates in a wafer mesh or multilayer topology). Kriging interpolation or radial basis function interpolation is used to generate a continuous parameter drift field (e.g., interconnect impedance drift field or leakage current increment field). During interpolation, the confidence level of the measurement points is retained as a weighting factor, and the weight of low-confidence points is reduced to minimize noise. Subsequently, numerical gradient operators (such as central difference or higher-order derivative approximations) are applied to this continuous field to calculate the gradient vector field, obtaining the direction (θ) and magnitude (|θ|) of each point. |), with units such as µA / mm or Ω / mm. To eliminate local noise, spatial smoothing (Gaussian or anisotropic diffusion filtering) is used, and a local consistency metric is calculated: if the gradient direction consistency of adjacent grids is greater than a threshold (e.g., greater than 70%), then that direction is considered a valid main current direction. Finally, principal component analysis (PCA) or streamline tracing methods are applied to extract several main drift direction vectors (e.g., diffusion from measurement point A to B and C), and these vectors are mapped back to the electrical topology (identified as diffusion along a power supply / signal path or cross-layer thermal channel). In addition, the flux intensity integral of the gradient field is calculated to assess the probability that a certain region is a "source" or "sink". The output is a set of parametric drift gradient directions, with each vector accompanied by the source probability, intensity, and spatial extent, so that the next stage of fault location and propagation prediction can use a vector field-driven method. The location process is based on coupled reasoning of gradient field and topology mapping. First, the drift gradient principal vectors are superimposed on the electrical / physical topology map: if the gradient direction gathers along one side of a power grid or signal bus, the fault source is preferentially searched at the line intersection or power supply node. A reverse streamline backtracking method is employed: tracing from the point of maximum intensity in the gradient field along the negative gradient direction (i.e., in reverse streamline direction) to a local maximum or gradient source to locate the candidate fault origin. To improve positioning accuracy, multivariate fusion is introduced: the reverse streamline results for different parameters (such as impedance, leakage current, and temperature) are cross-referenced, and the intersection region is used as the high-confidence positioning region. For example, the intersection of a gradient source with rising interconnect impedance and a local temperature peak in the reverse backtracking indicates that there may be interface cracks or bonding failures at that interface. Positioning accuracy is limited by the density of measurement points and interlayer observability. When outputting the position, the positioning algorithm simultaneously provides the uncertainty ellipse (e.g., center coordinates ±σ_x, ±σ_y) and the confidence value. For complex multi-source scenarios, a sparse solution method (L1 regularization) and Bayesian sparse regression are used to select the most probable small set from multiple candidate sources to avoid overfitting. The final result is a location report, which includes precise coordinates (in wafer coordinates or hierarchical mesh), adjacent critical structures (such as TSVs, microbumps, RDL nodes), and suggested follow-up verification actions (such as local microscopic inspection or targeted high stress loading), and provides a location reliability level (high / medium / low) to develop targeted solutions for subsequent fault propagation and repair.

[0034] Extended evolutionary analysis, based on a fault mechanism model and drift gradient field, aims to predict how faults will propagate and expand under the same or different operating conditions in the future. This analysis employs a coupled physics-probabilistic model: at the physical level, migration dynamics, thermo-mechanical coupling, and interface fatigue models (e.g., diffusion models, fatigue crack growth models) are used to model the propagation rate of the fault source under time and stress; at the probabilistic level, Markov chain or random walk models are used to describe the propagation probability of the fault between discrete network nodes. The process begins with the location results, calculating the failure propagation probability for neighboring structural nodes connected to the fault source (according to topological depths 1, 2, and 3). This probability is determined by the propagation medium (e.g., current density, heat flux, stress concentration) and node vulnerability. A weighted propagation matrix P is used, where P_ij represents the propagation probability from node i to j, and the propagation intensity accumulates over time: the failure probability vector at subsequent time points is obtained through power-law iterations of P. To introduce operating condition dependence, the propagation probability matrix is ​​parameterized for different temperatures, Vdd, and vibration spectra; for example, under high-temperature and high-power conditions, the inter-node propagation coefficient caused by metal migration may be amplified by 3 to 10 times. Based on a time step Δt (e.g., 1 hour or 1 cycle), equiprobability contour lines of the fault propagation range over time (e.g., 24 hours, 168 hours) can be obtained. The propagation range is represented by a region shape or a set of nodes, along with confidence intervals. Outputs include the most likely propagation path, propagation speed (e.g., mm / day or number of nodes / hour), predicted time to reach critical nodes (e.g., the power distribution network backbone), and a critical control window (within which intervention can reduce the propagation probability to an acceptable level). This information is used to formulate priority repair or design mitigation strategies, such as localized bond reinforcement, increasing redundant interconnects, or adjusting power distribution to reduce the propagation coefficient. After obtaining the location and propagation prediction results, comprehensive distribution analysis and situation quantification are performed to form a fault profile under multiple operating conditions. Distribution analysis includes spatial statistics and network statistics: spatial statistics use kernel density estimation (KDE) or frequency grids to visualize heatmaps of location events, identifying high-risk clusters and hotspots; network statistics rank the failure rate, degree centrality, and betweenness centrality of topology nodes to assess which nodes play a pivotal role in fault propagation. The situation quantification adopts a multi-indicator fusion scoring mechanism, which may include: local severity index (based on fault degree and impact radius), propagation risk coefficient (based on expansion rate and accessibility), business impact (if mapped to user impact score of on-chip functional modules), and repairability index (dependent on topology redundancy and reachability). Each indicator is weighted to synthesize an overall situation score S (e.g., 0~100), and the risk level is divided into low / medium / high / critical according to the score range.For multi-condition evaluation, the above analysis is repeated for each scenario (temperature, Vdd, load spectrum), generating a set of scenario-based fault reports. Each report lists scenario parameters, location results, extended predictions, situational scores, key affected nodes, and a recommended priority action list (e.g., immediate power domain disconnection, increased local cooling, or controlled decommissioning). The reports also include a confidence matrix and uncertainty source analysis, explaining the impact of location errors, model assumptions, and observation sparsity on the conclusions. The final output is a set of multi-condition test fault reports that can be used for decision-making, directly serving as a basis for on-site judgment, subsequent diagnostic evidence collection, and design improvements.

[0035] The report's findings were applied to feedback-based structural improvements, encompassing both local and global levels. Local structural adjustments involved targeted engineering measures for identified high-risk nodes: for bonding interface issues, increasing solder joint diameter or density (e.g., increasing microbump diameter from 25µm to 35µm and increasing density by 20%) was recommended; redundant microbump arrays or bypass wires were introduced at critical interconnects to reduce single-point failure rates; for thermal migration / metal migration issues, adding barrier layers at critical interconnects or using higher melting point metals to increase diffusion barriers at boundaries was suggested. Global topology optimization, based on vulnerability scoring and propagation path analysis, employed topology reconfiguration strategies: increasing redundancy, segmenting power domains to limit fault propagation, and adding monitoring nodes to improve observability. Topology optimization utilized graph theory and constrained programming: the objective function was to minimize the sum of weighted propagation risk and manufacturing cost; constraints included area limitations, power budget, and process feasibility. Optimization variables included node reconnection selection, RDL layer routing rerouting, TSV clustering location adjustment, and power bus segmentation. Example optimization results might involve changing a backbone bus from a single path to a three-segment parallel layout to reduce propagation reach by 50%, or adding local bypass capacitors in critical areas to buffer short-term voltage drops. To verify the effectiveness of the changes, the expected reduction in fault propagation coefficient and the area / power overhead of redundant modifications are calculated for the improved layout, and a cost-benefit comparison of alternative solutions is generated. Finally, an improvement recommendation list is compiled: detailing local structural modifications, topology adjustment schemes, expected risk reduction quantifications, and implementation priorities for each item, for use in subsequent manufacturing change implementation and long-term reliability assessments. This feedback loop transforms the fault intelligence obtained from testing into actionable structural improvements and topology optimization strategies, thereby enhancing the robustness and lifespan of the wafer-level testability structure.

[0036] In this embodiment, the specific steps for adjusting the local structure at the fault location and optimizing the overall topology layout based on the test fault report are as follows: Based on the test failure report, structural layer attribution analysis is performed to identify the failure attribution; Based on the fault attribution, production process parameters are adjusted to obtain adaptive fault process adjustment parameters; The test fault report is used to perform local structural adjustment at the fault location, generating local structural adjustment data; The overall topology layout is optimized based on local structure adjustment data to generate a second wafer structure model. Based on the second wafer structure model and the fault industrial adjustment parameters, test evaluation and optimization are performed, and the test optimization results are output.

[0037] In this embodiment, after receiving the multi-condition test failure report, a structural layer attribution analysis is first performed to clarify the root cause of the failure and its level. This analysis is based on a multi-layer chip structure model, mapping the fault location, type, and expansion trend to the physical functions of each layer. The attribution process unfolds from top to bottom, first identifying the fault's layer domain at the macroscopic level (e.g., interconnect layer, computing layer, storage layer, packaging layer), and then further locating it to the microscopic level (e.g., RDL copper layer, TSV via region, interface passivation film, or intermetallic dielectric region). A multi-index matching principle is used in attribution determination: if the fault type manifests as a sharp increase in impedance accompanied by thermal drift, it is preferentially attributed to metal interconnect fatigue or electromigration; if it manifests as a sudden increase in leakage current and a decrease in breakdown voltage, it tends to be due to dielectric aging or localized breakdown. The attribution matching degree is calculated by comparing the similarity between the difference parameter matrix (e.g., ΔR, ΔI_leak, temperature gradient change) in the test report and the characteristic library of typical failure modes for each layer (e.g., metal migration, charge trap growth, stress void formation). If the matching degree of a certain layer exceeds a threshold (e.g., similarity > 0.85), then that layer is determined to be the dominant fault layer. To further verify the rationality of the attribution, the relevant parameters of adjacent layers are compared. If the changes in adjacent layers are low and the trends are consistent, then the fault source is confirmed to be located within that layer. The attribution results are recorded in a hierarchical tree format, including layer number, physical location, main failure mechanism, relevant parameters, and matching confidence. The final output is an attribution list to guide the direction of subsequent process parameter adjustments and structural modifications. After clarifying the fault attribution, the production process parameters are adjusted in a targeted manner based on the root cause, forming an adaptive process adjustment scheme. The process parameter adjustment is centered on the attribution layer, combined with the manufacturing process parameters of that layer (e.g., deposition temperature, sputtering power, annealing temperature, chemical vapor deposition reaction time, metal filling rate, etc.) for differentiated adjustment. Taking interconnect layer electromigration as an example, if the impedance increase is due to copper diffusion, the grain size and interface density can be improved by adjusting the copper sputtering deposition rate (e.g., increasing from 0.6 nm / s to 0.9 nm / s) and annealing temperature (optimized from 380℃ to 420℃), thereby enhancing the anti-migration capability. If the fault layer is a dielectric layer, the breakdown strength can be improved by adjusting the chemical vapor deposition time (e.g., extending from 42 s to 58 s) or replacing it with a low dielectric constant material. An adaptive control approach is introduced during process parameter adjustment, setting feedback coefficients based on parameter fluctuation characteristics from previous test results. For example, if a parameter deviation in a specific process batch affects reliability by more than ±10%, the adjustment weight of that parameter is increased by a factor of 2, automatically biasing subsequent production towards the optimal range. Finally, an adaptive process adjustment parameter table is formed, including the target layer, adjustment items, adjustment range, and applicable operating conditions. This parameter set provides dynamic constraints in subsequent wafer structure redesign and testing evaluation, achieving closed-loop optimization of the process and structural layers.

[0038] Based on test failure reports and attribution analysis results, local structural adjustments were made to the fault-concentrated areas. The adjustment goals were to weaken failure-sensitive points, balance stress distribution, and reduce local heat concentration. The adjustment methods were categorized into three types: geometric compensation, material reinforcement, and conductive path redistribution. Geometric compensation targets micro-bump arrays or TSV regions experiencing stress concentration by smoothing the local stress gradient by changing the layout density or cell size. For example, adjusting the TSV diameter from 2.5µm to 3.0µm and increasing the spacing from 10µm to 12µm reduces the vertical stress peak by approximately 15%. Material reinforcement introduces high-reliability materials into the dielectric layer or metal interface, such as adding a 0.5µm thick tantalum-nitrogen barrier layer at the copper interconnect-dielectric interface, or introducing a low-stress polyimide buffer film into the encapsulation layer to improve interface matching. Conductive path redistribution increases redundancy by changing the interconnect routing and the number of interlayer vias. For example, adding a parallel path on a critical signal line increases local conductivity redundancy to 120%, significantly reducing the probability of single-point failure. During the adjustment process, the thermal expansion mismatch of the material (CTE mismatch < 5 × 10) is calculated. -6 / ℃) and upper limit of current density (J_max<1.5×10) 6 (A / cm²) to ensure stable performance after adjustment. After adjustment, local structural adjustment data is output, including corrected coordinates, geometric parameters, material properties, adjustment ratios, and predicted thermal-stress distribution values, providing foundational data for subsequent overall topology optimization. After completing the local structural adjustment, its results are integrated with the overall wafer design to form a new global topology layout scheme. The goal of overall optimization is to minimize potential fault propagation paths and stress concentration areas while maintaining the original performance indicators (bandwidth, latency, power consumption). Optimization first reconstructs the network topology on the full-layer structural model, updates the node properties corresponding to the adjusted areas (such as material modulus, conductivity, thermal conductivity, etc.), and recalculates path weights through connectivity analysis. A layered optimization strategy is adopted: current distribution and path balancing are optimized at the interconnect layer level; heat dissipation and mechanical support are optimized at the packaging layer level. For example, by adjusting the routing of local interconnects, the average interconnect length is shortened by approximately 8%, while the maximum temperature rise is reduced by approximately 5°C. To prevent parasitic effects introduced by topology optimization, equivalent network analysis is used to verify signal integrity, ensuring that signal attenuation is less than 0.5dB / mm. After optimization, the uniformity of thermal distribution was reassessed, with the goal of limiting heat flux density variation to within ±10%. A second wafer structure model was then generated, incorporating updated geometry, material configuration, interconnect paths, and stress distribution information. This model not only exhibits greater structural robustness but also provides a new design benchmark for subsequent failure verification and reliability prediction of testable structures.

[0039] The final stage involves combining the optimized wafer structure model with adaptive process adjustment parameters to conduct comprehensive testing and evaluation. The purpose of this process is to verify the effectiveness of the optimization measures and quantify the degree of improvement. The evaluation includes: reliability improvement, changes in fault exposure time, the effect of local stress distribution adjustment, and overall power consumption and latency changes. Based on the previously defined operating scenarios, multi-parameter loading is applied to the second wafer structure model to calculate changes in key performance parameters. For example, at a high temperature of 125°C, the interconnect impedance change rate is reduced by approximately 42% compared to the initial design, and the power consumption fluctuation amplitude is reduced to 70% of its original value, indicating a significant reduction in electromigration risk. Further analysis is conducted at low temperatures... Using signal delay test results at 20℃ as a reference, a path delay stability improvement of approximately 15% was found. Furthermore, the signal integrity and redundancy path accessibility of the testability structure were reviewed to ensure coverage ≥98%. Sensitivity analysis was performed on the impact of process adjustment parameters during the evaluation to ensure reliable operation of the structure within a process deviation range of ±5%. All evaluation indicators were summarized to form the test optimization results, including a performance comparison table, a reliability index change graph, and a quantitative table of optimization benefits. For example, the reliability lifetime improvement factor reached 1.8 times, power consumption was reduced by approximately 12%, and the probability of local failure decreased by 60%. The test optimization results ultimately serve as the output of the design closed loop, providing a clear basis for continuous improvement of wafer-level testability structures, adaptive control of manufacturing processes, and optimization of subsequent product versions.

[0040] In this embodiment, an HBF chip wafer-level testability structure generation apparatus is provided for performing the HBF chip wafer-level testability structure generation method described above, including: The test structure unit is used to construct the first wafer test structure based on the HBF chip requirement design drawing and to build a distributed topology. The extreme condition fitting unit is used to perform extreme condition application analysis and set of condition parameters based on the HBF chip requirement design drawing, and to build an extreme test framework. The test unit is used to perform dynamic operation tests on the first wafer test structure based on the extreme test framework to obtain a standardized response dataset. The periodic difference unit is used to perform periodic parameter difference analysis based on the standardized response dataset and to label the response difference test parameters. The structural optimization unit is used to perform fault state analysis and topology layout optimization based on response difference test parameters, and output the test optimization results.

[0041] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0042] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein are implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for generating a wafer-level testability structure for an HBF chip, characterized in that, Includes the following steps: Step S1: Based on the HBF chip requirement design, construct the distributed topology and build the first wafer test structure; Step S2: Based on the HBF chip requirement design drawing, perform extreme operating condition application analysis and set of operating condition parameters to build an extreme test framework; Step S3: Perform dynamic operation tests on the first wafer test structure under each working condition based on the extreme testing framework to obtain a standardized response dataset; Step S4: Perform periodic parameter difference analysis based on the standardized response dataset and label the response difference test parameters; Step S5: Perform fault state analysis and topology layout optimization based on response difference test parameters, and output the test optimization results.

2. The method for generating HBF chip wafer-level testability structures according to claim 1, characterized in that, The specific steps of step S1 are as follows: Based on the HBF chip requirement design diagram, we analyze the usage requirements and extract multiple requirement indicators. The multiple requirements indicators include performance indicators, power consumption constraints, application scenarios, and reliability targets; Design multiple structural layers based on multiple demand indicators to generate a multi-layered structure; Based on multiple demand indicators, wafer microstructure and electronic circuit layout analysis is performed to obtain wafer microstructure and electronic circuit layout data. Based on the wafer microstructure and electronic circuit layout data, a distributed topology of the multilayer structure is constructed to build the first wafer test structure.

3. The method for generating HBF chip wafer-level testability structures according to claim 1, characterized in that, The specific steps of step S2 are as follows: Based on the HBF chip requirement design diagram, multi-extreme operating condition application analysis is performed to identify the chip's potential extreme operating conditions. The extreme working conditions are fitted with extreme working condition parameter boundaries to generate the parameter range for each working condition; Construct multiple extreme operating condition scenarios based on the parameter range; Based on the aforementioned multi-extreme operating conditions, the fault exposure time constant, reliability stress accumulation probability, and test resource constraints are determined, and the test time for each operating condition is planned. Based on the test time for each operating condition and the limits of the multiple extreme operating conditions, a comprehensive test architecture is generated to construct an extreme test framework.

4. The method for generating HBF chip wafer-level testability structures according to claim 1, characterized in that, Step S3 is as follows: Based on the extreme testing framework, dynamic operation testing of the first wafer test structure was carried out under each working condition, and the test response signal under each working condition was extracted. The test response signal is used to identify the response parameter type and to label different response parameters; By comprehensively analyzing different response parameters, a test response dataset is obtained. Anomaly parameters were detected and outliers were removed from the test response dataset to obtain a standardized response dataset.

5. The method for generating HBF chip wafer-level testability structures according to claim 1, characterized in that, The specific steps of step S4 are as follows: The adaptive duration is divided according to the test time of each working condition to obtain the adaptive cycle point; The standardized response dataset is dynamically decomposed based on adaptive period points to extract test response data from multiple periods. Extract the test response data of the first cycle and the test response data of the last cycle based on test response data from multiple cycles; Perform cycle parameter difference analysis on the test response data of the first cycle and the test response data of the last cycle, and mark the test parameters of response difference.

6. The method for generating HBF chip wafer-level testability structures according to claim 1, characterized in that, The specific steps of step S5 are as follows: Calculate the parameter difference value, change magnitude, change rate and change pattern of the response difference test parameters, and generate a difference parameter matrix; Fault state analysis is performed based on the limits of the difference parameter matrix to obtain the fault type and fault severity. Parameter drift gradient identification is performed based on the difference parameter matrix to generate parameter drift gradient directions; The fault location is determined by analyzing the direction of the parameter drift gradient. The fault type and fault severity are subjected to fault expansion evolution to generate a fault expansion range; The fault location and fault expansion range are analyzed, and the fault status is comprehensively quantified to generate test fault reports for various operating conditions. Based on the test fault report, local structural adjustments and overall topology optimization are performed at the fault location.

7. The method for generating HBF chip wafer-level testability structures according to claim 6, characterized in that, The specific steps for adjusting the local structure at the fault location and optimizing the overall topology layout based on the aforementioned test fault report are as follows: Based on the test failure report, structural layer attribution analysis is performed to identify the failure attribution; Based on the fault attribution, production process parameters are adjusted to obtain adaptive fault process adjustment parameters; The test fault report is used to perform local structural adjustment at the fault location, generating local structural adjustment data; The overall topology layout is optimized based on local structure adjustment data to generate a second wafer structure model. Based on the second wafer structure model and the fault industrial adjustment parameters, test evaluation and optimization are performed, and the test optimization results are output.

8. An apparatus for generating HBF chip wafer-level testability structures, characterized in that, The method for performing the HBF chip wafer-level testability structure generation method as described in claim 1 includes: The test structure unit is used to construct the first wafer test structure based on the HBF chip requirement design drawing and to build a distributed topology. The extreme condition fitting unit is used to perform extreme condition application analysis and set of condition parameters based on the HBF chip requirement design drawing, and to build an extreme test framework. The test unit is used to perform dynamic operation tests on the first wafer test structure based on the extreme test framework to obtain a standardized response dataset. The periodic difference unit is used to perform periodic parameter difference analysis based on the standardized response dataset and to label the response difference test parameters. The structural optimization unit is used to perform fault state analysis and topology layout optimization based on response difference test parameters, and output the test optimization results.

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