Full closed loop gate drive circuit for turn-off process optimization and control method thereof

Abstract

The application discloses a full-closed-loop gate drive circuit for shutdown process optimization and a control method thereof, which comprises a resistance voltage division network, a demand reference waveform generating unit, a proportional-integral control unit and an insulated gate bipolar transistor (IGBT). CE The resistance voltage division network is connected to the proportional-integral control unit after voltage division, the demand reference waveform generating unit is connected to the proportional-integral control unit, and the demand reference voltage V REF output by the demand reference waveform generating unit is compared with a feedback quantity after voltage division, an error signal generated is processed by the proportional-integral control unit to obtain a gate drive voltage V G , and finally fed to a gate drive circuit of the IGBT, so that a closed-loop control is formed. The amplitude of a pre-bias voltage is significantly reduced, and the additional power loss in a pre-bias processing stage is reduced.

Description

Technical Field

[0001] This invention belongs to the technical field of fully closed-loop gate drive circuits, and particularly relates to a fully closed-loop gate drive circuit and its control method for optimizing the turn-off process. Background Technology

[0002] With the rapid development of modern power electronics technology, Insulated Gate Bipolar Transistors (IGBTs), as an important power switching device, have been widely used in various application fields. However, electromagnetic interference (EMI) is a common and serious problem in the operating environment of IGBTs. The high-speed switching characteristics of IGBTs result in large voltage and current change rates (dvce / dt and dic / dt) during the switching process. These rapidly changing signals contain a large number of high-frequency components, extending over a wide frequency range, thus leading to EMI. This electromagnetic radiation propagates in the form of electromagnetic waves and can negatively impact surrounding electronic equipment, communication systems, and measurement systems. Therefore, the requirements for the dynamic performance of IGBT switching are becoming increasingly stringent, such as lower voltage stress, higher switching frequency, faster switching speed, and higher efficiency. Precise control of the IGBT switching process is usually achieved by optimizing the gate drive circuit.

[0003] To overcome this limitation, various active gate drive (AGD) technologies have emerged. AGD is mainly divided into open-loop and closed-loop types, with closed-loop types offering better control performance. However, existing closed-loop drive schemes have the following drawbacks: due to the bandwidth limitation of the drive circuit, many existing schemes struggle to achieve ideal full closed-loop control. To achieve full closed-loop control, one existing scheme is based on a pre-processing AGD strategy, which allows the IGBT to enter the broadband region earlier during the pre-processing stage. However, this method introduces significant additional power losses. To overcome the shortcomings of existing research, this invention proposes a closed-loop AGD scheme based on desaturation bias voltage.

[0004] Closed-loop AGD: Due to the high-speed switching characteristics of IGBTs, the bandwidth of the drive circuit is difficult to meet the control requirements. Closed-loop control will produce hysteresis control or control delay. The turn-off voltage waveform cannot strictly follow the changes of the required reference voltage waveform and often lags behind the required reference voltage waveform.

[0005] AGD strategy based on pre-processing: Using pre-bias voltage, the IGBT enters the broadband region in advance, thereby meeting the bandwidth requirements of the drive circuit and realizing closed-loop control. However, the pre-bias voltage processing stage will introduce significant additional power loss, and the bias voltage amplitude is relatively high. Summary of the Invention

[0006] The purpose of this invention is to provide a fully closed-loop gate drive circuit and its control method for optimizing the turn-off process, so as to solve the above-mentioned problems.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A fully closed-loop gate drive circuit for optimizing the turn-off process includes a resistor divider network, a demand reference waveform generation unit, a proportional-integral control unit, and an insulated-gate bipolar transistor (IGBT); the collector-emitter voltage V of the IGBT. CE The voltage is divided by a resistor divider network and then connected to the proportional-integral control unit. The required reference waveform generation unit is connected to the proportional-integral control unit, and the required reference voltage V is output by the required reference waveform generation unit. REF The error signal generated by comparing the feedback quantity after voltage division with the error signal is processed by the proportional-integral control unit to obtain the gate drive voltage V. G And finally fed to the gate drive circuit of the IGBT to form a closed-loop control.

[0008] Furthermore, the resistor divider network includes several resistors, each with a capacitor connected in parallel, for outputting a signal V that is reduced by a factor of 100. CE / 100.

[0009] Furthermore, the demand reference waveform generation unit includes two NOT gate NANDs, an RC circuit, an integrator, two first operational amplifiers, and a non-inverting summation circuit; the input signal Input is connected to the two NOT gate NANDs respectively, and each NOT gate NAND is equipped with an RC circuit; the output terminals of the two NOT gate NANDs are respectively connected to the first operational amplifiers, and each first operational amplifier is equipped with an integrator; the output terminals of the two first operational amplifiers are connected to the non-inverting summation circuit.

[0010] Furthermore, the RC circuit includes a capacitor and a resistor. The NAND gate has two input terminals. One end of the resistor in the RC circuit is connected to the input signal Input, and the other end is connected to one of the input terminals. One end of the capacitor in the RC circuit is connected to the resistor, and the other end is grounded. The other input terminal of the NAND gate is connected to the input signal Input.

[0011] Furthermore, the integrator includes two resistors and one capacitor. The capacitor of the integrator is connected in parallel with the first operational amplifier. One end of one resistor of the integrator is connected to the output terminal of the NAND gate, and the other end is connected to the negative input terminal of the first operational amplifier. One end of the other resistor of the integrator is connected to the negative input terminal of the first operational amplifier, and the other end is connected to the voltage source V. ee .

[0012] Furthermore, a Zener diode D1 is connected in parallel with one of the first operational amplifiers.

[0013] Furthermore, the in-phase summing operation circuit includes a second operational amplifier and resistors R5, R6, R7, R8, and R9. One end of resistors R5 and R6 are respectively connected to the output terminals of the two first operational amplifiers, and the other end of each is connected to the negative input terminal of the second operational amplifier. One end of resistor R7 is connected to the input signal Input, and the other end is connected to the negative input terminal of the second operational amplifier. One end of resistor R9 is connected to the positive input terminal of the second operational amplifier, and the other end is connected to the output terminal of the second operational amplifier. 8一端 It is connected to resistor R9, and the other end is grounded.

[0014] Furthermore, the proportional-integral control unit includes two operational amplifiers A, a buffer amplifier B, and a pair of driving MOSFETs; the two operational amplifiers A are connected in series, the output of operational amplifier A is connected to buffer amplifier B, the output of buffer amplifier B is connected to the pair of driving MOSFETs, and the output gate drive voltage V is... G .

[0015] Furthermore, the operational amplifier A is selected as LM7171, and the buffer amplifier B is BUF634A.

[0016] A control method for a fully closed-loop gate drive circuit for optimizing the turn-off process includes the following steps: The shutdown instruction is initiated, generating the demand reference waveform VREF. When the input signal Input switches to the shutdown instruction, the demand reference waveform generation unit is activated. First, the Input signal is input to two NAND gates with RC circuits. One input is directly connected to Input, and the other is connected to Input through an RC circuit. The charging and discharging characteristics of the RC circuit are used to adjust the shutdown delay time. Subsequently, the output signals of the two NAND gates are fed into the first operational amplifier with an integrator. The integrator consists of an operational amplifier LT1810 and a voltage source V. eeComposed of resistors and capacitors, the slope of the dv / dt reference waveform is set by adjusting the integrator parameters, and the Zener diode D1 limits the operational amplifier output saturation level Vpeak. Finally, the output signals of the two first operational amplifiers are weighted and summed with the input signal through a non-inverting summing circuit to generate the final required reference voltage V. REF This provides a standard control baseline for the shutdown process; After the IGBT enters the turn-off process, its collector-emitter voltage V CE Sampling is performed using a resistor divider network, which consists of several resistors, each with a capacitor connected in parallel to ensure sampling stability. The final output is a feedback signal V reduced by a factor of 100. CE / 100, to achieve V CE The signal undergoes a step-down preprocessing step to prevent high-voltage signals from damaging subsequent control units, while also ensuring compatibility with the required reference voltage V. REF The matching comparison provides conditions; The obtained feedback signal V CE / 100 is sent to the proportional-integral control unit, along with the generated required reference voltage V. REF A real-time comparison is performed to obtain the error signal between the two; this error signal is processed by a PI controller composed of two LM7171 operational amplifiers connected in series to eliminate static error and optimize dynamic response, and then the output current of the PI controller is amplified by a BUF634A buffer amplifier. The control signal processed by the proportional-integral control unit is further boosted by a pair of driving MOSFETs to generate the gate drive voltage V. G And feed it to the gate drive circuit of the IGBT; V G It acts on the IGBT gate to adjust the IGBT's turn-off speed, while simultaneously adjusting the IGBT's V... CE It updates in real time according to the change of the turn-off state, and samples the feedback again through the resistor voltage divider network. The process is repeated to form a continuous closed-loop control until the IGBT completes stable turn-off, thus achieving optimized control of the turn-off process.

[0017] Compared with the prior art, the present invention has the following technical effects: This invention enables IGBTs to enter the broadband region in advance before turn-off, thereby meeting the bandwidth requirements of the closed-loop drive circuit, realizing full closed-loop control, and ensuring that the turn-off voltage waveform strictly follows the changes in the required reference voltage waveform, thereby accurately controlling the turn-off voltage change rate dvce / dt and suppressing turn-off voltage spikes. Significantly reduce the amplitude of the pre-bias voltage, thereby reducing additional power loss during the pre-bias processing stage. Attached Figure Description

[0018] Figure 1This is a diagram showing the overall structure of the closed-loop control for desaturation bias voltage in this invention.

[0019] Figure 2 This is the resistor voltage divider network of the present invention.

[0020] Figure 3 The circuit diagram of the waveform generator is provided for reference in this invention.

[0021] Figure 4 These are the three bias voltage waveforms of the present invention.

[0022] Figure 5 This is the derivation of the required reference waveform for the present invention, taking the hybrid wave bias voltage as an example.

[0023] Figure 6 This invention relates to a proportional-integral (PI) control circuit.

[0024] Figure 7 This is the turn-off waveform of the present invention under square wave bias voltage control. The magnitude of the bias voltage is (a) 100V and (b) 15V.

[0025] Figure 8 This is the turn-off waveform under the slope bias voltage control of the present invention. The right side is an enlarged view of the shaded area.

[0026] Figure 9 This is the turn-off waveform under the hybrid wave bias voltage control of the present invention; the right side is an enlarged view of the shaded area.

[0027] Figure 10 For the turn-off waveform of this invention: different dv / dt reference voltages are set using capacitors of 25, 50 and 100 pF.

[0028] Figure 11 The turn-off waveforms of this invention are: reference voltages with saturation levels Vpeak of 830V, 850V, and 900V, respectively. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings: Example 1, please refer to Figure 1 This invention provides a fully closed-loop gate drive circuit for optimizing the turn-off process, including a resistor divider network, a demand reference waveform generation unit, a proportional-integral control unit, and an insulated-gate bipolar transistor (IGBT); the collector-emitter voltage V of the IGBT... CE The voltage is divided by a resistor divider network and then connected to the proportional-integral control unit. The required reference waveform generation unit is connected to the proportional-integral control unit, and the required reference voltage V is output by the required reference waveform generation unit. REF The error signal generated by comparing the feedback quantity after voltage division with the error signal is processed by the proportional-integral control unit to obtain the gate drive voltage V.G And finally fed to the gate drive circuit of the IGBT to form a closed-loop control.

[0030] Example 2: This invention provides a fully closed-loop gate drive circuit for optimizing the turn-off process, specifically: A resistor divider network consists of several resistors, each with a capacitor connected in parallel, used to output a signal V that is reduced by a factor of 100. CE / 100.

[0031] The demand reference waveform generation unit includes two NAND gates, an RC circuit, an integrator, two first operational amplifiers, and a non-inverting summation circuit. The input signal is connected to the two NAND gates respectively, and each NAND gate is equipped with an RC circuit. The output terminals of the two NAND gates are connected to the first operational amplifiers respectively, and each first operational amplifier is equipped with an integrator. The output terminals of the two first operational amplifiers are connected to the non-inverting summation circuit.

[0032] An RC circuit includes a capacitor and a resistor. A NAND gate has two input terminals. One end of the resistor in the RC circuit is connected to the input signal Input, and the other end is connected to one of the input terminals. One end of the capacitor in the RC circuit is connected to the resistor, and the other end is grounded. The other input terminal of the NAND gate is connected to the input signal Input.

[0033] The integrator includes two resistors and one capacitor. The capacitor of the integrator is connected in parallel with the first operational amplifier. One end of one resistor of the integrator is connected to the output of the NAND gate, and the other end is connected to the negative input of the first operational amplifier. One end of the other resistor of the integrator is connected to the negative input of the first operational amplifier, and the other end is connected to the voltage source V. ee .

[0034] One of the first operational amplifiers also has a Zener diode D1 connected in parallel.

[0035] The non-inverting summation circuit includes a second operational amplifier and resistors R5, R6, R7, R8, and R9. One end of resistors R5 and R6 are connected to the outputs of the two first operational amplifiers, and the other end of each is connected to the negative input of the second operational amplifier. One end of resistor R7 is connected to the input signal, and the other end is connected to the negative input of the second operational amplifier. One end of resistor R9 is connected to the positive input of the second operational amplifier, and the other end is connected to the output of the second operational amplifier. 8一端 It is connected to resistor R9, and the other end is grounded.

[0036] The proportional-integral control unit includes two operational amplifiers A, a buffer amplifier B, and a pair of driver MOSFETs; the two operational amplifiers A are connected in series, the output of operational amplifier A is connected to buffer amplifier B, and the output of buffer amplifier B is connected to the pair of driver MOSFETs, with an output gate drive voltage V. G .

[0037] Example 3: The present invention provides a fully closed-loop gate drive circuit for optimizing the turn-off process, comprising: Circuit structure: The overall structure diagram of the fully closed-loop gate drive circuit with optimized turn-off process is shown below. Figure 1 As shown, the specific implementation circuits for each part are labeled in the attached diagram. In the driver circuit, operational amplifier A is selected as LM7171, which has a unity-gain bandwidth of 200MHz and a slew rate of up to 4100 V / µs. Buffer amplifier B uses BUF634A, which has a maximum unity-gain bandwidth of up to 210 MHz and an output current of 250 mA.

[0038] Where V CE The voltage feedback ratio is 100:1, achieved through a resistor divider network, resulting in a signal V that is approximately reduced by a factor of 100. CE / 100, such as Figure 2 As shown.

[0039] Requirements for reference waveform generation circuit, such as Figure 3 As shown. The requirement reference waveform consists of two parts: a dv / dt reference waveform and a desaturation bias voltage waveform. There are three types of desaturation bias voltage waveforms (the first type, a square wave bias voltage, is the existing scheme mentioned in the background: a pre-processed AGD strategy. The latter two are the improved schemes proposed in this invention). Figure 4 As shown. Figure 5 The required reference waveform is composed of a mixed-wave bias voltage and a dv / dt reference waveform.

[0040] Figure 3 The specific working steps of the circuit are as follows: The generator's input signal is a 0 / 5V square wave, where 0V indicates on and 5V indicates off. v / d t The required delay time for the reference waveform ( Figure 5The time interval between the two dashed lines in the middle diagram (the time interval) is implemented using a NAND gate and an R1-C1 circuit. (A NAND gate has two inputs and one output. The output of the NAND gate is 0 only when all inputs are high. Here, an input voltage greater than 2.5V is recognized as a high level; otherwise, the output is 5V.) The specific implementation process is as follows: One input of the NAND gate (denoted as x1 for ease of description) is directly connected to the Input terminal, and the other input (denoted as y1) is connected to the Input terminal through the R1-C1 circuit. The output terminal is denoted as z1. When the shutdown begins, the Input signal changes from 0V to 5V. At this time, the input signal at x1 is 5V, which is recognized as a high level. The voltage at y1 is slowly charged from 0V to 5V through the R1-C1 circuit. When the voltage at y1 rises to 2.5V, it is recognized as a high level, and the output terminal z1 changes from 5V to 0V. The delay time can be adjusted by adjusting the values ​​of R1 and C1.

[0041] d v / d t The slope of the reference waveform is determined by the op-amp LT1810 and the voltage source V. ee The integrator, consisting of (-5 V) and R3, R4, and C3, generates the saturation level V, where R3 = R4. peak The voltage is set by Zener diode D1. The specific implementation process is as follows: Due to the virtual short and virtual open characteristics of the op-amp, its negative input voltage V- is equal to its positive input voltage V+. Since the positive input is grounded, both are 0V. When the output z1 of the upper NAND gate is 5V, since Vee=-5V and R3=R4, the current flowing through R3 is equal to the current flowing through R4. The current flows from the NAND gate output z1 through R3 and R4 into V+. ee No current flows through C3, and the output of op-amp LT1810 remains at 0V. This corresponds to the aforementioned delay time. When the output z1 of the upper NAND gate becomes 0V, since both ends of R3 are at 0V, there is no current flowing through R3. At this time, the current flow direction changes to: from the output of op-amp LT1810 through C3 and R4 into V. ee And the charging current is always I = -V ee / R4, by I=C3d v / d t Therefore, the output voltage rise rate d of the op-amp LT1810 is... v / d t =I / C3, by adjusting the value of C3, d can be adjusted. v / d t That is, d v / d tRefer to the slope of the waveform. By selecting Zener diodes D1 with different voltage regulation values, the maximum value of the output voltage of the operational amplifier LT1810 can be limited, thereby setting the saturation level V. peak .

[0042] The slope of the ramp component in the mixed-wave bias voltage is determined by the op-amp LT1810 and the voltage source V. ee An integrator consisting of (-5 V) resistors and resistors R3, R4, and C4. The delay of the slope component is set by the NAND gate and the R2-C2 circuit. The specific method is the same as described above and will not be repeated.

[0043] The square wave component in the mixed-wave bias voltage is directly taken from the input signal Input.

[0044] Finally, the operational amplifier LT1815 and resistors R5, R6, R7, R8, and R9 form a non-inverting summing circuit for d. v / d t The reference waveform and the desaturation bias voltage reference waveform are weighted and summed to generate the final required reference waveform V. REF .

[0045] Example 4: The present invention provides a control method for a fully closed-loop gate drive circuit for optimizing the turn-off process, comprising: In the feedback control loop, two LM7171 operational amplifiers (A1, A2) form a proportional-integral (PI) controller. The collector-emitter voltage V of the IGBT is... CE pass Figure 2 V obtained from the resistor voltage divider network in CE / 100 is sampled as the feedback quantity and compared with... Figure 3 The required reference voltage V obtained from the process REF The comparison is performed. The resulting error signal is processed by the PI controller to generate a control signal, which is then amplified by the BUF634A buffer amplifier to amplify the PI controller's output current. The buffer's output power is boosted by a pair of driving MOSFETs to obtain the gate drive voltage V. G And finally fed into the IGBT gate drive circuit, forming a closed-loop control. The specific circuit of this process is as follows: Figure 6 As shown.

[0046] Control effect: (1) Square wave bias voltage control effect (existing scheme) The turn-off waveform of the IGBT with a square wave bias voltage at an operating voltage of 800 V is as follows: Figure 7 As shown. After desaturation treatment with a 100 V square wave bias voltage, V CE It can approximate the required reference waveform V REF ,like Figure 7As shown in (a). However, during the desaturation phase, after a typical delay time, V CE Instead of stabilizing directly at the step level, a significant overshoot Vov appeared, with an amplitude of 432.13 V. This overshoot phenomenon, combined with the delay process, leads to significant additional turn-off losses.

[0047] like Figure 7 As shown in (b), an attempt was made to reduce voltage overshoot and losses by decreasing the amplitude of the square wave voltage. The amplitude of the square wave voltage was reduced from 100 V to 15 V. However, during the desaturation phase, the device did not enter the broadband region, leading to subsequent losses. vce / d t Closed-loop control failed.

[0048] (2) Effect of ramp bias voltage control (improved solution of this invention) Figure 8 The diagram shows the turn-off waveform using a ramp bias voltage, with all operating conditions remaining constant. (Example:) Figure 8 As shown, the desaturation stage and V CE The system operates normally and performs stably during the ascent phase.

[0049] During the desaturation phase, after a typical delay, although V CE It still doesn't closely follow the bias voltage, but its overshoot has significantly decreased, such as... Figure 8 As shown. Compared to the square wave bias scheme, Vov drops to 28.51 V, effectively reducing the additional turn-off losses caused by voltage over-adjustment during the desaturation stage. However, since the ramp bias voltage rises relatively slowly, the required reference voltage V is higher in the early stages of desaturation. REF Compared with the actual collector-emitter voltage V CE The difference is small, and the error signal accumulation rate of the closed-loop control is slow, resulting in a longer desaturation time. Although the overshoot loss Eov is reduced, it will cause a relatively large delay loss Edel, resulting in a total loss E during the desaturation process. des = E ov + E del It is still quite large.

[0050] (3) Effect of hybrid wave bias voltage control (improved solution of this invention) Combining the advantages of the two schemes above, Figure 9 The mixed-wave bias voltage turn-off waveform is displayed.

[0051] like Figure 9 As shown, this scheme applies a square wave bias voltage during the early stage of desaturation to accelerate the accumulation of closed-loop control error, thereby shortening the desaturation time t. des Reduce latency loss E delIn the later desaturation stage, switching to a ramp bias voltage can effectively reduce Vov to 32.15 V, as shown below. Figure 9 As shown, this reduces the overadjustment loss E generated during the desaturation stage. ov .

[0052] (4) Comparison of three bias voltage control schemes Table 1 summarizes the additional turn-off losses and desaturation times caused by using different desaturation bias voltages.

[0053] Table 1. Comparison of desaturation performance under three bias voltages

[0054] The hybrid-wave bias voltage scheme has significant advantages in overall desaturation performance. While maintaining the drive amplitude V... amp Under a voltage of 10 V, the overvoltage V during the desaturation stage can be effectively suppressed. ov The voltage drops to 32.15 V, a 93% reduction from the square wave's 432.13 V, with an overshoot loss E ov The energy dissipation is only 1.198 mJ. Meanwhile, the hybrid wave achieves an optimal balance between desaturation time and loss. Its desaturation time is shorter than that of a square wave but much shorter than that of a ramp wave, while its desaturation loss is 65% lower than that of a square wave and significantly lower than that of a ramp wave. This indicates that the hybrid wave, by coordinating dynamic response and energy consumption, significantly improves the system's energy efficiency while ensuring the system's desaturation rate, making it the best-performing desaturation strategy overall.

[0055] (5) The IGBT turn-off voltage V under the AGD strategy based on the hybrid wave bias voltage CE Closed-loop control effect reference voltage d v / d t The slope can be adjusted Figure 3 Adjust according to the value of capacitor C3 in the reference voltage generator. For example... Figure 10 As shown, under the premise that the drive signal trigger time and desaturation time are the same, the corresponding d values ​​under three different C3 values ​​are tested. vce / d t Waveform. The results show that as the value of C3 increases, the required reference waveform d v / d t Decrease, d vce / d t It also decreases accordingly. When C3 is 25pF, 50pF, and 100pF, V CE The slopes are 1830 Vµs, 1020 Vµs, and 548 Vµs, respectively. This indicates that this method can control the IGBT turn-off voltage V. CE The waveform is well controlled in a closed loop.

[0056] The saturation level V of the required reference voltage waveform peak can be Figure 3 Zener diode D1 adjustment. For example... Figure 11 (As shown in the diagram, due to the large area of ​​overlap in the waveforms, each waveform has been appropriately horizontally offset for easier viewing.) Under the premise that other conditions remain unchanged, the saturation level of the reference voltage is changed.

[0057] The results show that as V peak The decrease of V is equivalent to CE Active clamping. This results in a reduced rate of charge extraction from the gate via closed-loop feedback, thereby slowing the rate of collector current decline. Collector current decline rate d ic / d t The reduction in Ls decreases the induced electromotive force Ls caused by the stray inductance Ls in the circuit. dic / d t This reduces the overshoot of the turn-off voltage.

[0058] This invention enables precise closed-loop control of the turn-off voltage waveform by adjusting the demand reference voltage waveform, ensuring that the turn-off voltage waveform strictly follows the changes in the demand reference voltage waveform. This allows for precise control of the turn-off voltage change rate d. vce / d t ,like Figure 10 As shown, by adjusting C3 to change the dv / dt of the required reference voltage, the turn-off voltage d can be precisely controlled. vce / d t It can suppress turn-off voltage spikes, such as Figure 11 As shown, the saturation level V of the required reference voltage is reduced by adjusting D1. peak This suppresses turn-off voltage spikes.

[0059] This invention significantly reduces the amplitude of the pre-bias voltage and the additional power loss in the pre-bias processing stage. As shown in Table 1, the proposed hybrid-wave bias voltage scheme greatly reduces the additional power loss and bias voltage amplitude in the pre-bias voltage processing stage.

[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A fully closed-loop gate drive circuit for optimizing the turn-off process, characterized in that, This includes a resistor divider network, a demand reference waveform generation unit, a proportional-integral control unit, and an insulated-gate bipolar transistor (IGBT); the collector-emitter voltage V of the IGBT. CE The voltage is divided by a resistor divider network and then connected to the proportional-integral control unit. The required reference waveform generation unit is connected to the proportional-integral control unit, and the required reference voltage V is output by the required reference waveform generation unit. REF The error signal generated by comparing the feedback quantity after voltage division with the error signal is processed by the proportional-integral control unit to obtain the gate drive voltage V. G And finally fed to the gate drive circuit of the IGBT to form a closed-loop control.

2. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 1, characterized in that, A resistor divider network consists of several resistors, each with a capacitor connected in parallel, used to output a signal V that is reduced by a factor of 100. CE / 100.

3. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 1, characterized in that, The demand reference waveform generation unit includes two NAND gates, an RC circuit, an integrator, two first operational amplifiers, and a non-inverting summation circuit. The input signal is connected to the two NAND gates respectively, and each NAND gate is equipped with an RC circuit. The output terminals of the two NAND gates are connected to the first operational amplifiers respectively, and each first operational amplifier is equipped with an integrator. The output terminals of the two first operational amplifiers are connected to the non-inverting summation circuit.

4. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 3, characterized in that, An RC circuit includes a capacitor and a resistor. A NAND gate has two input terminals. One end of the resistor in the RC circuit is connected to the input signal Input, and the other end is connected to one of the input terminals. One end of the capacitor in the RC circuit is connected to the resistor, and the other end is grounded. The other input terminal of the NAND gate is connected to the input signal Input.

5. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 3, characterized in that, The integrator includes two resistors and one capacitor. The capacitor of the integrator is connected in parallel with the first operational amplifier. One end of one resistor of the integrator is connected to the output of the NAND gate, and the other end is connected to the negative input of the first operational amplifier. One end of the other resistor of the integrator is connected to the negative input of the first operational amplifier, and the other end is connected to the voltage source V. ee .

6. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 5, characterized in that, One of the first operational amplifiers also has a Zener diode D1 connected in parallel.

7. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 3, characterized in that, The non-inverting summation circuit includes a second operational amplifier and resistors R5, R6, R7, R8, and R9. One end of resistors R5 and R6 are connected to the outputs of the two first operational amplifiers, and the other end of each is connected to the negative input of the second operational amplifier. One end of resistor R7 is connected to the input signal, and the other end is connected to the negative input of the second operational amplifier. One end of resistor R9 is connected to the positive input of the second operational amplifier, and the other end is connected to the output of the second operational amplifier. 8一端 It is connected to resistor R9, and the other end is grounded.

8. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 1, characterized in that, The proportional-integral control unit includes two operational amplifiers A, a buffer amplifier B, and a pair of driver MOSFETs; the two operational amplifiers A are connected in series, the output of operational amplifier A is connected to buffer amplifier B, and the output of buffer amplifier B is connected to the pair of driver MOSFETs, with an output gate drive voltage V. G .

9. The fully closed-loop gate drive circuit for turn-off process optimization according to claim 8, characterized in that, Operational amplifier A is selected as LM7171, and buffer amplifier B is BUF634A.

10. A control method for a fully closed-loop gate drive circuit for turn-off process optimization based on any one of claims 1 to 9, characterized in that, Includes the following steps: The shutdown instruction is initiated, generating the demand reference waveform VREF. When the input signal Input switches to the shutdown instruction, the demand reference waveform generation unit is activated. First, the Input signal is input to two NAND gates with RC circuits. One input is directly connected to Input, and the other is connected to Input through an RC circuit. The charging and discharging characteristics of the RC circuit are used to adjust the shutdown delay time. Subsequently, the output signals of the two NAND gates are fed into the first operational amplifier with an integrator. The integrator consists of an operational amplifier LT1810 and a voltage source V. ee Composed of resistors and capacitors, the slope of the dv / dt reference waveform is set by adjusting the integrator parameters, and the Zener diode D1 limits the operational amplifier output saturation level Vpeak. Finally, the output signals of the two first operational amplifiers are weighted and summed with the input signal through a non-inverting summing circuit to generate the final required reference voltage V. REF This provides a standard control baseline for the shutdown process; After the IGBT enters the turn-off process, its collector-emitter voltage V CE Sampling is performed using a resistor divider network, which consists of several resistors, each with a capacitor connected in parallel to ensure sampling stability. The final output is a feedback signal V reduced by a factor of 100. CE / 100, to achieve V CE The signal undergoes a step-down preprocessing step to prevent high-voltage signals from damaging subsequent control units, while also ensuring compatibility with the required reference voltage V. REF The matching comparison provides conditions; The obtained feedback signal V CE / 100 is sent to the proportional-integral control unit, along with the generated required reference voltage V. REF A real-time comparison is performed to obtain the error signal between the two; this error signal is processed by a PI controller composed of two LM7171 operational amplifiers connected in series to eliminate static error and optimize dynamic response, and then the output current of the PI controller is amplified by a BUF634A buffer amplifier. The control signal processed by the proportional-integral control unit is further boosted by a pair of driving MOSFETs to generate the gate drive voltage V. G And feed it to the gate drive circuit of the IGBT; V G It acts on the IGBT gate to adjust the IGBT's turn-off speed, while simultaneously adjusting the IGBT's V... CE It updates in real time according to the change of the turn-off state, and samples the feedback again through the resistor voltage divider network. The process is repeated to form a continuous closed-loop control until the IGBT completes stable turn-off, thus achieving optimized control of the turn-off process.

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