Dut signal access method, device and storage medium for soc test
By combining C and SystemVerilog languages on the UVM platform and using callback functions to transmit event signals, the problems of test redundancy and event delay in SOC testing are solved, thereby simplifying the testing process and improving verification performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHENZHEN AOWEI LINGXIN TECH CO LTD
- Filing Date
- 2026-03-13
- Publication Date
- 2026-06-16
Smart Images
Figure CN122220166A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip verification, and more particularly to a method, apparatus, and storage medium for accessing DUT signals in SOC testing. Background Technology
[0002] Currently, SOC verification generally falls into three categories: pure UVM, UVM+CPU C, and UVM+DPI-C. UVM+DPI-C is more commonly used in actual SOC projects because it allows for the reuse of some basic C functions by driver developers, resulting in C language examples that are easier for them to understand and reference. It also allows software engineers to participate in verification and is faster than UVM+CPU C. In this UVM+DPI-C method, the C language, in addition to manipulating internal SOC registers, also needs to wait for some TESTBENCH or SOC DUT internal signal events. This is a fundamental requirement in the SOC UVM+DPI-C verification platform. Since DPI-C itself does not implement this method, and SystemVerilog does not support waiting for string-type signal events, and VPI does not support direct signal event waiting, two methods are generally used in the verification environment to complete event waiting: 1. Write the specific event waiting task in the SystemVerilog system and then export it to the C language system for calling; 2. Loop and wait in the C language system, using delay and check values to determine the event.
[0003] In the first approach, the specific wait event tasks are written in SystemVerilog and then exported to C for system calls. The advantage is that it is simple to implement and performs well. The disadvantage is that it is very redundant. Every time a verification result or an internal signal event of the SOC DUT is waited for, a SystemVerilog task needs to be rewritten and exported to C. If there are many events to wait for, a lot of redundant code will be generated, increasing the workload and making it easy to generate various errors.
[0004] In the second approach, a loop is used in the C language system to wait, delay, and read signal values to determine the method. The advantage of this approach is that it requires less code and is simpler to implement. However, the disadvantage is that there is a time difference between the time the event is waiting for the result and the time the event actually occurs. Frequent delays in checking signal values can significantly impact verification performance. Increasing the delay time unit will further lengthen the time difference between the event's result and its actual occurrence.
[0005] Therefore, a new technology is needed to address the technical issues of redundant and cumbersome testing schemes and significant event delays on the UVM platform's SOC testing solution. Summary of the Invention
[0006] The main objective of this invention is to solve the technical problems of redundant and cumbersome testing schemes and large event delays on the UVM platform for SOC testing.
[0007] The first aspect of this invention provides a method for accessing DUT signals in SOC testing. This method is applied to a DUT signal access system for SOC testing, which includes a SystemVerilog language system and a C language system. The method for accessing DUT signals in SOC testing includes: The C language system call preset wait signal function writes the wait event parameters into the SystemVerilog language system, wherein the wait event parameters include: signal hierarchy string and event instance; The SystemVerilog language system receives the waiting event parameters, performs registration processing on the waiting event parameters, generates a registration success signal, and calls a preset signal interface function to transmit the registration success signal to the C language system; The C language system receives the registration success signal, generates a callback pointer based on the registration success signal, and sends the callback pointer to the SystemVerilog language system; The SystemVerilog language system receives the callback pointer and determines whether the event instance corresponding to the signal hierarchy string has been triggered. When the event instance corresponding to the signal hierarchy string is triggered, the preset trigger function is called according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system.
[0008] Optionally, in a first implementation of the first aspect of the present invention, the step of calling a preset wait signal function in the C language system to write the wait event parameter into the SystemVerilog language system includes: The C language system call sv_signal_wait() function, based on the DPI-C interface, writes the wait event parameters into the SystemVerilog language system.
[0009] Optionally, in a second implementation of the first aspect of the present invention, the wait event parameter further includes: the number of waits; the steps of the SystemVerilog language system receiving the wait event parameter, performing registration processing on the wait event parameter, generating a registration success signal, and calling a preset signal interface function to transmit the registration success signal to the C language system include: The SystemVerilog language system receives the wait event parameters, adds the signal hierarchy string to a preset global dictionary, and adds the event instance and the number of waits to the content corresponding to the signal hierarchy string in the preset global dictionary, thereby generating a registration success signal; The signal_wait_cb() function is called to transmit the registration success signal to the C language system.
[0010] Optionally, in a third implementation of the first aspect of the present invention, the step of adding the signal hierarchy string to a preset global dictionary and adding the event instance and the number of waits to the content corresponding to the signal hierarchy string in the preset global dictionary to generate a registration success signal includes: Determine whether the signal hierarchy string exists in a preset global dictionary; If the signal exists in the preset global dictionary, the number of waits corresponding to the signal level string is incremented. If the signal level string, the event instance, and the number of waits are not present in the preset global dictionary, then the signal level string, the event instance, and the number of waits are combined into a key and added to the preset global dictionary.
[0011] Optionally, in a fourth implementation of the first aspect of the present invention, the step of calling a preset trigger function according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system includes: Query the number of waits corresponding to the signal level string in the preset global dictionary to obtain the query wait count; The number of query wait times is deducted to obtain the deducted wait times; Determine whether the number of waiting times deducted is zero; When the value is not zero, the preset trigger function is called according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system; When the value is zero, the preset trigger function is called according to the callback pointer's callback_del() function, and the event trigger signal corresponding to the signal hierarchy string is sent to the C language system.
[0012] Optionally, in the fifth implementation of the first aspect of the present invention, the step of the C language system receiving the registration success signal, generating a callback pointer based on the registration success signal, and sending the callback pointer to the SystemVerilog language system includes: The C language system receives the registration success signal based on the signal_wait_cb() function; Based on the registration success signal, register the VPI callback function and generate a callback() function pointer; Send the callback() function pointer to the SystemVerilog language system.
[0013] Optionally, in a sixth implementation of the first aspect of the present invention, the step of calling a preset trigger function according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system includes: Based on the callback pointer, the sp_trigger() function is called to send the event trigger signal corresponding to the signal hierarchy string to the C language system.
[0014] Optionally, in a seventh implementation of the first aspect of the present invention, the event instance includes: positive edge triggering type, negative edge triggering type, and logic value matching type.
[0015] A second aspect of the present invention provides a DUT signal access device for SOC testing, comprising: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a line; the at least one processor invokes the instructions in the memory to cause the DUT signal access device for SOC testing to execute the above-described DUT signal access method for SOC testing.
[0016] A third aspect of the present invention provides a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the DUT signal access method for the SOC test described above.
[0017] In this embodiment of the invention, in the UVM-DPI-C verification environment, a wait event is registered in the SystemVerilog language system using a signal wait function in the C language system. After the registered wait event occurs in the SystemVerilog language system, the SystemVerilog language system processes the registered event, and then a callback function is used to transmit the relevant event occurrence signal back to the C language system. Compared with the C language system call scheme, this simplifies the testing process and eliminates redundant code. Compared with the loop wait scheme in the C language system, the test results are more timely. This solves the technical problems of relatively redundant and cumbersome testing schemes and large event delays in SOC testing schemes on the UVM platform. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of an embodiment of the DUT signal access method for SOC testing in this invention. Figure 2 This is a schematic diagram of a specific embodiment of the 102 steps of the DUT signal access method for SOC testing in this invention. Figure 3 This is a schematic diagram of a specific embodiment of step 1021 of the DUT signal access method for SOC testing in this invention. Figure 4 This is a schematic diagram of a specific embodiment of the DUT signal access method for SOC testing in this invention. Figure 5 This is a schematic diagram of an embodiment of the DUT signal access device for SOC testing in this invention. Detailed Implementation
[0019] This invention provides a method, device, and storage medium for accessing DUT signals during SOC testing.
[0020] The embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While some embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the accompanying drawings and embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention.
[0021] In the description of the embodiments disclosed in this invention, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.
[0022] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 This invention illustrates an embodiment of a DUT signal access method for SOC testing. The DUT signal access method is applied to a DUT signal access system for SOC testing, which includes a SystemVerilog language system and a C language system. The DUT signal access method for SOC testing includes: 101. The C language system call preset wait signal function writes the wait event parameters into the SystemVerilog language system, wherein the wait event parameters include: signal hierarchy string and event instance; In this embodiment, SystemVerilog is a hardware-oriented design and verification language. The SystemVerilog language system is mainly a SOC simulation and testing platform, while the C language system mainly runs on a host computer platform such as a PC. The C language system and the SystemVerilog language system communicate with each other through a DPI-C interface, but the C language code or the DPI-C interface cannot directly monitor the internal signal changes of the SystemVerilog language system.
[0023] In the C language system, calling the wait signal function and writing the wait event parameter into the SystemVerilog language system only requires calling a C function in the C language system, passing in the signal hierarchy string and the event to be waited for. This allows you to wait for test results or internal signal events of the SOC DUT in C, and directly use the string to wait for a specific signal event in the UVM environment. For example, waiting for events of internal hierarchical signals within the SOC DUT using the `for generate` method would require writing out each hierarchy structure directly in the UVM environment, making it impossible to simplify the code using a `for` loop. However, if string waiting is supported, the `for` loop can be used to simplify the code.
[0024] Specifically, the event instances include: positive edge triggering type, negative edge triggering type, and logical value matching type.
[0025] A positive edge trigger type is a transition of a signal from a first logic level to a second logic level, where the first logic level is lower than the second logic level.
[0026] Negative edge triggering type is a signal transition from a first logic level to a second logic level, where the first logic level is higher than the second logic level.
[0027] The logical value matching type is a matching type where the signal value equals a predetermined value, and it is triggered when the signal equals the preset value.
[0028] Specifically, step 101 includes the following specific implementation methods: 1011. The C language system call sv_signal_wait() function, based on the DPI-C interface, writes the wait event parameters into the SystemVerilog language system.
[0029] In step 1011, the C language system calls the sv_signal_wait() function imported by the SystemVerilog language system, and imports the wait event parameters into the SystemVerilog language system through the DPI-C interface. The injected wait event parameters include the signal hierarchy string and the event type corresponding to the signal hierarchy string.
[0030] 102. The SystemVerilog language system receives the waiting event parameters, performs registration processing on the waiting event parameters, generates a registration success signal, and calls a preset signal interface function to transmit the registration success signal to the C language system; In this embodiment, the SystemVerilog language system receives the wait event parameter, registers the signal hierarchy string and the event type corresponding to the signal hierarchy string, generates a registration success signal after registration is completed, and returns the registration success signal to the C language system based on the call to the signal interface function imported by the C language system.
[0031] Specifically, the waiting event parameters also include: the number of waits, please refer to [link / reference]. Figure 2 , Figure 2 This is a schematic diagram of a specific embodiment of step 102 of the DUT signal access method for SOC testing in this invention. Step 102 includes the following specific implementation methods: 1021. The SystemVerilog language system receives the wait event parameter, adds the signal hierarchy string to a preset global dictionary, and adds the event instance and the number of waits to the content corresponding to the signal hierarchy string in the preset global dictionary, thereby generating a registration success signal; 1022. Call the signal_wait_cb() function to transmit the registration success signal to the C language system.
[0032] In steps 1021-1022, after receiving the wait event parameters, the SystemVerilog language system retrieves the signal hierarchy string, event instance, and wait count from the wait event parameters. It adds the signal hierarchy string to the preset global dictionary, and then adds the event instance and wait count to the corresponding content of the signal hierarchy string in the global dictionary. After registration is completed, a registration success signal is generated and written to the signal_wait_cb() function imported by the C language system, and the registration success signal is transmitted to the C language system.
[0033] For details, please refer to Figure 3 , Figure 3 This is a schematic diagram of step 1021 of the DUT signal access method for SOC testing in this invention. Step 1021 includes the following specific implementation: 10211. Determine whether the signal hierarchy string exists in a preset global dictionary; 10212. If the signal exists in the preset global dictionary, the number of waits corresponding to the signal level string is increased. 10213. If the signal level string, the event instance, and the number of waits are not present in the preset global dictionary, the signal level string, the event instance, and the number of waits are combined into a key and added to the preset global dictionary.
[0034] In steps 10211-10213, the registration process first checks if a corresponding signal hierarchy exists, determining if the signal hierarchy string exists in the preset global dictionary. If the signal hierarchy string is already in the global dictionary, the wait count corresponding to the signal hierarchy string in the global dictionary is incremented, for example, by 1. If it does not exist in the preset global dictionary, it means the signal hierarchy string is a new registration event, so a new key-value pair is created in the global dictionary, containing a newly created signal hierarchy string, the event instance corresponding to the signal hierarchy string, and a wait count initialized to 1.
[0035] It should be noted that registering wait events in the global dictionary allows for simultaneous waiting of multiple signal events in C / SV, and also supports multiple waits for a single signal. Therefore, the number of waits can be greater than 1 for registration.
[0036] 103. The C language system receives the registration success signal, generates a callback pointer based on the registration success signal, and sends the callback pointer to the SystemVerilog language system; In this embodiment, the C language system receives the registration success signal, performs VPI registration in the C language system, and generates a callback pointer for the callback function. Then, the callback pointer is sent to the SystemVerilog language system.
[0037] Specifically, step 103 includes the following specific implementation methods: 1031. The C language system receives the registration success signal based on the signal_wait_cb() function; 1032. Based on the registration success signal, register the VPI callback function and generate a callback() function pointer; 1033. The callback() function pointer is sent to the SystemVerilog language system.
[0038] In steps 1031-1033, the C language system receives a registration success signal through the `signal_wait_cb()` function. Then, it writes the registration success signal to the VPI callback function, thus registering the VPI callback function and generating a `callback()` function pointer.
[0039] Sending the callback() function pointer to the SystemVerilog language system will cause the SystemVerilog simulator to perform operations asynchronously in the background: the callback function will be called when the specified signal level value changes.
[0040] 104. The SystemVerilog language system receives the callback pointer and determines whether the event instance corresponding to the signal hierarchy string has been triggered; In this embodiment, after receiving the callback pointer, the SystemVerilog language system executes the following two methods in parallel: 1. Wait for the event instance corresponding to the signal hierarchy string to occur.
[0041] 2. If there is a change in the signal value, the callback() function in the C language system will be called. The callback() function will determine whether the corresponding event has occurred based on the value. If the event has occurred, the sp_trigger function exported from the SystemVerilog language system will be called, and the signal hierarchy parameter will be passed in.
[0042] 105. When the event instance corresponding to the signal hierarchy string is triggered, the preset trigger function is called according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system.
[0043] In this embodiment, when the event instance corresponding to the signal hierarchy string is triggered, the pointer to the callback() function in the C language system is called, the sp_trigger function in the SystemVerilog language system is exported, and the event trigger signal corresponding to the signal hierarchy string is sent to the C language system.
[0044] For details, please refer to Figure 4 , Figure 4 This is a schematic diagram of step 105 of the DUT signal access method for SOC testing in this invention. In embodiments of steps 1021-1022 or steps 10211-10213, step 105 includes the following specific implementation: 1051. Query the number of waits corresponding to the signal level string in the preset global dictionary to obtain the query wait count; 1052. The number of query wait times is deducted to obtain the deducted wait times; 1053. Determine whether the number of waiting times deducted is zero; 1054. When the value is not zero, the preset trigger function is called according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system; 1055. When the value is zero, the preset trigger function is called according to the callback_del() function of the callback pointer, and the event trigger signal corresponding to the signal hierarchy string is sent to the C language system.
[0045] In steps 1051-1055, first query the number of waits corresponding to the signal level string in the preset global dictionary, subtract 1 from the queryed number of waits, and then get a deducted number of waits.
[0046] Check if the deducted wait count is zero. If the deducted wait count is zero, call the callback_del() function imported into the C language system to delete the corresponding callback() function, passing a callback() pointer as the parameter. Then call the sp_trigger function to send the event trigger signal corresponding to the signal hierarchy string to the C language system.
[0047] If the number of wait counts is not zero, the preset trigger function is called according to the callback() function pointer, and the event trigger signal corresponding to the signal level string is sent to the C language system. There is no need to delete the corresponding callback() function in the C language system.
[0048] Specifically, step 105 also includes the following specific implementation methods: 1056. Based on the callback pointer, call the sp_trigger() function to send the event trigger signal corresponding to the signal hierarchy string to the C language system.
[0049] In step 1056, the sp_trigger() function is passively called by callback(). After the call, the corresponding instance event is found in the global dictionary through the signal hierarchy input parameters and the event trigger signal corresponding to the signal hierarchy string is sent to the C language system through the callback pointer.
[0050] In this embodiment of the invention, in the UVM-DPI-C verification environment, a wait event is registered in the SystemVerilog language system using a signal wait function in the C language system. After the registered wait event occurs in the SystemVerilog language system, the SystemVerilog language system processes the registered event, and then a callback function is used to transmit the relevant event occurrence signal back to the C language system. Compared with the C language system call scheme, this simplifies the testing process and eliminates redundant code. Compared with the loop wait scheme in the C language system, the test results are more timely. This solves the technical problems of relatively redundant and cumbersome testing schemes and large event delays in SOC testing schemes on the UVM platform.
[0051] Figure 5 This is a schematic diagram of a DUT signal access device for SOC testing provided in an embodiment of the present invention. The DUT signal access device 500 for SOC testing can vary significantly due to different configurations or performance characteristics. It may include one or more central processing units (CPUs) 510 and memory 520, and one or more storage media 530 storing application programs 533 or data 532. The memory 520 and storage media 530 can be temporary or persistent storage. The program stored in the storage media 530 may include one or more modules (not shown in the diagram), each module including a series of instruction operations on the DUT signal access device 500 for SOC testing. Furthermore, the processor 510 may be configured to communicate with the storage media 530 and execute the series of instruction operations in the storage media 530 on the DUT signal access device 500 for SOC testing.
[0052] The DUT signal access device 500 based on SOC testing may also include one or more power supplies 540, one or more wired or wireless network interfaces 550, one or more input / output interfaces 560, and / or one or more operating systems 531, such as Windows Server, Mac OS X, Unix, Linux, Free BSD, etc. Those skilled in the art will understand that... Figure 5 The structure of the DUT signal access device shown for SOC testing does not constitute a limitation on the DUT signal access device for SOC testing. It may include more or fewer components than shown, or combine certain components, or have different component arrangements.
[0053] The present invention also provides a computer-readable storage medium, which may be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when the instructions are executed on a computer, cause the computer to perform the steps of the DUT signal access method of the SOC test.
[0054] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0055] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.
[0056] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.
Claims
1. A method for accessing DUT signals during SOC testing, characterized in that, The DUT signal access method for SOC testing is applied to the DUT signal access system for SOC testing. The DUT signal access system for SOC testing includes: a SystemVerilog language system and a C language system. The DUT signal access method for SOC testing includes: The C language system call preset wait signal function writes the wait event parameters into the SystemVerilog language system, wherein the wait event parameters include: signal hierarchy string and event instance; The SystemVerilog language system receives the waiting event parameters, performs registration processing on the waiting event parameters, generates a registration success signal, and calls a preset signal interface function to transmit the registration success signal to the C language system; The C language system receives the registration success signal, generates a callback pointer based on the registration success signal, and sends the callback pointer to the SystemVerilog language system; The SystemVerilog language system receives the callback pointer and determines whether the event instance corresponding to the signal hierarchy string has been triggered. When the event instance corresponding to the signal hierarchy string is triggered, the preset trigger function is called according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system.
2. The DUT signal access method for SOC testing according to claim 1, characterized in that, The steps of calling the preset wait signal function in the C language system and writing the wait event parameters into the SystemVerilog language system include: The C language system call sv_signal_wait() function, based on the DPI-C interface, writes the wait event parameters into the SystemVerilog language system.
3. The DUT signal access method for SOC testing according to claim 1, characterized in that, The wait event parameter further includes: the number of waits. The steps of the SystemVerilog language system receiving the wait event parameter, registering the wait event parameter, generating a registration success signal, and calling a preset signal interface function to transmit the registration success signal to the C language system include: The SystemVerilog language system receives the wait event parameters, adds the signal hierarchy string to a preset global dictionary, and adds the event instance and the number of waits to the content corresponding to the signal hierarchy string in the preset global dictionary, thereby generating a registration success signal; The signal_wait_cb() function is called to transmit the registration success signal to the C language system.
4. The DUT signal access method for SOC testing according to claim 3, characterized in that, The step of adding the signal hierarchy string to a preset global dictionary and adding the event instance and the number of waits to the corresponding content of the signal hierarchy string in the preset global dictionary to generate a registration success signal includes: Determine whether the signal hierarchy string exists in a preset global dictionary; If the signal exists in the preset global dictionary, the number of waits corresponding to the signal level string is incremented. If the signal level string, the event instance, and the number of waits are not present in the preset global dictionary, then the signal level string, the event instance, and the number of waits are combined into a key and added to the preset global dictionary.
5. The DUT signal access method for SOC testing according to any one of claims 3 or 4, characterized in that, The step of calling a preset trigger function based on the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system includes: Query the number of waits corresponding to the signal level string in the preset global dictionary to obtain the query wait count; The number of query wait times is deducted to obtain the deducted wait times; Determine whether the number of waiting times deducted is zero; When the value is not zero, the preset trigger function is called according to the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system; When the value is zero, the preset trigger function is called according to the callback pointer's callback_del() function, and the event trigger signal corresponding to the signal hierarchy string is sent to the C language system.
6. The DUT signal access method for SOC testing according to claim 1, characterized in that, The steps of the C language system receiving the registration success signal, generating a callback pointer based on the registration success signal, and sending the callback pointer to the SystemVerilog language system include: The C language system receives the registration success signal based on the signal_wait_cb() function; Based on the registration success signal, register the VPI callback function and generate a callback() function pointer; Send the callback() function pointer to the SystemVerilog language system.
7. The DUT signal access method for SOC testing according to claim 1, characterized in that, The step of calling a preset trigger function based on the callback pointer to send the event trigger signal corresponding to the signal hierarchy string to the C language system includes: Based on the callback pointer, the sp_trigger() function is called to send the event trigger signal corresponding to the signal hierarchy string to the C language system.
8. The DUT signal access method for SOC testing according to claim 1, characterized in that, The event instances include: positive edge trigger type, negative edge trigger type, and logical value matching type.
9. A DUT signal access device for SOC testing, characterized in that, The DUT signal access device for the SOC test includes: a memory and at least one processor, wherein the memory stores instructions and the memory and the at least one processor are interconnected via a line; The at least one processor invokes the instructions in the memory to cause the DUT signal access device for SOC testing to perform the DUT signal access method for SOC testing as described in any one of claims 1-8.
10. A computer-readable storage medium storing a computer program thereon, characterized in that, When the computer program is executed by the processor, it implements the DUT signal access method for SOC testing as described in any one of claims 1-8.