Register processing method and device, computer device, chip and chip module

Abstract

The application relates to a register processing method and device, computer equipment, a chip and a chip module, which can be used in the technical field of registers. The method comprises the following steps: obtaining register values of permission configuration registers corresponding to each memory protection region; performing analysis processing on the register values of the permission configuration registers according to preset bit field information, to obtain address matching mode information, access permission information and lock state information corresponding to each memory protection region; performing analysis processing on register values of address registers corresponding to each memory protection region according to the address matching mode information, to obtain address interval information of each memory protection region; and determining protection configuration information of each memory protection region according to the access permission information, the address interval information and the lock state information. The method can improve the efficiency and accuracy of determining the protection configuration information.

Description

Technical Field

[0001] This application relates to the field of register technology, and in particular to a register processing method, apparatus, computer equipment, chip, and chip module. Background Technology

[0002] With the development of embedded systems, memory protection units have become an important component of processor security mechanisms, used to prevent unauthorized memory access and ensure stable system operation. During system development and debugging, it is necessary to obtain the configuration information of the memory protection area to verify whether the memory protection strategy is correctly deployed.

[0003] In related technologies, manual processing is mainly used to obtain the protection configuration information of the memory protection area; however, this method requires developers to manually parse complex encoded information, which results in low efficiency in determining the protection configuration information and is prone to human error, leading to low accuracy in determining the protection configuration information. Summary of the Invention

[0004] Therefore, it is necessary to provide a register processing method, apparatus, computer device, chip, chip module, computer-readable storage medium, and computer program product that can improve the efficiency and accuracy of determining protection configuration information in order to address the above-mentioned technical problems.

[0005] Firstly, this application provides a register processing method. The method includes:

[0006] Obtain the register values ​​of the permission configuration registers corresponding to each memory protection region;

[0007] Based on the preset bit field information, the register value of the permission configuration register is parsed to obtain the address matching mode information, access permission information and lock status information corresponding to each memory protection area;

[0008] Based on the address matching pattern information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information of each memory protection region;

[0009] Based on the access permission information, the address range information, and the lock status information, the protection configuration information for each memory protection region is determined.

[0010] In one embodiment, the address matching pattern information includes at least one of a first address matching pattern information, a second address matching pattern information, a third address matching pattern information, and a fourth address matching pattern information;

[0011] The step of parsing the register values ​​of the address registers corresponding to each memory protection region based on the address matching pattern information to obtain the address range information of each memory protection region includes:

[0012] When the address matching mode information is the first address matching mode information, the register value of the address register is used as the starting address, and the preset width information is used as the address width information. The address range information is determined based on the starting address and the address width information.

[0013] When the address matching mode information is the second address matching mode information, the start address and end address are determined according to the register value of the address register and the register value of the second adjacent address register in sequence, and the address range information is determined according to the start address and the end address;

[0014] When the address matching mode information is the third address matching mode information, the register value of the address register is subjected to statistical processing of consecutive preset value bits to obtain the statistical processing result. The address width information is determined according to the statistical processing result. The register value of the address register is parsed according to the address width information to obtain the address range information.

[0015] When the address matching mode information is the fourth address matching mode information, it is determined that the register value of the address register does not point to any address range.

[0016] In one embodiment, the statistical processing of the register value of the address register to obtain a statistical processing result by performing a continuous preset value bit statistical processing includes:

[0017] The register value of the address register is converted to obtain the target register value;

[0018] The target register value is subjected to statistical processing of consecutive preset numerical bits to obtain the statistical processing result.

[0019] In one embodiment, the method further includes:

[0020] Obtain the target address range information, target access permission information, and target address matching pattern information to be configured;

[0021] Based on the target address matching mode information and the target address range information, determine the register configuration value of the target address register to be configured, and perform configuration processing on the target address register based on the register configuration value of the target address register;

[0022] Based on the target access permission information, the target address matching mode information, and the preset bit field information, determine the register configuration value of the target permission configuration register to be configured, and perform configuration processing on the target permission configuration register according to the register configuration value of the target permission configuration register.

[0023] In one embodiment, determining the register configuration value of the target address register to be configured based on the target address matching pattern information and the target address range information includes:

[0024] When the target address matching mode information is the first address matching mode information, the starting address in the target address range information is used as the register configuration value of the target address register;

[0025] When the target address matching mode information is the second address matching mode information, the start address and end address in the target address range information are respectively used as the register configuration values ​​of two adjacent target address registers;

[0026] When the target address matching mode information is the third address matching mode information, the target continuous preset value bits are determined according to the address width information in the target address range information, and the register configuration value of the target address register is determined according to the target continuous preset value bits.

[0027] In one embodiment, determining the register configuration value of the target permission configuration register to be configured based on the target access permission information, the target address matching pattern information, and the preset bit field information includes:

[0028] Based on the target access permission information, determine the read permission configuration bit, write permission configuration bit, and execute permission configuration bit; based on the target address matching mode information, determine the address matching mode configuration bit; and based on the obtained target lock status information, determine the lock status configuration bit.

[0029] The register configuration value of the target permission configuration register is determined based on the read permission configuration bit, the write permission configuration bit, the execute permission configuration bit, the address matching mode configuration bit, the lock status configuration bit, and the preset bit field information.

[0030] Secondly, this application also provides a register processing apparatus. The apparatus includes:

[0031] The target acquisition module is used to obtain the register values ​​of the permission configuration registers corresponding to each memory protection region;

[0032] The first parsing module is used to parse the register value of the permission configuration register according to the preset bit field information to obtain the address matching mode information, access permission information and locking status information corresponding to each memory protection area.

[0033] The second parsing module is used to parse the register values ​​of the address registers corresponding to each memory protection region according to the address matching mode information, so as to obtain the address range information of each memory protection region.

[0034] The information determination module is used to determine the protection configuration information of each memory protection region based on the access permission information, the address range information, and the locking status information.

[0035] Thirdly, this application also provides a computer device. The computer device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to perform the following steps:

[0036] Obtain the register values ​​of the permission configuration registers corresponding to each memory protection region;

[0037] Based on the preset bit field information, the register value of the permission configuration register is parsed to obtain the address matching mode information, access permission information and lock status information corresponding to each memory protection area;

[0038] Based on the address matching pattern information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information of each memory protection region;

[0039] Based on the access permission information, the address range information, and the lock status information, the protection configuration information for each memory protection region is determined.

[0040] Fourthly, this application also provides a chip, including a processor and a communication interface, wherein the processor is configured to cause the chip to perform:

[0041] Obtain the register values ​​of the permission configuration registers corresponding to each memory protection region;

[0042] Based on the preset bit field information, the register value of the permission configuration register is parsed to obtain the address matching mode information, access permission information and lock status information corresponding to each memory protection area;

[0043] Based on the address matching pattern information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information of each memory protection region;

[0044] Based on the access permission information, the address range information, and the lock status information, the protection configuration information for each memory protection region is determined.

[0045] Fifthly, this application also provides a chip module, including a communication module, a power module, a storage module, and a chip, wherein:

[0046] The power module is used to provide power to the chip module;

[0047] The storage module is used to store data and instructions;

[0048] The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices.

[0049] The chip is used to perform the steps of the method provided in the first aspect above.

[0050] Sixthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, performs the following steps:

[0051] Obtain the register values ​​of the permission configuration registers corresponding to each memory protection region;

[0052] Based on the preset bit field information, the register value of the permission configuration register is parsed to obtain the address matching mode information, access permission information and lock status information corresponding to each memory protection area;

[0053] Based on the address matching pattern information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information of each memory protection region;

[0054] Based on the access permission information, the address range information, and the lock status information, the protection configuration information for each memory protection region is determined.

[0055] Seventhly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, performs the following steps:

[0056] Obtain the register values ​​of the permission configuration registers corresponding to each memory protection region;

[0057] Based on the preset bit field information, the register value of the permission configuration register is parsed to obtain the address matching mode information, access permission information and lock status information corresponding to each memory protection area;

[0058] Based on the address matching pattern information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information of each memory protection region;

[0059] Based on the access permission information, the address range information, and the lock status information, the protection configuration information for each memory protection region is determined.

[0060] The aforementioned register processing methods, devices, computer equipment, chips, chip modules, computer-readable storage media, and computer program products, by obtaining the register values ​​of the permission configuration registers corresponding to each memory protection region and parsing the register values ​​of the permission configuration registers according to preset bit field information, facilitate the extraction of address matching mode information, access permission information, and lock status information corresponding to each memory protection region from the register values, avoiding the process of manually consulting documents and manually calculating bit by bit. By performing targeted parsing processing on the register values ​​of the address registers according to the address matching mode information, it is beneficial to automatically calculate the address range information of each memory protection region according to different address matching modes using corresponding parsing methods, reducing manual operations such as address width calculation and number system conversion. By associating access permission information with address range information and lock status information to determine the protection configuration information of each memory protection region, it is beneficial to realize the automated conversion from register values ​​to protection configuration information, thereby improving the efficiency and accuracy of determining protection configuration information. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a flowchart illustrating a register processing method in one embodiment;

[0063] Figure 2 This is a schematic diagram of the framework of a register processing method in one embodiment;

[0064] Figure 3 This is a schematic diagram of the graphical user interface after startup in one embodiment;

[0065] Figure 4 This is a schematic diagram of the calculated graphical user interface in one embodiment;

[0066] Figure 5 This is a block diagram of the register processing device in one embodiment;

[0067] Figure 6 This is an internal structural diagram of a computer device in one embodiment;

[0068] Figure 7 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0070] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0071] In one exemplary embodiment, such as Figure 1 As shown, a register processing method is provided. This embodiment illustrates the application of this method to a chip. It is understood that this method can also be applied to a terminal or server, and further to a system including both a terminal and a server, implemented through interaction between the terminal and the server. The terminal can be, but is not limited to, various personal computers, laptops, smartphones, tablets, etc.; the server can be a standalone physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing cloud computing services. In this embodiment, the method includes the following steps:

[0072] Step S101: Obtain the register values ​​of the permission configuration registers corresponding to each memory protection region;

[0073] Step S102: Based on the preset bit field information, the register value of the permission configuration register is parsed to obtain the address matching mode information, access permission information and lock status information corresponding to each memory protection area.

[0074] Step S103: Based on the address matching mode information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information of each memory protection region.

[0075] Step S104: Determine the protection configuration information for each memory protection zone based on access permission information, address range information, and lock status information.

[0076] Among them, the memory protection region can refer to an independent storage area that is divided by physical memory protection mechanisms and used to implement memory access control.

[0077] The permission configuration register can be a register used to store access permission information and address matching mode information of memory protection areas. The configuration information corresponding to each memory protection area in the permission configuration register occupies 8 bits.

[0078] Register values ​​can refer to the data stored in a register, and can be represented in hexadecimal or binary formats.

[0079] Bit field information can refer to the functional definition information corresponding to each bit in the register. Bit field information is used to indicate the specific meaning represented by each bit or combination of bits in the register value.

[0080] Parsing can refer to the process of splitting and converting register values ​​to obtain various configuration information contained in the register values.

[0081] The address matching mode information can refer to the address matching method used by the memory protection region. The address matching mode information can include one of the following: Natural Aligned Four-Byte Mode (NA4), Top of Address Range Mode (TOR), Natural Aligned Power Mode (NAPOT), or Off Mode (OFF).

[0082] Access permission information can refer to the types of access operations allowed in the memory protection area. Access permission information can include at least one of read permission, write permission, execute permission, and locked status.

[0083] The address register can refer to a register used to store the address information of the memory protection area, and the number of address registers corresponds to the number of memory protection areas.

[0084] The address range information can refer to the physical address range covered by the memory protection region. The address range information can include at least one of the start address, end address, and address width.

[0085] The protection configuration information can refer to the complete configuration result of the memory protection region, which includes a combination of address range information and access permission information of the memory protection region.

[0086] Among them, the lock status information can be the lock status of the memory protection area, which is used to indicate whether the configuration of the memory protection area is locked.

[0087] Optionally, the chip obtains the register values ​​of the permission configuration registers corresponding to each memory protection region, and performs bit-by-bit parsing processing on the register values ​​of the permission configuration registers according to preset bit field information, thereby obtaining the address matching mode information, access permission information, and lock status information corresponding to each memory protection region. Based on the address matching mode information, the chip determines the address matching method used by each memory protection region, and based on the address matching mode information, parses the register values ​​of the address registers corresponding to each memory protection region to obtain the address range information of each memory protection region. The chip then associates the access permission information with the address range information and the lock status information to determine the protection configuration information of each memory protection region.

[0088] For example, the chip obtains the register values ​​of the permission configuration registers corresponding to the four memory protection regions. The register values ​​of the permission configuration registers are 32 bits of data. According to the preset bit field information, the register values ​​of the permission configuration registers are parsed in groups of 8 bits. From each group of 8 bits, the address matching mode information, access permission information, and lock status information of the corresponding memory protection region are extracted. The access permission information includes read permission, write permission, execute permission, and lock status. Based on the address matching mode information, the address matching method used by each memory protection region is determined. When the address matching mode information indicates a naturally aligned four-byte mode, the register value of the address register is resolved into an address range with a width of 4 bytes, starting at that register value. When the address matching mode information indicates a top-of-the-range mode, the register value of the current address register and the register value of the previous address register are resolved into an address range consisting of a start address and an end address. When the address matching mode information indicates a naturally aligned power mode, the register value of the address register is converted into binary data, and the number of consecutive 1 bits starting from the least significant bit is calculated. The address width is then calculated based on the number of consecutive 1 bits to obtain the address range information. The access permission information of each memory protection region is associated with the address range information and the lock status information to obtain the protection configuration information of each memory protection region.

[0089] In the above register processing method, by obtaining the register values ​​of the permission configuration registers corresponding to each memory protection region and parsing the register values ​​of the permission configuration registers according to the preset bit field information, it is beneficial to extract the address matching mode information and access permission information corresponding to each memory protection region from the register values, avoiding the process of manually consulting documents and manually calculating bit by bit. By performing targeted parsing processing on the register values ​​of the address registers according to the address matching mode information and the locking status information, it is beneficial to automatically calculate the address range information of each memory protection region according to different address matching modes and adopt the corresponding parsing methods, reducing the manual operation of complex calculations such as address width calculation and number system conversion. By associating the access permission information with the address range information and the locking status information to determine the protection configuration information of each memory protection region, it is beneficial to realize the automated conversion from register values ​​to protection configuration information, thereby improving the efficiency and accuracy of determining the protection configuration information.

[0090] In an exemplary embodiment, the address matching pattern information includes at least one of a first address matching pattern, a second address matching pattern, a third address matching pattern, and a fourth address matching pattern. Based on the address matching pattern information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information for each memory protection region. This includes: when the address matching pattern information is the first address matching pattern, using the register value of the address register as the starting address and a preset width information as the address width information, and determining the address range information based on the starting address and the address width information; when the address matching pattern information is the second address matching pattern... In the case of the address matching mode information, the start address and end address are determined based on the register value of the address register and the register value of the second adjacent address register in sequence. The address range information is then determined based on the start address and end address. In the case of the address matching mode information being the third address matching mode information, the register value of the address register is subjected to statistical processing of consecutive preset value bits to obtain the statistical processing result. The address width information is determined based on the statistical processing result. The register value of the address register is then parsed based on the address width information to obtain the address range information. In the case of the address matching mode information being the fourth address matching mode information, it is determined that the register value of the address register does not point to any address range.

[0091] The first address matching mode information can refer to the naturally aligned four-byte mode (NA4), in which the address width of the memory protection region is fixed at 4 bytes.

[0092] The second address matching mode information can refer to the top of address range (TOR) mode, in which the start and end addresses of the memory protection region are represented by the register value of the address register and the register value of the next adjacent address register (i.e., the next address register adjacent to the address register).

[0093] The third address matching mode information can refer to the Natural Alignment Power Mode (NAPOT), in which the address width of the memory protection region is a power of 2 bytes.

[0094] The fourth address matching mode information can refer to the OFF mode, in which the memory protection region is disabled and the corresponding address range is invalid.

[0095] The preset width information can be a pre-set fixed address width value, and the preset width information is 4 bytes.

[0096] The starting address can be the first address of the address range of the memory protected region.

[0097] The end address can be the end address of the address range of the memory protected region.

[0098] The address width information can be the number of bytes covered by the address range of the memory protection region.

[0099] Among them, consecutive preset value bits can refer to bits that are consecutively preset values ​​starting from the least significant bit of the address register value, and the preset value can be 1.

[0100] The statistical processing result can be the number of consecutive preset numerical bits, which is used to calculate the address width information of the memory protection region.

[0101] In the case of address matching mode information being the fourth address matching mode information, the register value of the address register does not point to any address range, which can be understood as not participating in memory access control.

[0102] Optionally, the chip determines the address matching method used by each memory protection region based on the address matching mode information. When the address matching mode information is the first address matching mode, the register value of the address register is used as the starting address, and the preset width information is used as the address width information. The address interval information is determined based on the starting address and the address width information. When the address matching mode information is the second address matching mode, the register values ​​of two adjacent address registers (i.e., the register value of the address register and the register value of the second-to-last adjacent address register) are determined based on the register value of the address register. The register value of the address register is determined as the starting address, and the register value of the second-to-last adjacent address register is determined as the ending address. The address interval information is determined based on the starting address and the ending address. When the address matching mode information is the third address matching mode, the register value of the address register is subjected to statistical processing of consecutive preset value bits to obtain the statistical processing result. The address width information is determined based on the statistical processing result, and the register value of the address register is parsed based on the address width information to obtain the address interval information. When the address matching mode information is the fourth address matching mode, the register value of the address register does not point to any address interval.

[0103] For example, a chip acquires the address matching pattern information of a certain memory protection region. When the address matching pattern information is the first address matching pattern, the register value of the address register is used as the starting address, and the preset width information is 4 bytes. The address range information is determined based on the starting address and the 4-byte address width information. When the address matching pattern information is the second address matching pattern, the register value of the address register and the register value of the second adjacent address register are used as the starting address, and the register value of the second adjacent address register is used as the ending address. The address range information is determined based on the starting address and the ending address. When the address matching pattern information is the third address matching pattern, the register value of the address register is converted into binary data, and the number of consecutive 1 bits starting from the least significant bit is counted as the statistical processing result. The address width information is calculated based on the statistical processing result. The address width information is equal to 2 times the statistical processing result plus a power of 3 bytes, i.e., 2^3 bytes. 统计处理结果+3 For example, when the statistical processing result is 7, the address width information is equal to 2 bytes. 10 Byte; The address range information is determined based on the address width information and the register value of the address register. When the address matching mode information is the fourth address matching mode information, the register value of the address register does not point to any address range, and this memory protection region does not participate in memory access control.

[0104] The technical solution provided in this embodiment parses the register value of the address register according to different address matching mode information using corresponding parsing methods. This is beneficial for using the most suitable parsing logic for the first address matching mode information, the second address matching mode information, the third address matching mode information, and the fourth address matching mode information, thereby improving the accuracy of address range information parsing.

[0105] In an exemplary embodiment, the register value of the address register is subjected to statistical processing of consecutive preset numerical bits to obtain a statistical processing result, including: performing numerical conversion processing on the register value of the address register to obtain a target register value; and performing statistical processing on the target register value of consecutive preset numerical bits to obtain a statistical processing result.

[0106] Among them, numerical conversion processing can be the process of converting the register value of the address register from hexadecimal format to binary format.

[0107] The target register value can be a binary register value obtained after numerical conversion.

[0108] Optionally, before performing the statistical processing on the consecutive preset value bits of the address register value, the chip first performs a value conversion process on the address register value, converting the address register value from hexadecimal format to binary format to obtain the target register value. Then, the chip performs the statistical processing on the consecutive preset value bits of the target register value, starting from the least significant bit, counting the number of consecutive bits that are the preset value to obtain the statistical processing result.

[0109] The technical solution provided in this embodiment obtains the target register value by performing numerical conversion processing on the register value of the address register, and performs statistical processing on the target register value for consecutive preset numerical bits, thereby improving the accuracy of the statistical processing for consecutive preset numerical bits.

[0110] In an exemplary embodiment, the method further includes: obtaining target address range information to be configured, target access permission information, and target address matching mode information; determining the register configuration value of the target address register to be configured based on the target address matching mode information and the target address range information; performing configuration processing on the target address register based on the register configuration value of the target address register; determining the register configuration value of the target permission configuration register to be configured based on the target access permission information, the target address matching mode information, and preset bit field information; and performing configuration processing on the target permission configuration register based on the register configuration value of the target permission configuration register.

[0111] The target address range information can be the address range information of the memory protection region configured by the user.

[0112] The target access permission information can be the access operation type information of the memory protection area configured by the user, and the target access permission information includes at least one of read permission, write permission and execute permission.

[0113] The target address matching mode information can be the address matching method used by the user-configured memory protection region.

[0114] The target address register can be an address register used to store target address range information.

[0115] The register configuration value can be a data value calculated based on the configuration information input by the user and used to write to the register.

[0116] The target permission configuration register can be a permission configuration register used to store target access permission information and target address matching pattern information.

[0117] The configuration processing can be the process of writing the register configuration value into the corresponding register.

[0118] Optionally, the chip acquires the target address range information, target access permission information, and target address matching mode information input by the user. Based on the target address matching mode information and target address range information, and according to the configuration logic corresponding to the target address matching mode information, the chip calculates the register configuration value of the target address register to be configured, and performs configuration processing on the target address register based on the register configuration value. Based on the target access permission information, target address matching mode information, and preset bit field information, and according to the bit distribution information defined by the preset bit field information, the chip calculates the register configuration value of the target permission configuration register to be configured, and performs configuration processing on the target permission configuration register based on the register configuration value.

[0119] The technical solution provided in this embodiment obtains the target address range information, target access permission information, and target address matching mode information to be configured, and calculates the register configuration values ​​of the target address register and the target permission configuration register based on this information. This facilitates the automatic conversion from user configuration information to register values, thereby improving the accuracy of register configuration.

[0120] In an exemplary embodiment, determining the register configuration value of the target address register to be configured based on the target address matching mode information and the target address range information includes: when the target address matching mode information is a first address matching mode information, using the starting address in the target address range information as the register configuration value of the target address register; when the target address matching mode information is a second address matching mode information, using the starting address and ending address in the target address range information as the register configuration values ​​of two adjacent target address registers respectively; when the target address matching mode information is a third address matching mode information, determining the target continuous preset value bits based on the address width information in the target address range information, and determining the register configuration value of the target address register based on the target continuous preset value bits.

[0121] The target consecutive preset value bits can be the number of bits in the register configuration value of the target address register that are consecutively set to preset values ​​starting from the least significant bit.

[0122] Optionally, the chip determines the configuration method of the target address register based on the target address matching mode information. If the target address matching mode information is the first address matching mode, the starting address in the target address range information is used as the register configuration value of the target address register. If the target address matching mode information is the second address matching mode, the starting address in the target address range information is used as the register configuration value of the previous target address register, and the ending address in the target address range information is used as the register configuration value of the current target address register. If the target address matching mode information is the third address matching mode, the chip calculates the target continuous preset value bits based on the address width information in the target address range information, and calculates the register configuration value of the target address register based on the target continuous preset value bits and the starting address.

[0123] The technical solution provided in this embodiment determines the register configuration value of the target address register by adopting the corresponding configuration method according to different target address matching mode information. This is beneficial for adopting appropriate configuration logic for the first address matching mode information, the second address matching mode information, and the third address matching mode information, thereby improving the accuracy of the target address register configuration.

[0124] In an exemplary embodiment, determining the register configuration value of the target permission configuration register to be configured based on target access permission information, target address matching mode information, and preset bit field information includes: determining read permission configuration bits, write permission configuration bits, and execute permission configuration bits based on the target access permission information; determining address matching mode configuration bits based on the target address matching mode information; determining lock status configuration bits based on the acquired target lock status information; and determining the register configuration value of the target permission configuration register based on the read permission configuration bits, write permission configuration bits, execute permission configuration bits, address matching mode configuration bits, lock status configuration bits, and preset bit field information.

[0125] Specifically, the read permission configuration bit can be a bit in the target permission configuration register used to indicate whether read operations are allowed in the memory protected area. The write permission configuration bit can be a bit in the target permission configuration register used to indicate whether write operations are allowed in the memory protected area. The execute permission configuration bit can be a bit in the target permission configuration register used to indicate whether execute operations are allowed in the memory protected area.

[0126] The address matching mode configuration bit can be a combination of bits in the target permission configuration register that indicate the address matching mode used by the memory protection region.

[0127] The target lock status information can be the lock status of the memory protection area that the user wants to configure, which is used to indicate whether the configuration of the memory protection area is locked.

[0128] The lock status configuration bit can be a bit in the target permission configuration register used to indicate whether the configuration of the memory protection area is locked.

[0129] Optionally, the chip determines the values ​​of the read permission configuration bit, write permission configuration bit, and execute permission configuration bit based on the target access permission information. When the target access permission information indicates that a read operation is allowed, the read permission configuration bit is set to 1; otherwise, it is 0. The values ​​of the write permission configuration bit and execute permission configuration bit are determined in the same way as the read permission configuration bit. The value of the address matching mode configuration bit is determined based on the target address matching mode information; different address matching modes correspond to different values ​​of the address matching mode configuration bit. The value of the lock status configuration bit is determined based on the acquired target lock status information. When the target lock status information indicates that the device is locked, the lock status configuration bit is set to 1; otherwise, it is 0. Based on the read permission configuration bit, write permission configuration bit, execute permission configuration bit, address matching mode configuration bit, lock status configuration bit, and preset bit field information, each configuration bit is combined according to the bit positions defined by the preset bit field information to obtain the register configuration value of the target permission configuration register.

[0130] The technical solution provided in this embodiment determines the read permission configuration bit, write permission configuration bit, and execute permission configuration bit based on the target access permission information, determines the address matching mode configuration bit based on the target address matching mode information, and determines the lock status configuration bit based on the target lock status information. Combined with preset bit field information, each configuration bit is combined into the register configuration value of the target permission configuration register. This facilitates the accurate mapping of access permission information and address matching mode information to register values, thereby improving the configuration accuracy of the target permission configuration register.

[0131] The following example illustrates the register processing method provided in this application. This example demonstrates the application of this method to a chip.

[0132] This embodiment can be applied to the development and use of CPU (Central Processing Unit) chips that conform to the standard RISC-V (an open standard instruction set architecture for CPU design) protocol, simplifying the configuration and parsing process of the PMP (Physical Memory Protection / Physical Address Protection) mechanism while ensuring configuration and parsing accuracy. It accelerates the chip design and verification process, shortens the chip development cycle, and optimizes the chip user experience.

[0133] The PMP (Programmable Memory Manager) mechanism in the RISC-V standard protocol is crucial for precise memory access control and management within the CPU. However, the address matching mode and access control logic of PMP are complex, requiring users to read documentation and perform manual calculations, which is time-consuming and has low accuracy. This embodiment addresses this pain point by implementing automatic parsing and configuration of PMP addresses and permissions, significantly reducing the complexity and error rate of manual operations, accelerating chip development, and optimizing the user experience.

[0134] RISC-V is an open instruction set architecture (ISA). The PMP (Physical Memory Protection Address Register) mechanism is a memory protection scheme provided by RISC-V. By configuring PMP-related registers, including the PMPADDR (Physical Memory Protection Address Register) address register and the PMPCFG (Physical Memory Protection Configuration Register) permission register, the memory space can be divided into N memory protection regions, where N is less than or equal to 16, and the access permissions of each memory protection region can be dynamically controlled. This mechanism allows the system to restrict access to specific hardware resources, which is particularly important for building secure computing environments.

[0135] The use of the PMP mechanism is divided into two directions: Direction 1 is to parse the corresponding address and permission information based on the value of the PMP register; Direction 2 is to configure the PMP register based on the address and the corresponding permission information.

[0136] Assuming the chip supports dividing the memory space into four memory protection regions, i.e., N = 4, the number of registers that need to be configured or parsed is PMPADDR = 4 and PMPCFG = 1. In manual calculation, taking direction 1 as an example, parsing the address and permission information from the registers requires five steps:

[0137] The first step is to parse the PMPCFG register bit by bit according to the RISC-V official documentation. This register occupies 32 bits and includes the address matching modes of 4 memory protection regions, namely NA4 (naturally aligned four-byte mode), TOR (top of address range mode), NAPOT (naturally aligned power mode), and OFF (off mode), as well as read permission, write permission, execute permission, and lock status.

[0138] The second step is to parse the values ​​of the four PMPADDR registers according to the address matching mode obtained from PMPCFG. When the modes are NA4, TOR, and OFF, they are parsed as follows: NA4 represents an address range with a width of 4 bytes starting from the PMPADDR register value; TOR represents an address range with a starting address from the previous PMPADDR register value and an ending address from the current PMPADDR register value; and OFF represents an address register value that does not point to any address range. When the mode is NAPOT, proceed to the third step.

[0139] The third step is to convert the PMPADDR register value of the corresponding memory protection area into binary data and calculate the number of consecutive 1 bits starting from the least significant bit.

[0140] The fourth step is to calculate the address width of the PMPADDR register by referring to the RISC-V official documentation based on the number of consecutive 1 bits.

[0141] The fifth step involves mapping the permission information and lock status of the four memory protection regions parsed by PMPCFG to the address ranges parsed by the four PMPADDRs.

[0142] Direction 2 is the reverse of Direction 1, calculating the register value using the address range and corresponding permission information. This requires the same number of steps and resources, including documentation and a number base converter. It's clear that this process, traditionally done manually, is cumbersome, computationally complex, resource-intensive, and prone to errors. Therefore, an automated tool is needed to simplify this process and improve configuration accuracy and efficiency. Against this backdrop, the PMP Configuration and Resolution Calculator was developed to provide an efficient and reliable solution, helping chip designers and users manage memory addresses faster and better.

[0143] In this embodiment:

[0144] refer to Figure 2 , Figure 2 This is a schematic diagram of the framework. Figure 2 It includes the following: GUI (Graphical User Interface), reg to config (register to configuration information), pmpcfg parsing (physical memory protection configuration register parsing), pmpaddr parsing (physical memory protection address register parsing), config to reg (configuration information to registers), pmpcfg configuration (physical memory protection configuration register configuration), pmpaddr configuration (physical memory protection address register configuration), exception handling, inputreg (input register), output info (output information), input info (input information), outputreg (output register), and error info (error information).

[0145] refer to Figure 2 :

[0146] 1) The PMP calculator is divided into three parts: graphical user interface, parsing module (reg->config) and configuration module (config->reg).

[0147] 2) Graphical User Interface: Responsible for interacting with the user. The user can input the values ​​of the PMPADDR and PMPCFG registers or the address range configured by the user and its corresponding access permissions to obtain the register parsing result or register configuration result.

[0148] 3) Parsing Module: This module parses the address range and corresponding permissions of each memory protection region using the PMP register value. It includes two sub-modules:

[0149] The pmpcfg parsing module parses the user-inputted PMPCFG register value bit by bit to obtain information such as the address matching mode and access permissions for the four memory protection regions.

[0150] The pmpaddr parsing module: After address matching mode judgment, this judgment performs steps such as calculating the number of consecutive 1 bits, calculating the interval width, and arithmetic left shift based on the information output from the pmpcfg parsing module, to parse the corresponding start address, end address, and address width from the four PMPADDR register values ​​input by the user.

[0151] 4) Configuration Module: Configures the corresponding PMP register values ​​according to user needs, including three sub-modules:

[0152] The pmpcfg configuration module configures the value of the PMPCFG register bit by bit based on the user-input permission information, lock status, and address matching mode.

[0153] The pmpaddr configuration module: After steps such as address matching mode judgment, address width calculation, and arithmetic right shift, it configures the value of the PMPADDR register based on the user-input start address, address width, permission information, and address matching mode.

[0154] Anomaly detection module: During register configuration, it detects anomalies such as invalid user input format and invalid address, and outputs error messages to provide feedback to the user through a graphical user interface.

[0155] 5) The correspondence between the PMPCFG register and the address matching mode, access permissions, lock status and other information contained therein are all derived from the RISC-V official documentation.

[0156] 6) Figure 3 The graphical user interface (GUI) of the PMP calculator is shown after startup. Users can choose to use either the PMP register parsing function or the PMP register configuration function. The upper part of the interface is for parsing PMP registers. After entering the PMPADDR and PMPCFG register values ​​in the blank fields, clicking the "Register to Configuration Information" (reg->config) button will retrieve the parsed address and permission information, displayed below the results. The lower part of the interface is for configuring PMP registers. After entering the starting address, address width, permission information, address matching mode, and lock status, clicking the "Configure Information to Registers" (config->reg) button will retrieve the PMPADDR and PMPCFG register values, displayed below the register results. Both functions allow repeated input and calculations; they are independent and do not affect each other.

[0157] like Figure 3 As shown, Figure 3It contains the following: PMP calculator (Physical Memory Protection Calculator), PMPADDR0 (hex) (Physical Memory Protection Address Register 0, hexadecimal), PMPADDR1 (hex) (Physical Memory Protection Address Register 1, hexadecimal), PMPADDR2 (hex) (Physical Memory Protection Address Register 2, hexadecimal), PMPADDR3 (hex) (Physical Memory Protection Address Register 3, hexadecimal), PMPCFG (hex) (Physical Memory Protection Configuration Register, hexadecimal), reg to config (Register to Configuration Information), Info Results, Start Address (hex) (Start Address, hexadecimal), Size (Greater than or equal to 4 bytes), Permissions, Read, Write, Execute, Mode, NAPOT (Natural Alignment Power), Lock, Locked, config to reg (Configuration Information to Register), Reg Results.

[0158] 7) Figure 4 The graphical user interface after performing calculations using both functions.

[0159] like Figure 4 As shown, Figure 4It contains the following: PMP calculator (Physical Memory Protection Calculator), PMPADDR0 (hex) (Physical Memory Protection Address Register 0, hexadecimal), PMPADDR1 (hex) (Physical Memory Protection Address Register 1, hexadecimal), PMPADDR2 (hex) (Physical Memory Protection Address Register 2, hexadecimal), PMPADDR3 (hex) (Physical Memory Protection Address Register 3, hexadecimal), PMPCFG (hex) (Physical Memory Protection Configuration Register, hexadecimal), 1544178f, 51cb756e, 842fc35f, deaf278f, 16848afc, reg to config (Register to Configuration Information), Info Results, PMP window0 (Physical Memory Protection Window 0), NAPOT (Natural Alignment Power), Locked equals True, Permissions, R equals False, W equals False, X equals True, Range, Size, 128 B (bytes), PMPwindow1 (Physical Memory Protection Window 1), TOR (Top of Address Range), forced, 968 MB (megabytes), PMPwindow2 (Physical Memory Protection Window 2), OFF (Off), NA (Not Available), PMP window3 (Physical Memory Protection Window 3), NA4 (Naturally Aligned Four-Byte), 4B (bytes), Start Address (hexadecimal), 10551120, Size (size), greater than or equal to 4B (bytes), 16B (bytes), Permissions, Read, Write, Execute, NAPOT (Naturally Aligned Power), Mode, Lock, Locked, config to reg (Configuration Information to Register), Reg Results (Register Results), CalculatedPMPADDR (Calculated Physical Memory Protection Address Register), real_range (Actual Range), CalculatedPMPCFG (Calculated Physical Memory Protection Configuration Register).

[0160] In the technical solution provided in this embodiment, from the perspective of chip development and use, PMP is the most important dynamic memory management mechanism in RISC-V architecture-based CPU chips. However, the use of the PMP mechanism is complex, cumbersome, and prone to errors. This embodiment provides an efficient solution through a self-designed graphical user interface and built-in computing module, which greatly simplifies the use and development process of the PMP mechanism. This allows users to easily configure and use the chip, while development and verification personnel can more conveniently develop and verify the chip. This not only optimizes the user experience but also accelerates the development cycle and ensures the efficiency and reliability of the chip design.

[0161] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0162] Based on the same inventive concept, this application also provides a register processing apparatus for implementing the register processing method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more register processing apparatus embodiments provided below can be found in the limitations of the register processing method above, and will not be repeated here.

[0163] In one exemplary embodiment, such as Figure 5 As shown, a register processing apparatus 500 is provided, which may include:

[0164] The target acquisition module 501 is used to acquire the register values ​​of the permission configuration registers corresponding to each memory protection area;

[0165] The first parsing module 502 is used to parse the register value of the permission configuration register according to the preset bit field information to obtain the address matching mode information, access permission information and locking status information corresponding to each memory protection area.

[0166] The second parsing module 503 is used to parse the register values ​​of the address registers corresponding to each memory protection region according to the address matching mode information, so as to obtain the address range information of each memory protection region.

[0167] The information determination module 504 is used to determine the protection configuration information of each memory protection area based on access permission information, address range information and lock status information.

[0168] In an exemplary embodiment, the address matching pattern information includes at least one of first address matching pattern information, second address matching pattern information, third address matching pattern information, and fourth address matching pattern information; the second parsing module 503 is further configured to: when the address matching pattern information is the first address matching pattern information, use the register value of the address register as the starting address and the preset width information as the address width information, and determine the address interval information based on the starting address and the address width information; when the address matching pattern information is the second address matching pattern information, determine the starting address and the ending address based on the register value of the address register and the register value of the second adjacent address register in sequence, and determine the address interval information based on the starting address and the ending address; when the address matching pattern information is the third address matching pattern information, perform statistical processing on the register value of the address register for consecutive preset numerical bits to obtain a statistical processing result, determine the address width information based on the statistical processing result, and perform parsing processing on the register value of the address register based on the address width information to obtain the address interval information; when the address matching pattern information is the fourth address matching pattern information, determine that the register value of the address register does not point to any address interval.

[0169] In an exemplary embodiment, the second parsing module 503 is further configured to perform numerical conversion processing on the register value of the address register to obtain the target register value; and to perform statistical processing on the target register value for consecutive preset numerical bits to obtain the statistical processing result.

[0170] In an exemplary embodiment, the device 500 further includes: a configuration processing module, configured to acquire target address range information to be configured, target access permission information, and target address matching mode information; determine the register configuration value of the target address register to be configured based on the target address matching mode information and the target address range information; perform configuration processing on the target address register based on the register configuration value of the target address register; determine the register configuration value of the target permission configuration register to be configured based on the target access permission information, the target address matching mode information, and preset bit field information; and perform configuration processing on the target permission configuration register based on the register configuration value of the target permission configuration register.

[0171] In an exemplary embodiment, the configuration processing module is further configured to: when the target address matching mode information is a first address matching mode information, use the starting address in the target address interval information as the register configuration value of the target address register; when the target address matching mode information is a second address matching mode information, use the starting address and ending address in the target address interval information as the register configuration values ​​of two adjacent target address registers respectively; and when the target address matching mode information is a third address matching mode information, determine the target continuous preset value bits according to the address width information in the target address interval information, and determine the register configuration value of the target address register according to the target continuous preset value bits.

[0172] In an exemplary embodiment, the configuration processing module is further configured to determine read permission configuration bits, write permission configuration bits, and execute permission configuration bits based on target access permission information; determine address matching mode configuration bits based on target address matching mode information; determine lock status configuration bits based on acquired target lock status information; and determine the register configuration value of the target permission configuration register based on the read permission configuration bits, write permission configuration bits, execute permission configuration bits, address matching mode configuration bits, lock status configuration bits, and preset bit field information.

[0173] Each module in the aforementioned register processing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can invoke and execute the operations corresponding to each module.

[0174] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0175] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 6As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a register processing method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0176] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0177] In one exemplary embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0178] In one exemplary embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above-described method embodiments.

[0179] In one exemplary embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.

[0180] Based on the same inventive concept, this application also provides a chip, including a processor coupled to a memory, for executing a computer program or instructions stored in the memory, and implementing the steps in the above method embodiments when the processor executes the computer program or instructions.

[0181] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may be an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD) or other integrated chips, etc.

[0182] Based on the same inventive concept, this application also provides a chip module, such as... Figure 7 As shown, the chip module includes a communication module, a power module, a storage module, and a chip. Among them:

[0183] The power module is used to provide power to the chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the chip module, or for communication between the chip module and external devices; this chip corresponds to the chip in the above chip embodiment.

[0184] The implementation method of this chip module can be found in the relevant content of the above chip embodiment, and will not be repeated here.

[0185] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0186] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0187] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A register processing method, characterized in that, The method includes: Obtain the register values ​​of the permission configuration registers corresponding to each memory protection region; Based on the preset bit field information, the register value of the permission configuration register is parsed to obtain the address matching mode information, access permission information and lock status information corresponding to each memory protection area; Based on the address matching pattern information, the register values ​​of the address registers corresponding to each memory protection region are parsed to obtain the address range information of each memory protection region; Based on the access permission information, the address range information, and the lock status information, the protection configuration information for each memory protection region is determined.

2. The method according to claim 1, characterized in that, The address matching pattern information includes at least one of the following: first address matching pattern information, second address matching pattern information, third address matching pattern information, and fourth address matching pattern information; The step of parsing the register values ​​of the address registers corresponding to each memory protection region based on the address matching pattern information to obtain the address range information of each memory protection region includes: When the address matching mode information is the first address matching mode information, the register value of the address register is used as the starting address, and the preset width information is used as the address width information. The address range information is determined based on the starting address and the address width information. When the address matching mode information is the second address matching mode information, the start address and end address are determined according to the register value of the address register and the register value of the second adjacent address register in sequence, and the address range information is determined according to the start address and the end address; When the address matching mode information is the third address matching mode information, the register value of the address register is subjected to statistical processing of consecutive preset value bits to obtain the statistical processing result. The address width information is determined according to the statistical processing result. The register value of the address register is parsed according to the address width information to obtain the address range information. When the address matching mode information is the fourth address matching mode information, it is determined that the register value of the address register does not point to any address range.

3. The method according to claim 2, characterized in that, The step of performing statistical processing on the register value of the address register, involving consecutive preset value bits, to obtain the statistical processing result includes: The register value of the address register is converted to obtain the target register value; The target register value is subjected to statistical processing of consecutive preset numerical bits to obtain the statistical processing result.

4. The method according to claim 1, characterized in that, The method further includes: Obtain the target address range information, target access permission information, and target address matching pattern information to be configured; Based on the target address matching mode information and the target address range information, determine the register configuration value of the target address register to be configured, and perform configuration processing on the target address register based on the register configuration value of the target address register; Based on the target access permission information, the target address matching mode information, and the preset bit field information, determine the register configuration value of the target permission configuration register to be configured, and perform configuration processing on the target permission configuration register according to the register configuration value of the target permission configuration register.

5. The method according to claim 4, characterized in that, The step of determining the register configuration value of the target address register to be configured based on the target address matching mode information and the target address range information includes: When the target address matching mode information is the first address matching mode information, the starting address in the target address range information is used as the register configuration value of the target address register; When the target address matching mode information is the second address matching mode information, the start address and end address in the target address range information are respectively used as the register configuration values ​​of two adjacent target address registers; When the target address matching mode information is the third address matching mode information, the target continuous preset value bits are determined according to the address width information in the target address range information, and the register configuration value of the target address register is determined according to the target continuous preset value bits.

6. The method according to claim 4, characterized in that, The step of determining the register configuration value of the target permission configuration register to be configured based on the target access permission information, the target address matching mode information, and the preset bit field information includes: Based on the target access permission information, determine the read permission configuration bit, write permission configuration bit, and execute permission configuration bit; based on the target address matching mode information, determine the address matching mode configuration bit; and based on the obtained target lock status information, determine the lock status configuration bit. The register configuration value of the target permission configuration register is determined based on the read permission configuration bit, the write permission configuration bit, the execute permission configuration bit, the address matching mode configuration bit, the lock status configuration bit, and the preset bit field information.

7. A register processing apparatus, characterized in that, The device includes: The target acquisition module is used to obtain the register values ​​of the permission configuration registers corresponding to each memory protection region; The first parsing module is used to parse the register value of the permission configuration register according to the preset bit field information to obtain the address matching mode information, access permission information and locking status information corresponding to each memory protection area. The second parsing module is used to parse the register values ​​of the address registers corresponding to each memory protection region according to the address matching mode information, so as to obtain the address range information of each memory protection region. The information determination module is used to determine the protection configuration information of each memory protection region based on the access permission information, the address range information, and the locking status information.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A chip, characterized in that, The device includes a processor and a communication interface, wherein the processor is configured to cause the chip to perform the steps of the method described in any one of claims 1 to 6.

10. A chip module, characterized in that, This includes communication modules, power modules, storage modules, and chips, among which: The power module is used to provide power to the chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the chip module, or for communication between the chip module and external devices. The chip is used to perform the steps of the method according to any one of claims 1 to 6.

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