A method for automatic generation of options for a parameterized unit of a semiconductor device
By automatically generating parameterized cell options for semiconductor devices and automatically setting metal layers, the problem of increased workload and verification times caused by adding metal layers is solved, thus improving design efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NEXCHIP SEMICON CO LTD
- Filing Date
- 2026-05-19
- Publication Date
- 2026-08-04
AI Technical Summary
In semiconductor devices, as the number of metal layers increases, the number of MOM devices that need to be fabricated and verified also increases, leading to an increase in workload and verification frequency.
A method for automatically generating parameterized unit options for semiconductor devices is provided. By reading user technical documents, the method automatically sets and displays the metal layer options of the parameterized units, reducing the amount of manual coding work and realizing the automatic configuration of metal layer options.
This reduces the workload and verification times for setting parameterized unit options for semiconductor devices, thus improving design efficiency.
Smart Images
Figure CN122221790B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor design and manufacturing technology, and particularly relates to a method for automatically generating options for parameterized units of a semiconductor device. Background Technology
[0002] Semiconductor devices typically include a Component Description Format (CDF), symbols, parameterized cells, and callbacks. For semiconductor devices such as stacked finger metal-oxide-metal (MOM) capacitors, the CDF changes depending on the metal layer selection of the MOM capacitor. Therefore, when the metal layer of a semiconductor device like a MOM capacitor changes, it's necessary to first copy the metal layer options from the previous MOM device and then create a CDF based on the changed metal layer structure to form the MOM device, followed by MOM device verification.
[0003] Therefore, when manufacturing semiconductor devices such as MOM devices, as the number of metal layers increases, the number of MOM devices that need to be manufactured also increases, and the number of verifications of MOM devices also increases accordingly. Summary of the Invention
[0004] The purpose of this invention is to provide an automatic generation method for the options of parameterized units in semiconductor devices, which can reduce the workload and verification times when setting the options of parameterized units in semiconductor devices.
[0005] To solve the above-mentioned technical problems, the present invention is achieved through the following technical solution: This invention provides a method for automatically generating options for parameterized units of a semiconductor device, comprising at least the following steps: When adding an instance of the semiconductor device, read the description in the technical documentation used by the user; Obtain the metal list corresponding to the example from the technical document; and When the instance is configured in the cell, the option to set and display the metal layer of the parameterized cell is provided.
[0006] In one embodiment of the present invention, the semiconductor device is a metal-oxide-metal capacitor, and the metal layer is an electrode constituting the metal-oxide-metal capacitor.
[0007] In one embodiment of the present invention, the semiconductor device is a metal-insulator-metal capacitor, and the metal layer is an electrode constituting the metal-insulator-metal capacitor.
[0008] In one embodiment of the present invention, the semiconductor device is a metal resistor.
[0009] In one embodiment of the present invention, the semiconductor device is a metal-oxide-semiconductor device, and the metal layer is a metal layer that forms the lead-out wiring connecting the source diffusion layer and the drain diffusion layer of the metal-oxide-semiconductor device.
[0010] In one embodiment of the present invention, the metal list is a fine metal list.
[0011] In one embodiment of the present invention, the automatic generation method further includes the following steps: by adding an instance of the semiconductor device as a trigger to automatically execute the steps of reading the description of the technical document used by the user, obtaining the metal list corresponding to the instance from the technical document, and setting and displaying the metal layer of the parameterized unit, thereby changing the component description format of the semiconductor device.
[0012] In one embodiment of the present invention, the automatic generation method further includes the following step: selecting a top metal layer and a bottom metal layer as electrodes of the semiconductor device from the options of the modified component description format, thereby forming an MOM device.
[0013] In one embodiment of the present invention, the automatic generation method further includes the following steps: selecting, from the options of the modified component description format, the metal layer forming the lead-out wiring for the source diffusion layer connection of the MOS device and the metal layer forming the lead-out wiring for the drain diffusion layer connection of the MOS device, thereby forming the MOS device.
[0014] In one embodiment of the present invention, the method for automatically generating options of the parameterization unit of the semiconductor device is programmed as software and installed on a computer device for execution by the computer device.
[0015] In summary, the automatic generation method for the parameterization unit of a semiconductor device provided by the present invention has the unexpected effect that when an instance of a semiconductor device is configured into a unit, the metal layer option is automatically set in the parameterization unit of the semiconductor device, thereby reducing the amount of work required to set the option and further reducing the number of verifications of the semiconductor device.
[0016] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a flowchart illustrating the metal layer technology process of existing MOM devices.
[0019] Figure 2 This is a flowchart of a method for automatically generating parameterized unit options for a semiconductor device (MOM capacitor) in the first embodiment of the present invention.
[0020] Figure 3 This is a schematic diagram of the MOM capacitor in this invention, wherein... Figure 3 Part (a) is a top view of the MOM capacitor in one embodiment of the present invention. Figure 3 Part (b) is a cross-sectional view of the MOM capacitor in one embodiment of the present invention.
[0021] Figure 4 This is a flowchart of a method for automatically generating metal layer options in the application of parameterized units in MOM capacitors according to an embodiment of the present invention.
[0022] Figure 5 This is a flowchart of a method for automatically generating parameterized unit options for a semiconductor device (MOS device) in a second embodiment of the present invention.
[0023] Figure 6 These are three MOS devices with different structures in this invention, wherein... Figure 6 Part (A) in the text represents a MOS device with two metal layers. Figure 6 Part (B) in the text represents a MOS device with three metal layers. Figure 6 The (C) part in the text represents a MOS device with four metal layers.
[0024] Figure 7 This is a flowchart of a method for automatically generating metal layer options in the parameterized cell application of an N-channel MOS device according to an embodiment of the present invention. Detailed Implementation
[0025] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0026] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0027] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.
[0028] Stacked finger metal-oxide-metal (MOM) capacitors are widely used in Large Scale Integration (LSI) designs, where two metal patterns form the two electrodes of the capacitor, thus creating capacitance. The capacitance of an MOM capacitor increases with the number of metal layers with metal patterns. Furthermore, various proposals for the capacitance implementation and modeling of MOM capacitors have been disclosed in the prior art.
[0029] On the other hand, the available metal layer combinations in a MOM capacitor vary depending on the number of metal layers used in the product. Therefore, it is necessary to be able to change the available bottom and top metals based on the number of metal layers used in the product. The bottom and top metals are the metal layers that constitute the electrodes of the MOM capacitor; paired electrodes constitute the MOM capacitor.
[0030] In general, parameterized cells (P-cells) are frequently used in full-custom layout design of semiconductor chips to improve layout design efficiency. P-cells are usually included in the process design kit (PDK) provided by the semiconductor manufacturing plant (FAB), and the process design kit meets the design rules of each manufacturing process.
[0031] In this application, the P-cell of the MOM capacitor is a library included in the PDK provided by FAB and used in the full-custom design rules.
[0032] Generally, the device components of an MOM device consist of a Component Description Format (CDF), symbols, P-cells, and callbacks. Since the CDF varies depending on the metal layers chosen for the MOM capacitors, a CDF needs to be fabricated for each MOM device's structure. In this disclosure, the structure of the MOM device refers to the structure defined by metal layers stacked in the chip thickness direction that can serve as electrodes for the MOM capacitors.
[0033] like Figure 1 As shown, PDK developers first set the metal layer options for the two-layer metal structure (M1to2) and create CDF parameters, then create and verify the two-layer metal MOM device. The verification of the MOM device includes, for example, source code syntax checking (Lint checking), callback checking, and P-cell design rule checking / layout and circuitry. Figure 1 Consistency checks (DRC / LVS) and Hspice / Spectre simulation checks are performed. Next, when setting the metal layer options for the three-layer metal structure (M1to3), the metal layer options for the two-layer structure are copied, and the CDF parameters of the two-layer metal structure are corrected to create the CDF parameters for the three-layer metal structure, thereby creating and verifying the three-layer metal MOM device. CDF parameters are then created sequentially for metal layer combinations supported by the PDK, such as four-layer metal structures (M1to4), five-layer metal structures (M1to5), and six-layer metal structures (M1to6), thereby creating and verifying the MOM device.
[0034] Combination Figure 1 As shown, since MOM devices need to be fabricated for different structures composed of multiple stacked metal layers along the chip thickness direction, the number of MOM devices required increases as the number of combinable metal layers increases. That is, PDK developers need to prepare all available structures in advance and fabricate MOM devices for each structure. For example, in... Figure 1 As shown in the flowchart, five types of MOM devices need to be manufactured in advance. Increasing the number of MOM devices will not only increase the workload, but also increase the number of verifications required for the manufactured MOM devices.
[0035] In the first embodiment of the invention, such as Figure 2 As shown, Figure 2 The flowchart of the automatic generation method for the parameterization unit options of the semiconductor device (MOM capacitor) provided in this application can be applied to semiconductor devices such as MOM capacitors. Furthermore, the automatic generation method for the parameterization unit options of the semiconductor device is programmed as software and installed on a computer device for execution by the computer device.
[0036] like Figure 2As shown, the automatic generation method for the parameterization unit options of the semiconductor device provided in this application includes steps S1 to S5.
[0037] Step S1: When adding an embodiment of a semiconductor device, read the description in the technical documents used by the user.
[0038] In one embodiment of the present invention, when a program installed on a computer device is launched, and the circuit designer (user) instructs the addition of an MOM capacitor, the description of the technical document used by the user is read. The technical document is contained in a process design kit owned by the user and includes information such as metal layers.
[0039] Step S2: Obtain the list of metals corresponding to the example from the technical documents.
[0040] In one embodiment of the present invention, after reading the description in the technical document, a metal list is automatically obtained from the technical document. When a circuit designer (user) instructs the addition of an MOM capacitor, since the metal layer used in MOM devices is typically thin, the metals in the obtained list are thin-film and fine metals, i.e., fine metals. In this case, the obtained metal list is a fine metal list.
[0041] Step S3: When configuring an instance into a cell, set and display the options for the metal layer of the parameterized cell.
[0042] In one embodiment of the present invention, when a circuit designer (user) instructs the addition of an instance of a MOM capacitor, and a list of fine metals is obtained, the metal layer options of the MOM capacitor are set and displayed when the instance of the MOM capacitor is configured into the cell.
[0043] Step S4: The component description format of the semiconductor device is changed.
[0044] In one embodiment of the present invention, steps S1 to S3 are automatically executed by appending an instance of MOM as a trigger, thereby changing the CDF of the MOM device.
[0045] Step S5: Semiconductor device formation.
[0046] In one embodiment of the present invention, from the options of the modified CDF, the user selects the top metal layer and the bottom metal layer as electrodes of the MOM device, thereby forming the MOM device.
[0047] like Figure 2 As shown, steps S1 to S3 are executed automatically when adding MOM capacitors, without the need for manual operation.
[0048] The following describes the application of the method described in the above embodiments to the manufacturing process of MOM capacitors with a four-layer metal structure (M1to4).
[0049] like Figure 3 As shown in part (a), the above method applies to a four-layer MOM capacitor, which is a multi-finger capacitor formed by interlocking two electrodes, A and B, as metal patterns within a semiconductor chip. The electrodes are made using metal wiring formed on the chip, and electrostatic capacitance is generated through the capacitive coupling effect between the metal wirings. Furthermore, as... Figure 3 As shown in part (b), four metal wirings M1, M2, M3, and M4 are arranged at intervals along the thickness direction of the chip as metal layers. For example, the uppermost metal wiring M4 can be selected as the top metal, and the lowermost metal wiring M1 can be selected as the bottom metal, thereby forming a MOM capacitor with the top and bottom metals as electrodes. However, the selection of the top and bottom metals is not limited to the above method. For example, metal wiring M2 can also be selected as the bottom metal, and metal wiring M3 can be selected as the top metal layer to form an MOM capacitor.
[0050] Next, refer to Figure 4 The implementation method for setting the top metal layer and bottom metal layer options of the MOM device will be described.
[0051] First, the program is started by launching a computer device, and the circuit designer (user) selects "Add Instance" from the menu displayed in the program. In this embodiment, the added instance is a four-layer metal structure. Next, triggered by the addition of the instance, the settings that are automatically executed when configuring components into the instance form are set as options, and three scripts 1, 2, and 3 are set (step S10). In script 1, the CDF window will display "Library Name" as "M1to4", "Cell Name" as "MOM", and the MOM capacitor as the circuit diagram. Since the bottom metal layer and top metal layer options are not set in script 1, these two items are not displayed. Triggered by the selection of "Add Instance", the program automatically accesses the technical documents used by the user and reads the description (step S11).
[0052] Next, a list of layers used as metals (electrodes) and meeting the requirements of thin films and fine textures is obtained from the technical documents, i.e., a fine metal list (step S12). In this embodiment, since the example is a four-layer metal structure, as shown in script 2, information on each metal used as metal, namely “1M”, “2M”, “3M”, and “4M”, is obtained. Then, step S13 is performed. As shown in script 3, in the CDF window, in addition to displaying “M1to4” for “Library Name” and “MOM” for “Cell Name”, “1M”, “2M”, “3M”, and “4M” are set as options for bottom metal layers, and “1M”, “2M”, “3M”, and “4M” are set as options for top metal layers.
[0053] Steps S11 to S13 are executed automatically after step S10. In step S13, after the circuit designer selects the options for the pre-set bottom metal layer and top metal layer respectively, an instance of the MOM device with the selected bottom metal layer and top metal layer as electrodes is configured into the cell (step S14).
[0054] According to the above implementation method, the design of the P-cell is simplified compared to existing methods. Specifically, when an instance of the MOM device is configured into the cell, the metal layer options of the MOM device are automatically loaded and configured in conjunction with the technical documentation, thus reducing the amount of manual coding work required to cover the metal combinations supported by the PDK. In other words, there is no need to fabricate multiple MOM devices in advance; the circuit designer only needs to select one structure. When an instance of the MOM device is configured into the cell, the system reads and sets the metal layer options of the MOM device from the technical documentation used by the circuit designer, so a single MOM device can adapt to multiple structures. Furthermore, even if the total number of metal layers constituting the metal structure is different, only one MOM device needs to be fabricated, thus reducing the number of verifications required for the MOM device.
[0055] In the second embodiment of the invention, such as Figure 5 As shown, Figure 5 The flowchart of the automatic generation method for the parameterization unit options of a semiconductor device (MOS device) provided in this application can be applied to semiconductor devices such as metal-oxide-semiconductor (MOS) devices. Similar to the first embodiment, the automatic generation method for the parameterization unit options of the semiconductor device is programmed as software and installed on a computer device for execution by the computer device.
[0056] like Figure 5 As shown, the automatic generation method for the parameterization unit options of the semiconductor device provided in this application includes steps S21 to S25.
[0057] Step S21: When adding an embodiment of a semiconductor device, read the description in the technical documents used by the user.
[0058] In one embodiment of the present invention, when a program installed on a computer device is launched, and the circuit designer (user) instructs the addition of an instance of a MOS device, the description of the technical document used by the user is read. The technical document is contained in a process design kit owned by the user and includes information such as metal layers.
[0059] Step S22: Obtain the metal list corresponding to the example from the technical documents.
[0060] In one embodiment of the present invention, after reading the description in the technical document, a metal list is automatically obtained from the technical document. When a circuit designer (user) instructs the addition of an instance of a MOS device, since the metal layers of the lead-out wiring connected to the source and drain diffusion layers of the MOS device are typically thin, the metals in the obtained list are thin-film and fine metals, i.e., fine metals. In this case, the obtained metal list is a fine metal list.
[0061] Step S23: When configuring an instance into a cell, set and display the options for the metal layer of the parameterized cell.
[0062] In one embodiment of the present invention, when a circuit designer (user) instructs the addition of an instance of a MOS device to be configured into a cell, after obtaining a list of fine metals, the metal layer option for forming the lead-out wiring connecting the source diffusion layer and the drain diffusion layer of the MOS device is set and displayed when the instance of the MOS device is configured into the cell.
[0063] Step S24: The component description format of the semiconductor device is changed.
[0064] In one embodiment of the present invention, steps S21 to S23 are automatically executed by adding an instance of the MOS as a trigger, thereby changing the CDF of the MOS device.
[0065] Step S25: Semiconductor device formation.
[0066] In one embodiment of the present invention, from the options of the modified CDF, the user selects the metal layer for forming the lead-out wiring of the source diffusion layer connection of the MOS device and the metal layer for forming the lead-out wiring of the drain diffusion layer connection of the MOS device, thereby forming the MOS device.
[0067] like Figure 5 As shown, steps S21 to S23 are executed automatically when adding MOM capacitors, without the need for manual operation.
[0068] like Figure 6 As shown, the MOS device applied in the second embodiment will be described below. Figure 6 Part (A) of the middle Figure 6 Part (B) of the text, and Figure 6 In section (C), the top view is the top view and the bottom view is the cross-sectional view.
[0069] like Figure 6 As shown, Figure 6 The MOS device 1a shown in part (A) employs a two-layer metal structure (M1 to M2). The metal layers forming the lead-out wiring connecting the source diffusion layer 2a and the drain diffusion layer 3a are stacked in the order of M11 and M12. A gate electrode 4a is disposed between the source diffusion layer 2a and the drain diffusion layer 3a. Either of the metal layers M11 and M12 stacked along the film thickness direction for connection to the source diffusion layer 2a can serve as the lead-out wiring connected to the source diffusion layer 2a. Similarly, either of the metal layers M11 and M12 stacked along the film thickness direction for connection to the drain diffusion layer 3a can serve as the lead-out wiring connected to the drain diffusion layer 3a.
[0070] like Figure 6 As shown, Figure 6 The MOS device 1b shown in section (B) employs a three-layer metal structure (M1 to M3). The metal layers forming the lead-out wiring connecting the source diffusion layer 2b and the drain diffusion layer 3b are stacked in the order of M11, M12, and M13. A gate electrode 4b is disposed between the source diffusion layer 2b and the drain diffusion layer 3b. Any one of the metal layers M11, M12, and M13 stacked along the film thickness direction for connection to the source diffusion layer 2b can serve as a lead-out wiring connected to the source diffusion layer 2b. Similarly, any one of the metal layers M11, M12, and M13 stacked along the film thickness direction for connection to the drain diffusion layer 3b can serve as a lead-out wiring connected to the drain diffusion layer 3b.
[0071] like Figure 6 As shown, Figure 6The MOS device 1c shown in section (C) employs a three-layer metal structure (M1 to M4). The metal layers forming the lead-out wiring connecting the source diffusion layer 2c and the drain diffusion layer 3c are stacked in the order of M11, M12, M13, and M14. A gate electrode 4c is disposed between the source diffusion layer 2c and the drain diffusion layer 3c. Any one of the metal layers M11, M12, M13, and M14 stacked along the film thickness direction for connection to the source diffusion layer 2c can serve as a lead-out wiring connected to the source diffusion layer 2c. Similarly, any one of the metal layers M11, M12, M13, and M14 stacked along the film thickness direction for connection to the drain diffusion layer 3b can serve as a lead-out wiring connected to the drain diffusion layer 3c.
[0072] Please see Figure 6 As shown, in Figure 6 The MOS device 1a shown in part (A) is described in the text. Figure 6 The MOS device 1b shown in section (B) is... Figure 6 In the cross-sectional view of MOS device 1c shown in part (C), metal layers M11, M12, M13 and M14 and gate electrodes 4a, 4b and 4c are surrounded by oxides such as silicon oxide. For the selected source metal layer, drain metal layer and gate electrode, wiring (not shown) is electrically connected respectively. These wirings are used to control the corresponding MOS devices 1a, MOS devices 1b and MOS devices 1c.
[0073] Next, refer to Figure 7 The implementation method for setting the metal layer options for the lead-out wiring of the source diffusion layer and drain diffusion layer of the MOS device will be described.
[0074] First, the program is started by booting a computer device, and the circuit designer (user) selects "Add Instance" from the menu displayed in the program. In this embodiment, the added instance is an N-channel MOS device (NMOS) with a four-layer metal structure. The four-layer metal structure N-channel MOS device is a type of MOS device.
[0075] Next, triggered by adding an instance, i.e., setting the automatic execution of the configuration when the component is configured to the instantiation form, three scripts 1, 2, and 3 are set (step S31). In script 1, the CDF window will display "Library Name" as "M1to4", "Cell Name" as "NMOS", and the N-channel MOS device as a circuit diagram. Since script 1 does not set the option for the metal layer forming the lead-out wiring connecting the source diffusion layer and the drain diffusion layer, these two items are not displayed. Triggered by selecting "Add Instance", the program automatically accesses the technical document used by the user and reads the description (step S32).
[0076] Next, a list of layers whose purpose is metal (lead wiring) and which meet the requirements of thin film and fine detail is obtained from the technical documents, i.e., a fine metal list (step S33). In this embodiment, since the example is a four-layer metal structure, as shown in script 2, information on each metal whose purpose is metal, namely “1M”, “2M”, “3M”, and “4M”, is obtained. Then, proceed to step S34. As shown in script 3, in the CDF window, in addition to displaying “M1to4” in “Library Name” and “NMOS” in “Cell Name”, “1M”, “2M”, “3M”, and “4M” are set as the source metal layers for lead wiring connected to the source diffusion layer. Figure 7 The option is labeled "Source Metal Layer" and "1M", "2M", "3M" and "4M" are set as the drain metal layer for the lead-out wiring connected to the drain diffusion layer. Figure 7 The option is denoted as "drain metal layer".
[0077] Steps S32 to S34 are executed automatically after step S31. In step S34, after the circuit designer selects the pre-defined source metal layer and drain metal layer options respectively, an instance of a MOS device with the selected source metal layer as a lead-out wiring connected to the source diffusion layer and the selected drain metal layer as a lead-out wiring connected to the drain diffusion layer is configured in the cell (step S35). Furthermore, the same metal layer will not be selected as both the source and drain metal layers simultaneously.
[0078] According to the above implementation method, the design of the P-cell is simplified compared to existing methods. Specifically, when an instance of an N-channel MOS device is configured into the cell, the options for the metal layers used for the lead-out wiring connecting the source and drain diffusion layers of the N-channel MOS device are automatically loaded and configured in conjunction with the technical documentation. Therefore, similar to the first embodiment, the amount of manual coding work required to cover the metal combinations supported by the PDK can be reduced. In other words, it is not necessary to fabricate multiple N-channel MOS devices in advance. The circuit designer only needs to select one structure. When an instance of an N-channel MOS device is configured into the cell, the system reads from the technical documentation used by the circuit designer and sets the options for the metal layers that can be used as lead-out wiring connecting the source and drain diffusion layers of the N-channel MOS device. Therefore, a single N-channel MOS device can adapt to multiple structures. Furthermore, even if the total number of metal layers constituting the metal structure is different, only one N-channel MOS device needs to be fabricated, thus reducing the number of verification steps for the N-channel MOS device.
[0079] Furthermore, this invention can be applied not only to MOM devices and MOS devices, but also to semiconductor devices such as metal-insulator-metal (MIM) capacitors and metal resistors, whose layout is modified according to the number of metal combinations supported by the PDK. Specifically, when the semiconductor device is a metal-oxide-metal (MOM) capacitor, the metal layer constitutes the electrode of the MOM capacitor. When the semiconductor device is a metal-insulator-metal (MIM) capacitor, the metal layer constitutes the electrode of the MIM capacitor.
[0080] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims
1. A method for automatically generating options for parameterized units of a semiconductor device, characterized in that, At least the following steps are included: When adding an instance of the semiconductor device, read the description in the technical documentation used by the user; Obtain the metal list corresponding to the example from the technical document; as well as When the instance is configured in the cell, the option to set and display the metal layer of the parameterized cell is provided. Specifically, by adding an instance of the semiconductor device as a trigger to automatically execute the steps of reading the description of the technical document used by the user, obtaining the metal list corresponding to the instance from the technical document, and setting and displaying the metal layer of the parameterized unit, the component description format of the semiconductor device is changed.
2. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, The semiconductor device is a metal-oxide-metal capacitor, and the metal layer is the electrode constituting the metal-oxide-metal capacitor.
3. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, The semiconductor device is a metal-insulator-metal capacitor, and the metal layer is the electrode constituting the metal-insulator-metal capacitor.
4. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, The semiconductor device is a metal resistor.
5. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, The semiconductor device is a metal-oxide-semiconductor device, and the metal layer is the metal layer that forms the lead-out wiring connecting the source diffusion layer and the drain diffusion layer of the metal-oxide-semiconductor device.
6. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, The metal list is a fine metal list.
7. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, The automatic generation method further includes the following steps: selecting a top metal layer and a bottom metal layer as electrodes of the semiconductor device from the options of the modified component description format, thereby forming an MOM device.
8. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, From the options in the modified component description format, select the metal layers that form the lead-out wiring for the source diffusion layer connection of the MOS device and the metal layers that form the lead-out wiring for the drain diffusion layer connection of the MOS device to form the MOS device, thereby forming the MOS device.
9. The method for automatically generating options for the parameterization unit of a semiconductor device according to claim 1, characterized in that, The method for automatically generating options for the parameterization unit of the semiconductor device is programmed as software and installed on a computer device for execution by the computer device.