Chip verification method, device, equipment, medium and program product

Abstract

Embodiments of the present application disclose a chip verification method, a chip verification device, computer equipment, a computer readable storage medium and a computer program product. The method comprises: initiating a memory access transaction to a first chip to be tested; the memory access transaction is for a first address in an intermediate physical address of the first chip, and an expected global physical address corresponding to the first address is located in a second chip; detecting the output of a target inter-chip interconnection interface of the first chip, the target inter-chip interconnection interface being an inter-chip interconnection interface connected with the second chip in the first chip; and determining that the first chip passes the inter-chip interconnection transmission verification when it is determined that a target address of a memory access request detected on the target inter-chip interconnection interface is the expected global physical address.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of integrated circuit technology, and in particular to a chip verification method, a chip verification apparatus, a computer device, a computer-readable storage medium, and a computer program product. Background Technology

[0002] In virtualization scenarios, virtual machines need to access resources across multiple chips based on inter-chip interconnection and address mapping mechanisms, which necessitates verification of inter-chip interconnection performance. In related technologies, this can typically be verified through simulation methods. This involves instantiating multiple complete chip models in a simulation platform and physically connecting them via interconnect interfaces to construct a multi-chip simulation environment for verifying inter-chip interconnection performance. However, this method consumes significant computing resources and simulation licenses, resulting in slow simulation speeds and lengthy verification iteration cycles. Summary of the Invention

[0003] This application provides at least one chip verification method, a chip verification device, a computer device, a computer-readable storage medium, and a computer program product.

[0004] The technical solution of this application embodiment is implemented as follows: On one hand, embodiments of this application provide a chip verification method, the method comprising: initiating a memory access transaction to a first chip to be tested; the memory access transaction being directed to a first address in the intermediate physical addresses of the first chip, the expected global physical address corresponding to the first address being located in a second chip; detecting the output of a target inter-chip interconnect interface of the first chip, the target inter-chip interconnect interface being an inter-chip interconnect interface in the first chip connected to the second chip; and determining that the first chip is verified through inter-chip interconnect transmission when it is determined that the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address.

[0005] In some embodiments, the method further includes: determining the expected global physical address corresponding to the first address of the memory access transaction based on the address mapping relationship of the first chip; the address mapping relationship includes a mapping relationship that maps the intermediate physical address of the first chip to the global physical address belonging to the second chip; and determining the target inter-chip interconnect interface for connecting the second chip from multiple interfaces of the first chip according to the expected global physical address and preset routing information, wherein the preset routing information is used to indicate the inter-chip interconnect interface corresponding to different global physical address ranges, and different chips manage different global physical address ranges.

[0006] In some embodiments, determining the target inter-chip interconnect interface for connecting the second chip from multiple interfaces of the first chip based on the expected global physical address and preset routing information includes: comparing the expected global physical address with different global physical address ranges in the preset routing information; when the expected global physical address belongs to the global physical address range of the second chip, using the inter-chip interconnect interface corresponding to the second chip in the preset routing information as the target inter-chip interconnect interface for connecting the second chip.

[0007] In some embodiments, the method further includes: if a data packet with a destination address of the expected global physical address is detected on the target inter-chip interconnect interface, and the data packet is not detected on other inter-chip interconnect interfaces of the first chip, determining that the destination address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address.

[0008] In some embodiments, the method further includes: detecting the output data of the address translation unit of the first chip; and determining that the first chip passes the address translation verification if the expected global physical address is detected in the output data of the address translation unit.

[0009] In some embodiments, the method further includes: determining the target inter-chip interconnect interface for connecting the second chip from a plurality of interfaces of the first chip based on the expected global physical address and preset routing information, comprising: determining the target inter-chip interconnect interface for connecting the second chip from a plurality of interfaces of the first chip based on the expected global physical address and preset routing information when it is determined that the first chip has passed address translation verification.

[0010] In some embodiments, the method further includes: writing the address mapping relationship and the preset routing information into the mapping table of the address translation unit of the first chip through the configuration interface of the first chip; wherein, the global physical address range allocated for the second chip in the preset routing information is pre-allocated according to the logical location of the second chip in the on-chip network, and the second chip is a chip that is logically interconnected with the first chip but does not physically exist in the chip emulation environment; the expected global physical address is located within the global physical address range allocated for the second chip in the preset routing information.

[0011] Secondly, embodiments of this application provide a chip verification apparatus, the apparatus comprising: The memory access module is used to initiate a memory access transaction to the first chip to be tested; the memory access transaction is for any first address in the intermediate physical addresses of the first chip, and the expected global physical address corresponding to the first address is located in the second chip; The first determining module is used to detect the output of the inter-chip interconnection interface of the first chip, wherein the inter-chip interconnection interface is the inter-chip interconnection interface in the first chip that is connected to the second chip; The verification module is used to determine that the first chip has verified the data through the inter-chip interconnect when a memory access request with the target address being the expected global physical address is detected on the inter-chip interconnect interface.

[0012] Thirdly, embodiments of this application provide a computer device, including a memory and a processor. The memory stores a computer program that can run on the processor, and when the processor executes the program, it implements the steps in the method provided in the first aspect of embodiments of this application.

[0013] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method described in the first aspect of embodiments of this application.

[0014] Fifthly, embodiments of this application provide a computer program product, the computer program product including a non-transitory computer-readable storage medium storing a computer program, wherein when the computer program is read and executed by a computer, it implements the steps of the method provided in the first aspect of embodiments of this application.

[0015] This application provides a chip verification method that initiates a memory access transaction to a first chip under test. The memory access transaction targets a first address in the intermediate physical address of the first chip, and the expected global physical address corresponding to the first address is located in a second chip. The method detects the output of a target inter-chip interconnect interface of the first chip, where the target inter-chip interconnect interface is the inter-chip interconnect interface in the first chip connected to the second chip. When it is determined that the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address, it is determined that the first chip is verified through inter-chip interconnect transmission. In this way, by detecting whether the expected global physical address of the memory access transaction exists in the inter-chip interconnect interface connected to the second chip when initiating a memory access transaction to the first chip, a mapping relationship can be configured in the chip to the global physical address of any interconnected second chip. This allows a single chip to have the ability to access a virtual second chip, so that when verifying the chip, it is no longer necessary to rely on real multi-chip physical connections. Instead, only a single chip model can be instantiated in the chip simulation environment to simulate and verify its complete data path to the virtual remote chip (i.e., the second chip). This can save computing resources and thus improve simulation speed and accelerate the verification iteration cycle.

[0016] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this application. Attached Figure Description

[0017] Figure 1 This is a flowchart of a chip verification method provided in an embodiment of this application; Figure 2 This is a schematic diagram of a chip verification device provided in an embodiment of this application; Figure 3 This is a flowchart of a chip verification method provided in an embodiment of this application. Figure 2 ; Figure 4 This is a schematic diagram of a multi-chip interconnection provided in the background technology of this application; Figure 5 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application.

[0018] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In the following description, references to "some embodiments" refer to a subset of all possible embodiments. It is understood that "some embodiments" may be the same or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this application.

[0022] In the following description, terms such as intermediate physical address, global physical address, inter-chip interconnection interface, and address translation unit are key concepts in this invention. For ease of understanding, these terms are briefly explained below: 1) Intermediate Physical Address (IPA): In a virtualization environment, this is the address used by the virtual machine when initiating an access request. After address translation, this address is mapped to the actual physical address on the remote chip, enabling cross-chip resource access.

[0023] 2) Global Physical Address (GPA): This refers to a unique physical address identifier in the entire multi-chip system. It usually includes the chip identifier and the local address offset, and is used to uniquely identify the physical location of a memory block or resource.

[0024] 3) Inter-Chip Interface: This refers to the communication channel connecting two different chips, such as the MTLINK interface, which is used to realize transaction transmission and data exchange between chips.

[0025] 4) Extended Address Translation Agent (EATA): This is a hardware module located inside the chip that is responsible for translating intermediate physical addresses (IPAs) into corresponding global physical addresses (GPAs), thereby supporting cross-chip memory access operations.

[0026] 5) Single-Chip Emulation Environment: This refers to instantiating only one chip's RTL model during the verification process and simulating its behavior in a multi-chip cluster through configuration, in order to reduce resource consumption and improve verification efficiency.

[0027] 6) Cross-Card Virtualization Logic: This refers to the mechanism by which a virtual machine can use resources across multiple physical chips in a virtualization scenario, including functions such as address translation, routing judgment, and resource isolation.

[0028] 7) Verification Criteria: These are standards used to determine whether a chip has correctly performed the cross-card access function, such as whether the address translation is correct and whether the transaction has been sent to the correct inter-chip interconnect interface.

[0029] Currently, in virtualization scenarios, virtual machines need to access resources across multiple chips based on inter-chip interconnection and address mapping mechanisms. Therefore, it is necessary to verify whether the chip design can correctly handle such cross-chip access. In related technologies, a full-system multi-chip simulation environment is typically built, and multiple (e.g., 2, 4, or 8) complete chip register transfer level (RTL) design models are loaded and instantiated. Through simulation scripts or test platforms, the inter-chip physical interconnect interfaces of these chip models are connected according to the actual topology of the target system to simulate the electrical and protocol layer links between chips. Test programs or verification scenarios are then run on the virtual multi-chip system built in this environment to stimulate cross-chip memory access requests and observe the data transmission path, latency, bandwidth, and the correctness of the final result between chips.

[0030] However, using the above method, because each complete chip RTL model is extremely complex, the multi-chip simulation environment consumes a large amount of memory and CPU computing resources during verification. Simulating multiple such models simultaneously places extremely high demands on the server cluster configuration, consuming a large amount of computing resources and simulation licenses. Moreover, the complexity of multiple chips is superimposed in the multi-chip simulation environment, making the simulator run extremely slowly, which in turn makes the chip development and verification iteration cycle extremely slow, seriously dragging down the overall project progress. On the other hand, once the multi-chip simulation environment is connected according to a certain physical topology, the connection relationship between the chips is fixed. If you want to verify the behavior of the chips under different interconnect topologies (e.g., from a 4-card full connection to an 8-card ring connection), the simulation environment must be rebuilt, which is cumbersome and time-consuming.

[0031] To address the aforementioned issues, this application proposes a chip verification method, a chip verification apparatus, a computer device, a computer-readable storage medium, and a computer program product. By detecting the existence of the expected global physical address for the memory access transaction at the inter-chip interconnect interface connecting the first chip to the second chip when a memory access transaction is initiated to the first chip, a mapping relationship can be configured in the chip to the global physical address of any interconnected second chip. This enables a single chip to access a virtual second chip, eliminating the need for real multi-chip physical connections during chip verification. Instead, a single chip model can be instantiated in the chip simulation environment to simulate and verify its complete data path to the virtual remote chip (i.e., the second chip). This saves computational resources, thereby improving simulation speed and accelerating the verification iteration cycle.

[0032] Figure 1 This is a flowchart of a chip verification method provided in an embodiment of this application, such as... Figure 1 As shown, the method can be applied to a chip simulation environment, which can be a single-chip simulation environment that only instantiates the RTL model of the chip under test and supports configuring simulations of its behavior in a multi-chip cluster. The method includes the following steps.

[0033] Step S101: Initiate a memory access transaction to the first chip to be tested.

[0034] The memory access transaction targets the first address in the intermediate physical address of the first chip, and the expected global physical address corresponding to the first address is located in the second chip.

[0035] In this embodiment, the first chip to be tested can refer to a digital circuit design model of the target chip that is loaded, instantiated, and used as the sole verification subject in a single-chip simulation environment. Specifically, the model may include a configurable address mapping unit and one or more inter-chip interconnect protocol interface controllers. In this application, the first chip can be used to receive stimuli sent by the single-chip simulation environment and execute logical functions and generate responses based on the stimuli.

[0036] A memory access transaction refers to a read or write operation request to a memory address initiated by a virtual machine or verification environment. The resource accessed by the memory access transaction can be a local resource on the first chip or a resource on a remote chip interconnected with the first chip. When the resource accessed by the memory access transaction is a resource on a remote chip, the local address in the memory access request corresponding to the memory access transaction can be converted into a global physical address through a mapping relationship to achieve cross-chip resource access.

[0037] The intermediate physical address of the first chip can be a logical address sub-range with specific functions, specifically defined by the chip architecture within the unified physical address space of the first chip. Addresses within this logical address sub-range are not directly mapped to any physical memory array within the chip; instead, they serve as indexes to trigger address remapping mechanisms, mapping to physical memory arrays on remote chips interconnected with the first chip. The first address is any address within this range, and it can be used to activate address mapping units for query and conversion operations. In one possible implementation, the first address, acting as an index, can be used to further map to the physical memory array on a second chip interconnected with the first chip; that is, the expected global physical address corresponding to the first address is located on the second chip.

[0038] In this embodiment, the single-chip simulation environment can generate a complete transaction descriptor containing a specific command, a specific first address, specific data and attributes according to the test case requirements, and convert the transaction descriptor into a link layer data packet according to the interconnection protocol followed by the first chip, and then drive the link layer data packet to the signal line of the first chip interface.

[0039] When the first chip receives a memory access transaction from the single-chip simulation environment, it can parse the transaction to obtain the first address. Then, using the first address as an index, the first chip can perform queries and calculations based on the pre-loaded address mapping relationship to determine the expected global physical address corresponding to the first address, as well as the identifier of the target inter-chip interconnect interface. The expected global physical address is a calculated address within the global address space of the virtual second chip. This address simulates the final destination of the transaction in a real multi-chip system. The identifier of the target inter-chip interconnect interface indicates which specific physical or logical inter-chip interconnect interface controller on the first chip should send the routing instruction for this access.

[0040] After the first chip determines the expected global physical address corresponding to the first address and the identifier of the target inter-chip interconnect interface, the first address in the original memory access transaction can be replaced with the queried expected global physical address. The memory access transaction is then rewritten according to the protocol requirements of the target inter-chip interconnect interface to obtain a protocol-encapsulated memory access transaction. This rewritten transaction can then be submitted to the corresponding interface controller based on the identifier of the target inter-chip interconnect interface. The transaction layer and link layer logic within this interface controller will re-encapsulate the protocol-encapsulated memory access transaction into a standard link layer data packet according to the interconnect protocol followed by the first chip, and send the link layer data packet through the target inter-chip interconnect interface. In the single-chip simulation environment of this application, the link layer data packet sent through the target inter-chip interconnect interface is not sent to a real physical link, but rather to the monitoring unit of the connected single-chip simulation environment.

[0041] Step S102: Detect the output of the target inter-chip interconnect interface of the first chip.

[0042] The target inter-chip interconnect interface is the inter-chip interconnect interface in the first chip that connects to the second chip.

[0043] In this embodiment, the inter-chip interconnection interface that connects the first chip to the second chip can first be determined from multiple interfaces of the first chip based on the address mapping relationship of the first chip.

[0044] The address mapping relationship includes the mapping relationship that maps the intermediate physical address of the first chip to the global physical address belonging to the second chip.

[0045] In this embodiment, the address mapping relationship is a mapping relationship that is actively configured into the first chip by the verification environment (single-chip simulation environment) before the verification test case begins execution. Specifically, during the configuration phase before the simulation time zero point or before the test stimulus is applied, the single-chip simulation environment can write the defined address translation mapping rules (i.e., address mapping relationship) into the configuration register or memory of the first chip through the configuration interface provided by the first chip.

[0046] It should be noted that in related technologies, the configuration and verification of address mapping relationships in address translation units heavily rely on a complete system-level simulation environment or hardware platform that includes all physical chip models. Therefore, the verification of this mapping relationship and cross-chip access paths must be delayed until all relevant chip designs are completed, during the complex multi-chip integration phase. This results in delayed verification points, late problem detection, high modification costs, and long iteration cycles. In this application, however, the address mapping relationship is a pre-embedded configuration for actively stimulating and verifying the cross-card access logic within the chip. It allows for early verification of the cross-chip address mapping within the first chip in a single-chip-level simulation environment without waiting for other chip designs to be completed or system integration to be performed. This shifts the cross-card address mapping verification to the left, enabling critical verification work to be carried out at the earliest stage of the development process, thereby greatly accelerating the overall verification convergence and chip development process.

[0047] In this embodiment, during the configuration phase of the address mapping relationship for the first chip in the single-chip simulation environment, a copy of the address mapping configuration file can be stored simultaneously in the address mapping model of the single-chip simulation environment. After the single-chip simulation environment initiates a memory access transaction to the first chip under test, it can use the first address as input and execute address matching logic using the address mapping model inside the single-chip simulation environment to obtain the address range to which the expected global physical address belongs. After obtaining the address range to which the first address belongs, the single-chip simulation environment can read the pre-configured expected interface identifier from the mapping table entry corresponding to that range. This expected interface identifier uniquely corresponds to a specific inter-chip interconnect interface in the physical design of the first chip.

[0048] Step S103: When it is determined that the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address, it is determined that the first chip is verified through inter-chip interconnect transmission.

[0049] In this step, when determining whether the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address, the output data of the target inter-chip interconnect interface can be detected first. Then, the output data of the target inter-chip interconnect interface can be compared with the expected transaction data generated by the memory access transaction to determine whether the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address.

[0050] The output data of the target inter-chip interconnect interface can refer to the link layer data packets actually captured and decoded by the interface monitor from the signal lines of the target inter-chip interconnect interface determined by the single-chip simulation environment. The expected transaction data refers to the data payload directly related to this memory access transaction; in the case of a write transaction, the data payload may include, but is not limited to, the data content to be written in the transaction and the global physical address to be written; in the case of a read transaction, the data payload may include, but is not limited to, the data content expected to be read in the transaction and the global physical address expected to be read.

[0051] Inter-chip interconnect interfaces refer to physical or logical connection channels used to enable communication between multiple chips. In this application, the inter-chip interconnect interface typically refers to the MTLINK (Multi-Chip Link) interface, which is used to transmit transaction data packets, such as memory access requests or responses, in a multi-chip system. Output data refers to the data content sent out from the inter-chip interconnect interface after executing a memory access transaction. Output data typically includes information such as the destination address, data content, and transaction type, and is used to indicate the destination and operational intent of the current transaction.

[0052] In this step, the interface monitor in the single-chip simulation environment can be used to synchronously sample the differential signal, parallel bus or standard interface protocol signal of the link layer in the transmit clock domain of the interface, convert the analog or digital waveform into discrete, processable data streams or logical data packets, and then decode the captured raw data stream according to the protocol specification of the inter-chip interconnect interface (such as the MTLINK interface) to obtain the decoded actual data.

[0053] In this step, after the inter-chip interconnect interface is determined in the single-chip simulation environment, the result checker in the single-chip simulation environment can be controlled to run. This allows the interface monitor in the result checker to be dynamically bound to the signal line of the specific inter-chip interconnect interface of the first chip pointed to by the expected interface identifier (i.e., the target inter-chip interconnect interface determined by the single-chip simulation environment). The interface monitor can be configured to capture all protocol layer data packets sent from this interface and compare them with the expected transaction data generated based on the address mapping relationship and the original memory access transaction.

[0054] The first chip can be verified through inter-chip interconnect transmission if one or more of the following conditions are met.

[0055] In this embodiment of the application, it can first be determined that the protocol of the protocol layer data packets sent by the target inter-chip interconnection interface conforms to expectations.

[0056] Specifically, the output data packets captured and decoded by the interface monitor can be used to determine whether the protocol layer data packets sent by the inter-chip interconnection interface conform to the expected protocol if the format, sequence, control fields and transaction type of the output data packets all conform to the industry standards or proprietary protocol specifications defined by the inter-chip interconnection interface.

[0057] Secondly, it can be confirmed that the address of the protocol layer data packet sent by this inter-chip interconnection interface is as expected.

[0058] Specifically, the target address field can be parsed from the captured data packet and compared with the expected global physical address calculated by the single-chip simulation environment based on the address mapping relationship and the first address in the original memory access transaction. If the comparison is consistent, it can be determined that the address of the protocol layer data packet sent by this target inter-chip interconnect interface meets the expectation. Furthermore, it can be confirmed that the data integrity and consistency of the protocol layer data packets sent by this target inter-chip interconnection interface meet expectations.

[0059] Specifically, for write transactions, if the data payload carried in the captured data packet completely matches the memory access data to be written in the original memory access transaction in terms of content, byte enablement, and order, it can be determined that the data integrity and consistency of the protocol layer data packet sent by this inter-chip interconnect interface meet expectations. For read transactions, if the data payload returned in the read completion data packet subsequently captured by the interface monitor from the same interface after the first chip issues a read request is completely consistent with the data calculated by the single-chip simulation environment based on the simulated memory model or expected value of the second chip, it can be determined that the data integrity and consistency of the protocol layer data packet sent by this inter-chip interconnect interface meet expectations.

[0060] When all the above checkpoints show a match or pass, the single-chip simulation environment can generate a judgment result: confirming that the first chip has passed this inter-chip interconnection transmission verification.

[0061] By adopting the above technical solution, when a memory access transaction is initiated to the first chip, it is possible to detect whether there is an expected global physical address for the memory access transaction on the inter-chip interconnect interface connecting the first chip and the second chip. This allows the chip to configure a mapping relationship to the global physical address of any interconnected second chip, enabling a single chip to access a virtual second chip. This eliminates the need to rely on real multi-chip physical connections when verifying the chip. Instead, a single chip model can be instantiated in the chip simulation environment to simulate and verify its complete data path to the virtual remote chip (i.e., the second chip). This saves computing resources and improves simulation speed, thereby accelerating the verification iteration cycle.

[0062] In some embodiments, step S102 can be implemented by steps S1021 and S1022.

[0063] Step S1021: Based on the address mapping relationship of the first chip, determine the expected global physical address corresponding to the first address of the memory access transaction.

[0064] The address mapping relationship includes the mapping relationship that maps the intermediate physical address of the first chip to the global physical address belonging to the second chip.

[0065] In this step, the single-chip simulation environment may include a transaction generator. After the verification module in the single-chip simulation environment detects that the transaction generator has initiated a memory access transaction, it can capture the transaction descriptor. This descriptor may include, but is not limited to, the transaction type, intermediate physical address, and transaction attributes. After obtaining the intermediate physical address corresponding to the first address, the verification module can access the address mapping relationship model in the single-chip simulation environment to query the expected global physical address corresponding to the first address using the address mapping relationship model.

[0066] The address mapping model can be a file copy of the address mapping relationship written to the first chip. The address mapping model can take the form of a data structure, such as a lookup table, a range tree, or a rule linked list.

[0067] Specifically, each entry or rule in this address mapping model contains at least a correspondence between intermediate physical addresses and global physical addresses. The verification module can compare the intermediate physical address of the memory access transaction (i.e., the intermediate physical address corresponding to the first address) with all intermediate physical address intervals in the model to determine the unique interval to which the first address belongs; then, according to the mapping rule defined by the matched interval, it performs address translation calculations to obtain the expected global physical address corresponding to the first address.

[0068] Step S1022: Based on the expected global physical address and preset routing information, determine the target inter-chip interconnect interface for connecting the second chip from multiple interfaces of the first chip.

[0069] The preset routing information is used to indicate the inter-chip interconnect interfaces corresponding to different global physical address ranges. Different chips manage different global physical address ranges. The preset routing information can be a set of predefined rules, which typically include the connection direction and target chip identifier for each inter-chip interconnect interface.

[0070] In one possible implementation, the verification module can maintain an independent routing table as preset routing information. This routing table may include, but is not limited to, fields such as start global address, end global address, target chip identifier, and output interface identifier.

[0071] Specifically, the verification module can use the expected global physical address as the query key to search the global address range that the expected global physical address falls into in the routing table, and read the output interface identifier corresponding to the global address range based on the routing table. The read output interface identifier is then determined as the target inter-chip interconnection interface expected to be output by this memory access transaction.

[0072] In another possible implementation, the address mapping model may also include preset routing information. When the expected global physical address is obtained using step S1021, since the address mapping model directly includes the corresponding target chip identifier and output interface identifier, after completing the address translation calculation, the model can synchronously output the expected global physical address and the expected output interface identifier. The output interface identifier is then determined as the expected inter-chip interconnect interface for this memory access transaction.

[0073] In some embodiments, the expected global physical address can first be compared with different global physical address ranges in the preset routing information. Then, when the expected global physical address belongs to the global physical address range of the second chip, the inter-chip interconnection interface corresponding to the second chip in the preset routing information can be used as the target inter-chip interconnection interface for connecting the second chip.

[0074] In this step, the verification module can compare the expected global physical address with each global address range in the attribution information to determine which chip the expected global physical address belongs to. For example, it can determine that the expected global physical address falls into the address space of the second chip.

[0075] After determining which chip the expected global physical address belongs to, the specific interconnection topology between the first chip and its home chip (i.e., the second chip) can be queried from the preset routing information. This allows for the unique identification of the target inter-chip interconnection interface used to connect the second chip from among the multiple interfaces of the first chip. For example, the preset routing information can be queried to determine which specific physical interface connects the first chip and its home chip (i.e., the second chip), and that physical interface can then be used as the target inter-chip interconnection interface for connecting the second chip.

[0076] For example, in a practical application, if the first chip is configured with node identifier = 2 and the second chip is configured with node identifier = 3, then upon receiving an access request with an expected global physical address of 0xC000_0000_0000, the system can first determine, through the attribution information, that address 0xC000_0000_0000 belongs to the address space of the second chip. Next, based on the interconnection topology between node identifier = 2 and node identifier = 3 in the preset routing information, the corresponding MTLINK interface can be selected as the data output port. Finally, the verification module will capture and check whether the transaction was correctly sent on the selected MTLINK interface to confirm the correctness of the cross-card virtualization logic.

[0077] In this way, on the one hand, by matching the attribution information with the expected global physical address, it is possible to quickly determine whether the expected global physical address belongs to the current chip or a remote chip. The method of matching attribution information with the expected global physical address can help reduce the calculation of invalid routing paths and improve verification efficiency. On the other hand, by introducing attribution information and interconnection topology and efficiently determining the attribution chip and corresponding interconnection interface of the expected global physical address, it is possible to avoid indiscriminate testing of all interfaces, thereby reducing verification resource consumption, improving verification efficiency, and enabling the earlier detection and repair of potential design defects.

[0078] By adopting the above technical solution, the expected global physical address is determined based on the address mapping relationship, and the correct inter-chip interconnection interface is determined according to the expected global physical address and the preset routing information. This can effectively simulate the address translation and routing behavior in a multi-chip environment, thereby avoiding the resource consumption problem caused by instantiating multiple complete chip models, and thus significantly reducing verification costs and improving verification efficiency.

[0079] In some embodiments, if a data packet with a destination address of the expected global physical address is detected on the target inter-chip interconnect interface, and no data packet is detected on other inter-chip interconnect interfaces of the first chip, the target address of the memory access request detected on the target inter-chip interconnect interface is determined to be the expected global physical address.

[0080] In this step, the verification module can detect the expected target inter-chip interconnect interface determined in the above steps within a preset time window after the memory access transaction is triggered. In addition, it can also detect all other inter-chip interconnect interfaces on the first chip at the same time, so as to capture data packets in all transmission directions through the monitors deployed on all inter-chip interconnect interfaces on the first chip.

[0081] Each interface monitor can reconstruct multiple transaction layer data packets from the captured raw bit stream according to a protocol (such as MTLINK). Then, the destination address field of all data packets can be extracted and compared. If the address detected on the expected target inter-chip interconnect interface is completely consistent with the expected global physical address of the second chip pre-calculated in step S1021, and no data packets carrying the expected global physical address as the destination address are captured on any other inter-chip interconnect interface on the first chip, it can be determined that the memory access transaction has been successfully converted and sent out uniquely and correctly through the predetermined data path.

[0082] By adopting the above technical solution, not only was the correctness of address mapping and routing verified in terms of functionality, but also the uniqueness of the path was verified with exclusivity. Thus, at the single-chip simulation level, it was proven with high confidence that the chip has the ability to correctly handle cross-chip transactions and send them in a targeted manner.

[0083] Considering that if the address translation unit of the chip is faulty, subsequent verification of the routing path will lose its benchmark and will also mask the real root cause of the error inside the chip, resulting in low debugging efficiency based on the verification results, in some embodiments, the method further includes steps S104 and S105.

[0084] Step S104: Detect the output data of the address translation unit of the first chip.

[0085] The address translation unit can be an internal chip module used to translate local physical addresses (such as intermediate physical addresses, IPAs) into global physical addresses (GPAs). In a multi-chip system, different chips have different address spaces, and the address translation unit performs the operation of translating local access requests into actual addresses on remote chips. For example, in the technical solution of this invention, the address translation unit can be configured to translate memory access requests from a virtual machine into video memory addresses belonging to other chips, thereby simulating cross-chip access behavior.

[0086] In this step, the verification module can set a monitoring point at the output of the address translation unit to capture and record the result of each address translation.

[0087] In step S105, if the expected global physical address is detected in the output data of the address translation unit, it is determined that the first chip has passed the address translation verification.

[0088] The expected physical address is the global physical address pre-calculated by the single-chip simulation environment based on the address mapping relationship as the first address.

[0089] In this step, while the memory access transaction flows through the address translation unit, the verification module can capture the output data of the translation unit at its output port and extract the address from the output data. Then, the captured address (the actual hardware result) can be compared with the previously calculated expected physical address (the theoretical software expectation). If the comparison result is consistent, it can be determined that the expected global physical address has been detected in the output data of the address translation unit, that is, the address translation function of the chip hardware is consistent with the preset mapping rule. Therefore, it is determined that the first chip has passed the address translation verification.

[0090] In some embodiments, if it is determined that the first chip has passed address translation verification, a target inter-chip interconnect interface for connecting the second chip can be determined from multiple interfaces of the first chip based on the expected global physical address and preset routing information.

[0091] It should be noted that in this embodiment, step S103 can be executed after it is determined that the first chip has passed the address translation verification. The implementation method can refer to step S103, and the specific details will not be repeated here.

[0092] By adopting the above technical solution, address translation can be verified separately at the single-chip level. If this step fails, the problem can be immediately located to the address mapping configuration or the hardware logic of the translation unit, without the need to analyze subsequent more complex routing and data packets, which greatly improves debugging efficiency.

[0093] In some embodiments, the address mapping relationship can be written into the mapping table of the address translation unit of the first chip through the configuration interface of the first chip.

[0094] In this configuration, the address range of the second chip is pre-allocated based on its logical location within the on-chip network. The second chip is logically interconnected with the first chip but physically does not exist in the single-chip simulation environment. Even in the single-chip simulation environment, where the second chip is not instantiated, its address range is still configured according to the actual deployment. In this case, the address range can be configured based on the topology and resource distribution of the multi-chip system.

[0095] For example, in a system containing four GPU cards, each card's memory address space might be divided into 256GB. The address range for the second chip might be [512GB, 768GB), while the address range for the third chip would be [768GB, 1024GB]. This address range configuration based on topology and resource distribution ensures accurate simulation of cross-chip memory access behavior even in a single-chip environment.

[0096] In this embodiment, the global physical address corresponding to the intermediate physical address of the memory access transaction is located within the local address range of the second chip in the on-chip system. The configuration interface refers to a dedicated communication channel used to inject configuration data into internal modules of the first chip (such as the address translation unit). The single-chip simulation environment can use the configuration interface to set the address mapping entries of the Extended Address Translation Agent (EATA) to simulate global address allocation between different chips in a multi-chip node.

[0097] By configuring the address mapping relationships into the address translation unit's mapping table via an interface, a global address distribution model in a multi-chip system can be constructed. This allows for the simulation of address mapping and routing behavior of multi-chip nodes in a single-chip environment, avoiding the resource consumption of full-system simulation. Furthermore, this method enables efficient verification of the chip's address translation and routing exit logic in cross-card virtualization scenarios, improving verification efficiency and reducing costs. Consequently, it significantly shortens regression testing cycles and accelerates design iteration.

[0098] Figure 2 This is a schematic diagram of a chip verification device provided in an embodiment of this application, as shown below. Figure 2 As shown, the chip verification device 200 may include a memory access module 201, a first determination module 202, and a verification module 203.

[0099] The memory access module 201 is used to initiate a memory access transaction to the first chip to be tested; the memory access transaction is for the first address in the intermediate physical address of the first chip, and the expected global physical address corresponding to the first address is located in the second chip; The first determining module 202 is used to detect the output of the target inter-chip interconnection interface of the first chip, wherein the target inter-chip interconnection interface is the inter-chip interconnection interface in the first chip that is connected to the second chip. The verification module 203 is used to determine that the first chip is verified through inter-chip interconnect transmission when the target address of the memory access request detected on the target inter-chip interconnect interface is determined to be the expected global physical address.

[0100] In some embodiments, the chip verification apparatus 200 further includes a second determining module and a third determining module.

[0101] The second determining module is used to determine the expected global physical address corresponding to the first address of the memory access transaction based on the address mapping relationship of the first chip; the address mapping relationship includes the mapping relationship of mapping the intermediate physical address of the first chip to the global physical address belonging to the second chip; The third determining module is used to determine the target inter-chip interconnect interface for connecting the second chip from multiple interfaces of the first chip based on the expected global physical address and preset routing information. The preset routing information is used to indicate the inter-chip interconnect interface corresponding to different global physical address ranges, and different chips manage different global physical address ranges.

[0102] In some embodiments, the third determining module is used to compare the expected global physical address with different global physical address ranges in the preset routing information; when the expected global physical address belongs to the global physical address range of the second chip, the inter-chip interconnection interface corresponding to the second chip in the preset routing information is used as the target inter-chip interconnection interface for connecting the second chip.

[0103] In some embodiments, the verification module 203 is further configured to determine that the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address when a data packet with a destination address of the expected global physical address is detected on the target inter-chip interconnect interface and no data packet is detected on other inter-chip interconnect interfaces of the first chip.

[0104] In some embodiments, the chip verification device 200 may further include a detection module and an address verification module.

[0105] The detection module is used to detect the output data of the address translation unit of the first chip; The address verification module is used to determine if the first chip passes the address translation verification when the expected global physical address is detected in the output data of the address translation unit.

[0106] In some embodiments, the third determining module is configured to, upon determining that the first chip has passed address translation verification, determine, from multiple interfaces of the first chip, a target inter-chip interconnect interface for connecting the second chip based on the expected global physical address and preset routing information.

[0107] In some embodiments, the chip verification device 200 may further include a configuration module.

[0108] The configuration module is used to write the address mapping relationship and preset routing information into the mapping table of the address translation unit of the first chip through the configuration interface of the first chip; wherein, the global physical address range allocated for the second chip in the preset routing information is pre-allocated according to the logical location of the second chip in the on-chip network, the second chip is a chip that is logically interconnected with the first chip, but does not physically exist in the chip simulation environment; the expected global physical address is within the global physical address range allocated for the second chip in the preset routing information.

[0109] By adopting the above technical solution, when a memory access transaction is initiated to the first chip, it is possible to detect whether there is an expected global physical address for the memory access transaction on the inter-chip interconnect interface connecting the first chip and the second chip. This allows the chip to configure a mapping relationship to the global physical address of any interconnected second chip, enabling a single chip to access a virtual second chip. This eliminates the need to rely on real multi-chip physical connections when verifying the chip. Instead, a single chip model can be instantiated in the chip simulation environment to simulate and verify its complete data path to the virtual remote chip (i.e., the second chip). This saves computing resources and improves simulation speed, thereby accelerating the verification iteration cycle.

[0110] The description of the above device-side embodiments is similar to the description of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0111] The following describes the application of the chip verification method provided in the embodiments of this application in a real-world scenario, mainly involving a multi-chip virtualization logic verification method and apparatus based on a single-chip environment.

[0112] With the increasing demand for data centers and high-performance computing, single graphics processing units (GPUs) or artificial intelligence chips are often combined into multi-chip clusters or supernodes to work collaboratively. In virtualization scenarios, virtual machines need to access resources across chips; for example, a virtual machine may be able to use resources on at least two chips simultaneously, which necessitates verification of the performance of inter-chip interconnects.

[0113] In related technologies, verification is typically performed through simulation. This involves instantiating multiple complete chip models in a simulation platform and physically connecting them via interconnect interfaces to build a multi-chip simulation environment, thereby verifying the interconnect performance between chips. Specifically, a complete system-level simulation environment containing all physical chip models can be built. For example, to verify the virtualization logic of a 4-chip node, the verifier needs to instantiate four complete chip RTL (Register-Transfer Level) models in an EDA (Electronic Design Automation Simulation Tool) and physically connect them via interconnect interfaces to form a multi-chip environment.

[0114] However, using this method to instantiate large RTL models of multiple chips simultaneously places extremely high demands on server memory and computing power, resulting in extremely slow simulation speed and huge consumption of computing resources. Moreover, the configuration of interconnection, reset synchronization, clock synchronization, etc. in the multi-chip interconnection environment is extremely complex, and the environment setup is complicated, which can easily introduce environmental problems that are not related to the design itself. Furthermore, when locating problems in a multi-chip environment, the large amount of waveform data makes it difficult to quickly distinguish whether the problem is a logic error in the transmitting chip or the receiving chip, resulting in low debugging efficiency.

[0115] To address the aforementioned issues and efficiently and accurately verify the address translation, resource isolation, and data routing logic of a single chip in a multi-chip virtualization scenario without instantiating a complete multi-chip physical model, thereby reducing verification costs and improving iteration efficiency, this application proposes a method for verifying multi-chip cross-card virtualization logic using a single-chip environment. By simulating the global address mapping and configuration of multiple chips in a single-chip simulation environment, the correctness of the cross-card function is derived solely by verifying the logical correctness of the sending end (i.e., correct address translation and correct routing exit), thus avoiding the waste of resources from full-system simulation.

[0116] Figure 3 This is a flowchart of a chip verification method provided in an embodiment of this application. Figure 2 ,like Figure 3 As shown, the method includes the following steps.

[0117] Step S301: Construct a single-chip simulation environment.

[0118] In this step, a register-transfer level model of a single chip under test (and the first chip in the above embodiments) can be instantiated as the device under test in the verification platform. The register-transfer level model of the chip under test integrates a graphics processing unit, an on-chip network, an address translation unit, and at least one inter-chip interconnect interface module.

[0119] Step S302: Configure the virtualization topology and address mapping for the chip under test.

[0120] In this step, the verification environment simulates host behavior and the virtualization topology and address mapping are configured for the chip under test. This may include virtualization topology configuration and address mapping relationship configuration.

[0121] Specifically, when configuring the virtualization topology, the address mapping table management module within the chip under test (DUT) can be used to configure the DUT to a specified logical location in a virtual multi-chip system; for example, it can be configured as chip 2 in a virtual four-chip node. When configuring the address mapping relationship, the address mapping table entries within the extended address translation proxy unit of the DUT can be configured. Although only a single chip is instantiated in the single-chip simulation environment, the address mapping table entries still contain a mapping relationship from the intermediate physical address of the device under test to the global physical address belonging to at least one virtual remote chip.

[0122] Step S303: Generate and inject verification stimuli.

[0123] In this step, the verification environment can generate and inject stimulus transactions that simulate cross-chip access into the chip under test.

[0124] The incentive transaction can be used to simulate a memory access request initiated by an external computing entity on the chip under test. This memory access request is used to point to an intermediate physical address. The intermediate physical address can be mapped to the global physical address space of the virtual second chip through the address mapping relationship configured in step S302.

[0125] Step S304, address translation check.

[0126] In this step, the input and output of the address translation unit can be monitored to determine whether the input intermediate physical address is correctly converted into the expected global physical address that belongs to the address range of the virtual second chip, according to the address mapping relationship configured in step S302.

[0127] Step S305, route exit check.

[0128] In this step, the on-chip network and inter-chip interconnect interfaces can be monitored to determine whether memory access requests carrying global physical addresses are correctly routed to the specific inter-chip interconnect interface connecting the virtual second chip.

[0129] Step S306: If both the address translation check and the routing exit check pass, the cross-chip virtualization access and transmission logic function of the device under test is determined to be correct.

[0130] The access request output from the address translation unit is encapsulated into a transaction data packet containing the target chip identifier and the chip address. This transaction data packet is routed to the corresponding inter-chip interconnect interface via the on-chip network.

[0131] In this step, monitoring points are set at key routing nodes of the on-chip network and output ports of inter-chip interconnect interfaces to verify whether the routing path of transaction data packets and the correspondence between the target chip identifier and the port carried by them conform to the expected configuration. If both the address translation check and the routing exit check pass, the cross-chip virtualization access and transmission logic function of the device under test is determined to be correct.

[0132] By adopting the above technical solution, by configuring a global physical address mapping relationship in the chip that can be mapped to any interconnected second chip, a single chip can have the ability to access a virtual second chip. This means that when verifying the chip, it is no longer necessary to rely on real multi-chip physical connections. Instead, a single chip model can be instantiated in a single-chip simulation environment to simulate and verify its complete data path to access the virtual remote chip (i.e., the second chip). This can save on computing resource consumption, thereby improving simulation speed and accelerating the verification iteration cycle.

[0133] In such Figure 4 In the context of multi-chip interconnection shown, for Figure 4 Any chip in the process can be verified in a single-chip simulation environment using the chip verification method described in this embodiment of the application, following the procedure below: T1 can build a verification environment for a register-transfer level model that instantiates only the first chip (such as Chip 2), which integrates functional modules including an address translation unit and an inter-chip interconnect interface.

[0134] T2, the verification environment initializes and configures the first chip. Not only is it configured as a specific logical location (such as node 2) in a virtual multi-chip node (such as a four-chip system), but its address translation unit is also pre-configured with an address mapping relationship that maps a local intermediate physical address to the global physical address space belonging to a virtual second chip (such as Chip 3).

[0135] After T3 is configured, the verification environment injects a memory access stimulus transaction for the intermediate physical address into the first chip.

[0136] T4, the verification environment can perform critical verifications through monitoring points deployed inside the chip.

[0137] Specifically, on the one hand, it can check whether the address translation unit correctly translates the intermediate physical address into the expected global physical address belonging to the virtual second chip according to the mapping relationship; on the other hand, it can monitor all inter-chip interconnection interfaces of the first chip to confirm whether the transaction data packet carrying the global physical address is uniquely routed to the expected physical interface connecting the virtual second chip and sent out, and whether the data packet format and content are correct.

[0138] T5. If both of the above checks pass, the verification environment determines that the cross-chip access and transmission logic function of the first chip is correct.

[0139] By adopting the above technical solution, the closed-loop verification of core pathways such as cross-chip address translation, routing decision and protocol encapsulation is completed in the simulation of a single chip by simulating the address mapping and topology of a virtual remote chip, realizing early intervention and efficient execution of the verification task.

[0140] In this embodiment, compared to the full-system simulation that requires instantiating complete RTL models of all N chips (e.g., 2, 4, or 8 chips) in related technologies, this application only requires simulating a single chip. This reduces the computational burden on server memory, CPU cores, and simulation licenses, and avoids the additional overhead introduced by simulating complex physical interconnect links. Furthermore, since the simulator only needs to handle the complexity of a single chip, it avoids the scheduling overhead and synchronization delay caused by parallel operation of multiple chip models, improving the execution speed of a single simulation, thereby shortening regression testing time. This allows for more frequent and faster execution of verification test cases, enabling rapid exposure, location, and repair of defects, thus significantly compressing the overall chip development and verification cycle and accelerating project progress.

[0141] Furthermore, in this embodiment, the verification focuses on address mapping, routing decisions, and protocol encapsulation. This allows for separate verification from the physical layer and electrical characteristics. The complexity and uncertainty of the physical layer (such as SerDes / PMA) no longer become a bottleneck for early logic verification, enabling parallel development and independent verification of both. Moreover, by dynamically configuring the chip's internal address mapping table through software, the chip's behavior in different multi-chip topologies (such as ring, full mesh, and star) can be quickly simulated in the same simulation environment without reconnecting the RTL model or rebuilding the simulation environment. This significantly improves the breadth and depth of verification coverage, allowing for thorough verification in the early stages of module-level / single-chip development. This helps to identify and fix architectural and logical defects at the design front end, preventing problems from being carried over to the later integration stage, thereby reducing project risks and modification costs.

[0142] It should be noted that, in the embodiments of this application, if any of the above methods are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the related technology, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks. Thus, the embodiments of this application are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0143] This application also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, implement the above-described method. The computer-readable storage medium can be transient or non-transient.

[0144] This application also provides a computer program product, which includes a computer program or instructions that, when executed by a processor, implement some or all of the steps in any of the above-described methods. The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one optional embodiment, the computer program product is specifically embodied in a computer storage medium; in another optional embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0145] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referred to interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0146] Figure 5 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this application, such as... Figure 5As shown, the hardware entity of the computer device 500 includes a processor 501 and a memory 502, wherein the memory 502 stores a computer program that can run on the processor 501, and the processor 501 executes the program to implement the steps in the method of any of the above embodiments.

[0147] The memory 502 stores computer programs that can run on the processor. The memory 502 is configured to store instructions and applications that can be executed by the processor 501. It can also cache data to be processed or already processed by the processor 501 and various modules in the computer device 500 (e.g., image data, audio data, voice communication data and video communication data). It can be implemented by flash memory or random access memory (RAM).

[0148] The processor 501 executes the steps of the above-described task execution method when executing the program. The processor 501 typically controls the overall operation of the computer device 500.

[0149] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0150] The aforementioned processor can be at least one of the following: Application Specific Integrated Circuit (ASIC), Digital Signal Processor (DSP), Digital Signal Processing Device (DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller, and Microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0151] The aforementioned computer storage media / memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM), etc.; or it can be various terminals that include one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc.

[0152] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above embodiments of this application are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0153] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0154] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0155] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0156] Furthermore, in the various embodiments of this application, all functional units can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in a combination of hardware and software functional units. Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0157] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0158] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A chip verification method, characterized in that, The method, applied in a single-chip simulation environment, includes: A memory access transaction is initiated to the only chip under test in the single-chip simulation environment; the memory access transaction is for a first address in the intermediate physical address of the first chip, and the expected global physical address corresponding to the first address is located in the second chip; the first chip includes multiple interfaces for communicating with different chips, and the global physical address range managed by different chips is different. Based on the expected global physical address and preset routing information, a target inter-chip interconnect interface for connecting to the second chip is determined from multiple interfaces of the first chip; the preset routing information is used to indicate the inter-chip interconnect interface corresponding to different global physical address ranges. The output of the target inter-chip interconnect interface of the first chip is detected, wherein the target inter-chip interconnect interface is the inter-chip interconnect interface in the first chip that connects to the second chip. When it is determined that the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address, it is determined that the first chip verifies the inter-chip interconnect transmission.

2. The method according to claim 1, characterized in that, The method further includes: Based on the address mapping relationship of the first chip, the expected global physical address corresponding to the first address of the memory access transaction is determined; the address mapping relationship includes a mapping relationship that maps the intermediate physical address of the first chip to the global physical address belonging to the second chip.

3. The method according to claim 2, characterized in that, The step of determining the target inter-chip interconnect interface for connecting the second chip from multiple interfaces of the first chip based on the expected global physical address and preset routing information includes: The expected global physical address is compared with the different global physical address ranges in the preset routing information; When the expected global physical address belongs to the global physical address range of the second chip, the inter-chip interconnect interface corresponding to the second chip in the preset routing information is used as the target inter-chip interconnect interface for connecting the second chip.

4. The method according to claim 1, characterized in that, The method further includes: If a data packet with a destination address of the expected global physical address is detected on the target inter-chip interconnect interface, and the data packet is not detected on other inter-chip interconnect interfaces of the first chip, then the target address of the memory access request detected on the target inter-chip interconnect interface is determined to be the expected global physical address.

5. The method according to claim 2 or 3, characterized in that, The method further includes: The output data of the address translation unit of the first chip is detected; If the expected global physical address is detected in the output data of the address translation unit, it is determined that the first chip has passed the address translation verification.

6. The method according to claim 5, characterized in that, The step of determining the target inter-chip interconnect interface for connecting the second chip from multiple interfaces of the first chip based on the expected global physical address and preset routing information includes: If the first chip passes the address translation verification, the target inter-chip interconnect interface for connecting the second chip is determined from multiple interfaces of the first chip based on the expected global physical address and preset routing information.

7. The method according to claim 2 or 3, characterized in that, The method further includes: The address mapping relationship and the preset routing information are written into the mapping table of the address translation unit of the first chip through the configuration interface of the first chip; The global physical address range allocated to the second chip in the preset routing information is pre-allocated based on the logical location of the second chip in the on-chip network, and the second chip is a chip that is logically interconnected with the first chip; the expected global physical address is located within the global physical address range allocated to the second chip in the preset routing information.

8. A chip verification device, characterized in that, The device, used in a single-chip simulation environment, includes: The memory access module is used to initiate a memory access transaction to the only chip under test in the single-chip simulation environment; the memory access transaction is for a first address in the intermediate physical address of the first chip, and the expected global physical address corresponding to the first address is located in the second chip; the first chip includes multiple interfaces for communicating with different chips, and the global physical address range managed by different chips is different. The second determining module is used to determine, from multiple interfaces of the first chip, a target inter-chip interconnect interface for connecting to the second chip based on the expected global physical address and preset routing information; the preset routing information is used to indicate the inter-chip interconnect interface corresponding to different global physical address ranges. The first determining module is used to detect the output of the target inter-chip interconnection interface of the first chip, wherein the target inter-chip interconnection interface is the inter-chip interconnection interface in the first chip that is connected to the second chip. The verification module is used to determine that the first chip verifies the inter-chip interconnect transmission when it is determined that the target address of the memory access request detected on the target inter-chip interconnect interface is the expected global physical address.

9. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

11. A computer program product, the computer program product comprising a non-transitory computer-readable storage medium storing a computer program, characterized in that, When the computer program is read and executed by a computer, it implements the method described in any one of claims 1 to 7.

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