A method and system for current sharing control of active gate drive of parallel SiC MOSFETs

Abstract

The application discloses a parallel SiC MOSFET active gate driving current sharing control method and system, the method is through the stage discrete sampling and statistics to the drain current signal, extracts the corresponding current error in the three stages of opening transient, steady-state conduction and closing transient, and carries out the corresponding gate driving voltage adjustment and PWM driving timing compensation, effectively solves the problem that the dynamic and steady-state current of the parallel SiC MOSFET in the prior art is obviously unbalanced under the high-speed switching working condition, the traditional passive current sharing method is difficult to adjust online, and the existing active current sharing method is difficult to consider the current deviation control in different working stages.

Description

Technical Field

[0001] This invention belongs to the field of power conversion, and particularly relates to a method and system for controlling the current sharing of parallel SiC MOSFET active gate drive. Background Technology

[0002] Silicon carbide (SiC) MOSFETs offer advantages such as fast switching speed, high voltage withstand capability, low conduction loss, and good high-temperature performance, leading to their widespread application in high-frequency power supplies, motor drivers, energy storage converters, and high-power-density power conversion devices in recent years. In high-current applications, due to limitations in the current capacity and heat dissipation of individual power devices, multiple SiC MOSFETs are often connected in parallel to improve system output capacity and power rating.

[0003] However, in parallel applications, due to the inherent dispersion of parameters such as threshold voltage, transconductance, and on-resistance of the devices themselves, and the differences in parasitic inductance and resistance between the power circuit and the drive circuit, parallel devices are prone to current distribution imbalance during operation. During the steady-state turn-on phase, the current deviation in each parallel branch mainly manifests as inconsistent current distribution on the conduction plateau; during the transient turn-on and turn-off phases, the parallel devices exhibit significant peak current mismatch due to differences in switching speed, conduction sequence, and current change rate. These uneven current problems cause some devices to bear excessive current and thermal stress, increasing device losses and failure risks, thereby reducing the overall reliability of the parallel system.

[0004] In existing technologies, passive current sharing methods are typically employed to improve the current distribution of parallel SiC MOSFETs, such as device selection and matching, optimization of PCB layout and busbar structure, and reduction of parasitic parameter differences. These methods are simple to implement and require minimal modification to the system control structure. However, under high-speed switching conditions, relying solely on device consistency and layout symmetry makes it difficult to effectively suppress dynamic current imbalances caused by parameter differences and inconsistencies in parasitic parameters, and they are also difficult to adjust online according to changes in operating conditions.

[0005] To further improve the current sharing performance of parallel systems, some active current sharing methods have been developed to achieve current sharing control by detecting branch currents and adjusting drive parameters, such as adjusting gate drive voltage, gate resistance, gate drive current, or switching timing. However, in practical applications, these methods often exhibit the following shortcomings:

[0006] Firstly, when simply adjusting the gate drive voltage, the current distribution during the steady-state conduction phase often improves, but the peak current mismatch during turn-on may increase. Conversely, when simply adjusting the switching timing, the improvement in current distribution during the steady-state conduction phase may be limited, resulting in some improvement in the current distribution during turn-on or turn-off transients, but the current deviation during the steady-state conduction phase remains difficult to suppress effectively. This is because the current distribution of parallel SiC MOSFETs in the turn-on transient, steady-state conduction, and turn-off transient phases is dominated by different physical factors. The turn-on transient is mainly affected by the conduction timing and current change rate, the steady-state conduction is mainly affected by the difference in on-resistance, and the turn-off transient is mainly affected by the turn-off timing and current decay process. Existing methods typically treat the parallel current deviation as a single quantity, failing to differentiate the physical mechanisms of different phases, making it difficult for a single adjustment method to simultaneously suppress uneven current in all three phases.

[0007] Secondly, some solutions directly use single-point peak values ​​or instantaneous sampled values ​​as the control basis. Under high-speed switching transient and high di / dt operating conditions, due to the influence of high-frequency oscillations, sampling phase deviations, and abnormal sampling points, error judgment fluctuations, false triggering of adjustments, or oscillations in the adjustment amount often occur. The root cause of this phenomenon is that single-point sampled values ​​are easily affected by transient interference, lack statistical stability and disturbance rejection capability, and are difficult to use as a reliable error control benchmark.

[0008] Third, some schemes lack system evaluation and feedback mechanisms during parameter updates. When the adjustment amount is set improperly or the adjustment direction gradually deviates from the optimal direction, it cannot be automatically identified and corrected, resulting in the parameter iteration failing to converge or converging slowly during the control process. This indicates that existing schemes lack the ability to adapt to error thresholds under different operating conditions, and also lack a closed-loop verification mechanism for the adjustment effect.

[0009] Therefore, it is necessary to study a current sharing control method and system for the active gate drive of parallel SiC MOSFETs based on phased current error. This method can extract and differentiate the current deviation of the parallel device in three stages: turn-on transient, steady-state conduction, and turn-off transient. Without relying on the precise model identification of the device, it can comprehensively suppress the dynamic and steady-state current imbalance of the parallel SiC MOSFET, thereby improving the stability and reliability of the parallel system under high-speed switching conditions. Summary of the Invention

[0010] To address the problems existing in the prior art, this invention proposes a method and system for controlling the current sharing of parallel SiC MOSFET active gate drive.

[0011] The technical solution of the present invention is as follows:

[0012] A method for current sharing control of active gate drive of parallel SiC MOSFETs, wherein the parallel SiC MOSFETs are composed of at least two parallel-connected SiC MOSFET branches, comprising:

[0013] Collect the drain current signal of each branch and perform proportional calibration on the current sampling signal of each branch to obtain a discrete current sequence that can be directly compared.

[0014] Based on the rising edge, conduction interval, and falling edge of the PWM drive signal, a single switching cycle is divided into a turn-on transient stage, a steady-state conduction stage, and a turn-off transient stage, and a sampling window is established for each stage.

[0015] Discrete statistics are performed on the current of each parallel branch in the sampling window of each stage. The following are extracted: the turn-on transient current error, which is used to characterize the comprehensive difference in the conduction timing and current build-up speed of the parallel branches; the steady-state conduction current error, which is used to characterize the steady-state current distribution deviation caused by the difference in conduction resistance and branch impedance; and the turn-off transient current error, which is used to characterize the difference in the turn-off timing and current decay process of the parallel branches.

[0016] The positive gate drive voltage of the corresponding branch is adjusted according to the steady-state on-current error. The turn-on timing and turn-off timing of the corresponding branch are compensated according to the turn-on transient current error and turn-off transient current error, respectively. When the positive gate drive voltage is reduced, the negative turn-off voltage of the corresponding branch is switched synchronously.

[0017] The average current level of each stage is extracted and combined with the pre-set target imbalance threshold corresponding to each stage to obtain the current error threshold, and it is determined whether to trigger the update of the positive gate drive voltage, turn-on timing, turn-off timing and negative turn-off voltage.

[0018] Based on the comprehensive error evaluation results before and after the update, it will be decided whether to accept this update or to roll back the parameters and limit the amplitude.

[0019] Furthermore, the specific method for dividing a single switching cycle into a turn-on transient stage, a steady-state turn-on stage, and a turn-off transient stage based on the rising edge, conduction interval, and falling edge of the PWM drive signal, and establishing a sampling window for each stage, includes: establishing a turn-on transient sampling window based on the sampling sequence number corresponding to the rising edge of the PWM signal to cover the rapid rise of the current in the parallel device; establishing a steady-state turn-on sampling window based on the middle and later stages of the PWM conduction time to cover the current range of the conduction plateau of the parallel device; and establishing a turn-off transient sampling window based on the sampling sequence number corresponding to the falling edge of the PWM signal to cover the rapid decrease of the current in the parallel device.

[0020] Furthermore, the sampling window includes an on-state transient sampling window, an off-state transient sampling window, and a steady-state on-state sampling window: the on-state transient sampling window is Ω. pk_on =[k on ,k on +N on ], where k on N represents the sampling sequence number corresponding to the start of the rising edge of the PWM. on The number of sampling points covering the current rise transient; the turn-off transient sampling window is Ω. pk_off =[k off ,k off +N off ], where k off N represents the sampling number corresponding to the falling edge of the PWM. off The number of sampling points covering the transient state of current drop; the steady-state conduction sampling window is Ω. ss =[k 0.5Ton ,k 0.75Ton ], where k 0.5Ton and k 0.75Ton These are the PWM on-time T. on The sampling sequence numbers corresponding to the 1 / 2 and 3 / 4 time points.

[0021] Furthermore, the turn-on transient current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the turn-on transient sampling window; the steady-state conduction current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the steady-state conduction sampling window; and the turn-off transient current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the turn-off transient sampling window.

[0022] Furthermore, for a structure consisting of two parallel SiC MOSFET branches, the turn-on transient current error, steady-state on-current error, and turn-off transient current error are defined by discrete statistical values ​​of the current difference between the two branches within the corresponding sampling window.

[0023] For a structure consisting of N parallel-connected SiC MOSFET branches, the turn-on transient current error, steady-state on-current error, and turn-off transient current error are defined by the deviation of each branch relative to the average parallel current, and the maximum deviation is taken as the comprehensive error for this stage.

[0024] Furthermore, the adjustment range of the forward gate drive voltage is 11V to 20V, and it adopts a step-by-step adjustment method; the compensation of the turn-on timing and turn-off timing adopts a step-by-step adjustment method based on the control cycle.

[0025] Furthermore, the adjustment of the forward gate drive voltage includes: maintaining or increasing the forward gate drive voltage of a branch when the steady-state on-current of a branch is relatively small; and decreasing the forward gate drive voltage of a branch when the steady-state on-current of a branch is relatively large.

[0026] The compensation for turn-on and turn-off timing includes: when the turn-on transient current error of a branch exceeds the corresponding threshold, turn-on timing compensation is applied to the turn-on time of the PWM drive signal of that branch to reduce the actual turn-on time deviation between parallel branches; when the turn-off transient current error of a branch exceeds the corresponding threshold, turn-off timing compensation is applied to the turn-off time of the PWM drive signal of that branch to reduce the actual turn-off time deviation between parallel branches; both the turn-on timing compensation and the turn-off timing compensation are updated independently in stages based on the current error of the corresponding stage.

[0027] The synchronous switching of the negative turn-off voltage includes: when the positive gate drive voltage of a certain branch is reduced, the negative turn-off voltage of that branch is simultaneously switched between two or more levels to reduce the absolute value of the negative voltage and compensate for the actual turn-on delay caused by the reduction of the positive gate drive voltage.

[0028] Furthermore, the current error threshold satisfies: Where p∈{pk} on ,ss,pk off} indicates the transient turn-on phase, steady-state turn-on phase, or transient turn-off phase. The target imbalance threshold for the corresponding stage. This is the average current reference value for the corresponding stage. Where N is the number of parallel branches, Let be the average current of the j-th branch within the sampling window of the corresponding stage.

[0029] Furthermore, the comprehensive error evaluation index is obtained by weighting the turn-on transient current error, the steady-state turn-on current error, and the turn-off transient current error, and the comprehensive error evaluation index satisfies: ;in, , and These are the weighting coefficients for the turn-on transient phase, the steady-state turn-on phase, and the turn-off transient phase, respectively.

[0030] If the updated comprehensive error evaluation index is less than the previous comprehensive error evaluation index, the update is accepted; if the updated comprehensive error evaluation index is greater than or equal to the previous comprehensive error evaluation index, parameter rollback and amplitude limiting are executed.

[0031] A parallel SiC MOSFET active gate drive current sharing control system is used in any of the parallel SiC MOSFET active gate drive current sharing control methods described above, including a parallel power device unit, a current sampling unit, an analog-to-digital conversion unit, a digital control unit, and an active gate drive unit.

[0032] The parallel power device unit includes at least two parallel SiC MOSFET branches, and each SiC MOSFET branch is connected to a power circuit;

[0033] The current sampling unit is coupled to each of the SiC MOSFET branches respectively, and is used to collect the drain current signal of each branch respectively;

[0034] The analog-to-digital conversion unit is connected to the current sampling unit and is used to sample the drain current signal and convert it into a discrete current sequence corresponding to each branch.

[0035] The digital control unit is connected to the analog-to-digital conversion unit and the active gate drive unit. It is used to extract the turn-on transient current error, steady-state turn-on current error and turn-off transient current error based on the discrete current sequence of each branch, generate drive parameter update, and output drive control commands corresponding to each branch.

[0036] The active gate drive unit is configured corresponding to each of the SiC MOSFET branches, and is used to receive the drive control command and adjust the positive gate drive voltage, negative turn-off voltage and PWM drive timing of the corresponding branch respectively, so as to realize the dynamic and steady-state integrated current sharing control of each branch of the parallel SiC MOSFET.

[0037] Compared with the prior art, the present invention has the following beneficial effects:

[0038] This invention proposes a current sharing control method and system for active gate drive of parallel SiC MOSFETs. This method performs staged discrete sampling and statistics on the drain current signal, extracts the corresponding current error in the three stages of turn-on transient, steady-state conduction, and turn-off transient, and performs targeted gate drive voltage adjustment and PWM drive timing compensation accordingly. This effectively solves the problems in the prior art where the dynamic and steady-state current of parallel SiC MOSFETs is significantly unbalanced under high-speed switching conditions, traditional passive current sharing methods are difficult to adjust online, and existing active current sharing methods are difficult to take into account the current deviation control in different operating stages.

[0039] This invention's method precisely divides a single switching cycle into three stages—the turn-on transient stage, the steady-state turn-on stage, and the turn-off transient stage—based on the rising edge, conduction interval, and falling edge of the PWM drive signal. A corresponding sampling window is established for each stage, and the current in the parallel branches is discretely statistically analyzed within each window to extract the current error for each stage. This staged processing approach overcomes the shortcomings of existing technologies that treat parallel current deviation as a single quantity and fail to adequately distinguish the current sharing mechanisms of different stages. It enables the control strategy to differentiate and adjust according to the current distribution characteristics and dominant influencing factors of each stage, significantly improving the effectiveness and specificity of current sharing control.

[0040] This invention utilizes the steady-state on-current error to adjust the positive gate drive voltage of the corresponding branch, and uses the turn-on transient current error and turn-off transient current error to adjust the turn-on and turn-off timing of the corresponding branch, respectively. It also synchronously switches the negative turn-off voltage when the positive gate drive voltage decreases. This design enables differentiated adjustment of the dominant influencing factors of parallel SiC MOSFETs at different operating stages. Specifically, it improves current distribution during the steady-state on-state conduction stage by adjusting the positive gate drive voltage, suppresses peak current mismatch during turn-on and turn-off transients by compensating for turn-on and turn-off timing, and compensates for the actual turn-on delay caused by changes in the positive gate drive voltage by synchronously switching the negative turn-off voltage. Thus, without relying on precise device model identification, it achieves synergistic suppression of dynamic and steady-state current imbalances in parallel SiC MOSFETs, improving the effectiveness, specificity, and system operational stability of current sharing control.

[0041] The method of this invention extracts the current error by using statistical methods such as discrete cumulative values, average values, or relative average current deviations within the sampling window at each stage. This overcomes the shortcomings of existing technologies that directly use single-point peak values ​​or instantaneous sampled values ​​as the control basis, which are easily affected by high-frequency oscillations and sampling deviations. It significantly improves the anti-interference capability and stability of the control system. The control algorithm is clear, the implementation method is simple, and the performance requirements of the digital controller are low. It can ensure that the parallel SiC MOSFETs achieve stable current distribution under different current levels.

[0042] The method of the present invention also sets target unbalance thresholds for different stages, and calculates dynamic current error thresholds by combining the average current level of the corresponding stage, so that the control criteria can adapt to different current level operating conditions, solving the application problem of lacking a unified error threshold mechanism applicable to multiple operating conditions in the prior art.

[0043] This invention introduces a comprehensive error evaluation index obtained by weighted summation of current errors in three stages. After parameter updates, the old and new comprehensive error indices are compared, and updates are only accepted when the index improves; otherwise, parameter rollback and limiting are implemented. This closed-loop evaluation and rollback mechanism overcomes the shortcomings of existing technologies, such as the lack of evaluation of regulation effects and the difficulty in long-term stable operation, thus ensuring the long-term operational stability of the control process.

[0044] The method and system of this invention do not rely on precise device model identification, have a clear control algorithm, are simple to implement, and have low requirements for the performance of digital controllers. They can achieve dynamic current sharing control of parallel SiC MOSFETs during the entire process of turn-on transients, steady-state conduction, and turn-off transients under different current levels. This effectively suppresses uneven current distribution in parallel devices, reduces thermal stress and turn-off stress, improves the reliability of the system, and to a certain extent expands the engineering application range of parallel SiC MOSFETs in high-frequency, high-power-density application scenarios. Attached Figure Description

[0045] Figure 1 This is a block diagram of the parallel SiC MOSFET active current sharing system of the present invention;

[0046] Figure 2 This is a diagram showing the switching waveforms and dynamic and static current characteristics of a dual-transistor parallel SiC MOSFET without current sharing measures according to the present invention.

[0047] Figure 3 This is a schematic diagram of the time window and statistical method for extracting current error in this invention;

[0048] Figure 4 This is a comparison diagram of the switching waveforms and dynamic and static current characteristics of the dual-transistor parallel SiC MOSFET after the gate voltage regulation and drive timing compensation of this invention;

[0049] Figure 5 This is a flowchart of the active current sharing control based on current error regulation and drive timing compensation of the present invention;

[0050] Figure 6(a) is the turn-on transient current distribution diagram under the single tube 10A operating condition without regulation strategy;

[0051] Figure 6(b) is the turn-on transient current distribution diagram of the voltage regulation strategy under the single tube 10A operating condition;

[0052] Figure 6(c) is the turn-on transient current distribution diagram of the full regulation strategy under the single tube 10A operating condition;

[0053] Figure 7(a) shows the steady-state turn-on and turn-off transient current distribution under the single-tube 10A operating condition without adjustment strategy;

[0054] Figure 7(b) is a diagram showing the steady-state turn-on and turn-off transient current distribution under the single-tube 10A operating condition with only voltage regulation strategy;

[0055] Figure 7(c) is a diagram showing the steady-state turn-on and turn-off transient current distribution under the full regulation strategy in the case of a single tube operating at 10A.

[0056] Figure 8(a) shows the turn-on transient current distribution before and after current sharing regulation without regulation strategy under the single tube 20A operating condition;

[0057] Figure 8(b) shows the turn-on transient current distribution before and after the current sharing regulation of the full regulation strategy under the single tube 20A operating condition;

[0058] Figure 9(a) shows the steady-state on- and off transient current distribution before and after current sharing regulation without regulation strategy under the single tube 20A operating condition;

[0059] Figure 9(b) shows the steady-state on-state and off-state transient current distribution before and after the current sharing regulation of the full regulation strategy under the single tube 20A operating condition.

[0060] Figure 10(a) shows the turn-on transient current distribution before and after current sharing regulation without regulation strategy under the single tube 50A operating condition.

[0061] Figure 10(b) shows the turn-on transient current distribution before and after the current sharing regulation of the full regulation strategy under the single tube 50A operating condition;

[0062] Figure 11(a) shows the steady-state on- and off transient current distribution before and after current sharing regulation without regulation strategy under the single tube 50A operating condition.

[0063] Figure 11(b) shows the steady-state on-state and off-state transient current distribution before and after the current sharing regulation of the full regulation strategy under the single tube 50A operating condition. Detailed Implementation

[0064] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading this invention, any modifications of the invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0065] Example 1:

[0066] The present invention discloses a current sharing control method for active gate drive of parallel SiC MOSFETs, wherein the parallel SiC MOSFETs are composed of at least two parallel-connected SiC MOSFET branches, comprising:

[0067] The drain current signals of each branch are collected, and the current sampling signals of each branch are proportionally calibrated to obtain directly comparable discrete current sequences. Specifically, after proportional calibration, the discrete current sequences of each branch are under a unified dimension and a unified gain reference, which can be used to calculate the current error between branches. In this embodiment, in order to reduce the impact of differences in sensor sensitivity, subsequent analog conditioning circuit gain, and sampling link transmission coefficient between different branch current detection channels on the calculation of parallel current error, the current detection channels of each branch are uniformly calibrated.

[0068] Specifically, frequency response tests can be performed on the current detection channels of each branch first, and each channel can be adjusted to a similar effective operating bandwidth range. The effective operating bandwidth can be determined according to the conventional definition of bandwidth in the field of current detection, such as the frequency range corresponding to a 3 dB drop in amplitude-frequency response relative to the passband reference. Subsequently, a preset reference frequency point or reference band is selected within the similar effective operating bandwidth range, and the amplitude gain of each branch channel is calibrated to obtain the proportional calibration coefficient between the current detection channels of each branch.

[0069] Furthermore, proportional calibration can be achieved through one or more of the following methods:

[0070] Firstly, the device parameters of the subsequent analog conditioning circuit are designed to be consistent in order to reduce the analog gain deviation between channels;

[0071] Secondly, a unified reference excitation signal is injected into the current detection channel of each branch, and the output response of each branch is compared to obtain the corresponding digital normalization coefficient.

[0072] Third, the sampling results are converted and processed according to the proportional calibration coefficient in the digital control system.

[0073] After the above calibration, the discrete current sequences of each branch are under a unified dimension and a unified gain reference, and the response differences between their channels are suppressed within a preset allowable range, so they can be directly used for the extraction and comparison of current error between parallel branches.

[0074] To reduce the impact of differences in mutual inductance and analog gain between different branch current detection channels on the calculation of parallel current error, a proportional calibration coefficient is introduced in the digital processing stage to perform uniform gain correction on the sampling signals of each branch, resulting in a directly comparable discrete current sequence i. dj (k), where j is the parallel branch number and k is the discrete sampling sequence number.

[0075] In this example, the drain current signal is obtained through a high-bandwidth current sensor, which is one of the following: a planar Rogowski coil, a current transformer, or other high-bandwidth current detection devices. The discrete current sequence is sampled by an analog-to-digital converter and then sent to a digital control chip for processing.

[0076] Based on the rising edge, conduction interval, and falling edge of the PWM drive signal, a single switching cycle is divided into a turn-on transient stage, a steady-state conduction stage, and a turn-off transient stage, and a sampling window is established for each stage. Figure 2 The diagram shows the switching waveforms and dynamic / static current characteristics of a dual-transistor parallel SiC MOSFET without current sharing measures. Figure 2 It can be seen that, without active adjustment, parallel devices exhibit significantly different forms of current imbalance during the turn-on, steady-state conduction, and turn-off phases, where i d1 i d2 The drain current signals of the two branches, v gs1 v gs2 This is the gate drive signal, and its turn-on and turn-off times are t. on t off The main differences during the turn-on phase are in the peak current and the current build-up rate; the main difference during the steady-state conduction phase is in the continuous shift of the conduction plateau current; and the main difference during the turn-off phase is in the peak current and the current decay process. To quantify the current differences during the sampled turn-on transient, steady-state conduction, and turn-off transient phases, the peak current difference during the turn-on phase is denoted as Δi. pk_on The turn-off time t near the end of the steady-state conduction phase off The corresponding current difference is denoted as Δi. ss The maximum value of the current difference in the current oscillation region during the turn-off transient phase is denoted as Δi. pk_off All the above current differences are absolute values.

[0077] Discrete statistics are performed on the current of each parallel branch in the sampling window of each stage. The following are extracted: the turn-on transient current error, which is used to characterize the comprehensive difference in the conduction timing and current build-up speed of the parallel branches; the steady-state conduction current error, which is used to characterize the steady-state current distribution deviation caused by the difference in conduction resistance and branch impedance; and the turn-off transient current error, which is used to characterize the difference in the turn-off timing and current decay process of the parallel branches.

[0078] The forward gate drive voltage V of the corresponding branch is determined based on the steady-state on-current error. CC Adjustments are made to compensate for the turn-on and turn-off timings of the corresponding branches based on the turn-on transient current error and the turn-off transient current error, respectively, and the positive gate drive voltage V is applied. CC When the voltage is lowered, the negative turn-off voltage V of the corresponding branch is switched synchronously. EE ;

[0079] Based on the discrete current sequence, the average current level of each stage is extracted. Combined with the pre-set target imbalance threshold corresponding to each stage, the current error threshold is obtained, and it is determined whether to trigger the update of the positive gate drive voltage, turn-on timing, turn-off timing and negative turn-off voltage. Generally, when the current error of any stage exceeds the current error threshold corresponding to that stage, the update of the corresponding branch is triggered.

[0080] Based on the comprehensive error evaluation results before and after the update, it was decided to accept the update or implement parameter rollback and limiting to complete the dynamic and steady-state comprehensive current sharing control of the parallel SiC MOSFET.

[0081] Example 2:

[0082] This embodiment, based on Embodiment 1, further designs the following: In this example, based on the rising edge, conduction interval, and falling edge of the PWM drive signal, a single switching cycle is divided into a turn-on transient stage, a steady-state conduction stage, and a turn-off transient stage. The specific method for establishing a sampling window for each stage includes: establishing a turn-on transient sampling window based on the sampling sequence number corresponding to the rising edge of the PWM signal to cover the rapid rise of the current in the parallel device; establishing a steady-state conduction sampling window based on the middle and later stages of the PWM conduction time to cover the conduction plateau current range of the parallel device; and establishing a turn-off transient sampling window based on the sampling sequence number corresponding to the falling edge of the PWM signal to cover the rapid decrease of the current in the parallel device.

[0083] Example 3:

[0084] This embodiment, based on Embodiment 2, further designs the sampling window as follows: the sampling window includes an on-state transient sampling window, an off-state transient sampling window, and a steady-state on-state sampling window; the on-state transient sampling window is Ω. pk_on =[k on ,k on +N on ], where k on N represents the sampling sequence number corresponding to the start of the rising edge of the PWM. on The number of sampling points covering the current rise transient; the turn-off transient sampling window is Ω. pk_off =[k off ,k off +N off ], where k off N represents the sampling number corresponding to the falling edge of the PWM. off The number of sampling points covering the transient state of current drop; the steady-state conduction sampling window is Ω. ss =[k 0.5Ton ,k 0.75Ton ], where k 0.5Ton and k 0.75Ton These are the PWM on-time T. onThe sampling sequence numbers corresponding to the 1 / 2 and 3 / 4 time points.

[0085] Example 4:

[0086] This embodiment, based on Embodiment 1, is further designed in that the turn-on transient current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the turn-on transient sampling window; the steady-state conduction current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the steady-state conduction sampling window; and the turn-off transient current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the turn-off transient sampling window.

[0087] Specifically, the following are examples: Figure 3 The following example illustrates the division of a single switching cycle and the establishment of a sampling window. Figure 3 The diagram shows the time window and statistical method for current error extraction in this invention. Within a single PWM switching cycle, the operation of the parallel SiC MOSFET is divided into a turn-on transient phase, a steady-state conduction phase, and a turn-off transient phase.

[0088] During the turn-on transient phase, the sampling sequence number k corresponds to the rising edge of the PWM. on Establish the transient sampling window Ω based on the benchmark. pk_on =[k on ,k on +N on ], where N on This is the number of sampling points to cover the transient current rise. Within this sampling window, the current difference between each parallel branch is discretely statistically analyzed to extract the transient current error I during turn-on. err_pk_on It is used to characterize the comprehensive differences in conduction timing and current build-up speed of parallel branches.

[0089] During the steady-state conduction phase, the PWM conduction time T on Establish a steady-state conduction sampling window Ω as a reference. ss =[k 0.5Ton ,k 0.75Ton ], where k 0.5Ton and k 0.75Ton These are the PWM on-time T. on The sampling sequence numbers corresponding to the 1 / 2 and 3 / 4 time points are determined. Within this sampling window, the current difference of each parallel branch is discretely statistically analyzed to extract the steady-state conduction current error I. err_ss It is used to characterize the steady-state current distribution deviation caused by differences in conduction resistance and branch impedance.

[0090] During the turn-off transient phase, the sampling sequence number k corresponds to the falling edge of the PWM. off Establish the turn-off transient sampling window Ω as a benchmarkpk_off =[k off ,k off +N off ], where N off The number of sampling points is set to cover the transient current drop. Within this sampling window, the current difference between each parallel branch is discretely statistically analyzed to extract the turn-off transient current error I. err_pk_off It is used to characterize the differences in the turn-off timing and current decay process of parallel branches.

[0091] Example 5:

[0092] This embodiment is further designed based on the first embodiment in that, for the structure consisting of two parallel SiC MOSFET branches (dual-tube parallel structure), the turn-on transient current error, steady-state conduction current error, and turn-off transient current error are defined by discrete statistical values ​​of the current difference between the two branches within the corresponding sampling window.

[0093] For a structure consisting of N parallel SiC MOSFET branches (N-MOSFET parallel structure), the turn-on transient current error, steady-state conduction current error, and turn-off transient current error are defined by the deviation of each branch relative to the average parallel current, and the maximum deviation is taken as the comprehensive error for this stage.

[0094] Example 6:

[0095] This embodiment, based on Embodiment 1, is further designed in that the forward gate drive voltage V in this example is... CC The adjustment range is 11V to 20V, and it adopts a stepped adjustment or graded adjustment method to avoid new dynamic disturbances caused by excessive adjustment in a single step. The compensation for the turn-on and turn-off timing adopts a step adjustment method based on the control cycle. Furthermore, the turn-on transient current error corresponds to the turn-on timing compensation amount Δt. on The turn-off transient current error corresponds to the turn-off timing compensation amount Δt. off , Δt on and Δt off A step-by-step adjustment method based on the control cycle is adopted, Δt on and Δt off Used to adjust the turn-on and turn-off times of the corresponding branch's PWM drive signal.

[0096] Example 7:

[0097] This embodiment is further designed based on Embodiment 1, in that the adjustment of the forward gate drive voltage in this example includes: when the steady-state conduction current of a certain branch is relatively small, maintaining or increasing the forward gate drive voltage of that branch; when the steady-state conduction current of a certain branch is relatively large, decreasing the forward gate drive voltage of that branch.

[0098] The compensation for turn-on and turn-off timing includes: when the turn-on transient current error of a branch exceeds the corresponding threshold, turn-on timing compensation is applied to the turn-on time of the PWM drive signal of that branch to reduce the actual turn-on time deviation between parallel branches; when the turn-off transient current error of a branch exceeds the corresponding threshold, turn-off timing compensation is applied to the turn-off time of the PWM drive signal of that branch to reduce the actual turn-off time deviation between parallel branches; both turn-on timing compensation and turn-off timing compensation are updated independently in stages based on the current error of the corresponding stage.

[0099] Synchronous switching of the negative turn-off voltage includes: when the positive gate drive voltage of a branch is reduced, simultaneously switching the negative turn-off voltage V of that branch. EE Switch between two or more gears to reduce the absolute value of the negative pressure and compensate for the V CC This reduces the actual turn-on delay and accelerates the process of the gate voltage recovering from the negative voltage region to the threshold voltage.

[0100] Specifically, the following are examples: Figure 4 Taking the example of using gate voltage regulation and drive timing compensation, we will explain in detail how they are applied. Figure 4 The figure shows a comparison of the switching waveforms and dynamic / static current characteristics of the dual-transistor parallel SiC MOSFET after applying gate voltage regulation and drive timing compensation according to the present invention. The dominant influencing factors of the device drain current differ at different operating stages; therefore, the present invention establishes a correspondence between the current error extracted at different stages and different drive regulation methods.

[0101] During the steady-state conduction phase, when the steady-state conduction current error I is detected... err_ss When the corresponding threshold is exceeded, the controller applies a positive gate drive voltage V to the corresponding branch. CC Perform adjustments in stages. For branches with relatively low steady-state conduction current, maintain or increase V. CC To reduce its equivalent on-resistance; for branches with relatively large steady-state on-current, reduce V CC This increases its equivalent on-resistance, thereby improving the current distribution during the steady-state conduction phase.

[0102] In this embodiment, V CC The adjustment range is set to 11V~20V, where the lower limit is limited by the undervoltage protection threshold of the secondary side of the driver chip, and the upper limit meets the maximum gate drive voltage requirement recommended by the device. To reduce new dynamic disturbances caused by a single adjustment, V CC It adopts a step-by-step adjustment method or a graded adjustment method.

[0103] During the turn-on transient phase, when the turn-on transient current error I is detected... err_pk_on When the corresponding threshold is exceeded, the controller applies a turn-on timing compensation amount Δt to the relevant branch. onThis reduces the deviation in the actual turn-on time of parallel devices and suppresses the difference in peak current during the turn-on phase.

[0104] During the turn-off transient phase, when the turn-off transient current error I is detected... err_pk_off When the corresponding threshold is exceeded, the controller applies a shutdown timing compensation amount Δt to the relevant branch. off This reduces the deviation in the actual turn-off time of parallel devices and improves the distribution of transient turn-off current.

[0105] Furthermore, the forward gate drive voltage V of a certain branch CC When reduced, to compensate V CC The reduced turn-on delay caused by the negative turn-off voltage V of this branch EE Coordinated switching is performed to reduce the absolute value of the negative voltage, thereby accelerating the recovery of the gate voltage from the negative voltage region to the threshold voltage. In this embodiment, V EE It can be switched between two gears, or multiple gears can be switched as needed.

[0106] Example 8:

[0107] This embodiment, based on Embodiment 1, is further designed in that the current error threshold in this example satisfies: Where p∈{pk} on ,ss,pk off} indicates the transient turn-on phase, steady-state turn-on phase, or transient turn-off phase. The target imbalance threshold for the corresponding stage. This is the average current reference value for the corresponding stage. Where N is the number of parallel branches, Let be the average current of the j-th branch within the sampling window of the corresponding stage.

[0108] Example 9:

[0109] This embodiment, based on Embodiment 1, further designs the comprehensive error evaluation index by weighting the turn-on transient current error, the steady-state turn-on current error, and the turn-off transient current error, and the comprehensive error evaluation index satisfies: ;in, , and These are the weighting coefficients for the turn-on transient phase, the steady-state conduction phase, and the turn-off transient phase, respectively; such as Figure 5 As shown, after the controller completes error extraction and drive parameter update in each control cycle, it compares the comprehensive error evaluation index before and after the update:

[0110] If the updated comprehensive error evaluation index is less than the previous comprehensive error evaluation index, the update is accepted; if the updated comprehensive error evaluation index is greater than or equal to the previous comprehensive error evaluation index, parameter rollback and amplitude limiting are executed to ensure the stable operation of the parallel system.

[0111] Specifically, such as Figure 5 As shown, the active current sharing control process of the present invention sequentially executes the following steps in each switching cycle:

[0112] 1) Initialize all parameters, including the forward gate drive voltage V. CC Negative turn-off voltage V EE Δt, the timing compensation amount during commissioning on and shutdown timing compensation amount Δt off Target imbalance threshold ;

[0113] 2) Perform sampling and calibration, and obtain the discrete current sequence i for each branch. dj (k) is used to establish turn-on transient, steady-state turn-on and turn-off transient sampling windows based on the PWM edge;

[0114] 3) Error calculation and threshold conversion: Extract the error amount through discrete statistics within each window. Based on the average current reference value of each stage Imbalance threshold with the preset target Calculate the current error threshold for the corresponding stage. ;

[0115] 4) Exceedance Detection: Compare the error amount with the threshold to determine whether to trigger a parameter update; if... If the condition is met, the parameter update will be executed according to the driving parameter update strategy; otherwise, the current driving parameters will be maintained and the next cycle will begin.

[0116] 5) After updating the parameters, recalculate the comprehensive error evaluation index J. err_new The updated indicator J err_new Compared with the previous indicator J err_old Compared, if the indicator J improves err_new Greater than or equal to J err_old If J err_new <J err_old The backoff parameters and amplitude limit are applied before proceeding to the next cycle, thus ensuring the convergence of the control process and the stability of system operation. The comprehensive error evaluation index J... err =f( f(*) represents the comprehensive error evaluation index and the error quantity. The relational function.

[0117] Furthermore, parameter rollback refers to restoring one or more driving parameters involved in the update to their pre-update values ​​when the overall error evaluation index fails to improve after the update. This is to avoid ineffective adjustments that could cause system oscillations or error amplification. The following example illustrates parameter rollback and limiting in detail:

[0118] The following example uses a dual-parallel SiC MOSFET to illustrate parameter rollback and limiting.

[0119] Assuming that within a certain control cycle, the controller, based on the detected steady-state on-current error and turn-on transient current error, intends to reduce the forward gate drive voltage of the first branch from 18V to 17V, and adjust the turn-on timing compensation of this branch from 10ns to 20ns. After the update, the comprehensive error evaluation index is recalculated; if the comprehensive error evaluation index before the update is J... err_old =0.82, the updated comprehensive error evaluation index is J err_new =0.87, then since J err_new ≥J err_old This indicates that the parameter update did not bring any improvement. At this point, parameter rollback is performed, which means restoring the positive gate drive voltage of the first branch to 18V and restoring the turn-on timing compensation to 10ns.

[0120] In the above process, limiting is used to constrain the allowable range of driving parameters. For example, the forward gate drive voltage V CC Limited to the range of 11V to 20V, the turn-on timing compensation amount Δt on and shutdown timing compensation amount Δt off It is limited to a preset timing compensation range, such as 0–50 ns or ±50 ns. When the update result obtained from a calculation exceeds the allowable range, the corresponding parameter is truncated to the boundary value. For example, when V is calculated... CC When the voltage drops to 10V, since it is below the lower limit of 11V, it is limited to 11V; when Δt is calculated... on When it should be increased to 60ns, since it exceeds the 50ns upper limit, it is limited to 50ns.

[0121] By combining parameter rollback with limiting, error deterioration caused by invalid updates can be avoided, while ensuring that the driving parameters are always within a safe and achievable range for the system.

[0122] Example 10:

[0123] The present invention provides a parallel SiC MOSFET active gate drive current sharing control system for executing the parallel SiC MOSFET active gate drive current sharing control method described in any of the above embodiments, comprising a parallel power device unit, a current sampling unit, an analog-to-digital conversion unit, a digital control unit, and an active gate drive unit.

[0124] The parallel power device unit includes at least two parallel SiC MOSFET branches, each of which is connected to a power circuit.

[0125] The current sampling unit is coupled to each SiC MOSFET branch to collect the drain current signal of each branch.

[0126] The analog-to-digital conversion unit is connected to the current sampling unit and is used to sample the drain current signal and convert it into a discrete current sequence corresponding to each branch.

[0127] The digital control unit is connected to the analog-to-digital conversion unit and the active gate drive unit. It is used to extract the turn-on transient current error, steady-state turn-on current error and turn-off transient current error based on the discrete current sequence of each branch, generate the drive parameter update, and output the corresponding drive control command for each branch.

[0128] An active gate drive unit is configured corresponding to each SiC MOSFET branch to receive drive control commands and adjust the positive gate drive voltage, negative turn-off voltage and PWM drive timing of the corresponding branch to achieve dynamic and steady-state integrated current sharing control of each branch of the parallel SiC MOSFET.

[0129] Reference Figure 1 In this example, the parallel SiC MOSFET active gate drive current sharing control system includes a current sampling unit, an analog-to-digital conversion unit, a digital control unit, two active gate drive units, a parallel power device unit, and a power circuit. Figure 1 The digital control unit on the left includes an error extraction and threshold comparison module, a gate voltage adjustment calculation module, a timing compensation calculation module, and a comprehensive evaluation module; the middle part consists of two active gate drive units; the right part consists of Q... L1 Q L2 The parallel power device unit and the power circuit in which it is located.

[0130] The parallel power device unit includes a first SiC MOSFET branch and a second SiC MOSFET branch, which correspond to Q in the figure, respectively. L1 Branch and Q L2The first SiC MOSFET branch and the second SiC MOSFET branch are connected in parallel in the power circuit, with their upper ends connected to the DC bus VDC and their lower ends connected to the reference ground GND. The power circuit also includes a load inductor L. load The freewheeling branch, shown in the figure, includes diode D. Hl .

[0131] The current sampling unit is respectively connected to Q L1 Branch and Q L2 Branch coupling is used to separately acquire the drain current signals i of the two branches. d1 i d2 The acquired analog current signal is sent to the digital control unit via an analog-to-digital converter to form the discrete current sequence i corresponding to each branch. d1 (k), i d2 (k). Figure 1 The two discrete current sequences can be represented as the first branch discrete current sequence and the second branch discrete current sequence, respectively.

[0132] The digital control unit is used to perform proportional calibration on two discrete current sequences and extract the turn-on transient current error I during the turn-on transient phase, steady-state conduction phase, and turn-off transient phase, respectively. err_pk_on Steady-state conduction current error I err_ss and the turn-off transient current error I err_pk_off Furthermore, the digital control unit calculates the corresponding drive parameter update amounts based on the extracted error amount via the gate voltage adjustment calculation module and the timing compensation calculation module. These update amounts include the positive gate drive voltage adjustment amount, the negative turn-off voltage adjustment amount, and the turn-on timing compensation amount Δt. on and shutdown timing compensation amount Δt off .

[0133] The two active gate drive units are respectively connected to Q L1 Branch and Q L2 The branches are connected accordingly. Each active gate drive unit includes an isolation drive circuit and a drive power supply branch. The isolation drive circuit receives the PWM control signal output from the digital control unit, which corresponds to PWM1 and PWM2 in the figure, and provides the corresponding gate drive signal v to the parallel power device unit. gs1 v gs2 Its high level corresponds to the positive gate drive voltage V. CC A low level corresponds to a negative turn-off voltage V. EE The drive power supply branch receives the PWMV drive signal output from the digital control unit, which corresponds to PWMV1 and PWMV2 in the diagram, respectively. It provides independently adjustable positive gate drive voltage and negative turn-off voltage to the corresponding branch, which correspond to the V of the first branch in the diagram. CC1 VEE1 And the V of the second branch road CC2 V EE2 .

[0134] In this embodiment, the gate drive parameters of the first branch and the second branch can be adjusted independently, thereby affecting Q. L1 and Q L2 Differentiated control is implemented for the turn-on time, turn-off time, and effective gate voltage during the conduction phase.

[0135] Based on the current error calculated from the discrete current sequences of the two branches and the comprehensive error evaluation result obtained by the comprehensive evaluation module, the digital control unit outputs corresponding drive control commands to the two active gate drive units, adjusting V respectively. CC1 V EE1 V CC2 V EE2 And the timing compensation amounts (Δt) of PWM1 and PWM2 on Δt off This is to achieve active flow sharing control between parallel branches.

[0136] Furthermore, the digital control unit is a DSP digital controller, a microcontroller (MCU), an FPGA controller, or a combination thereof.

[0137] Example 11:

[0138] An electronic device according to the present invention includes a memory and a processor. The memory stores a computer program, and the processor is used to call and run the computer program stored in the memory to perform the method as described in any of the above embodiments.

[0139] The present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above embodiments.

[0140] Application Examples:

[0141] This embodiment uses a continuous pulse test platform for experimental verification. The test platform generates a low duty cycle PWM signal based on the DSP28377D development board, and adopts the same power main circuit as the dual-pulse test, with a load inductance L. load The voltage is 21.7 μH. In the experiment, two SiC MOSFETs with significantly different parameters were selected for parallel testing. The drive parameters were uniformly set to R. gon =3.3Ω, R goff =0Ω. Figures 6(a) to 6(c) The gate drive signal v is given in Figures 7(a) to 7(c), 8(a) and 8(b). gs1 v gs2 With the drain current signal i of the two branchesd1 i d2 The no-regulation strategy uses the same drive parameters and PWM timing, and can be regarded as the baseline operating condition under fixed drive conditions, used to characterize the parallel current distribution characteristics without active regulation; the voltage-only regulation strategy and the full regulation strategy correspond to the drive voltage amplitude (V) in AGD, respectively. CC V EE The adjustment of the driving voltage amplitude and timing compensation (Δt) on Δt off ( ) combined regulation.

[0142] To verify the superiority and feasibility of this invention, continuous pulse experiments were conducted under steady-state current levels of 10A, 20A, and 50A for a single transistor, respectively. The steps are as follows:

[0143] 1) Under a single-pipe 10A operating condition, a comparison is made between the no-regulation strategy, the voltage-regulation-only strategy, and the fully-regulation strategy proposed in this invention. Figures 6(a) to 6(c) and Figures 7(a) to 7(c) It is known that without the adjustment strategy, parallel devices exhibit significant current mismatch during the steady-state conduction and turn-off phases. While the voltage regulation strategy alone can significantly reduce the steady-state conduction current deviation, it exacerbates the difference in transient peak current during turn-on. By adopting the full adjustment strategy proposed in this invention, the peak imbalance during turn-on, the average current imbalance during steady-state, and the peak imbalance during turn-off are all significantly reduced, achieving integrated current sharing control of dynamic and steady-state conditions.

[0144] 2) Under the single tube 20A operating condition, as shown in Figures 8(a), 8(b), 9(a) and 9(b), after adopting the method of the present invention, the uneven current in the steady-state conduction stage and the turn-off stage is significantly reduced. Although the transient imbalance during turn-on changes to some extent compared with the no-adjustment strategy, it is still controlled within the acceptable range for engineering, indicating that the present invention still has good applicability under high current conditions.

[0145] 3) Under the single-tube 50A operating condition, as shown in Figures 10(a), 10(b), 11(a) and 11(b), the current distribution during the steady-state conduction and turn-off stages is significantly improved after adopting the method of the present invention, indicating that the present invention still has good robustness and engineering applicability under high current conditions.

[0146] The experimental results show that the control method proposed in this invention can effectively suppress the dynamic and steady-state current mismatch of parallel SiC MOSFETs under high-speed switching conditions, thereby improving the operational reliability of the parallel system.

[0147] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for current sharing control of a parallel SiC MOSFET active gate drive, wherein the parallel SiC MOSFET is composed of at least two parallel-connected SiC MOSFET branches, characterized in that, include: Collect the drain current signal of each branch and perform proportional calibration on the current sampling signal of each branch to obtain a discrete current sequence that can be directly compared. Based on the rising edge, conduction interval, and falling edge of the PWM drive signal, a single switching cycle is divided into a turn-on transient stage, a steady-state conduction stage, and a turn-off transient stage, and a sampling window is established for each stage. Discrete statistics are performed on the current of each parallel branch in the sampling window of each stage. The following are extracted: the turn-on transient current error, which is used to characterize the comprehensive difference in the conduction timing and current build-up speed of the parallel branches; the steady-state conduction current error, which is used to characterize the steady-state current distribution deviation caused by the difference in conduction resistance and branch impedance; and the turn-off transient current error, which is used to characterize the difference in the turn-off timing and current decay process of the parallel branches. The positive gate drive voltage of the corresponding branch is adjusted according to the steady-state on-current error. The turn-on timing and turn-off timing of the corresponding branch are compensated according to the turn-on transient current error and turn-off transient current error, respectively. When the positive gate drive voltage is reduced, the negative turn-off voltage of the corresponding branch is switched synchronously. The average current level of each stage is extracted and combined with the pre-set target imbalance threshold corresponding to each stage to obtain the current error threshold, and it is determined whether to trigger the update of the positive gate drive voltage, turn-on timing, turn-off timing and negative turn-off voltage. Based on the comprehensive error evaluation results before and after the update, it will be decided whether to accept this update or to roll back the parameters and limit the amplitude.

2. The parallel SiC MOSFET active gate drive current sharing control method according to claim 1, characterized in that, The specific method for dividing a single switching cycle into a turn-on transient phase, a steady-state turn-on phase, and a turn-off transient phase based on the rising edge, conduction interval, and falling edge of the PWM drive signal, and establishing a sampling window for each phase, includes: establishing a turn-on transient sampling window based on the sampling sequence number corresponding to the rising edge of the PWM signal to cover the rapid rise of the current in the parallel device; establishing a steady-state turn-on sampling window based on the middle and later stages of the PWM conduction time to cover the current range of the conduction plateau of the parallel device; and establishing a turn-off transient sampling window based on the sampling sequence number corresponding to the falling edge of the PWM signal to cover the rapid decrease of the current in the parallel device.

3. The parallel SiC MOSFET active gate drive current sharing control method according to claim 2, characterized in that, The sampling window includes an on-state transient sampling window, an off-state transient sampling window, and a steady-state on-state sampling window: the on-state transient sampling window is Ω. pk_on =[k on ,k on +N on ], where k on N represents the sampling sequence number corresponding to the start of the rising edge of the PWM. on The number of sampling points covering the current rise transient; the turn-off transient sampling window is Ω. pk_off =[k off ,k off +N off ], where k off N represents the sampling number corresponding to the falling edge of the PWM. off The number of sampling points covering the transient state of current drop; the steady-state conduction sampling window is Ω. ss =[k 0.5Ton ,k 0.75Ton ], where k 0.5Ton and k 0.75Ton These are the PWM on-time T. on The sampling sequence numbers corresponding to the 1 / 2 and 3 / 4 time points.

4. The parallel SiC MOSFET active gate drive current sharing control method according to claim 1, characterized in that, The turn-on transient current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the turn-on transient sampling window; the steady-state conduction current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the steady-state conduction sampling window; the turn-off transient current error is obtained from the discrete cumulative value, average value, or relative average current deviation of the current difference of each parallel branch within the turn-off transient sampling window.

5. The parallel SiC MOSFET active gate drive current sharing control method according to claim 1, characterized in that, For a structure consisting of two parallel SiC MOSFET branches, the turn-on transient current error, steady-state on-current error, and turn-off transient current error are defined by discrete statistical values ​​of the current difference between the two branches within the corresponding sampling window. For a structure consisting of N parallel-connected SiC MOSFET branches, the turn-on transient current error, steady-state on-current error, and turn-off transient current error are defined by the deviation of each branch relative to the average parallel current, and the maximum deviation is taken as the comprehensive error for this stage.

6. The parallel SiC MOSFET active gate drive current sharing control method according to claim 1, characterized in that, The adjustment range of the forward gate drive voltage is 11V to 20V, and it adopts a step-by-step adjustment method; the compensation of the turn-on timing and turn-off timing adopts a step-by-step adjustment method based on the control cycle.

7. The parallel SiC MOSFET active gate drive current sharing control method according to claim 1, characterized in that, The adjustment of the forward gate drive voltage includes: maintaining or increasing the forward gate drive voltage of a branch when the steady-state on-current of a branch is relatively small; and decreasing the forward gate drive voltage of a branch when the steady-state on-current of a branch is relatively large. The compensation for turn-on and turn-off timing includes: when the turn-on transient current error of a branch exceeds the corresponding threshold, turn-on timing compensation is applied to the turn-on time of the PWM drive signal of that branch to reduce the actual turn-on time deviation between parallel branches; when the turn-off transient current error of a branch exceeds the corresponding threshold, turn-off timing compensation is applied to the turn-off time of the PWM drive signal of that branch to reduce the actual turn-off time deviation between parallel branches; both the turn-on timing compensation and the turn-off timing compensation are updated independently in stages based on the current error of the corresponding stage. The synchronous switching of the negative turn-off voltage includes: when the positive gate drive voltage of a certain branch is reduced, the negative turn-off voltage of that branch is simultaneously switched between two or more levels to reduce the absolute value of the negative voltage and compensate for the actual turn-on delay caused by the reduction of the positive gate drive voltage.

8. The parallel SiC MOSFET active gate drive current sharing control method according to claim 1, characterized in that, The current error threshold satisfies: Where p∈{pk} on ,ss,pk off } indicates the transient turn-on phase, steady-state turn-on phase, or transient turn-off phase. The target imbalance threshold for the corresponding stage. This is the average current reference value for the corresponding stage. Where N is the number of parallel branches, Let be the average current of the j-th branch within the sampling window of the corresponding stage.

9. The parallel SiC MOSFET active gate drive current sharing control method according to claim 1, characterized in that, The comprehensive error evaluation index is obtained by weighting the turn-on transient current error, the steady-state turn-on current error, and the turn-off transient current error, and the comprehensive error evaluation index satisfies: ;in, , and These are the weighting coefficients for the turn-on transient phase, the steady-state turn-on phase, and the turn-off transient phase, respectively. If the updated comprehensive error evaluation index is less than the previous comprehensive error evaluation index, the update is accepted; if the updated comprehensive error evaluation index is greater than or equal to the previous comprehensive error evaluation index, parameter rollback and amplitude limiting are executed.

10. A parallel SiC MOSFET active gate drive current sharing control system, used to execute the parallel SiC MOSFET active gate drive current sharing control method according to any one of claims 1 to 9, characterized in that, It includes a parallel power device unit, a current sampling unit, an analog-to-digital conversion unit, a digital control unit, and an active gate drive unit; The parallel power device unit includes at least two parallel SiC MOSFET branches, and each SiC MOSFET branch is connected to a power circuit; The current sampling unit is coupled to each of the SiC MOSFET branches respectively, and is used to collect the drain current signal of each branch respectively; The analog-to-digital conversion unit is connected to the current sampling unit and is used to sample the drain current signal and convert it into a discrete current sequence corresponding to each branch. The digital control unit is connected to the analog-to-digital conversion unit and the active gate drive unit. It is used to extract the turn-on transient current error, steady-state turn-on current error and turn-off transient current error based on the discrete current sequence of each branch, generate drive parameter update, and output drive control commands corresponding to each branch. The active gate drive unit is configured corresponding to each of the SiC MOSFET branches, and is used to receive the drive control command and adjust the positive gate drive voltage, negative turn-off voltage and PWM drive timing of the corresponding branch respectively, so as to realize the dynamic and steady-state integrated current sharing control of each branch of the parallel SiC MOSFET.

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