Direct current pulsed signal control system and semiconductor processing apparatus

Abstract

The application provides a direct current pulse signal control system and a semiconductor processing device, which combines a first control signal generated according to an alternating current analog signal and a second control signal generated according to a pulse digital signal into a mixed synchronization signal, the first control signal acts on a direct current energy supply module through a direct current state control module to control the charging state of the direct current energy supply module, so that the output direct current voltage signal is within a threshold range; the second control signal acts on the direct current energy supply module through a direct current output control module to modulate the direct current voltage signal, so that a direct current pulse signal meeting process requirements is obtained and output to the semiconductor processing device as a bias voltage. The application can accurately regulate and control the bias voltage, improve the adaptability, anti-interference ability and response stability of the system, and optimize the process performance of semiconductor processing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a DC pulse signal control system and semiconductor processing equipment. Background Technology

[0002] As the market demand for advanced storage devices continues to expand, the requirements for semiconductor manufacturing processes are becoming increasingly stringent, making voltage bias particularly important in the processing. In traditional semiconductor processing equipment, a high-frequency radio frequency (RF) signal excites neutral gas within a reaction chamber to generate plasma, which serves as the source of charged particles. Then, a low-frequency RF signal creates a strong negative bias voltage, accelerating the positively charged particles and causing them to rapidly bombard the substrate surface to form the desired micro / nano structures. For example, in high aspect ratio etching processes, it is necessary to form high aspect ratio structures where the etching depth is much greater than the etching width.

[0003] However, in the above-mentioned RF bias scheme, the RF signal has the characteristics of alternating positive and negative amplitudes and periodic changes in intensity over time. The voltage is at its peak for a very short time, which makes it impossible for the generated bias to maintain a stable maximum acceleration capability during the acceleration of charged particles. The charged particle path is prone to deviation, making it difficult to process the structural features that meet the expectations. This has limitations in the research and development and use of high aspect ratio etching processes.

[0004] To address this, some existing technologies have begun to use bias schemes based on high-voltage DC pulses. These schemes retain high-frequency radio frequency (RF) signals to generate plasma, while replacing low-frequency RF signals with high-voltage DC pulses to generate the bias voltage. By controlling the switching devices with pulse digital signals, the parameters of the high-voltage DC pulses can be flexibly adjusted, enabling effective control of the charged particle acceleration process. However, with increasing complexity in process conditions, the requirements for bias strength and control speed have also increased. Simultaneously, the sources of interference noise have become more diverse. In this context, relying solely on pulse digital signals to control the high-voltage DC pulse is insufficient to achieve ideal control accuracy, necessitating a more stable and reliable DC bias control scheme. Summary of the Invention

[0005] This invention provides a semiconductor processing device and a DC pulse signal control system for providing bias voltage to it. It enables two control signals generated based on digital and analog signals to have a stable correlation in the time domain. Under the action of these two control signals, the DC supply control module can precisely regulate the high-voltage DC pulse signal required to generate bias voltage, thereby improving the system's adaptability, anti-interference ability and response stability, and optimizing the process performance of semiconductor processing.

[0006] One technical solution of the present invention is to provide a DC pulse signal control system, which includes:

[0007] DC power supply module, used to provide DC voltage signal;

[0008] The control signal generation module is used to generate a first control signal based on an AC analog signal, generate a second control signal based on a pulse digital signal, and provide a mixed synchronization signal containing the first control signal and the second control signal.

[0009] A DC state control module, coupled to the control signal generation module and the DC energy supply module respectively, is used to control the charging state of the DC energy supply module according to the first control signal in the hybrid synchronization signal, so that the DC voltage signal output by the DC energy supply module is within the threshold range.

[0010] The DC output control module is coupled to the control signal generation module and the DC energy supply module respectively, and is used to modulate the DC voltage signal output by the DC energy supply module according to the second control signal in the hybrid synchronization signal to obtain a DC pulse signal.

[0011] Optionally, the control signal generation module further includes a central control module;

[0012] The master control module is equipped with a signal source to provide pulse digital signals and AC analog signals generated by the same source clock.

[0013] Optionally, the control signal generation module further includes:

[0014] An auxiliary processing module, coupled to the main control module, is used to process AC analog signals to obtain trigger signals.

[0015] The trigger module, coupled to the auxiliary processing module, is used to convert the trigger signal into a first control signal;

[0016] The trigger signal has a voltage oscillation waveform; when the voltage in the trigger signal rises above the high-level trigger point set by the trigger module, the first control signal outputs a high level, which serves as a start command to drive the DC energy supply module to start charging operation, causing the DC energy supply module to start adjusting the voltage value of the DC voltage signal.

[0017] When the voltage of the trigger signal drops below the low-level trigger point set by the trigger module, the first control signal outputs a low level, serving as a termination command to drive the DC energy supply module to end the charging operation, thereby causing the DC energy supply module to stop adjusting the voltage value of the DC voltage signal.

[0018] Optionally, the control signal generation module further includes a first isolation protection module;

[0019] The first isolation protection module is coupled to the trigger module and the DC state control module respectively, and is used to transmit the first control signal to the DC state control module without loss.

[0020] Optionally, the auxiliary processing module is used to amplify, rectify, and adjust the signal parameters of the AC analog signal; the adjustable signal parameters include at least one of the following: amplitude, waveform, and time delay;

[0021] The auxiliary processing module is implemented through analog circuits and / or digital circuits; the analog circuits contain several electronic components capable of performing set functions; the digital circuits contain several controllable electrical modules connected to the main control module via a control bus, receiving instructions to adjust their respective electrical parameters to perform corresponding adjustment operations.

[0022] Optionally, the control signal generation module further includes:

[0023] A buffer module, coupled to the main control module, is used to provide a second control signal synchronized with the pulse digital signal. The second control signal reflects the state changes of the pulse digital signal. The second control signal is synchronized in the time domain with the first control signal output by the trigger module.

[0024] The second isolation protection module is coupled to the buffer module and the DC output control module respectively, and is used to transmit the second control signal to the DC output control module without loss.

[0025] Optionally, the DC pulse signal control system includes a sensing module for monitoring the operating status of one or more other modules within the system, load terminals that receive DC pulse signals from the system, or power supply modules that provide DC energy to the system, and feeding back the monitoring data to the central control module for analysis and processing, so that the central control module generates instructions to control the relevant modules within the system.

[0026] Optionally, the DC power supply module is coupled to the power supply module to obtain DC power provided by the power supply module;

[0027] Links for transmitting energy and / or information are provided between the DC energy supply module and the power supply module, between the modules of the DC pulse signal control system, and between the system and the load terminal receiving the DC pulse signal; the links include transmission paths based on at least one of electrical, mechanical, and optical methods.

[0028] Optionally, when the DC voltage signal output by the DC power supply module is not within the threshold range, the first control signal drives the DC power supply module to perform a charging operation, so that the output DC voltage signal returns to the threshold range.

[0029] Optionally, when the voltage value of the DC voltage signal drops to a set lower limit, the first control signal drives the DC energy supply module to start a charging operation to increase the voltage value of the output DC voltage signal.

[0030] When the voltage value of the DC voltage signal rises to a threshold range that is higher than the lower limit but lower than or equal to the rated value, the first control signal drives the DC energy supply module to end the current charging operation and stop adjusting the voltage value of the DC voltage signal.

[0031] Optionally, the second control signal is synchronized with the trigger signal in the time domain;

[0032] In a single pulse cycle of the second control signal, the voltage oscillation waveform of the trigger signal includes one or more charging times; each charging time corresponds to the time it takes for the voltage of the trigger signal to rise from a high-level trigger point to a voltage peak and then drop to the next adjacent low-level trigger point.

[0033] Each charging time corresponds to the time it takes for the DC power supply module to perform one charging operation.

[0034] Optionally, in a single pulse cycle of the second control signal, the voltage oscillation waveform of the trigger signal further includes a duration; during the duration, the first control signal provides an instruction to drive the DC power supply module to maintain the voltage value of the DC voltage signal at a rated value.

[0035] In the current pulse cycle of the second control signal, if the voltage oscillation waveform includes a charging time, the start of the sustaining time corresponds to the end time of this charging time; if the voltage oscillation waveform includes multiple charging times, the start of the sustaining time corresponds to the end time of the last charging time.

[0036] The end of the duration corresponds to the end time of the current pulse cycle of the second control signal.

[0037] Optionally, in the voltage waveform of the DC pulse signal, corresponding to a single pulse period of the second control signal, the voltage value of the DC pulse signal rises from the baseline value to the rated value when the second control signal has a rising edge;

[0038] When the second control signal is at a high level, the voltage value of the DC pulse signal is maintained within the threshold range, including: the voltage value of the DC pulse signal drops from the rated value to the lower limit value, and the voltage value rises from the lower limit value to the threshold range that is higher than the lower limit value and lower than or equal to the rated value.

[0039] When the second control signal has a falling edge, the voltage value of the DC pulse signal drops from the threshold range to the baseline value; when the second control signal is at a low level, the voltage value of the DC pulse signal remains at the baseline value.

[0040] The DC power supply module, driven by the first control signal, performs one or more charging operations to raise the voltage value of the DC pulse signal from the lower limit to a threshold range that is higher than the lower limit but lower than or equal to the rated value.

[0041] Optionally, the load terminal coupled to the DC pulse signal control system to receive the DC pulse signal includes a semiconductor processing device; when the voltage value of the DC pulse signal is maintained within a threshold range, it provides the semiconductor processing device with the required bias voltage.

[0042] Another technical solution of the present invention is to provide a semiconductor processing device, including a vacuum reaction chamber, which has a base inside to support a substrate; a process gas introduced into the reaction chamber is excited by radio frequency energy coupled into the reaction chamber to form plasma, which is used to process the substrate; any of the above-mentioned DC pulse signal control systems provides a DC pulse signal as a bias voltage to the bias electrode in the base.

[0043] Optionally, the semiconductor processing equipment is used to perform a high aspect ratio etching process.

[0044] Compared with the prior art, the semiconductor processing device and the DC pulse signal control system for providing bias voltage to it of the present invention have at least the following beneficial effects:

[0045] The embodiments of the present invention utilize the control characteristics of digital and analog signals to improve the voltage uniformity of DC bias in the working pulse envelope under high-voltage environments with complex process conditions and diverse sources of interference and noise. It can also precisely control the time characteristics such as pulse frequency and duty cycle, realizing a hybrid bias control scheme with strong anti-interference ability, high response stability, and strong adaptability. This improves the processing accuracy and reliability of semiconductor processes, and enhances product performance and manufacturing efficiency.

[0046] The embodiments of the present invention effectively decouple the various stages of signal time-domain synchronization through two independent signal processing paths and modular system design, enabling digital and analog signals to have flexible and adjustable characteristics at each stage, reducing mutual interference and noise transmission, and facilitating stable and accurate bias control to meet the requirements of different process conditions.

[0047] The embodiments of the present invention associate and map different process conditions and processing environments with a bias control strategy that is optimized for them. During the processing, the system status and environmental parameters monitored in real time are analyzed, and an appropriate bias control strategy is automatically selected to achieve dynamic adjustment of the signal generation and synchronization process, thereby improving the bias control accuracy and improving the process performance of semiconductor processing. Attached Figure Description

[0048] Figure 1 This is a schematic block diagram of the architecture of the DC pulse signal control system described in an embodiment of the present invention.

[0049] Figure 2 This is a schematic diagram of the composition structure of the DC pulse signal control system described in an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of a device configuration for the control signal generation module described in an embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of another device configuration for the control signal generation module described in an embodiment of the present invention.

[0052] Figure 5 These are waveform diagrams of the trigger signal and pulse digital signal described in three examples of embodiments of the present invention.

[0053] Figure 6 This is a waveform diagram of the DC voltage signal and the DC pulse signal under the control of the hybrid synchronization signal described in the embodiment of the present invention.

[0054] Figure 7 This is a schematic diagram of the semiconductor processing device described in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] like Figure 1As shown, an embodiment of the present invention provides a DC pulse signal control system 102, which is coupled to a power module 101 and a load terminal 103 via corresponding links 104. The DC pulse signal control system 102 can generate a high-voltage DC pulse signal based on the DC energy provided by the power module 101 and output it to the load terminal 103. The example load terminal 103 is a semiconductor processing device, such as a voltage coupling and reaction unit within the semiconductor processing device, which can receive the DC pulse signal output by the DC pulse signal control system 102 as a bias voltage required for semiconductor process processing.

[0057] like Figure 2 , Figure 3 As shown, in the DC pulse signal control system 102, DC energy is obtained from the power supply module 101 through the DC energy supply module 206 and a DC voltage signal is generated; a hybrid synchronization signal is provided by the control signal generation module to control the state of the DC voltage signal; the hybrid synchronization signal includes a first control signal and a second control signal that have a stable correlation in the time domain, wherein the first control signal is generated based on the AC analog signal 304, and the second control signal is generated based on the pulse digital signal 305.

[0058] The DC state control module 207, coupled to the control signal generation module and the DC power supply module 206 respectively, can control the operation of the DC power supply module 206 according to the first control signal in the mixed synchronization signal, so that when the DC power supply module 206 outputs a DC voltage signal, the voltage value can be maintained within a set threshold range, thereby improving the uniformity and stability of the output voltage. Another DC output control module 205, coupled to the control signal generation module and the DC power supply module 206 respectively, can modulate the DC voltage signal output by the DC power supply module 206, which is within the threshold range, according to the second control signal in the mixed synchronization signal, to obtain a DC pulse signal that meets the process requirements and provide it to the load terminal 103.

[0059] The example control signal generation module includes a master control module 201, which is based on a control chip and can control the operation of other modules in the system. The master control module 201 is equipped with a signal source that operates at an extremely high clock frequency, providing an AC analog signal 304 and a pulse digital signal 305 generated by the same source clock, which helps to reduce timing errors and provides a stable and accurate time reference for the subsequent generation of the first control signal and the second control signal.

[0060] In one branch of the control signal generation module, there is a buffer module 208 coupled to the main control module 201. This buffer module can provide a second control signal synchronized with the pulse digital signal 305, which reflects the state changes of the pulse digital signal 305. For example, the buffer module 208 uses a buffer, which is constructed using several logic gates or transistors. This enhances the signal driving capability without changing the logic state of the preceding and following signals. Therefore, the second control signal output by the buffer module 208 can remain synchronized with the input pulse digital signal 305.

[0061] In another branch of the control signal generation module, there is an auxiliary processing module 202 coupled to the main control module 201. This module receives the AC analog signal 304 output by the main control module 201 and processes it to ensure that the resulting trigger signal and pulse digital signal 305 have a stable correlation in the time domain. For example, the trigger signal and pulse digital signal 305 can be time-domain synchronized, perfectly aligned, or maintain a stable phase difference. The trigger module 203, coupled to the auxiliary processing module 202, further converts the trigger signal into a first control signal, ensuring that the first control signal, the synchronized pulse digital signal 305, and the second control signal are also time-domain synchronized.

[0062] The AC analog signal 304 output by the main control module 201, such as an AC signal in the form of a sine wave, triangle wave, or sawtooth wave, can be amplified, rectified, and have its signal parameters adjusted by the auxiliary processing module 202. This auxiliary processing module 202 can be implemented using analog and / or digital circuits. Figure 3 As shown, when the auxiliary processing module 202 uses analog circuits, it includes an amplification module 301, a rectification module 302, and a resonant module 303. Each of these modules contains several electronic components that can perform set functions. For example, the amplification module 301 has an operational amplifier to amplify the received AC analog signal 304; the rectification module 302 has a full-bridge or half-bridge topology to rectify the amplified signal; the resonant module 303 uses a combination of capacitors, resistors, inductors, etc., to form an LC resonant circuit or an RC filter circuit, etc., to adjust the amplitude, waveform, time delay, and other parameters of the rectified signal to obtain a trigger signal that matches the control strategy. In some examples, the electronic components in the amplification module 301, rectification module 302, and resonant module 303 have fixed values, and can directly process the AC analog signal 304 according to the set parameter configuration (the configuration can be changed by removing and installing electronic components with other values). In other examples, the electronic components in the amplification module 301, rectification module 302, and resonant module 303 are numerically adjustable variable components that can be adjusted according to the parameter requirements of the trigger signal under different process conditions.

[0063] like Figure 4 As shown, when the auxiliary processing module 202 uses digital circuits, it includes several controllable electrical modules. These controllable electrical modules are connected to the main control module 201 through the control bus 602, and receive instructions from the main control module 201 to adjust their respective electrical parameters. This allows for the corresponding processing of the AC analog signal 304 to obtain trigger signals that meet the requirements of different process conditions. Furthermore, during operation, the electrical parameters of one or more controllable electrical modules can be automatically adjusted as needed to improve the dynamic adjustment capability of the entire system. For example, a first controllable electrical module 604 is configured as an amplification module, which can adjust the gain and other parameters according to instructions to amplify the received AC analog signal 304 accordingly; a second controllable electrical module 603 is configured to construct different topologies of the rectifier module (full bridge or half bridge, etc.) or adjust the on / off time and other parameters of the equivalent switching devices in the topology according to instructions to rectify the amplified signal; a third controllable electrical module 601 is configured to construct a resonant module by equivalently using several capacitors, resistors, inductors and other components according to instructions, or adjust the values ​​of the equivalent components to change certain resonant characteristics to adjust the amplitude, waveform, time delay and other parameters of the rectified signal.

[0064] like Figures 2-4 As shown, the trigger module 203 is implemented, for example, by a Schmitt trigger or a comparator. The first control signal output by the trigger module 203 is synchronized in the time domain with the second control signal output by the buffer module 208 (the two are fully aligned or maintain a stable phase difference), and combined to form a mixed synchronization signal of the control signal generation module. The first control signal and the second control signal are applied to the DC energy supply module 206 via the corresponding DC state control module 207 and DC output control module 205, respectively, to control and adjust the state of the DC voltage signal.

[0065] In some examples, the first control signal output by the trigger module 203 is directly output to the DC state control module 207; in other examples, a first isolation protection module 204-1 coupled to the trigger module 203 and the DC state control module 207 can be set to receive the first control signal output by the trigger module 203 and transmit it to the DC state control module 207 without loss.

[0066] In some examples, the second control signal output by the buffer module 208 is directly output to the DC output control module 205; in other examples, a second isolation protection module 204-2, coupled to both the buffer module 208 and the DC output control module 205, can be set to receive the second control signal output by the buffer module 208 and transmit it to the DC output control module 205 without loss. The first isolation protection module 204-1 and the second isolation protection module 204-2 can be implemented, for example, through optocouplers, magnetically coupled digital isolators, or isolated serial communication transceivers, to avoid the first and second control signals from being affected by noise interference or voltage surges during their respective transmission.

[0067] The DC power supply module 206 includes energy storage devices (such as capacitors or batteries), and its input is coupled to the power module 101 via a corresponding link 104. It obtains and stores the high-voltage DC power provided by the power module 101, and with the assistance of the DC state control module 207 and the DC output control module 205, forms a stable bias output. The power module 101 provides the DC power required to generate DC pulse signals and can also power other modules in the system. For example, the power module 101 includes a power adapter that can convert external AC power into the DC power required by the system, or a DC-DC converter that can convert other DC voltage levels to the DC voltage level required by the system.

[0068] Under the action of the first control signal, the DC state control module 207 can control the charging state of the DC energy supply module 206. For example, when the voltage value of the DC voltage signal output by the DC energy supply module 206 is lower than the lower limit of the threshold range, the DC state control module 207 controls the DC energy supply module 206 to enter the charging state. Through one or more charging operations, the DC voltage signal is restored to the threshold range. The example DC state control module 207 is provided with a first switching device, coupled to the input terminal of the DC energy supply module 206, and can be turned on or off under the action of the first control signal. Thus, during each charging operation, the input terminal of the DC energy supply module 206 is connected to the power supply module 101, so that the DC energy supply module 206 receives high-voltage DC power to increase the energy storage voltage, thereby increasing the voltage value of the output DC voltage signal.

[0069] The DC output control module 205 is equipped with a second switching device coupled to the output terminal of the DC power supply module 206. This device can be turned on or off under the action of a second control signal. It modulates the DC voltage signal output by the DC power supply module 206, which is within a threshold range, into a DC pulse signal with a specific frequency and duty cycle, and provides it to the load terminal 103 as a bias voltage. For example, when the second switching device of the DC output control module 205 is turned on, the DC power supply module 206 is allowed to output a DC voltage signal within the threshold range; when the second switching device is turned off, the DC power supply module 206 stops outputting a DC voltage signal. Alternatively, the DC power supply module 206 can always output a DC voltage signal within a threshold range. When the second switching device of the DC output control module 205 is turned on, the link 104 between the DC power supply module 206 and the load terminal 103 is connected, allowing the load terminal 103 to obtain a DC voltage signal. When the second switching device is turned off, the link 104 is turned off, and the DC voltage signal output by the DC power supply module 206 is not provided to the load terminal 103. Instead, it can be transmitted to other devices inside or outside the system for processing or use, or recycled back to the DC power supply module 206 through a bypass circuit. The first and second switching devices may include, for example, electrically controlled switches such as transistors and relays, or switching components with hydraulic, pneumatic, or mechanical transmissions, or light-controlled components such as photoresistors, and are not limited to these.

[0070] The DC pulse signal control system 102 is equipped with several sensing modules 209, which can monitor the operating status of one or more of the modules mentioned above in the system, and can further monitor the operating status of the load terminal 103 or power supply module 101 coupled to the system. The sensing modules 209 send the monitoring data to the central control module 201 for analysis and processing, and the central control module 201 generates instructions to control the relevant modules in the system to realize feedback control.

[0071] For example, sensor module 209 detects the voltage value of the DC voltage signal output by DC power supply module 206, and main control module 201 determines whether the voltage value is within a threshold range based on the detection result. Alternatively, sensor module 209 detects the status of the switching devices of DC state control module 207 and DC output control module 205, and main control module 201 determines whether these switching devices have correctly executed the opening and closing actions according to the first control signal and the second control signal based on the detection result. Or, sensor module 209 monitors the key features of trigger signal and pulse digital signal 305 or the second control signal, respectively.

[0072] (For example, whether the voltage of the trigger signal reaches certain set values ​​and the time when the set values ​​are reached, or the rising and falling edges of the pulse digital signal 305 or the second control signal, etc.), the main control module 201 determines whether the time interval between the trigger signal and the key characteristics of the pulse digital signal 305 or the second control signal meets the expectation based on the detection results, and then determines whether the trigger signal and the pulse digital signal 305 or the second control signal are synchronized in the time domain. For example, the main control module 201 can adjust the instructions provided to the signal source to change the parameters when the signal source generates the AC analog signal 304 and / or the pulse digital signal 305; or, adjust the instructions provided to certain variable elements or controllable electrical modules in the auxiliary processing module 202 to change the electrical parameters of these devices, thereby adjusting the state of the trigger signal.

[0073] The links 104 between the DC pulse signal control system 102 and the power module 101 and the load terminal 103, as well as the links 104 between the various modules within the DC pulse signal control system 102, can have different physical forms depending on the type of energy and / or information transmitted, such as forming transmission paths based on at least one of electrical, mechanical, or optical principles. Devices such as electrical protection and signal isolation can also be provided on the links 104 as needed. For example, an electrical link coupling the DC pulse signal control system 102 to the power module 101 to receive DC power, or an electrical link transmitting DC pulse signals to the load terminal 103, can be implemented, for example, using a DC cable capable of withstanding high voltage (e.g., tens of thousands of volts). The links 104 used for transmitting information can be wired links, such as electrical connection lines between modules, traces on printed circuit boards, various data communication buses (e.g., I2C, SPI, CAN, RS-485, etc.), or links for various wireless communications such as WiFi and Bluetooth, or optical links using fiber optics, optocouplers, etc., and are not limited to these. The information transmitted includes, for example, instructions issued by the main control module 201, AC analog signals 304 and pulse digital signals 305, signals to be processed transmitted between various modules in the auxiliary processing module 202, trigger signals output by the auxiliary processing module 202, monitoring information collected by the sensing module 209, and so on.

[0074] The following further explains the hybrid synchronization signal described in the embodiments of the present invention and its effect on the DC power supply module 206. Figure 5 The waveform diagrams of the trigger signal output by the auxiliary processing module 202 and the pulse digital signal 305 output by the signal source are provided in three examples.

[0075] The trigger signal obtained after processing by the auxiliary processing module 202 is an AC signal with a voltage oscillation waveform. Figure 5In Example (a), when the voltage of the trigger signal 401a rises to a level higher than the high-level trigger point 405a set by the trigger module 203, the output of the first control signal is high (not shown in the figure), which serves as a start command to drive the DC energy supply module 206 to start a charging operation, enabling the DC energy supply module 206 to start adjusting the voltage value of the DC voltage signal (at this time, the first switching device of the DC state control module 207 is turned on, and the DC energy supply module 206 can obtain DC power from the power module 101 to increase the energy storage voltage, thereby increasing the voltage value of the DC voltage signal). When the voltage of the trigger signal 401a drops below the low-level trigger point 406a set by the trigger module 203, the output of the first control signal is low (not shown in the figure), which serves as a termination command to drive the DC energy supply module 206 to end the current charging operation. This causes the DC energy supply module 206 to stop adjusting the DC voltage signal value (at this time, the first switching device of the DC state control module 207 is turned off, and the DC energy supply module 206 stops acquiring additional DC power and instead outputs the DC voltage signal based on the existing energy storage).

[0076] Within one cycle of the trigger signal 401a (hereinafter referred to as the trigger cycle), the waveform of the trigger signal 401a includes the front, middle, and rear segments: the voltage of the front segment rises from the reference value 408a to the high-level trigger point 405a over a period of 403a; when the voltage reaches the high-level trigger point 405a, it enters the middle segment, and the voltage continues to rise above the high-level trigger point 405a to the peak value, and then falls back from the peak value to the low-level trigger point 406a. The time spent in this middle segment is the charging time 404a, and the DC energy supply module 206 will perform a charging operation once within the time corresponding to the charging time 404a; when the voltage reaches the low-level trigger point 406a, it enters the rear segment, and the voltage continues to drop from the low-level trigger point 406a to the valley value and then rises back to the reference value 408a; then the next trigger cycle of the trigger signal 401a begins, and the front, middle, and rear segments of the waveform of the trigger signal 401a are repeated.

[0077] The intersection of the trigger signal 401a waveform with the high-level trigger point 405a during the voltage rise process serves as the starting point of the charging time 404a, determining the start time of a charging operation. Conversely, the intersection of the trigger signal 401a waveform with the low-level trigger point 406a during the voltage fall process serves as the ending point of the charging time 404a, determining the end time of the charging operation. It can be understood that if the high-level trigger point value set by the trigger module 203 is lowered, or the trigger signal frequency is increased to shorten the trigger period, the intersection of the trigger signal waveform and the high-level trigger point will occur earlier, causing the charging time to start earlier. Conversely, if the high-level trigger point value is increased, or the trigger signal frequency is lowered to lengthen the trigger period, the intersection of the trigger signal waveform and the high-level trigger point will occur later, causing the charging time to start later. On the other hand, if the value of the low-level trigger point is increased or the trigger signal frequency is increased to shorten the trigger period, the intersection of the trigger signal waveform and the low-level trigger point will be brought forward, causing the charging time to end earlier; if the value of the low-level trigger point is decreased or the trigger signal frequency is decreased to lengthen the trigger period, the intersection of the trigger signal waveform and the low-level trigger point will be delayed, causing the charging time to end later.

[0078] The trigger signal 401a is synchronized with the pulse digital signal 305 in the time domain. For example... Figure 5 As shown in Example (a), in a single pulse cycle of the pulse digital signal 305, there is a propagation delay 402a between the rising edge of the pulse digital signal 305 and the moment when the voltage of the trigger signal 401a rises to the reference value 408a. Following the propagation delay 402a is a time 403a corresponding to the beginning of the waveform of the trigger signal 401a (the voltage rises from the reference value 408a to the high-level trigger point 405a). This reference value 408a is mainly used as one of the monitoring nodes when calculating the propagation delay 402a. Any value selected between the valley of the voltage of the trigger signal 401a and the high-level trigger point 405a can be used as the reference value 408a as needed. That is, when the rising edge of the pulse digital signal 305 is detected and the voltage of the trigger signal 401a rises to the reference value 408a, the time interval between the two can be analyzed to calculate the value of the propagation delay 402a, thereby determining whether the time interval meets the process requirements or whether the two signals are stably synchronized. The transmission delay 402a may be caused by the separate transmission of the digital signal 305 (pulse digital signal) and the AC signal 401a (AC analog signal 304 to trigger signal 401a), resulting in different physical structures of the two paths. Alternatively, it may be caused by the auxiliary processing module 202 performing delay processing on the trigger signal 401a according to the control strategy.

[0079] In an optional example, if there is remaining time between the end of the charging time 404a and the end of the current pulse cycle of the pulse digital signal 305 (i.e., the time remaining between the moment the voltage drops to the low-level trigger point 406a and the next rising edge of the pulse digital signal 305), then this remaining time is used as the sustain time 407a; the DC power supply module 206 will continue to output the DC voltage signal at the voltage value reached at the end of the charging time 404a during the corresponding sustain time 407a; for example, if the voltage value of the DC voltage signal has been adjusted to the rated value at the end of the charging time 404a, then the DC voltage signal will continue to be output at the rated value during the sustain time 407a.

[0080] Will Figure 5 Comparing the three examples, the first half-cycle time 306 and the second half-cycle time 307 of the pulse digital signal 305 remain unchanged in all three cases. Figure 5 Comparing examples (a) and (b), the waveforms of the trigger signal 401a are identical in the beginning, middle, and end segments; the physical structure of the transmission paths for each signal is the same, and the delay parameters are also the same, making the transmission delay 402a identical in both examples. The time 403a of the beginning segment of the waveform of the trigger signal 401a is also the same.

[0081] In a single pulse cycle of the pulse digital signal 305, the waveforms of the trigger signal 401a shown in examples (a) and (b) each include a charging time 404a and 404b. Compared with example (a), the high-level trigger point 405a in example (b) remains unchanged, while the low-level trigger point 406b is set to a value higher than that of the low-level trigger point 406a (but both are lower than the value of the high-level trigger point 405a). Therefore, the charging time 404b in example (b) will be shorter than the charging time 404a in example (a). The DC power supply module 206 will also perform a charging operation within the time corresponding to the charging time 404b, but the charging operation in example (b) ends earlier than the charging operation in example (a). In both examples, because the value of the high-level trigger point 405a remains unchanged, the start time of the charging time 404b does not change. Assuming all other conditions are the same, a charging operation performed with a shorter charging time will result in a smaller increase in the DC voltage signal by the DC power supply module 206 in Example (b) compared to Example (a).

[0082] Furthermore, since the charging time 404b is shorter and ends earlier, and the pulse period remains unchanged in both examples, the next rising edge time of the pulse digital signal 305 remains unchanged. Therefore, the sustaining time 407b in example (b) is longer than the sustaining time 407a in example (a). Assuming other conditions are the same, and the DC voltage signal fails to rise to the rated value at the end of the charging times 404a and 404b, the smaller rise of the DC voltage signal in example (b) will result in a lower voltage value output during its sustaining time 407b compared to the voltage value output during its sustaining time 407a in example (a).

[0083] Then Figure 5 Comparing examples (a) and (c), the high-level trigger point 405a and the low-level trigger point 406a remain unchanged, but the frequency of the trigger signal 401c in example (c) is higher, so that one pulse cycle of the pulse digital signal 305 corresponds to three trigger cycles of the trigger signal 401c. The transmission delay 402c shown in example (c) is different in duration from the transmission delay 402c in example (a). This may be due to differences in the physical structure of the signal transmission path from the main control module 201 to the auxiliary processing module 202 or within the auxiliary processing module 202 when trigger signals 401c and 401a are generated, or due to different delay parameters set by the auxiliary processing module 202 for trigger signals 401c and 401a. Specifically in example (c), among the three trigger cycles corresponding to a single pulse cycle of the pulse digital signal 305, the moment when the voltage of the trigger signal 401c rises to the reference value 408a in the first trigger cycle is closest to the rising edge of the current pulse cycle of the pulse digital signal 305, and the time between the two is taken as the transmission delay 402c.

[0084] The higher frequency of the trigger signal 401c in Example (c) makes the waveform of the trigger signal 401c voltage rising from the reference value 408a to the high-level trigger point 405a steeper, and the waveform duration 403c is shorter than that of Example (a).

[0085] In Example (c), one pulse cycle of the pulse digital signal 305 corresponds to three trigger cycles of the trigger signal 401c. Each trigger cycle has a charging time 404c. Therefore, within one pulse cycle of the pulse digital signal 305, the trigger signal 401c will have three charging times 404c. The DC power supply module 206 performs a charging operation once within the time corresponding to each charging time 404c. Each charging time 404c in Example (c) is shorter than the charging times 404a and 404b in Examples (a) and (b). If other conditions are the same, the increase in DC voltage signal when performing one charging operation in Example (c) is the smallest.

[0086] It can be understood that by adjusting the frequency of the pulse digital signal 305 and / or the trigger signal, one pulse cycle of the pulse digital signal 305 can correspond to m trigger cycles of the trigger signal (m is an integer greater than or equal to 1). Thus, the trigger signal will have m charging times in one pulse cycle, so that the DC energy supply module 206 can perform m charging operations within the time corresponding to one pulse cycle.

[0087] In Example (c), within the current pulse cycle of the pulse digital signal 305, the start of the sustain time 407c is the end time of the last charging time 404c corresponding to that pulse cycle, and the end time of the sustain time 407c is the end time of that pulse cycle. That is, in the third trigger cycle corresponding to a single pulse cycle, the remaining time between the moment the trigger signal 401c voltage drops to the low-level trigger point 406a and the rising edge of the next pulse cycle of the pulse digital signal 305 is used as the sustain time 407c. During the sustain time 407c, the DC power supply module 206 continues to output the DC voltage signal at the end of the third charging time 404c (e.g., the rated value). Within the first two trigger cycles corresponding to that pulse cycle, during the later part of the waveform after each charging time 404c, the DC power supply module 206 can continue to output based on the voltage value reached by the DC voltage signal at the end of that charging time 404c.

[0088] The following describes the control effect of the hybrid synchronization signal on the DC voltage signal and the DC pulse signal according to the embodiments of the present invention. (See also...) Figure 5 , Figure 6 As shown, Figure 6 The waveform diagram (bb) is an example of how the DC state control module 207 maintains the DC voltage signal 702 output by the DC energy supply module 206 within the threshold range under the action of the first control signal obtained by synchronous conversion of the trigger signal; Figure 6 The waveform diagram (aa) is the DC pulse signal 701 output to the load terminal 103 after the DC output control module 205 modulates the DC voltage signal 702 shown in the waveform diagram (bb) under the action of the second control signal obtained by synchronous conversion of the pulse digital signal 305.

[0089] In this circuit, one cycle of the DC pulse signal 701 corresponds to one pulse cycle of the pulse digital signal 305. The upper and lower edges of the DC pulse signal 701 are determined by the first half-cycle time 306 and the second half-cycle time 307 of the pulse digital signal 305. During the first half-cycle time 306, the DC pulse signal 701 and the DC voltage signal 702 are in the same state and are output at a voltage within the threshold range. During the second half-cycle time 307, the voltage of the DC pulse signal 701 is output at a set baseline value 501, while the voltage of the DC voltage signal 702 remains within the threshold range.

[0090] See first Figure 6 As shown in the waveform diagram (bb), within one pulse cycle, when the rising edge of the pulse digital signal 305 occurs, the DC voltage signal 702 begins to output at its rated value 504. As the semiconductor processing progresses, the voltage of the DC voltage signal 702 gradually decreases due to external influences. After processing time 502, the voltage of the DC voltage signal 702 decreases to the lower limit 505 of the threshold range. At this time, under the action of the first control signal triggering the signal conversion on the DC state control module 207, the DC energy supply module 206 enters the charging state and begins to perform the charging operation.

[0091] During the charging period 404 of the DC power supply module 206, the voltage of the DC voltage signal 702 increases from the lower limit 505 to the rated value 504. This can be as follows: Figure 5 As shown in Example (a) or (b), a charging time 404a or 404b corresponding to one pulse cycle is taken as the charging state duration 404, and a charging operation is performed within this time 404 to restore the DC voltage signal 702 to the rated value 504; or as shown in Example (a) or (b), the charging time 404a or 404b is taken as the charging state duration 404, and a charging operation is performed within this time 404 to restore the DC voltage signal 702 to the rated value 504; or as shown in Example (b) or (c) Figure 5 As shown in Example (c), one pulse cycle corresponds to three charging times 404c of the trigger signal 401c. The time from the start of the first charging time 404c to the end of the third charging time 404c is taken as the charging state duration 404. Through multiple charging operations performed within this time 404 (each charging time 404c corresponds to the start and end of one charging operation), the voltage of the DC voltage signal 702 is restored to the rated value 504.

[0092] After the charging state lasts for 404 hours, the voltage of the DC voltage signal 702 has returned to its rated value 504. Therefore, during the subsequent duration 507, the DC voltage signal 702 will continue to output at its rated value 504 until the next pulse cycle begins. If only one charging operation is performed within one pulse cycle, the duration 507 of the DC voltage signal 702 corresponds to... Figure 5The duration 407a or 407b is shown in example (a) or (b); if multiple charging operations are performed within one pulse cycle, the duration 507 of the DC voltage signal 702 corresponds to Figure 5 The duration 407c shown in Example (c) is the time between the end of the last charging operation in the current pulse cycle and the rising edge of the next pulse cycle of the pulse digital signal 305.

[0093] Comparison Figure 6 The waveforms of the DC pulse signal 701 and the DC voltage signal 702 are visible. These two signals are completely identical in the first half of the cycle 306, both including an attenuation segment 703 where the voltage drops from the rated value 504 to the lower limit value 505, and a first recovery segment 704 where the voltage rises from the lower limit value 505 back to the threshold range. The voltage in the first recovery segment 704 is higher than the lower limit value 505 but lower than or equal to the rated value 504. When the first half of the cycle 306 ends and the pulse digital signal 305 shows a falling edge, the DC pulse signal 701, after the first recovery segment 704, drops directly from the threshold range to the baseline value 501. In the second half of the cycle 307, the voltage of the DC pulse signal 701 remains at the baseline value 501 until the rising edge of the next pulse digital signal 305 arrives, entering the attenuation segment 703 of the next pulse cycle, causing the DC pulse signal 701 to start outputting again at the rated value 405.

[0094] During the charging period 404 of the DC power supply module 206, the DC voltage signal 702 successively experiences a first recovery phase 704 and a second recovery phase 705. In the first recovery phase 704, the voltage of the DC voltage signal 702 recovers from the lower limit 505 to the threshold range, and must be at least higher than the lower limit 505. In the second recovery phase 705, the voltage of the DC voltage signal 702 continues to rise within the threshold range until it reaches the rated value 504. That is, the start time of the first recovery phase 704 corresponds to the start time of the charging period 404; the end time of the first recovery phase 704 is determined by the falling edge of the pulse digital signal 305, and also corresponds to the start time of the second recovery phase 705; the end time of the second recovery phase 705 corresponds to the end time of the charging period 404.

[0095] If the DC power supply module 206 performs only one charging operation within time 404, then the start time of the first recovery segment 704 is the start time of this charging operation, and the end time of the second recovery segment 705 is the end time of this charging operation; according to Figure 5In the middle segment of the waveform of the trigger signal 401a shown in Example (a) or (b), the trigger module 203 generates a high-level component of the first control signal. The duration of this high-level component corresponds to the charging time 404a or 404b of the trigger signal 401a (also corresponding to...). Figure 6 During the charging state (404), when the DC state control module 207 acts on the DC energy supply module 206, the voltage of the DC voltage signal 702 completes the adjustment process from the beginning of the first recovery stage 704 to the end of the second recovery stage 705 (i.e., from the lower limit value 505 back to the rated value 504).

[0096] After the charging time 404a or 404b (i.e., the duration of the charging state 404) ends, according to the trigger signal 401a between the end of the waveform of the current trigger cycle and the beginning of the waveform of the next trigger cycle, the state of the first control signal generated by the trigger module 203 is flipped, and the low-level component of the first control signal is output. During the duration of the low-level component, if the current pulse cycle has not ended when this charging operation ends (i.e., the second recovery segment 705 ends), a maintenance segment 706 will be entered, so that the DC voltage signal 702 continues to output voltage within the maintenance segment 706 corresponding to the maintenance time 507, at the rated value 504 reached at the end of the second recovery segment 705, until the next pulse cycle starts, and the DC voltage signal 702 enters the voltage decay segment 703, and waits for the charging time 404a or 404b of the trigger signal 401a in the next pulse cycle to arrive before flipping the state of the first control signal again and outputting the high-level component of the first control signal to perform a new charging operation.

[0097] If the DC power supply module 206 performs multiple charging operations within time 404, the start time of the first recovery segment 704 is the start time of the first charging operation in the current pulse cycle, and the end time of the second recovery segment 705 is the end time of the last charging operation in the current pulse cycle; according to Figure 5As shown in Example (c), within the three trigger cycles corresponding to the current pulse cycle, the trigger signal 401c generates a high-level component of the first control signal through the trigger module 203 in the middle segment of the waveform within each trigger cycle. The duration of one high-level component corresponds to a charging time 404c. When the DC state control module 207 acts on the DC energy supply module 206, a charging operation is performed. Depending on the frequency of the trigger signal, in different examples, after one or more charging operations, the voltage of the DC voltage signal 702 may complete the adjustment process of the first recovery stage 704 (returning from the lower limit 505 to the threshold range, at least higher than the lower limit 505). After one or more charging operations, the voltage of the DC voltage signal 702 continues to complete the adjustment process of the second recovery stage 704 (the voltage continues to rise to the rated value 405).

[0098] After the charging time 404c ends in each trigger cycle, the first control signal generated by the trigger module 203 is flipped according to the trigger signal 401c between the end of the waveform of the current trigger cycle and the beginning of the waveform of the next trigger cycle, and the output of the low-level component of the first control signal is changed. During the duration of each low-level component, the output can continue based on the voltage value reached by the DC voltage signal 702 under the most recent high-level component. At this time, the DC power supply module 206 will not receive additional DC power replenishment, but will output the DC voltage signal 702 through the existing energy storage. The voltage value may be slightly attenuated. However, since the frequency of the trigger signal 401c is high and the interval between two adjacent charging operations is very short, even if the voltage value is attenuated in the low-level component, it can still be maintained within the threshold range of the lower limit 505 to the rated value 504. If the last charging operation corresponding to the current pulse cycle ends (i.e., the second recovery segment 705 ends) but the pulse cycle has not yet ended, a sustaining segment 706 will be entered, so that the DC voltage signal 702 continues to output voltage within the sustaining segment 706 corresponding to the sustaining time 507, at the rated value 504 reached at the end of the second recovery segment 705, until the next pulse cycle starts, and enters the attenuation segment 703 of the DC voltage signal 702. Then, when the charging time 404c of the trigger signal 401c in the first trigger cycle of the next pulse cycle arrives, the state of the first control signal will be flipped, and the high-level component of the first control signal will be output again to perform a new charging operation.

[0099] In summary, during one pulse cycle, in the processing time 502, the first control signal generated by the trigger signal is a low-level component. The DC voltage signal 702, based on the existing energy storage output of the DC energy supply module 206, is initially at the rated value 504. The energy storage potential gradually decays under external influences, causing the voltage of the output DC voltage signal 702 to gradually decrease. When the voltage of the DC voltage signal 702 is detected to drop to the lower limit 505, the trigger signal enters the middle segment of the waveform, causing the first control signal to become a high-level component. This drives the DC energy supply module 206 to gradually restore the energy storage potential to the rated value 504 within the charging state duration 404 through one or more charging operations. This allows the DC voltage signal 702 to output a voltage higher than the lower limit 505 and lower than or equal to the rated value 504 within the time 404. If only one charging operation is performed during time 404, the first control signal remains at a high level during time 404 and switches to a low level at the end of time 404. If multiple charging operations are performed during time 404, the first control signal switches between high and low levels multiple times and remains at a low level at the end of time 404. During the subsequent sustaining time 507, the DC voltage signal 702 continues to output voltage at the rated value 504 reached at the end of time 404 until the next pulse cycle begins. Therefore, under the action of the first control signal, the energy storage potential of the DC energy supply module 206 can be boosted when it is too low, keeping the output DC voltage signal 702 within the threshold range.

[0100] The second control signal, synchronously converted from the pulse digital signal 305, modulates the DC voltage signal 702 by determining the required frequency and duty cycle of the pulse bias according to the semiconductor process requirements. This is equivalent to extracting the required waveform portion from the already adjusted DC voltage signal 702 waveform, which is within the threshold range. Specifically, the first half-cycle time 306 of the pulse digital signal 305 controls the waveform portion to be extracted (including the attenuation segment 703 where the voltage drops from the rated value 504 to the lower limit value 505, and the first recovery segment 704 where the charging operation has been initiated to allow the voltage to rise back from the lower limit value 505 to the threshold range). The falling edge of the pulse digital signal 305 needs to be within the recovery time 503 of the DC voltage signal 702. This recovery time 503 corresponds to the time during which the DC voltage signal 702 exceeds the lower limit value 505, gradually recovers to the rated value 504, and remains at the rated value 504. That is, the high-level component of the DC pulse signal 701 is formed by the DC voltage signal 702 corresponding to the first half-cycle time 306 of the pulse digital signal 305, and the voltage is switched to the set baseline value 501 during the second half-cycle time 307 of the pulse digital signal 305 to form the low-level component of the DC pulse signal 701. The DC pulse signal 701 is then output to the load terminal 103 as a bias voltage.

[0101] like Figure 7 As shown in the figure, the semiconductor processing equipment of this embodiment includes a vacuum-ejectable reaction chamber 10, which has a generally cylindrical metal cavity. The cavity sidewall has an opening (not shown) for a robotic arm to carry a substrate w into and out of the reaction chamber 10. A base 20 with an electrostatic chuck is provided inside the reaction chamber 10 to support the substrate w. Source radio frequency power (frequency range, for example, 100kHz-200MHz) provided by a radio frequency source 30 is coupled into the reaction chamber 10, exciting the injected process gas to form plasma. The plasma contains a large number of active particles such as electrons, ions, excited atoms, molecules, and free radicals. These active particles can undergo various physical and chemical reactions with the surface of the substrate w, changing the morphology of the substrate w surface and completing processes such as etching. A vacuum pump 50, connected to the reaction chamber 10, can discharge the remaining gas and reaction byproducts after processing from the reaction chamber 10, maintaining a vacuum environment within the chamber.

[0102] The semiconductor processing equipment includes, for example, a capacitively coupled plasma reactor, an inductively coupled plasma reactor, an electron cyclotron resonance plasma reactor, a long-range plasma reactor, and a plasma edge etching apparatus, but is not limited thereto. Figure 7 Taking the capacitively coupled plasma reactor shown as an example, a gas spray head 60, which introduces process gas into the reaction chamber 10, is used as the upper electrode and is positioned opposite to the base 20, which is used as the lower electrode. A radio frequency source 30 is connected to the upper electrode and / or the lower electrode to apply source radio frequency power, thereby generating a radio frequency electric field between the upper electrode and the lower electrode, which dissociates the process gas in the chamber into plasma.

[0103] The DC pulse signal control system 102 described in this embodiment of the invention can generate a high-voltage DC pulse signal and apply it to the bias electrode in the base 20 to form a bias voltage in the reaction chamber 10 to control the acceleration process when charged particles in the plasma bombard the substrate w. In this system, the pulse digital signal has the characteristics of precise timing control and rapid switching response, while the trigger signal has smooth response characteristics and flexible parameter adjustment capability. A stable time-domain correlation is established between the two, and the control signals (first control signal and second control signal) of their respective synchronization conversion are used to form a hybrid synchronization signal, which can meet the requirements of semiconductor processing equipment for different working conditions such as noise immunity, response speed, and spatial distribution, and achieve stable and accurate bias voltage control.

[0104] For example, when semiconductor processing equipment is used in high aspect ratio etching processes, it is necessary to form micro- and nano-structures on the substrate w with an etching depth much greater than the etching width. The DC pulse signal control system 102 equipped for the semiconductor processing equipment can generate DC pulse signals with high amplitude (such as voltages reaching thousands or even tens of thousands of volts) and short period (period in the microsecond or nanosecond range), and maintain the high-level component of the DC pulse signal within a set threshold range. This provides a bias voltage with better uniformity and stability for the high aspect ratio etching process, thereby improving etching uniformity and selectivity, and ensuring that the contour, size, morphology and other characteristics of the micro- and nano-structures meet the expected design, thus realizing high-quality microelectronic device manufacturing.

[0105] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A DC pulse signal control system, characterized in that, Include: DC power supply module, used to provide DC voltage signal; The control signal generation module is used to generate a first control signal based on an AC analog signal, generate a second control signal based on a pulse digital signal, and provide a mixed synchronization signal containing the first control signal and the second control signal. A DC state control module, coupled to the control signal generation module and the DC energy supply module respectively, is used to control the charging state of the DC energy supply module according to the first control signal in the hybrid synchronization signal, so that the DC voltage signal output by the DC energy supply module is within the threshold range. The DC output control module is coupled to the control signal generation module and the DC energy supply module respectively, and is used to modulate the DC voltage signal output by the DC energy supply module according to the second control signal in the hybrid synchronization signal to obtain a DC pulse signal.

2. The DC pulse signal control system as described in claim 1, characterized in that, The control signal generation module further includes a central control module; The master control module is equipped with a signal source to provide pulse digital signals and AC analog signals generated by the same source clock.

3. The DC pulse signal control system as described in claim 2, characterized in that, The control signal generation module further includes: An auxiliary processing module, coupled to the main control module, is used to process AC analog signals to obtain trigger signals. The trigger module, coupled to the auxiliary processing module, is used to convert the trigger signal into a first control signal; The trigger signal has a voltage oscillation waveform; when the voltage in the trigger signal rises above the high-level trigger point set by the trigger module, the first control signal outputs a high level, which serves as a start command to drive the DC energy supply module to start charging operation, causing the DC energy supply module to start adjusting the voltage value of the DC voltage signal. When the voltage of the trigger signal drops below the low-level trigger point set by the trigger module, the first control signal outputs a low level, serving as a termination command to drive the DC energy supply module to end the charging operation, thereby causing the DC energy supply module to stop adjusting the voltage value of the DC voltage signal.

4. The DC pulse signal control system as described in claim 3, characterized in that, The control signal generation module further includes a first isolation protection module; The first isolation protection module is coupled to the trigger module and the DC state control module respectively, and is used to transmit the first control signal to the DC state control module without loss.

5. The DC pulse signal control system as described in claim 3, characterized in that, The auxiliary processing module is used to amplify, rectify, and adjust the signal parameters of the AC analog signal; the adjustable signal parameters include at least one of the following: amplitude, waveform, and time delay; The auxiliary processing module is implemented through analog circuits and / or digital circuits; the analog circuits contain several electronic components capable of performing set functions; the digital circuits contain several controllable electrical modules connected to the main control module via a control bus, receiving instructions to adjust their respective electrical parameters to perform corresponding adjustment operations.

6. The DC pulse signal control system as described in claim 3, characterized in that, The control signal generation module further includes: A buffer module, coupled to the main control module, is used to provide a second control signal synchronized with the pulse digital signal. The second control signal reflects the state changes of the pulse digital signal. The second control signal is synchronized in the time domain with the first control signal output by the trigger module. The second isolation protection module is coupled to the buffer module and the DC output control module respectively, and is used to transmit the second control signal to the DC output control module without loss.

7. The DC pulse signal control system according to any one of claims 2-6, characterized in that, The DC pulse signal control system includes a sensing module for monitoring the operating status of one or more other modules within the system, load terminals that receive DC pulse signals from the system, or power supply modules that provide DC energy to the system. The sensing module feeds back the monitoring data to the central control module for analysis and processing, and the central control module generates instructions to control the relevant modules within the system.

8. The DC pulse signal control system as described in claim 7, characterized in that, The DC power supply module is coupled to the power module to obtain DC power provided by the power module. Links for transmitting energy and / or information are provided between the DC energy supply module and the power supply module, between the modules of the DC pulse signal control system, and between the system and the load terminal receiving the DC pulse signal; the links include transmission paths based on at least one of electrical, mechanical, and optical methods.

9. The DC pulse signal control system according to any one of claims 3-6, characterized in that, When the DC voltage signal output by the DC power supply module is not within the threshold range, the first control signal drives the DC power supply module to perform a charging operation, so that the output DC voltage signal returns to the threshold range.

10. The DC pulse signal control system as described in claim 9, characterized in that, When the voltage value of the DC voltage signal drops to the set lower limit, the first control signal drives the DC energy supply module to start a charging operation to increase the voltage value of the output DC voltage signal. When the voltage value of the DC voltage signal rises to a threshold range that is higher than the lower limit but lower than or equal to the rated value, the first control signal drives the DC energy supply module to end the current charging operation and stop adjusting the voltage value of the DC voltage signal.

11. The DC pulse signal control system as described in claim 10, characterized in that, The second control signal is synchronized with the trigger signal in the time domain; In a single pulse cycle of the second control signal, the voltage oscillation waveform of the trigger signal includes one or more charging times; each charging time corresponds to the time it takes for the voltage of the trigger signal to rise from a high-level trigger point to a voltage peak and then drop to the next adjacent low-level trigger point. Each charging time corresponds to the time it takes for the DC power supply module to perform one charging operation.

12. The DC pulse signal control system as described in claim 11, characterized in that, In a single pulse cycle of the second control signal, the voltage oscillation waveform of the trigger signal also includes a duration; during the duration, the first control signal provides an instruction to drive the DC power supply module to maintain the voltage value of the DC voltage signal at a rated value. In the current pulse cycle of the second control signal, if the voltage oscillation waveform includes a charging time, the start of the sustaining time corresponds to the end time of this charging time; if the voltage oscillation waveform includes multiple charging times, the start of the sustaining time corresponds to the end time of the last charging time. The end of the duration corresponds to the end time of the current pulse cycle of the second control signal.

13. The DC pulse signal control system as described in claim 12, characterized in that, In the voltage waveform of the DC pulse signal, corresponding to a single pulse period of the second control signal, when the rising edge of the second control signal occurs, the voltage value of the DC pulse signal rises from the baseline value to the rated value. When the second control signal is at a high level, the voltage value of the DC pulse signal is maintained within the threshold range, including: the voltage value of the DC pulse signal drops from the rated value to the lower limit value, and the voltage value rises from the lower limit value to the threshold range that is higher than the lower limit value and lower than or equal to the rated value. When the second control signal has a falling edge, the voltage value of the DC pulse signal drops from the threshold range to the baseline value; when the second control signal is at a low level, the voltage value of the DC pulse signal remains at the baseline value. The DC power supply module, driven by the first control signal, performs one or more charging operations to raise the voltage value of the DC pulse signal from the lower limit to a threshold range that is higher than the lower limit but lower than or equal to the rated value.

14. The DC pulse signal control system as described in claim 13, characterized in that, A load terminal coupled to the DC pulse signal control system to receive a DC pulse signal includes a semiconductor processing device; when the voltage value of the DC pulse signal is maintained within a threshold range, it provides the semiconductor processing device with the required bias voltage.

15. A semiconductor processing apparatus comprising a vacuum reaction chamber, wherein a base is provided inside to support a substrate; a process gas introduced into the reaction chamber is excited by radio frequency energy coupled into the reaction chamber to form plasma for processing the substrate; characterized in that, The DC pulse signal control system according to any one of claims 1-14 provides a DC pulse signal as a bias voltage to the bias electrode in the base.

16. The semiconductor processing apparatus as claimed in claim 15, characterized in that, The semiconductor processing equipment is used to perform high aspect ratio etching processes.

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