Chip, data transmission method, device and medium

Abstract

This disclosure provides a chip, a data transmission method, an apparatus, and a medium, relating to the field of chip technology. The chip includes a processor, a routing component corresponding to the processor, and a cross-chip transmission component. The routing component is connected to both the processor and the cross-chip transmission component. The routing component receives first transmission data sent by the processor and forwards the first transmission data to the cross-chip transmission component. The cross-chip transmission component sends the first transmission data to a target chip, which then forwards the first transmission data to its processor. The cross-chip transmission component also receives second transmission data sent by the target chip and forwards the second transmission data to the routing component. The routing component further forwards the second transmission data to the chip's processor. Thus, secure and efficient data transmission between multiple CPUs is achieved between different FPGA boards.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a chip, a data transmission method, a device, and a medium. Background Technology

[0002] Field-Programmable Gate Arrays (FPGAs) are widely used in communications, data processing, industrial control, aerospace, and other fields. As application demands become increasingly complex and diverse, the resources of a single FPGA chip are insufficient to meet the performance requirements of large-scale systems. Therefore, in practical engineering, multiple FPGA boards are typically required to work together to extend the processing performance of large-scale systems.

[0003] Meanwhile, to handle complex computing tasks, existing circuit systems often include multiple Central Processing Units (CPUs). These CPUs perform different computing tasks and play a crucial role in the operation of the entire system. However, due to the limited resources of a single FPGA board, it is often necessary to deploy these multiple CPUs on different FPGA boards.

[0004] In this architecture, frequent data interaction is required between different CPUs. Therefore, how to securely and efficiently realize data transmission between multiple CPUs between different FPGA boards is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This disclosure provides a chip, a data transmission method, an apparatus, and a medium to at least solve the above-mentioned technical problems existing in the prior art.

[0006] In a first aspect, embodiments of this disclosure provide a chip, including: The processor, the corresponding routing component, and the cross-chip transmission component are connected to the processor and the cross-chip transmission component, respectively. A routing component is used to receive the first transmission data sent by the processor and forward the first transmission data to the cross-chip transmission component; A cross-chip transmission component is used to send first transmission data to a target chip for the target chip to forward the first transmission data to the target chip's processor; The cross-chip transmission component is also used to receive the second transmission data sent by the target chip and forward the second transmission data to the routing component; The routing component is also used to forward the second transmission data to the chip's processor.

[0007] In a second aspect, embodiments of this disclosure provide a data transmission method applied to a first chip, the first chip including a first processor, a routing component corresponding to the first processor, and a cross-chip transmission component, the device including: The routing component obtains the first transmission data sent by the first processor and forwards the first transmission data to the cross-chip transmission component. First transmission data is sent to the second chip via a cross-chip transmission component, for the second chip to forward the first transmission data to the second processor of the second chip; The second transmission data sent by the second chip is received by the cross-chip transmission component, and the second transmission data is forwarded to the routing component. The second transmission data is forwarded to the first processor via the routing component; Both the first chip and the second chip are chips provided by the first party.

[0008] Thirdly, embodiments of this disclosure provide an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the data transmission method of the second aspect.

[0009] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the data transmission method of the second aspect.

[0010] Based on the chip provided in this embodiment, the chip internally deploys a processor, a routing component corresponding to the processor, and a cross-chip transmission component. The routing component is connected to both the processor and the cross-chip transmission component. Based on this structure, the routing component can receive first transmission data sent by the processor and forward the first transmission data to the cross-chip transmission component. Then, the cross-chip transmission component can send the first transmission data to a target chip, so that the target chip can forward the first transmission data to the processor deployed within the target chip. Based on this, the cross-chip transmission component can also receive second transmission data returned by the target chip based on the first transmission data and forward the second transmission data to the routing component. Then, the routing component forwards the second transmission data to the processor of the chip. Thus, by deploying an interconnected processor, routing component, and cross-chip transmission component internally, the cross-chip transmission component can acquire the first transmission data sent by the processor and send it to the target chip, while simultaneously receiving the second transmission data returned by the target chip and sending it back to the processor, thereby realizing data transmission between CPUs of different FPGA chips and effectively achieving inter-chip data transmission.

[0011] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0012] Figure 1 This is one of the schematic diagrams of a chip structure provided in this embodiment of the disclosure; Figure 2 This is an example diagram of inter-chip data transmission provided in an embodiment of this disclosure; Figure 3 This is a second schematic diagram of the structure of a chip provided in this embodiment of the present disclosure; Figure 4 This is a schematic flowchart of a data transmission method provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0013] To make the objectives, features, and advantages of this disclosure more apparent and understandable, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0014] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0016] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0017] As mentioned in the background section, in large-scale FPGA projects, when faced with the need for multiple CPUs, the limited resources of a single FPGA board often prevent the integration of all CPUs onto a single FPGA board, necessitating the allocation of multiple CPUs across different FPGA boards. Since frequent data exchange is required between different CPUs, ensuring secure and efficient data transmission between multiple CPUs across different FPGA boards is a pressing issue that needs to be addressed in this architecture.

[0018] In addition, data transmission between CPUs on multiple FPGA boards may be affected by interference (such as electromagnetic interference) or malicious tampering, which may cause changes to the transmitted data. The transmitted data may contain sensitive information or key instructions. Once the data is stolen, tampered with or leaked during the transmission process, it will pose a serious threat to the security of the system and may even lead to serious consequences.

[0019] Based on this, the present disclosure provides a chip to at least solve the technical problems existing in the prior art. The chip provided by the present disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Figure 1 This is one of the schematic diagrams of a chip structure provided in this embodiment.

[0021] like Figure 1 As shown, the chip 100 may include a processor 10, a routing component 20 corresponding to the processor 10, and a cross-chip transmission component 30. The routing component 20 is connected to the processor 10 and the cross-chip transmission component 30 respectively, without being specifically limited here.

[0022] The chip and the target chip can be the same or different; for example, both can be FPGA chips, and no specific limitation is made here. Furthermore, the processor deployed in the chip and the processor deployed in the target chip can be the same or different; for example, both can be CPUs, and no specific limitation is made here.

[0023] It should be noted that the number of processors 10 can be at least one, and correspondingly, the number of routing components 20 corresponding to processors 10 can also be at least one. That is, in this embodiment of the disclosure, one processor 10 corresponds to one routing component 20, and no specific limitation is made here.

[0024] Based on this, the routing component 20 is used to receive the first transmission data sent by the processor 10 and forward the first transmission data to the cross-chip transmission component 30; The cross-chip transmission component 30 is used to send first transmission data to the target chip for the target chip to forward the first transmission data to the processor of the target chip; The cross-chip transmission component 30 is also used to receive the second transmission data sent by the target chip and forward the second transmission data to the routing component 20.

[0025] The routing component 20 is also used to forward the second transmission data to the processor 10 of the chip 100.

[0026] It should be noted that the first and second transmitted data refer to the data transmitted between the processor 10 of chip 100 and the processor of the target chip. The first transmitted data may be data carried in a request sent by the processor 10 of chip 100 to the processor of the target chip (i.e., request data), or data carried in a response sent by the processor 10 of chip 100 to the processor of the target chip (i.e., response data). Correspondingly, the second transmitted data may be data carried in a request sent by the processor of the target chip to the processor 10 of chip 100, or data carried in a response sent by the processor of the target chip to the processor 10 of chip 100. The only difference between the two is the direction of transmission, which is not specifically limited here.

[0027] Furthermore, the aforementioned request data may include read request data or write request data for a specific address, or it may include other types of request data, which are not specifically limited in this disclosure. The aforementioned response data may be normal response data (e.g., valid data returned when the request is successful) and error response data (e.g., error codes or exception information returned when the request fails), which are not specifically limited here.

[0028] It is conceivable that when the processor 10 sends the first transmission data to the routing component 20, the routing component 20 can receive the first transmission data sent by the processor 10 and forward the first transmission data to the cross-chip transmission component 30. Then, after receiving the first transmission data forwarded by the routing component 20, the cross-chip transmission component 30 can send the first transmission data to the target chip for the target chip to forward the first transmission data to its processor.

[0029] Based on this, the cross-chip transmission component 30 can also receive the second transmission data sent by the target chip based on the first transmission data, and forward the second transmission data to the routing component 20. Then, the routing component 20 can forward the second transmission data to the processor 10 of the chip 100.

[0030] It should be noted that, based on the chip provided in this embodiment, processors of different chips can achieve data transmission. For example... Figure 2As shown, this example includes four chips, denoted as chip 201, chip 202, chip 203, and chip 204. Taking chip 201 as an example, chip 201 can perform inter-processor data transmission with any one of the chips 202, 203, and 204. That is, the processor of chip 201 can send first transmission data to the processors of chip 202, chip 203, or chip 204, and receive second transmission data from these chip processors.

[0031] Based on the chip provided in this embodiment, the chip internally deploys a processor, a routing component corresponding to the processor, and a cross-chip transmission component. The routing component is connected to both the processor and the cross-chip transmission component. Based on this structure, the routing component can receive first transmission data sent by the processor and forward the first transmission data to the cross-chip transmission component. The cross-chip transmission component then sends the first transmission data to a target chip, which forwards the first transmission data to the processor deployed within the target chip. Furthermore, the cross-chip transmission component can also receive second transmission data returned by the target chip based on the first transmission data and forward the second transmission data to the routing component. The routing component then forwards the second transmission data to the processor of the chip. Thus, by deploying interconnected processors, routing components, and cross-chip transmission components internally, the cross-chip transmission component can acquire the first transmission data sent by the processor and send it to the target chip, while simultaneously receiving the second transmission data returned by the target chip and sending it back to the processor. This securely and efficiently enables data transmission between multiple CPUs across different FPGA boards.

[0032] In order to accurately describe the chip provided in the embodiments of this disclosure, in one embodiment, such as Figure 3 As shown, the routing component 20 provided in this embodiment may include a first routing component 21 and a second routing component 22, both of which are connected to the processor 10 and the cross-chip transmission component 30, respectively. Specifically, as... Figure 3 As shown, the first routing component 21 can be connected to the cross-chip transmission component 30 through the request processing component 41, and correspondingly, the second routing component 22 can be connected to the cross-chip transmission component through the response processing component 42. Further details are omitted here.

[0033] In the chip provided in the embodiments of this disclosure, the processor 10 corresponds one-to-one with the routing component 20, that is, one processor 10 corresponds to one routing component 20. Similarly, one processor 10 also corresponds to one first routing component 21 and one second routing component 22, and this disclosure does not make specific limitations in this regard.

[0034] Based on this, the first routing component 21 is used to receive the first transmission data sent by the processor 10 and forward the first transmission data to the cross-chip transmission component 30; The cross-chip transmission component 30 is used to send first transmission data to the target chip for the target chip to forward the first transmission data to the processor of the target chip; The cross-chip transmission component 30 is also used to receive the second transmission data sent by the target chip and forward the second transmission data to the second routing component 22; The second routing component 22 is used to forward the second transmission data to the processor 10 of the chip 100.

[0035] It is conceivable that when the processor 10 sends the first transmission data to the first routing component 21, the first routing component 21 can receive the first transmission data sent by the processor 10 and forward the first transmission data to the cross-chip transmission component 30. Then, the cross-chip transmission component 30 can send the first transmission data to the target chip for the target chip to forward the first transmission data to its processor.

[0036] Based on this, the cross-chip transmission component 30 can also receive the second transmission data fed back by the target chip based on the first transmission data, and after receiving the second transmission data fed back by the target chip based on the first transmission data, forward the second transmission data to the second routing component 22, and then the second routing component 22 can forward the second transmission data to the processor 10 of the chip 100.

[0037] In this embodiment, a corresponding first routing component and a second routing component can be configured within the chip for each processor. The first routing component is connected to both the processor and the cross-chip transmission component, and the second routing component is connected to both the processor and the cross-chip transmission component. Based on this structure, the first routing component can accurately distribute the received first transmission data to the cross-chip transmission component, which then forwards the first transmission data to the target chip. The second routing component can receive the second transmission data forwarded by the cross-chip transmission component and forward it to the chip's processor. This achieves physical separation of the request path and the response path, allowing the first and second transmission data to be transmitted in parallel through independent channels, avoiding potential conflicts or blockages that might occur when the same routing component needs to process both sending and receiving data simultaneously.

[0038] Therefore, in one embodiment, the first transmission data may include a request address that points to the transmission destination of the first transmission data, which is not specifically limited here.

[0039] It should be noted that, as Figure 3As shown, the chip 100 provided in this embodiment may further include a bus device 50, which is connected to the first routing component 21 described above, and is not specifically limited here.

[0040] Based on the above structure, the first routing component 21 is used for: If it is determined that the request address in the first transmission data points to the target chip, the first transmission data is forwarded to the cross-chip transmission component 30 so that the cross-chip transmission component 30 forwards the first transmission data to the target chip. And, if it is determined that the request address in the first transmission data points to a bus device, the first transmission data is forwarded to the bus device.

[0041] It is conceivable that the first routing component 21 corresponding to the processor can receive the first transmission data sent by the processor 10. Since the first transmission data may include a request address, which may point to the transmission destination of the first transmission data, the first routing component 21 corresponding to the processor 10 can determine whether the request address points to the target chip. If the request address points to the target chip, the first routing component 21 corresponding to the processor 10 can forward the first transmission data to the cross-chip transmission component 30, so that the cross-chip transmission component 30 forwards the first transmission data to the target chip.

[0042] If the request address points to bus device 50, the first routing component 21 can send the first transmission data to bus device 50 for bus device 50 to process the first transmission data.

[0043] In this embodiment, the first transmission data sent by the processor may include a request address, which can be used to point to the transmission destination corresponding to the first transmission data. Furthermore, a bus device can be configured in the chip, which can be connected to both a first routing component and a second routing component. Based on this, the first routing component can receive the first transmission data sent by the processor and accurately distribute the first transmission data to the cross-chip transmission component and the bus device using the request address in the first transmission data. Thus, accurate distribution of the first transmission data is effectively achieved.

[0044] In one embodiment, such as Figure 3 As shown, the chip 100 provided in this embodiment may further include a bus device 50, which is connected to the second routing component 22 described above, and is not specifically limited here.

[0045] Based on the above structure, the second routing component 22 can be used for: Read the data processing flag; When the data processing flag is set to the first flag, the second transmission data sent by the cross-chip transmission component 30 is forwarded to the processor 10, and the data processing flag is updated to the second flag. When the data processing flag is set to the second flag, the second transmission data sent by the bus device 50 is forwarded to the processor 10, and the data processing flag is updated to the first flag.

[0046] In some embodiments, the aforementioned data processing flag is used to characterize the source type of the second transmission data currently to be processed by the second routing component 22. The source type includes a first type from the cross-chip transmission component 30 and a second type from the bus device 50. For example, if the data processing flag is the first flag, it indicates that the source type of the second transmission data currently to be processed by the second routing component 22 is the first type; if the data processing flag is the second flag, it indicates that the source type of the second transmission data currently to be processed by the second routing component 22 is the second type. No specific limitation is made here. In addition, the aforementioned first flag and second flag can be determined according to the actual situation. For example, the first flag can be set to 0 and the second flag can be set to 1. No specific limitation is made here.

[0047] It is conceivable that when the second routing component 22 simultaneously receives second transmission data sent by the cross-chip transmission component 30 and second transmission data sent by the bus device 50, the second routing component 22 can read the data processing flag bit. This data processing flag bit indicates the source type of the second transmission data currently to be processed by the second routing component 22. If the data processing flag bit is the first flag bit, indicating that the second transmission data currently to be processed comes from the cross-chip transmission component 30, the second transmission data sent by the cross-chip transmission component 30 can be forwarded to the processor 10, and the data processing flag bit can be updated to the second flag bit. If the data processing flag bit is the second flag bit, indicating that the second transmission data currently to be processed comes from the bus device 50, the second transmission data sent by the bus device 50 can be forwarded to the processor 10, and the data processing flag bit can be updated to the first flag bit.

[0048] In this embodiment, the chip may include a bus device that can connect to the second routing component. Based on this structure, when the second routing component simultaneously receives second transmission data forwarded by the cross-chip transmission component (i.e., external second transmission data) and second transmission data forwarded by the bus device (local second transmission data), it can read the data processing flag bit, select to process the corresponding external second transmission data or local second transmission data according to the specific value of the data processing flag bit, and update the data flag bit to mark the source of the most recently processed second transmission data. This effectively avoids the situation where the system is busy and frequently processes external second transmission data while neglecting local second transmission data. In order to provide a comprehensive and detailed description of the chip provided in the embodiments of this disclosure, in one embodiment, the following continues... Figure 3 As shown, the cross-chip transmission component 30 provided in this embodiment may include: a first cross-chip transmission component 31 and a second cross-chip transmission component 32, both of which are connected to the routing component 20. Specifically, as... Figure 3 As shown, the first cross-chip transmission component 31 is connected to the routing component through the request processing component 41, and the second cross-chip transmission component 32 is connected to the routing component through the response processing component 42. No specific limitations are made here.

[0049] Based on this, the first cross-chip transmission component 31 is used to send first transmission data to the target chip, so that the target chip can forward the first transmission data to the processor of the target chip. The second cross-chip transmission component 32 is also used to receive the second transmission data sent by the target chip and forward the second transmission data to the routing component 20.

[0050] It is conceivable that when the routing component 20 receives the first transmission data sent by the processor 10 and forwards the first transmission data to the first cross-chip transmission component 31, the first cross-chip transmission component 31 can send the first transmission data to the target chip so that the target chip can forward the first transmission data to the processor of the target chip.

[0051] Next, the second cross-chip transmission component 32 can receive the second transmission data sent by the target chip and forward the second transmission data to the routing component 20, so that the routing component 20 can forward the second transmission data to the processor 10 of the chip 100.

[0052] More specifically, such as Figure 3 As shown, since the routing component 20 may include a first routing component 21 and a second routing component 22, the first routing component 21 can be connected to the first cross-chip transmission component 31 through the request processing component 41, and correspondingly, the second routing component 22 can be connected to the second cross-chip transmission component 32 through the response processing component 42. No specific limitation is made here.

[0053] Therefore, it can be conceived that the first routing component 21 can receive the first transmission data sent by the processor 10 and forward the first transmission data to the first cross-chip transmission component 31. Then, the first cross-chip transmission component 31 can send the first transmission data to the target chip so that the target chip can forward the first transmission data to the processor of the target chip.

[0054] Based on this, the second cross-chip transmission component 32 can receive the second transmission data sent by the target chip and forward the second transmission data to the second routing component 22, so that the second routing component 22 can forward the second transmission data to the processor 10 of the chip 100.

[0055] In this embodiment, a first cross-chip transmission component and a second cross-chip transmission component can be configured within the cross-chip transmission assembly. Both the first and second cross-chip transmission components are connected to a routing component. Based on this structure, the first cross-chip transmission component is responsible for sending first transmission data to the target chip, and the second cross-chip transmission component is responsible for receiving second transmission data from the target chip. This achieves physical separation of the sending and receiving paths in cross-chip transmission, meaning that requesting to send data and responding to receive data can be performed in parallel without interference, avoiding waiting delays caused by the same transmission component needing to process both sending and receiving data.

[0056] Based on this, in one embodiment, such as Figure 3 As shown, the first cross-chip transmission component 31 provided in this embodiment may include an encryption component 311 and a transmission component 312, wherein the encryption component 311 is connected to the routing component 20 and the transmission component 312 respectively.

[0057] More specifically, the encryption component 311 can be connected to the first routing component 21 in sequence through the sorting component 314 and the request processing component 41, and the encryption component 311 can be connected to the sending component 312 through the verification component 313, without further limitations.

[0058] Based on the above structure, the encryption component 311 is used to encrypt the first transmitted data to obtain the first encrypted data, and send the first encrypted data to the sending component 312. The transmitting component 312 is used to send first encrypted data to the target chip, so that the target chip can decrypt the first encrypted data to obtain first transmitted data, and forward the first transmitted data to the processor of the target chip.

[0059] It is conceivable that after the routing component 20 forwards the first transmission data to the first cross-chip transmission component 31, the encryption component 311 can encrypt the first transmission data to obtain first encrypted data, and send the first encrypted data to the sending component 312. Then, the sending component 312 can send the first encrypted data to the target chip, so that the target chip can decrypt the first encrypted data to obtain the first transmission data, and forward the first transmission data to the processor deployed inside the target chip.

[0060] In this embodiment, an encryption component and a transmission component are set in the first cross-chip transmission component, and the encryption component is connected to the routing component and the transmission component respectively. Based on this structure, the first transmission data can be encrypted before being sent to the target chip, effectively preventing the first transmission data from being stolen or tampered with during cross-chip transmission, ensuring the confidentiality and security of data transmission, and thus realizing secure and reliable cross-chip communication.

[0061] In another embodiment, the first cross-chip transmission component 31 provided in this disclosure further includes a verification component 313 and a transmission component 312. The verification component 313 can be connected to the routing component 20 and the transmission component 312 respectively, without specific limitations here.

[0062] More specifically, continuing as Figure 3 As shown, the verification component 313 can be connected to the first routing component 21 in sequence through the encryption component 311, the sorting component 314, and the request processing component 41. The verification component 313 can be directly connected to the sending component 312, without any specific limitation here.

[0063] The verification component 313 is used to generate source verification information corresponding to the first transmitted data and send the source verification data corresponding to the first transmitted data to the sending component 312. The transmitting component 312 is used to send first transmission data and source verification information corresponding to the first transmission data to the target chip, so that if the target chip passes the verification of the first transmission data based on the source verification information corresponding to the first transmission data, it will forward the first transmission data to the processor of the target chip.

[0064] It should be noted that the source verification information generated by the verification component 313 varies depending on the connection method. When the verification component 313 is directly connected to the routing component 20 (specifically the first routing component 21) and other components between them are disabled, the source verification information is generated based on the first transmitted data; when the verification component 313 is connected to the routing component 20 (specifically the first routing component 21) through the encryption component 311, the source verification information is generated based on the first encrypted data. This disclosure does not impose specific limitations on this.

[0065] Thus, in one example, if the verification component 313 is directly connected to the routing component 20 (specifically the first routing component 21) and other components between them are disabled, after the routing component 20 forwards the first transmission data to the first cross-chip transmission component 31, the verification component 313 can generate source verification information based on the first transmission data and send the source verification data to the sending component 312. Then, the sending component 312 can send the first transmission data and the source verification information generated based on the first transmission data to the target chip, so that the target chip can verify the first transmission data based on the source verification information and forward the first transmission data to its processor.

[0066] In another embodiment, after the routing component 20 forwards the first transmission data to the first inter-chip transmission component 31, the encryption component 311 can encrypt the first transmission data to obtain first encrypted data, and send the first encrypted data to the verification component 313. The verification component 313 can generate corresponding source verification information based on the first encrypted data, and send the first encrypted data and the corresponding source verification information to the sending component 312. Then, the sending component 312 can send the first encrypted data and the source verification information generated based on the first encrypted data to the target chip, so that the target chip can verify the first encrypted data based on the source verification information, and if the verification passes, forward the first transmission data to the processor deployed inside the target chip.

[0067] In this embodiment, the first cross-chip transmission component can include a verification component and a transmission component. The verification component can be connected to both the routing component and the transmission component. Based on this structure, the verification component can generate source verification information corresponding to the first transmitted data. Then, the transmission component can send the first transmitted data and the corresponding source verification information to the target chip. The target chip can then verify the integrity of the first transmitted data based on the source verification information. After successful verification, the data is forwarded to its internal processor. This effectively ensures the integrity of the first transmitted data during cross-chip transmission.

[0068] In one embodiment, in order to accurately and comprehensively describe the chip provided in the embodiments of this disclosure, such as... Figure 3 As shown, the first cross-chip transmission component 31 provided in this embodiment may include a sorting component 314 and a sending component 312. The sorting component 314 is connected to the routing component 20 and the sending component 312 respectively, and no specific limitation is made here.

[0069] More specifically, continuing as Figure 3As shown, the sorting component 314 can be connected to the first routing component 21 through the request processing component 41, and the sorting component 314 can be connected to the sending component 312 through the encryption component 311 and the verification component 313 in sequence, without specific limitations here.

[0070] Based on this, the sorting component 314 is used to sort multiple first transmission data, obtain sorting information of multiple first transmission data, and send multiple first transmission data and sorting information of multiple first transmission data to the sending component 312. The transmitting component 312 is used to sequentially transmit multiple first transmission data to the target chip according to the sorting information of multiple first transmission data.

[0071] It is conceivable that after the routing component 20 forwards multiple first transmission data to the first cross-chip transmission component 31, the sorting component 314 can sort the multiple first transmission data to obtain sorting information for the multiple first transmission data, and send the sorting information and the sorted multiple first transmission data to the sending component 312. Then, the sending component 312 can send the multiple first transmission data to the target chip sequentially according to the sorting information.

[0072] In one example, if the sorting component 314 is connected to the sending component 312 via the encryption component 311, the sorting component 314 can sort multiple first transmitted data to obtain sorting information for the multiple first transmitted data, and send the sorting information and the sorted multiple first transmitted data to the encryption component 311. Then, the encryption component 311 can encrypt the multiple first transmitted data sequentially according to the sorting information to obtain first encrypted data corresponding to each of the multiple first transmitted data, and sequentially send the first encrypted data corresponding to each of the multiple first transmitted data to the sending component 312. This allows the sending component 312 to sequentially send the multiple first encrypted data to the target chip, so that the target chip can sequentially decrypt the multiple first encrypted data to obtain multiple first transmitted data, and then sequentially forward the multiple first transmitted data to the processor deployed inside the target chip.

[0073] In another example, if the sorting component 314 is connected to the sending component 312 via the verification component 313, the sorting component 314 can sort multiple first transmission data to obtain sorting information for the multiple first transmission data, and send the sorting information and the sorted multiple first transmission data to the verification component 313. Then, the verification component 313 can generate source verification information corresponding to each of the multiple first transmission data according to the sorting information, and send the multiple first transmission data and the corresponding source verification information to the sending component 312 in sequence. This allows the sending component 312 to send the multiple first transmission data and the corresponding source verification information to the target chip in sequence, so that the target chip can verify the corresponding first transmission data based on the source verification information. If the verification passes, the target chip will forward the multiple first transmission data to the processor deployed inside the target chip in sequence.

[0074] In another example, if the sorting component 314 is connected to the sending component 312 via the encryption component 311 and the verification component 313, the sorting component 314 can sort multiple first transmitted data to obtain sorting information for the multiple first transmitted data, and send the sorting information and the sorted multiple first transmitted data to the encryption component 311. Then, the encryption component 311 can sequentially encrypt the multiple first transmitted data according to the sorting information to obtain first encrypted data corresponding to each of the multiple first transmitted data, and sequentially send the first encrypted data corresponding to each of the multiple first transmitted data to the verification component 313. Next, the verification component 313 sequentially generates source verification information corresponding to each of the multiple first encrypted data, and sequentially sends the multiple first encrypted data and the source verification information corresponding to each of the multiple first encrypted data to the sending component 312. This allows the sending component 312 to sequentially send the multiple first encrypted data and the source verification information corresponding to each of the multiple first encrypted data to the target chip, so that the target chip can sequentially verify the corresponding first transmitted data based on the source verification information. If the verification passes, the target chip decrypts the first encrypted data to obtain the first transmitted data, and sequentially forwards the multiple first transmitted data to the processor deployed inside the target chip.

[0075] In this embodiment, the first cross-chip transmission component includes a sorting module, which can be connected to both the routing component and the encryption component. Based on this structure, after the routing component forwards multiple first transmission data to the first cross-chip transmission component, the sorting component can sort the multiple first transmission data to obtain sorting information. Then, the encryption component can sequentially encrypt the multiple first transmission data according to the sorting information, so that the target chip can forward the multiple first transmission data to the processor deployed inside the target chip. Thus, efficient data transmission is effectively achieved.

[0076] In order to accurately and in detail describe the chip provided in the embodiments of this disclosure, in one embodiment, the second cross-chip transmission component 32 provided in the embodiments of this disclosure may include: a receiving component 321 and a verification and judgment component 322, wherein the verification and judgment component 322 is connected to the receiving component 321 and the routing component 20 respectively.

[0077] The receiving component 321 is used to receive the second transmission data sent by the target chip and the source verification information corresponding to the second transmission data; The verification and judgment component 322 is used to generate target verification information corresponding to the second transmission data, and forward the second transmission data to the routing component 20 when the source verification information corresponding to the second transmission data matches the target verification information corresponding to the second transmission data.

[0078] It is conceivable that after the target chip sends the source verification information corresponding to the second transmitted data to the second inter-chip transmission component 32, the receiving component 321 can receive the second transmitted data and the source verification information corresponding to the second transmitted data. The verification judgment component 322 can generate the target verification information corresponding to the second transmitted data, and determine whether the source verification information and the target verification information match. If the source verification information and the target verification information match, the component forwards the second transmitted data to the routing component 20, so that the routing component 20 can forward the second transmitted data to the processor 10.

[0079] Furthermore, if the verification fails, it indicates that the second transmitted data may be interfered with during transmission. In this case, the verification judgment component 322 will not forward the second transmitted data to the routing component 20. Instead, it can generate error response data corresponding to the second transmitted data and return it to the processor of the target chip. No further restrictions are imposed here.

[0080] In this embodiment, the second cross-chip transmission component can include a receiving component and a verification component. The verification component is connected to both the receiving component and the routing component. Based on this structure, the verification component can perform integrity verification on the received second transmission data. Only when the source verification information matches the target verification information will the second transmission data be forwarded to the routing component and the processor. This effectively ensures that only complete and error-free second transmission data can be submitted to the processor, avoiding system anomalies caused by transmission errors or data tampering, and improving the reliability of cross-chip communication.

[0081] In one embodiment, the second cross-chip transmission component 32 provided in this disclosure may include a receiving component 321 and a decryption component 323, wherein the decryption component 323 may be connected to the routing component 20 and the receiving component 321 respectively, without specific limitations.

[0082] More specifically, such as Figure 3 As shown, the decryption component 323 is connected to the routing component 20 (specifically the second routing component 22) in sequence through the permission verification component 324 and the response processing component 42. The decryption component 323 is connected to the receiving component 321 through the verification judgment component 322. No specific limitation is made here.

[0083] Based on this, receiving component 321 is used to receive the second encrypted data sent by the target chip and send the second encrypted data to decryption component 323; The decryption component 323 is used to decrypt the second encrypted data to obtain the second transmitted data, and forward the second transmitted data to the routing component 20.

[0084] It is conceivable that the receiving component 321 can receive the second encrypted data sent by the target chip and send the second encrypted data to the decryption component 323. Then, the decryption component 323 can decrypt the second encrypted data to obtain the second transmission data and forward the second transmission data to the routing component 20.

[0085] In one example, if the decryption component 322 is connected to the receiving component 321 through the verification and judgment component 322, the receiving component 321 can receive the second encrypted data and the corresponding source verification information sent by the target chip, and send the second encrypted data and the source verification information to the verification component 322. Then, the verification and judgment component 322 can generate target verification information corresponding to the second encrypted data, determine whether the source verification information matches the target verification information, and if the source verification information matches the target verification information, send the second encrypted data to the decryption component 323, so that the decryption component 323 decrypts the second encrypted data to obtain the second transmitted data, and forwards the second transmitted data to the routing component 20.

[0086] In this embodiment, the second cross-chip transmission component may include a receiving component and a decryption component. Based on this structure, the receiving component receives the second encrypted data sent by the target chip and passes it to the decryption component. The decryption component decrypts the second encrypted data to obtain the corresponding second transmission data, which is then forwarded to the routing component. This allows for accurate and efficient acquisition of the second transmission data, effectively achieving secure and efficient data transmission between CPUs of different FPGA chips.

[0087] In order to accurately and in detail describe the chip provided in the embodiments of this disclosure, in one embodiment, the second cross-chip transmission component 32 provided in the embodiments of this disclosure may include: a receiving component 321 and an authorization verification component 324, wherein the authorization verification component 324 is connected to the receiving component 321 and the routing component 20 respectively.

[0088] More specifically, such as Figure 3As shown, the permission verification component 324 can be connected to the routing component 20 (specifically the second routing component) through the response processing component 42. The permission verification component 324 can be connected to the receiving component 321 through the decryption component 323 and the verification judgment component 322. No specific limitations are made here.

[0089] The receiving component 321 is also used to receive the second transmission data sent by the target chip and the source device information corresponding to the second transmission data, and to send the second transmission data and the source device information corresponding to the second transmission data to the authorization verification component 324. The permission verification component 324 is used to query the permission information corresponding to the source device information based on the source device information corresponding to the second transmission data, and forward the second transmission data to the routing component 30 if the permission information corresponding to the source device information passes the verification.

[0090] It is conceivable that after the target chip sends the second transmission data to the second inter-chip transmission component 32, the receiving component 321 can receive the second transmission data sent by the target chip and the source device information corresponding to the second transmission data, and send the second transmission data and the source device information corresponding to the second transmission data to the authorization verification component 324. Then, the authorization verification component 324 can query the corresponding authorization information based on the source device information and then verify the authorization information. If the authorization information verification passes, the authorization verification component 324 forwards the second transmission data to the routing component 20, so that the routing component 20 can forward the second transmission data to the processor 10.

[0091] It should be noted that the permission verification component 324 can consist of multiple registers. The index of these registers can be the source device information corresponding to the first transmitted data, such as the source device number (req id). The registers can store permission information, such as read and write permission information. Furthermore, the second cross-chip transmission component can be equipped with a status monitoring register to provide feedback on the verification results (whether the second transmitted data has been tampered with) and permission verification results (whether permission is granted). Therefore, in the event of data verification failure or permission verification error, the status monitoring register can be updated. The processor can read the status monitoring register to view the source device information, read / write type, request address, etc., of the current error, without specific limitations.

[0092] In this embodiment, after the target chip sends the second transmission data to the second inter-chip transmission component, the permission verification component can obtain the source device information corresponding to the second transmission data, query the corresponding permission information based on the source device information, and then verify the permission information. If the permission information verification passes, the permission verification component forwards the second transmission data to the routing component, so that the routing component can forward the second transmission data to the processor.

[0093] In one embodiment, such as Figure 3 As shown, the chip 100 provided in this embodiment may further include a request processing component 41 and a response processing component 42 connected to each other. The request processing component 41 may be connected to the routing component 20 and the first cross-chip transmission component 31, respectively, and the response processing component 42 may be connected to the routing component 20 and the second cross-chip transmission component 32, respectively; no specific limitations are made here.

[0094] More precisely, since the routing component 20 may include a first routing component 21 and a second routing component 22, the request processing component 41 may be connected to the first routing component 21 and the first cross-chip transmission component 31 respectively, and the response processing component 42 may be connected to the second routing component 22 and the second cross-chip transmission component 32 respectively.

[0095] The routing component 20 is also used to send the first transmission data to the request processing component 41; The request processing component 41 is used to receive the first transmission data sent by the routing component 20, obtain the identification information of the first transmission data, forward the identification information of the first transmission data to the response processing component 42, and forward the first transmission data to the first cross-chip transmission component 31. The response processing component 42 is used to receive the identification information of the first transmission data forwarded by the request processing component 41, and to store the identification information of the first transmission data; In addition, the system acquires the identification information of the second transmission data received by the second cross-chip transmission component 32, and forwards the second transmission data to the routing component 20 if the identification information of the second transmission data matches the identification information of the stored first transmission data. The routing component 20 is also used to forward the second transmission data to the processor 10.

[0096] Based on this structure, it can be conceived that the routing component 20 can also send first transmission data to the request processing component 41. After receiving the first transmission data sent by the routing component 20, the request processing component 41 can obtain the identification information of the first transmission data and forward the identification information of the first transmission data to the response processing component 42. In addition, the request processing component 41 can also forward the first transmission data to the first cross-chip transmission component 31.

[0097] The response processing component 42 can receive and store the identification information of the first transmission data forwarded by the request processing component 41. Furthermore, the response processing component 42 can obtain the identification information of the second transmission data received by the second cross-chip transmission component 32, and match the identification information of the second transmission data with the identification information of the first transmission data already stored locally in the response processing component 42. If they match, the response processing component 42 can forward the second transmission data to the routing component 20, and then the routing component 20 can send the second transmission data to the corresponding processor 10.

[0098] At the system level, each CPU or bus device is assigned a unique identifier. The object-oriented device identifier is the same as the device identifier of the response source; the former is used to identify the initiator, and the latter is used to identify the responder.

[0099] The response processing component 42 maintains a request ID cache table, indexed by {request type, target device number, request ID}. The table stores the request's source ID (i.e., which processor or bus device it originates from). The request type, corresponding route, request ID, and request source all originate from the request processing component 41. For example, the request processing component 41 issues a write request from CPU0 (first route), directed to the second route, with a request ID of 3. The request processing component 41 transmits this information to the response processing component 42 and stores it in the request ID cache table. When the response processing component 42 receives a write response from the second route with a response ID of 3, it can locate the corresponding entry in the table using the index, determining that the write response should be sent to the second routing component 22, and subsequently to CPU0. If the request source is changed to peripheral 0 (first route), with the other conditions remaining the same, the corresponding entry can still be found in the table, determining that the response should be sent to the corresponding bus device.

[0100] The request processing component 41 also maintains a response identifier cache table (RSP ID table) to store external requests received by the response processing component 42. The index of this table is also {request type, response source device number, request identifier}, and the information stored in the table indicates which processor or bus device number it originated from. For example, the response processing component 42 receives a read request from device 4 on the second channel, which is directed to local device 1, and the read request identifier is 2. The response processing component 42 forwards this information to the request processing component 41, which uses {request type, response source device number, request identifier} as the index to record the request source "device 4 on the second channel" in the response identifier cache table. When the request processing component 41 receives a read response from local device 1 with a response ID of 2, it can determine through the index that the response should be sent to device 4 on the second channel.

[0101] The workflow of request processing component 41 is as follows: First, it receives requests from the first routing component 21, as well as requests and responses from the local bus to external locations. Then, it distributes these requests or responses to the corresponding first cross-chip transmission components 31 according to their destination. Specifically, for requests from the first routing component 21 and the local bus, request processing component 41 forwards all requests to the corresponding first cross-chip transmission components 31, and simultaneously transmits the request ID, corresponding route, request source, request type, and other information of the request to response processing component 42. For responses from the local bus to external locations, request processing component 41 extracts the {request type, device number of the response source, ID} of the response as an index to the response identifier cache table, finds which route the response should be returned to, and transmits the response to the corresponding route.

[0102] The workflow of response processing component 42 is as follows: It receives foreign requests and responses from the first cross-chip transmission component 31. For foreign requests, response processing component 42 first parses the request address to determine the target local device, forwards the request to the corresponding bus device, and then saves the request type, the target device number, the request source, and the request identifier, and forwards it to the request identifier cache table of request processing component 41. For foreign responses, response processing component 42 extracts the {response type, response source device number, identifier} of the response as an index to the response identifier cache table, finds which route the response should return to, and transmits the response to the corresponding route.

[0103] In this embodiment, by setting up a request processing component and a response processing component, and transmitting the identification information of the first transmitted data between the two, the response processing component can match the identification information of the received second transmitted data with the locally stored identification information of the first transmitted data. Only when a match is successful will the second transmitted data be forwarded to the processor via the routing component. This effectively achieves accurate correspondence between requests and responses, preventing the second transmitted data from being incorrectly forwarded to the processor that did not initiate the request, and ensuring the accuracy and reliability of cross-chip communication.

[0104] Based on the same inventive concept, this disclosure also provides a data transmission method. The data transmission method provided by this disclosure will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0105] Figure 4 This is a flowchart illustrating a data transmission method provided in an embodiment of this disclosure.

[0106] like Figure 4As shown, the execution entity of this method can be a first chip, which may include a processor, a routing component corresponding to the processor, and a cross-chip transmission component. Based on this, the data transmission method provided in this embodiment may include the following steps: S410 obtains the first transmission data sent by the first processor through the routing component and forwards the first transmission data to the cross-chip transmission component.

[0107] S420, first transmission data is sent to the second chip via a cross-chip transmission component for the second chip to forward the first transmission data to the second processor of the second chip.

[0108] S430 receives the second transmission data sent by the second chip through the cross-chip transmission component and forwards the second transmission data to the routing component.

[0109] S440 forwards the second transmission data to the first processor via the routing component.

[0110] Both the first chip and the second chip are Figure 1 The chip shown.

[0111] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0112] In this embodiment, a routing component can receive first transmission data sent by a processor and forward it to a cross-chip transmission component. The cross-chip transmission component then sends the first transmission data to a target chip, which forwards it to a processor deployed within the target chip. Based on this, the cross-chip transmission component can also receive second transmission data returned by the target chip based on the first transmission data and forward it to the routing component. The routing component then forwards the second transmission data to the chip's processor. Thus, by deploying interconnected processors, routing components, and cross-chip transmission components within the chip, the cross-chip transmission component can acquire the first transmission data sent by the processor and send it to the target chip, while simultaneously receiving the second transmission data returned by the target chip and sending it back to the processor. This enables secure and efficient data transmission between multiple CPUs across different FPGA boards.

[0113] In one embodiment, the routing component corresponding to the first processor includes a first routing component and a second routing component; The process involves obtaining the first transmission data sent by the first processor through the routing component corresponding to the first processor in the first chip, and forwarding the first transmission data to the cross-chip transmission component of the first chip, including: The first transmission data sent by the first processor is obtained through the first routing component, and the first transmission data is forwarded to the cross-chip transmission component of the first chip. The second transmission data is forwarded to the first processor via the routing component, including: The second transmission data is forwarded to the first processor via the second routing component.

[0114] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0115] In this embodiment, the first routing component accurately distributes the received first transmission data to the cross-chip transmission component, which then forwards the first transmission data to the target chip. The second routing component receives the second transmission data forwarded by the cross-chip transmission component and forwards it to the chip's processor. This achieves physical separation of the request and response paths, allowing the first and second transmission data to be transmitted in parallel through independent channels, avoiding potential conflicts or blockages that might occur when the same routing component needs to process both sending and receiving data simultaneously.

[0116] In one embodiment, the step of obtaining the first transmission data sent by the first processor through the first routing component and forwarding the first transmission data to the cross-chip transmission component of the first chip includes: When the first routing component determines that the request address in the first transmitted data points to the target chip, it forwards the first transmitted data to the cross-chip transmission component, so that the cross-chip transmission component forwards the first transmitted data to the target chip.

[0117] Furthermore, in one embodiment, the first chip may include a bus device connected to a first routing component, and the method may include: If the first routing component determines that the request address in the first transmitted data points to the bus device, it forwards the first transmitted data to the bus device.

[0118] In this embodiment, the first routing component can receive first transmission data sent by the processor and accurately distribute the first transmission data to the cross-chip transmission component and bus device using the request address in the first transmission data. This effectively achieves accurate distribution of the first transmission data.

[0119] In one embodiment, the forwarding of the second transmission data to the first processor via the second routing component includes: The data processing flag is read through the second routing component; When the data processing flag is set to the first flag, the second routing component forwards the second transmission data sent by the cross-chip transmission component to the processor and updates the data processing flag to the second flag. Furthermore, in one embodiment, the first chip may include a bus device connected to a second routing component, and the data transmission method provided in this disclosure embodiment may include: When the data processing flag is set to the second flag, the second routing component forwards the second transmission data sent by the bus device to the processor and updates the data processing flag to the first flag.

[0120] In this embodiment, the second routing component can read the data processing flag bit when simultaneously receiving second transmission data forwarded by the cross-chip transmission component (i.e., external second transmission data) and second transmission data forwarded by the bus device (local second transmission data). Based on the specific value of the data processing flag bit, it selects to process either the corresponding external second transmission data or the local second transmission data and updates the data flag bit to mark the source of the most recently processed second transmission data. This effectively avoids the situation where the system is busy and frequently processes external second transmission data while neglecting local second transmission data.

[0121] In one embodiment, the cross-chip transmission component includes a first cross-chip transmission component and a second cross-chip transmission component. Sending first transmission data to the second chip via a cross-chip transmission component includes: The first transmission data is sent to the second chip through the first cross-chip transmission component, so that the second chip can forward the first transmission data to the second processor of the second chip; Receiving second transmission data sent by the second chip through the cross-chip transmission component and forwarding the second transmission data to the routing component includes: The second cross-chip transmission component receives the second transmission data sent by the second chip and forwards the second transmission data to the routing component.

[0122] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0123] In this embodiment, the first cross-chip transmission component is responsible for sending the first transmission data to the target chip, and the second cross-chip transmission component is responsible for receiving the second transmission data from the target chip. This achieves physical separation of the sending and receiving paths in cross-chip transmission, meaning that requesting to send and responding to receive can be performed in parallel without interference, avoiding waiting delays caused by the same transmission component needing to process both sending and receiving data.

[0124] In one embodiment, the first inter-chip transmission component further includes an encryption component and a transmission component; transmitting first transmission data to the second chip via the first inter-chip transmission component includes: The first encrypted data is obtained by encrypting the first transmitted data using an encryption component; The first encrypted data is sent to the second chip by the sending component, so that the second chip can decrypt the first encrypted data to obtain the first transmitted data, and forward the first transmitted data to the second processor of the second chip.

[0125] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0126] In this embodiment, the first transmitted data can be encrypted by an encryption component before being sent to the target chip, which effectively prevents the first transmitted data from being stolen or tampered with during cross-chip transmission, ensuring the confidentiality and security of data transmission, and thus realizing secure and reliable cross-chip communication.

[0127] In one embodiment, the first inter-chip transmission component further includes a verification component and a transmission component; transmitting first transmission data to the second chip via the first inter-chip transmission component includes: The verification component generates source verification information corresponding to the first transmitted data. The sending component sends source verification information corresponding to the first transmitted data to the second chip, so that if the second chip passes the verification of the first transmitted data based on the source verification information corresponding to the first transmitted data, it can forward the first transmitted data to the second processor of the second chip.

[0128] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0129] In this embodiment, the verification component generates source verification information corresponding to the first transmitted data. Then, the sending component sends the first transmitted data and its corresponding source verification information to the target chip. The target chip verifies the integrity of the first transmitted data based on the source verification information. Once the verification is successful, the data is forwarded to its internal processor. This effectively ensures the integrity of the first transmitted data during cross-chip transmission.

[0130] In one embodiment, the first inter-chip transmission component further includes a sorting component and a sending component; sending first transmission data to the second chip via the first inter-chip transmission component includes: The sorting component sorts the multiple first transmission data to obtain the sorting information of the multiple first transmission data; The sending component sequentially sends multiple first transmission data to the second chip according to the sorting information of multiple first transmission data.

[0131] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0132] In this embodiment, after the routing component forwards multiple first transmission data to the first cross-chip transmission component, the sorting component can sort the multiple first transmission data to obtain sorting information. Then, the encryption component can sequentially encrypt the multiple first transmission data according to the sorting information, so that the target chip can forward the multiple first transmission data to the processor deployed inside the target chip. In this way, efficient data transmission is effectively achieved.

[0133] In one embodiment, the second cross-chip transmission component further includes a receiving component and a verification component; receiving second transmission data sent by the second chip through the second cross-chip transmission component includes: The receiving component receives the second transmission data sent by the second chip and the source verification information corresponding to the second transmission data. The verification component generates target verification information corresponding to the second transmission data, and forwards the second transmission data to the routing component if the source verification information corresponding to the second transmission data matches the target verification information corresponding to the second transmission data.

[0134] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0135] In this embodiment, the verification component can perform integrity verification on the received second transmitted data. The second transmitted data is only forwarded to the routing component and processor if the source verification information matches the target verification information. This effectively ensures that only complete and error-free second transmitted data is submitted to the processor, avoiding system anomalies caused by transmission errors or data tampering, and improving the reliability of cross-chip communication.

[0136] In one embodiment, the second cross-chip transmission component includes a receiving component and a decryption component; receiving second transmission data sent by the second chip through the second cross-chip transmission component includes: The receiving component receives the second encrypted data sent by the target chip. The second encrypted data is decrypted by the decryption component to obtain the second transmitted data, and then forwarded to the routing component.

[0137] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0138] In this embodiment, a receiving component receives the second encrypted data sent by the target chip and passes it to a decryption component. The decryption component decrypts the second encrypted data to obtain the corresponding second transmitted data, which is then forwarded to a routing component. This allows for accurate and efficient acquisition of the second transmitted data, effectively achieving secure and efficient data transmission between CPUs of different FPGA chips.

[0139] In one embodiment, the second cross-chip transmission component further includes a receiving component and an authorization verification component; it also includes: The receiving component receives the second transmission data sent by the target chip and the source device information corresponding to the second transmission data, and sends the second transmission data and the source device information corresponding to the second transmission data to the authorization verification component.

[0140] The permission verification component queries the source device information corresponding to the source device information based on the source device information corresponding to the second transmission data to obtain the permission information corresponding to the source device information. If the permission information corresponding to the source device information passes the verification, the second transmission data is forwarded to the routing component.

[0141] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0142] In this embodiment, after the target chip sends the second transmission data to the second inter-chip transmission component, the permission verification component can obtain the source device information corresponding to the second transmission data, query the corresponding permission information based on the source device information, and then verify the permission information. If the permission information verification passes, the permission verification component forwards the second transmission data to the routing component, so that the routing component can forward the second transmission data to the processor.

[0143] In one embodiment, the first chip further includes a request processing component and a response processing component; and also includes: The routing component sends the first transmission data to the request processing component. The first transmission data is obtained by the request processing component, and the first transmission data is forwarded to the response processing component and forwarded to the first cross-chip transmission component. The response processing component receives the identification information of the first transmitted data forwarded by the request processing component and stores the identification information of the first transmitted data. After receiving the second transmission data sent by the second chip through the cross-chip transmission component, it also includes: The response processing component obtains the identification information of the second transmission data received by the second cross-chip transmission component, and forwards the second transmission data to the routing component if the identification information of the second transmission data matches the identification information of the stored first transmission data. The second transmission data is forwarded to the processor via the routing component.

[0144] It should be noted that the specific details can be found in the above embodiments, and will not be repeated here.

[0145] In this embodiment, by setting up a request processing component and a response processing component, and transmitting the identification information of the first transmitted data between the two, the response processing component can match the identification information of the received second transmitted data with the locally stored identification information of the first transmitted data. Only when a match is successful will the second transmitted data be forwarded to the processor via the routing component. This effectively achieves accurate correspondence between requests and responses, preventing the second transmitted data from being incorrectly forwarded to the processor that did not initiate the request, and ensuring the accuracy and reliability of cross-chip communication.

[0146] This application provides a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a data transmission method.

[0147] This application provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored and when executed by a processor, the processor will execute the data transmission method provided in this application.

[0148] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0149] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0150] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborating files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0151] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0152] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure; as shown below. Figure 5 As shown, the electronic device 50 includes: a processor 501, and a memory 502 communicatively connected to the processor 501; the memory 502 stores instructions executable by the processor 501. The instructions are executed by the processor 501 to enable the processor 501 to perform: The routing component obtains the first transmission data sent by the first processor and forwards the first transmission data to the cross-chip transmission component. First transmission data is sent to the second chip via a cross-chip transmission component, for the second chip to forward the first transmission data to the second processor of the second chip; The second transmission data sent by the second chip is received by the cross-chip transmission component, and the second transmission data is forwarded to the routing component. The second transmission data is forwarded to the first processor via the routing component; Both the first chip and the second chip are Figure 1 The chip shown includes a first processor, a routing component corresponding to the first processor, and a cross-chip transmission component.

[0153] The electronic devices and corresponding data transmission methods provided in the above embodiments belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0154] In practical applications, electronic device 50 may further include at least one network interface 503. The various components in electronic device 50 are coupled together via bus system 504. It is understood that bus system 504 is used to implement communication between these components. In addition to a data bus, bus system 504 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 5 All buses are labeled as bus system 504. There can be at least one processor 501 and at least one memory 502. Network interface 503 is used for wired or wireless communication between electronic device 50 and other devices.

[0155] The memory 502 in this embodiment is used to store various types of data to support the operation of the electronic device 50.

[0156] The methods disclosed in the above embodiments of this disclosure can be applied to processor 501, or implemented by processor 501. Processor 501 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in processor 501 or by instructions in the form of software. The processor 501 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Processor 501 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. A general-purpose processor may be a microprocessor or any conventional processor, etc. The steps of the methods disclosed in the embodiments of this disclosure can be directly manifested as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software modules may be located in a storage medium, which is located in memory 502. Processor 501 reads the information in memory 502 and, in conjunction with its hardware, completes the steps of the aforementioned data transmission method.

[0157] In some embodiments, the electronic device 50 may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers (MCUs), microprocessors, or other electronic components to perform the aforementioned methods.

[0158] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0159] In the above description, the term "some embodiments" refers to a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0160] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in this disclosure is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0161] It should be understood that in the various embodiments of this disclosure, the sequence number of each implementation process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0162] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0163] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A chip, characterized in that, include: The processor, the routing component corresponding to the processor, and the cross-chip transmission component, wherein the routing component is connected to the processor and the cross-chip transmission component respectively; The routing component is used to receive the first transmission data sent by the processor and forward the first transmission data to the cross-chip transmission component; The cross-chip transmission component is used to send the first transmission data to the target chip, so that the target chip can forward the first transmission data to the processor of the target chip; The cross-chip transmission component is also used to receive the second transmission data sent by the target chip and forward the second transmission data to the routing component; The routing component is also used to forward the second transmission data to the processor of the chip.

2. The chip according to claim 1, characterized in that, The routing component includes: a first routing component and a second routing component, both of which are respectively connected to the processor and the cross-chip transmission component; The first routing component is configured to receive the first transmission data sent by the processor and forward the first transmission data to the cross-chip transmission component; The cross-chip transmission component is used to send the first transmission data to the target chip, so that the target chip can forward the first transmission data to the processor of the target chip; The cross-chip transmission component is also used to receive the second transmission data sent by the target chip and forward the second transmission data to the second routing component; The second routing component is used to forward the second transmission data to the processor of the chip.

3. The chip according to claim 1, characterized in that, The cross-chip transmission component includes: a first cross-chip transmission component and a second cross-chip transmission component, both of which are connected to the routing component. The first cross-chip transmission component is used to send the first transmission data to the target chip, so that the target chip can forward the first transmission data to the processor of the target chip; The second cross-chip transmission component is further configured to receive second transmission data sent by the target chip and forward the second transmission data to the routing component.

4. The chip according to claim 3, characterized in that, The first cross-chip transmission component further includes an encryption component and a transmission component, wherein the encryption component is connected to the routing component and the transmission component, respectively; The encryption component is used to encrypt the first transmitted data to obtain first encrypted data, and to send the first encrypted data to the sending component. The sending component is used to send the first encrypted data to the target chip, so that the target chip can decrypt the first encrypted data to obtain the first transmitted data, and forward the first transmitted data to the processor of the target chip.

5. The chip according to claim 3 or 4, characterized in that, The first cross-chip transmission component further includes a verification component and a transmission component, wherein the verification component is connected to the routing component and the transmission component, respectively; The verification component is used to generate source verification information corresponding to the first transmitted data and send the source verification data corresponding to the first transmitted data to the sending component. The sending component is configured to send the first transmitted data and source verification information corresponding to the first transmitted data to the target chip, so that if the target chip passes the verification of the first transmitted data based on the source verification information corresponding to the first transmitted data, it can forward the first transmitted data to the processor of the target chip.

6. The chip according to claim 3 or 4, characterized in that, The first cross-chip transmission component further includes a sorting component and a sending component, wherein the sorting component is connected to the routing component and the sending component, respectively; The sorting component is used to sort the multiple first transmitted data to obtain sorting information of the multiple first transmitted data, and send the multiple first transmitted data and the sorting information of the multiple first transmitted data to the sending component; The sending component is used to send multiple sets of the first transmission data to the target chip sequentially according to the sorting information of the multiple sets of the first transmission data.

7. The chip according to claim 3, characterized in that, The second cross-chip transmission component further includes a receiving component and a verification and judgment component, wherein the verification and judgment component is connected to the receiving component and the routing component respectively; The receiving component is used to receive the second transmission data sent by the target chip and the source verification information corresponding to the second transmission data; The verification judgment component is used to generate target verification information corresponding to the second transmission data, and forward the second transmission data to the routing component when the source verification information corresponding to the second transmission data matches the target verification information corresponding to the second transmission data.

8. The chip according to claim 3 or 7, characterized in that, The second cross-chip transmission component includes a receiving component and a decryption component, wherein the decryption component is connected to the receiving component and the routing component, respectively; The receiving component is used to receive the second encrypted data sent by the target chip and send the second encrypted data to the decryption component. The decryption component is used to decrypt the second encrypted data to obtain the second transmitted data, and forward the second transmitted data to the routing component.

9. The chip according to claim 3 or 7, characterized in that, The second cross-chip transmission component further includes a receiving component and an authorization verification component, wherein the authorization verification component is connected to the receiving component and the routing component, respectively; The receiving component is further configured to receive the second transmission data and the source device information corresponding to the second transmission data sent by the target chip, and send the second transmission data and the source device information corresponding to the second transmission data to the permission verification component; The permission verification component is used to query the permission information corresponding to the source device information based on the source device information corresponding to the second transmission data, and forward the second transmission data to the routing component if the permission information corresponding to the source device information passes the verification.

10. The chip according to claim 3, characterized in that, Also includes: The request processing component and response processing component are interconnected, wherein the request processing component is connected to the first cross-chip transmission component of the routing component, and the response processing component is connected to the processor and the second cross-chip transmission component. The routing component is also used to send the first transmission data to the request processing component; The request processing component is used to obtain the identification information of the first transmitted data, forward the identification information of the first transmitted data to the response processing component, and forward the first transmitted data to the first cross-chip transmission component. The response processing component is used to receive the identification information of the first transmitted data forwarded by the request processing component, and to store the identification information of the first transmitted data. In addition, the system obtains the identification information of the second transmission data received by the second cross-chip transmission component, and forwards the second transmission data to the routing component if the identification information of the second transmission data matches the identification information of the first transmission data that has been stored. The routing component is also used to forward the second transmission data to the processor.

11. A data transmission method, characterized in that, Applied to a first chip, the first chip including a first processor, a routing component corresponding to the first processor, and a cross-chip transmission component, including: The routing component obtains the first transmission data sent by the first processor and forwards the first transmission data to the cross-chip transmission component. The first transmission data is sent to the second chip through the cross-chip transmission component, so that the second chip can forward the first transmission data to the second processor of the second chip; The cross-chip transmission component receives the second transmission data sent by the second chip and forwards the second transmission data to the routing component, wherein the second transmission data is determined based on the first transmission data. The routing component forwards the second transmission data to the first processor; Both the first chip and the second chip are chips as described in any one of claims 1 to 10.

12. The method according to claim 11, characterized in that, The cross-chip transmission component includes a first cross-chip transmission component and a second cross-chip transmission component. Sending the first transmission data to the second chip via the cross-chip transmission component includes: The first transmission data is sent to the second chip through the first cross-chip transmission component, so that the second chip can forward the first transmission data to the second processor of the second chip; The step of receiving the second transmission data sent by the second chip through the cross-chip transmission component and forwarding the second transmission data to the routing component includes: The second cross-chip transmission component receives the second transmission data sent by the second chip and forwards the second transmission data to the routing component.

13. The method according to claim 12, characterized in that, The first cross-chip transmission component further includes an encryption component and a transmission component; the step of sending the first transmission data to the second chip through the first cross-chip transmission component includes: The first transmitted data is encrypted using the encryption component to obtain the first encrypted data; The first encrypted data is sent to the second chip through the sending component, so that the second chip can decrypt the first encrypted data to obtain the first transmitted data, and forward the first transmitted data to the second processor of the second chip.

14. An electronic device, characterized in that, include: At least one processor; And, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 11 to 13.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 11 to 13.

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