Semiconductor device and method of manufacturing the same

Abstract

This application provides a semiconductor device and a method for fabricating the same. The method includes: providing a substrate comprising a first region and a second region; forming a hard mask layer on the substrate to expose a field oxide layer region in the first region and an isolation region in the second region containing a portion of the isolation structure adjacent to the active region; performing an oxidation process to form a field oxide layer in the first region and a bird's beak oxide layer on the active region in the second region, the bird's beak oxide layer having a thin center and thick edges; and removing the hard mask layer and the bird's beak oxide layer to expose an active region in the second region with an upwardly curved upper surface. This application forms an upwardly curved active region without increasing process steps, and increases the effective width / length of the device without increasing the active region layout size, thereby simultaneously suppressing threshold voltage drift and increasing the device drive current, achieving high performance, low power consumption, and improved reliability.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] As the feature size of integrated circuits continues to shrink, semiconductor devices are constantly evolving towards higher integration, higher speed, and lower power consumption. In modern CMOS processes, not only are channel lengths continuously miniaturized to the nanometer level, but channel widths are also significantly reduced to meet the design requirements of high-density logic circuits and advanced logic process nodes. When the channel width of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) shrinks to a scale comparable to the lateral expansion of the source / drain depletion region, the device enters a narrow channel operating region, which triggers a series of significant physical effects, including threshold voltage drift and a decrease in drive current due to the reduction in effective channel width.

[0003] To address the aforementioned issues, existing technologies have proposed various improvement schemes, such as optimizing the STI (Shallow Trench Isolation) morphology, introducing localized oxide isolation, employing asymmetric channel design, and adjusting doping. However, these methods often struggle to balance suppressing threshold voltage drift and increasing drive current.

[0004] Therefore, there is an urgent need to provide a semiconductor device and its fabrication method that can simultaneously suppress threshold voltage drift and increase the device's drive current, thereby achieving a high-performance, low-power, and high-reliability semiconductor device. Summary of the Invention

[0005] The purpose of this application is to provide a semiconductor device and a method for fabricating the same, forming an upwardly curved active region that can simultaneously suppress threshold voltage drift and increase the drive current of the device.

[0006] To address the aforementioned technical problems, according to the first aspect of this application, a method for fabricating a semiconductor device is provided, comprising the following steps:

[0007] A substrate is provided, the substrate including a first region for forming a DMOS device and a second region for forming a CMOS device, wherein an active region and an isolation structure surrounding the active region are formed in both the first region and the second region;

[0008] A hard mask layer is formed on the substrate, which exposes the field oxide layer region in the first region where a field oxide layer is to be formed, and at the same time exposes the isolation region in the second region where a portion of the isolation structure adjacent to the active region is located;

[0009] An oxidation process is performed to form a field oxide layer in the field oxide layer region of the first region, and a beak oxide layer is formed on the active region of the second region, the beak oxide layer having a morphology that is thin in the middle and thick at the edges; and,

[0010] Remove the hard mask layer and the beak oxide layer to expose the active region with its upper surface curved upwards in the second region.

[0011] Optionally, a method for forming a hard mask layer on the substrate includes:

[0012] A hard mask material layer and a photoresist layer are formed on the substrate;

[0013] The photoresist layer is exposed and developed to form a patterned photoresist layer.

[0014] Using the patterned photoresist layer as a mask, the hard mask material layer is etched to expose the field oxide region in the first region and the isolation region in the second region; and,

[0015] Remove the patterned photoresist layer.

[0016] Optionally, the hard mask layer exposes the isolation regions where the isolation structures on both sides of the active region in the first direction are located within the second region, or / and the hard mask layer exposes the isolation regions where the isolation structures on both sides of the active region in the second direction are located within the second region, wherein the first direction is perpendicular to the second direction.

[0017] Optionally, the isolation areas exposed on both sides of the active region in the first direction are symmetrical; or / and, the isolation areas exposed on both sides of the active region in the second direction are symmetrical.

[0018] Optionally, the ratio of the size of the isolation region in the first direction to the size of the active region in the first direction is 10% to 30%, or / and the ratio of the size of the isolation region in the second direction to the size of the active region in the second direction is 10% to 30%.

[0019] Optionally, the distance from the edge of the exposed isolation area near the active area to the active area is 0~1μm.

[0020] Optionally, the hard mask layer includes a silicon oxide layer and a silicon nitride layer stacked sequentially.

[0021] Optionally, after removing the beak oxide layer, the method further includes: forming a gate on the substrate in the first region and the second region, wherein the gate in the first region covers a portion of the substrate and a portion of the field oxide layer; and forming source / drain regions in the substrate on both sides of the gate.

[0022] Optionally, the CMOS device may include a low-voltage device or a medium-voltage device.

[0023] To address the aforementioned technical problems, according to a second aspect of this application, a semiconductor device is also provided, comprising:

[0024] The substrate includes a first region for forming a DMOS device and a second region for forming a CMOS device, wherein active regions and isolation structures surrounding the active regions are formed in both the first and second regions; the upper surface of the active region in the second region is curved upward; and,

[0025] A field oxide layer is located on the substrate in the first region.

[0026] The semiconductor device and its fabrication method provided in this application expose the isolation region of the adjacent active region within the second region. Then, an oxidation process is performed to form a bird's beak oxide layer with a thin center and thick edges on the active region within the second region. After removing the bird's beak oxide layer, the upper surface of the active region within the second region bends upwards, forming a surface-bent active region. This increases the effective width / length of the device without increasing the active region layout size, thereby simultaneously suppressing threshold voltage drift and increasing the device's drive current, achieving high performance, low power consumption, and improved reliability. Furthermore, this application exposes the isolation region within the second region while simultaneously exposing the field oxide layer region within the first region. Forming the bird's beak oxide layer while forming the field oxide layer does not increase the number of process steps, thus achieving performance improvement for the CMOS device without adding process steps and reducing production costs. Attached Figure Description

[0027] Figure 1 This is a top-view schematic diagram of the hard mask layer formed in the related technology.

[0028] Figure 2 yes Figure 1 A schematic diagram of the cross section in the AA′ direction.

[0029] Figure 3 yes Figure 1 A schematic diagram of the cross-section in the BB′ direction.

[0030] Figure 4 This is a top-view diagram showing the oxidation process after oxidation in related technologies.

[0031] Figure 5 yes Figure 4 A schematic diagram of the cross-section in the AA′ direction.

[0032] Figure 6 yes Figure 4 Schematic diagram of the cross section in the BB′ direction.

[0033] Figure 7 This is a top view diagram of the process after removing the hard mask layer in related technologies.

[0034] Figure 8 yes Figure 7 A schematic diagram of the cross-section in the AA′ direction.

[0035] Figure 9 yes Figure 7 Schematic diagram of the cross section in the BB′ direction.

[0036] Figure 10 This is a top view schematic diagram of the gate after it has been formed in the related technology.

[0037] Figure 11 yes Figure 10 A schematic diagram of the cross-section in the AA′ direction.

[0038] Figure 12 yes Figure 10 Schematic diagram of the cross section in the BB′ direction.

[0039] Figure 13 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application.

[0040] Figure 14 This is a top view schematic diagram of the hard mask layer after its formation, provided in an embodiment of this application.

[0041] Figure 15 yes Figure 14 A schematic diagram of the cross-section in the BB′ direction.

[0042] Figure 16 This is a top view schematic diagram of the oxidation process provided in one embodiment of this application.

[0043] Figure 17 yes Figure 16 A schematic diagram of the cross-section in the BB′ direction.

[0044] Figure 18 This is a top view schematic diagram of the hard mask layer after removal, provided in an embodiment of this application.

[0045] Figure 19 yes Figure 18 A schematic diagram of the cross-section in the BB′ direction.

[0046] Figure 20 This is a top view schematic diagram of the bird's beak after the oxide layer has been removed, according to an embodiment of this application.

[0047] Figure 21 yes Figure 20 A schematic diagram of the cross-section in the BB′ direction.

[0048] Figure 22 This is a top view schematic diagram of the gate after it has been formed, provided in an embodiment of this application.

[0049] Figure 23 yes Figure 22 A schematic diagram of the cross-section in the BB′ direction.

[0050] Figure 24 This is a top view schematic diagram of the formation of a hard mask layer provided in another embodiment of this application.

[0051] Figure 25 yes Figure 24 A schematic diagram of the cross section in the AA′ direction.

[0052] Figure 26 This is a top view schematic diagram of the oxidation process provided in another embodiment of this application.

[0053] Figure 27 yes Figure 26 A schematic diagram of the cross section in the AA′ direction.

[0054] Figure 28 This is a top view schematic diagram of the hard mask layer after removal, provided in another embodiment of this application.

[0055] Figure 29 yes Figure 28 A schematic diagram of the cross section in the AA′ direction.

[0056] Figure 30 This is a top view schematic diagram of the bird's beak after the oxide layer has been removed, provided in another embodiment of this application.

[0057] Figure 31 yes Figure 30 A schematic diagram of the cross section in the AA′ direction.

[0058] Figure 32 This is a top view schematic diagram of the gate after it has been formed, provided in another embodiment of this application.

[0059] Figure 33 yes Figure 32 A schematic diagram of the cross section in the AA′ direction.

[0060] Figure 34 yes Figure 7 A schematic diagram of a scanning electron microscope in the BB′ direction.

[0061] Figure 35 yes Figure 20 A schematic diagram of a scanning electron microscope in the BB′ direction.

[0062] Explanation of reference numerals in the attached figures:

[0063] 10-Substrate; 11-Active region; 12-Isolation structure; 13-Hard mask layer; 14-Field oxide layer region; 15-Field oxide layer; 16-Gate; 17-Source / drain region; 18-Isolation region; 19-Bird's beak oxide layer. Detailed Implementation

[0064] Figure 1 This is a top-view schematic diagram showing the formation of a hard mask layer in related technologies. Figure 2 yes Figure 1 A schematic diagram of the cross-section in the AA′ direction. Figure 3 yes Figure 1 A schematic diagram of the cross-section in the BB′ direction. Please refer to... Figures 1 to 3 As shown, the substrate 10 includes a first region I for forming a DMOS device and a second region II for forming a CMOS device, such as a low-voltage or medium-voltage device. Active regions 11 and isolation structures 12 surrounding the active regions 11 are formed in both the first region I and the second region II, and the first region I and the second region II are also isolated by the isolation structures 12. A hard mask layer 13 is formed on the substrate 10, exposing a field oxide layer region 14 within the first region I to be formed, while completely covering the second region II. It is understood that in the top view, only the portion of the isolation structure 12 and the portion of the active region 11 exposed by the hard mask layer 13 and the field oxide layer region 14 are actually visible. Figure 1 To clearly illustrate the positional relationship between the active region 11 and the field oxide layer region 14, the active region 11 within the first region I and the second region II is also shown.

[0065] Figure 4 This is a top-view diagram showing the oxidation process in related technologies. Figure 5 yes Figure 4 Schematic diagram of the cross section in the AA′ direction. Figure 6 yes Figure 4 A schematic diagram of the cross-section in the BB′ direction. Please refer to... Figures 4 to 6As shown, the oxidation process forms a field oxide layer 15 in the field oxide layer region 14 within the first region I, while the second region II is covered by the hard mask layer 13 and remains unchanged. It is understood that the field oxide layer 15 is formed only on the substrate 10 within the field oxide layer region 14, and not on the isolation structure 12 within the field oxide layer region 14.

[0066] Figure 7 This is a schematic diagram of the structure after removing the hard mask layer in related technologies. Figure 8 yes Figure 7 Schematic diagram of the cross section in the AA′ direction. Figure 9 yes Figure 7 Top view diagram in the BB′ direction. Please refer to... Figures 7 to 9 As shown, the hard mask layer 13 is removed. In this embodiment, the above steps only form a field oxide layer 15 in the first region I, and no film layer is formed in the second region II.

[0067] Figure 10 This is a top view schematic diagram of the gate after it has been formed in the related technology. Figure 11 yes Figure 10 Schematic diagram of the cross section in the AA′ direction. Figure 12 yes Figure 10 A schematic diagram of the cross-section in the BB′ direction. Please refer to... Figures 10 to 12 As shown, a gate 16 is formed. In the first region I, the gate 16 covers a portion of the substrate 10 and a portion of the field oxide layer 15. In the second region II, the gate 16 covers a portion of the substrate 10. The process further includes forming source / drain regions 17 in the substrate 10 on both sides of the gate 16.

[0068] As described in the background art, in the above-mentioned semiconductor device fabrication method, as the channel width shrinks, a series of significant physical effects are triggered, including the drift of the threshold voltage and the decrease in drive current due to the reduction in effective channel width.

[0069] To address the aforementioned issues, research has shown that setting the active region to an upwardly curved shape can increase the effective width / length of the device, thereby simultaneously suppressing threshold voltage drift and increasing the device's drive current, achieving a high-performance, low-power, and highly reliable semiconductor device.

[0070] Further research reveals that this application provides a method for fabricating a semiconductor device, comprising: providing a substrate, the substrate including a first region for forming a DMOS device and a second region for forming a CMOS device, wherein active regions and isolation structures surrounding the active regions are formed in both the first and second regions; forming a hard mask layer on the substrate, the hard mask layer exposing a field oxide layer region in the first region where a predetermined field oxide layer is formed, and simultaneously exposing an isolation region in the second region where a portion of the isolation structure adjacent to the active region is located; performing an oxidation process to form a field oxide layer in the field oxide layer region in the first region, and forming a bird's beak oxide layer on the active region in the second region, the bird's beak oxide layer having a morphology that is thin in the middle and thick at the edges; and removing the hard mask layer and the bird's beak oxide layer to expose an active region in the second region whose upper surface is curved upwards.

[0071] Accordingly, this application also provides a semiconductor device, comprising: a substrate, the substrate including a first region for forming a DMOS device and a second region for forming a CMOS device, wherein an active region and an isolation structure surrounding the active region are formed in both the first region and the second region; the upper surface of the active region in the second region is bent; and a field oxide layer located on the substrate in the first region.

[0072] To make the objectives, advantages, and features of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, used only to facilitate and clarify the illustration of the embodiments of this application. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0073] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to include “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to include “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to include “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0074] Figure 13 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this application. Please refer to... Figure 13 As shown, the method for fabricating a semiconductor device provided in this application includes the following steps:

[0075] S1: Provide a substrate, the substrate including a first region for forming a DMOS device and a second region for forming a CMOS device, wherein an active region and an isolation structure surrounding the active region are formed in both the first region and the second region;

[0076] S2: A hard mask layer is formed on the substrate, the hard mask layer exposing the field oxide layer region in the first region where a field oxide layer is to be formed, and simultaneously exposing the isolation region in the second region where a portion of the isolation structure adjacent to the active region is located;

[0077] S3: An oxidation process is performed to form a field oxide layer in the field oxide layer region of the first region, and a beak oxide layer is formed on the active region of the second region, the beak oxide layer having a morphology that is thin in the middle and thick at the edges; and,

[0078] S4: Remove the hard mask layer and the beak oxide layer to expose the active region with the upper surface curved upwards in the second region.

[0079] This application exposes the isolation region containing a portion of the isolation structure adjacent to the active region within the second region. Then, an oxidation process is performed to form a bird's beak oxide layer with a thin center and thick edges on the active region within the second region. Removing the bird's beak oxide layer causes the upper surface of the active region within the second region to bend upwards, thus forming a curved active region. This increases the effective width / length of the device without increasing the active region layout size, thereby simultaneously suppressing threshold voltage drift and increasing the device's drive current, achieving high performance, low power consumption, and improved reliability. Furthermore, this application exposes the isolation region within the second region while simultaneously exposing the field oxide layer region within the first region. Forming the bird's beak oxide layer while forming the field oxide layer does not add process steps, thus achieving performance improvement for CMOS devices without increasing process steps and reducing costs.

[0080] The following detailed description of the method for fabricating the semiconductor device provided in this application is provided through specific embodiments.

[0081] Figures 14 to 23 This is a schematic diagram of the steps involved in fabricating a semiconductor structure according to an embodiment of this application. Next, we will combine... Figure 13 , Figures 14 to 23 A method for fabricating a semiconductor device according to an embodiment of this application will be described in detail.

[0082] In this embodiment, the hard mask layer exposes the field oxide layer region in the first region where a field oxide layer is to be formed, and at the same time exposes the isolation region where part of the isolation structure is located on both sides of the active region in the first direction (i.e., both sides of the short side direction of the active region) in the second region. The bird's beak oxide layer formed thereby has a shape that is thin in the middle and thick at the edges in the first direction, so that the upper surface of the active region in the second region is bent upward in the first direction, thereby increasing the channel width of the device and thus improving the performance of the device.

[0083] Figure 14 This is a top view schematic diagram of the hard mask layer after its formation, provided in an embodiment of this application. Figure 15 yes Figure 14 A schematic diagram of the cross-section in the BB′ direction. In step S1, please refer to... Figure 14 and Figure 15 As shown, a substrate 10 is provided, the substrate 10 including a first region I for forming a DMOS device and a second region II for forming a CMOS device, wherein an active region 11 and an isolation structure 12 surrounding the active region 11 are formed in both the first region I and the second region II.

[0084] The substrate 10 can be made of silicon, germanium, silicon germanide, silicon carbide, or other materials, such as gallium arsenide, gallium nitride, or indium gallium nitride, or silicon-on-insulator, germanium-on-insulator, etc. In this embodiment, the substrate 10 is a silicon substrate.

[0085] The substrate 10 includes two regions, a first region I and a second region II, wherein the first region I is used to form a DMOS device and the second region II is used to form a CMOS device. In one embodiment, the CMOS device is a low-voltage device or a medium-voltage device, but is not limited thereto. In another embodiment, the substrate 10 may further include regions for forming other devices.

[0086] An isolation structure 12 is formed within the substrate 10, the isolation structure 12 surrounding the active region 11, and adjacent regions are also isolated from each other by the isolation structure 12. In one embodiment, the isolation structure 12 is a shallow trench isolation structure.

[0087] In step S2, please continue to refer to Figure 14 and Figure 15 As shown, a hard mask layer 13 is formed on the substrate 10. The hard mask layer 13 exposes the field oxide layer region 14 in the first region I where a field oxide layer is to be formed, and at the same time exposes the isolation region 18 on both sides of the active region 11 in the first direction x in the second region II where the isolation structures 12 are located.

[0088] Please refer to Figure 14 As shown, the hard mask layer 13 exposes the field oxide layer region 14 within the first region I. The field oxide layer region 14 exposes a portion of the active region 11 within the first region I and portions of the isolation structures 12 on both sides of the active region 11 in the first direction x. The hard mask layer 13 also exposes two isolation regions 18 within the second region II, located on both sides of the active region 11 in the first direction x within the second region II. It is understood that in the top view, only the hard mask layer 13, the field oxide layer region 14, and the two isolation regions 18 are actually visible. Figure 14 To clearly illustrate the positional relationship between the active region 11, the field oxide layer region 14, and the two isolation regions 18, the active region 11 within the first region I and the second region II is also shown.

[0089] The two isolation regions 18 may be symmetrically located on either side of the active region 11. In one embodiment, the ratio of the size of the isolation region 18 in the first direction x to the size of the active region 11 in the first direction x is 10% to 30%. For example, the size of the isolation region 18 in the first direction x is 100nm to 2000nm, but it is not limited to this.

[0090] In one embodiment, the distance from the edge of the isolation region 18 near the active region 11 to the active region 11 is 0~1μm. Please refer to... Figure 15 As shown, in this embodiment, the edge of the isolation region 18 coincides with the edge of the active region 11, that is, the distance from the edge of the isolation region 18 to the active region 11 is 0.

[0091] In one embodiment of this application, a hard mask material layer and a photoresist layer are first formed on the substrate 10. Then, the photoresist layer is exposed and developed using a mask to form a patterned photoresist layer. Next, the hard mask material layer is etched using the patterned photoresist layer as a mask to form a hard mask layer 13. Finally, the patterned photoresist layer is removed. In this embodiment, the mask exposes the field oxide layer region 14 in the first region I and the isolation regions 18 on both sides of the active region 11 in the first direction x in the second region II, where the isolation structures 12 are located.

[0092] In one embodiment of this application, the hard mask layer 13 includes an oxide layer and a nitride layer stacked sequentially. For example, the hard mask layer 13 includes a silicon oxide layer and a silicon nitride layer stacked sequentially. In other embodiments, the hard mask layer 13 may also be a single-layer film.

[0093] Figure 16 This is a top view schematic diagram of the oxidation process provided in one embodiment of this application. Figure 17 yes Figure 16 A schematic diagram of the cross-section in the BB′ direction. In step S3, please refer to... Figure 16 and Figure 17 As shown, an oxidation process is performed to form a field oxide layer 15 in the field oxide layer region 14 within the first region I, and a bird's beak oxide layer 19 is formed on the active region 11 within the second region II. The bird's beak oxide layer 19 has a morphology that is thin in the middle and thick at the edges in the first direction x.

[0094] In this embodiment, during the oxidation process, the substrate 10 exposed in the first region I is oxidized to form a field oxide layer 15. Simultaneously, in the second region II, because the areas containing the isolation structures 12 on both sides of the active region 11 in the first direction x (i.e., isolation regions 18) are exposed, the oxidant undergoes lateral diffusion during the oxidation process, reaching the hard mask layer 13 ( Figure 17 The edge of the hard mask layer 13 between the two isolation structures 12 reacts with the substrate 10 to form an oxide layer. The oxidant diffuses laterally from the edge inward. The oxide layer formed below the edge of the hard mask layer 13 is thicker, while the oxide layer formed inside the hard mask layer 13 is thinner, ultimately forming a bird's beak-shaped oxide layer. In this embodiment, please refer to... Figure 17 As shown, the oxidant diffuses from the edges of the two isolation regions 18 into the substrate 10, and the resulting beak oxide layer 19 has a morphology that is thin in the middle and thick at the edges, resembling two bird beaks. In this embodiment, the two beaks are in contact; in other embodiments, the two beaks may not be in contact.

[0095] In one embodiment of this application, both the field oxide layer 15 and the bird's beak oxide layer 19 are made of silicon oxide. The field oxide layer 15 and the bird's beak oxide layer 19 can be formed using wet oxidation or dry oxidation methods.

[0096] It is understood that the field oxide layer 15 is formed only on the substrate 10 within the field oxide layer region 14, and the field oxide layer 15 is not formed on the isolation structure 12 within the field oxide layer region 14.

[0097] Figure 18 This is a top view schematic diagram of the result after removing the hard mask layer according to an embodiment of this application. Figure 19 yes Figure 18 A schematic diagram of the cross-section in the BB′ direction. Figure 20 This is a top view schematic diagram of the bird's beak after removing the oxide layer according to an embodiment of this application. Figure 21 yes Figure 20A schematic diagram of the cross-section in the BB′ direction. In step S4, please first refer to... Figure 18 and Figure 19 As shown, the hard mask layer 13 is removed, at which point the field oxide layer 15 is formed in the first region I, the field oxide layer 15 being located above a portion of the active region 11, and the beak oxide layer 19 is formed in the second region II, the beak oxide layer 19 being located above the active region 11. Then please refer to... Figure 20 and Figure 21 As shown, the beak oxide layer 19 is removed, causing the upper surface of the active region 11 within the second region II to bend upwards in the first direction x. It should be noted that the hard mask layer 13 and the beak oxide layer 19 can be removed together, thus reusing existing processes. Removing the beak oxide layer 19 simultaneously with removing the hard mask layer 13 does not add any process steps.

[0098] Because the beak-shaped oxide layer 19 is thinner in the middle and thicker at the edges, the upper surface of the active region 11 curves upward, meaning the active region 11 is higher in the middle and lower at the edges. This increases the width of the device channel, thereby simultaneously suppressing threshold voltage drift and increasing the device's drive current, achieving a high-performance, low-power, and high-reliability semiconductor device.

[0099] Figure 22 This is a top view schematic diagram of the gate after its formation according to an embodiment of this application. Figure 23 yes Figure 22 A schematic diagram of the cross-section in the BB′ direction. Please refer to... Figure 22 and Figure 23 As shown, after removing the beak oxide layer 19, the method further includes: forming a gate 16 on the substrate 10 in the first region I and the second region II, wherein the gate 16 in the first region I covers a portion of the active region 11 and a portion of the field oxide layer 15, and the gate 16 in the second region II covers a portion of the active region 11. The method further includes: forming source / drain regions 17 in the substrate 10 on both sides of the gate 16.

[0100] In the semiconductor device fabrication method provided in this embodiment, by exposing the isolation regions 18 containing the isolation structures 12 on both sides of the active region in the first direction x within the second region II, an oxidation process is performed to form a bird's beak oxide layer 19 with a thin center and thick edges on the active region 11 in the second region II. After removing the bird's beak oxide layer 19, the upper surface of the active region in the second region II is bent upward in the first direction x, thus forming a curved surface active region 11. This increases the channel width of the device, thereby simultaneously suppressing threshold voltage drift and increasing the drive current of the device, achieving high performance, low power consumption, and improved reliability. Furthermore, in this application, the isolation regions 18 in the second region II are exposed simultaneously with the field oxide layer region 14 in the first region I, and the bird's beak oxide layer 19 is formed simultaneously with the field oxide layer 15. This does not increase the number of process steps, thus achieving performance improvement of the CMOS device without increasing the number of process steps and reducing production costs.

[0101] Figures 24 to 33 This is a schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to another embodiment of this application. Next, we will combine... Figure 13 , Figures 24 to 33 A method for fabricating a semiconductor device according to another embodiment of this application will be described in detail.

[0102] In this embodiment, the hard mask layer exposes the field oxide layer region in the first region where a predetermined field oxide layer is formed, and at the same time exposes the isolation region where part of the isolation structure is located on both sides of the active region in the second direction (i.e., both sides of the long side direction of the active region) in the second region. The bird's beak oxide layer formed thereby has a shape that is thin in the middle and thick at the edges in the second direction, so that the upper surface of the active region in the second region is bent upward in the second direction, thereby increasing the channel length of the device and thus improving the performance of the device.

[0103] Figure 24 This is a top view schematic diagram of the hard mask layer after its formation, provided in another embodiment of this application. Figure 25 yes Figure 24 A schematic diagram of the cross-section in the AA′ direction. In step S1, please refer to... Figure 24 and Figure 25 As shown, a substrate 10 is provided, the substrate 10 including a first region I for forming a DMOS device and a second region II for forming a CMOS device, wherein an active region 11 and an isolation structure 12 surrounding the active region 11 are formed in both the first region I and the second region II.

[0104] In step S2, please continue to refer to Figure 24 and Figure 25As shown, a hard mask layer 13 is formed on the substrate 10. The hard mask layer 13 exposes the field oxide layer region 14 in the first region I where a field oxide layer is to be formed, and at the same time exposes the isolation region 18 on both sides of the active region 11 in the second region II where the isolation structures 12 are located, wherein the first direction x is perpendicular to the second direction y.

[0105] Please refer to Figure 24 As shown, the hard mask layer 13 exposes the field oxide layer region 14 within the first region I. The field oxide layer region 14 exposes a portion of the active region 11 within the first region I and portions of the isolation structures 12 on both sides of the active region 11 in the first direction x. The hard mask layer 13 also exposes two isolation regions 18 within the second region II, located on both sides of the active region 11 in the second direction y within the second region II. It is understood that in the top view, only the hard mask layer 13, the field oxide layer region 14, and the two isolation regions 18 are actually visible. Figure 24 To clearly illustrate the positional relationship between the two active regions 11 and the field oxide layer region 14 and the two isolation regions 18, the active regions 11 in the first region I and the second region II are also shown.

[0106] The two isolation regions 18 may be symmetrically located on either side of the active region 11. In one embodiment, the ratio of the size of the isolation region 18 in the second direction y to the size of the active region 11 in the second direction y is 10% to 30%. For example, the size of the isolation region 18 in the second direction y is 100nm to 2000nm, but it is not limited to this.

[0107] In one embodiment, the distance from the edge of the isolation region 18 closest to the active region 11 to the active region 11 is 0~1μm. Please refer to... Figure 25 As shown, in this embodiment, the edge of the isolation region 18 coincides with the edge of the active region 11, that is, the distance from the edge of the isolation region 18 to the active region 11 is 0.

[0108] Figure 26 This is a top view schematic diagram of the oxidation process provided in another embodiment of this application. Figure 27 yes Figure 26 A schematic diagram of the cross-section in the AA′ direction. In step S3, please refer to... Figure 26 and Figure 27As shown, an oxidation process is performed to form a field oxide layer 15 in the field oxide layer region 14 within the first region I, and a bird's beak oxide layer 19 is formed on the active region 11 within the second region II. The bird's beak oxide layer 19 has a morphology that is thin in the middle and thick at the edges in the second direction y.

[0109] In this embodiment, during the oxidation process, the substrate 10 exposed in the first region I is oxidized to form a field oxide layer 15. Simultaneously, in the second region II, because the areas containing the isolation structures 12 on both sides of the active region 11 in the second direction y (i.e., isolation regions 18) are exposed, the oxidant undergoes lateral diffusion during the oxidation process, reaching the hard mask layer 13 ( Figure 27 The edge of the hard mask layer 13 (between the two isolation structures 12) reacts with the substrate 10 to form an oxide layer. The oxidant diffuses laterally from the edge inward. The oxide layer formed below the edge of the hard mask layer 13 is thicker, while the oxide layer formed inside the hard mask layer 13 is thinner, ultimately forming a bird's beak-shaped oxide layer. In this embodiment, please refer to... Figure 27 As shown, the oxidant diffuses from the edges of the two isolation regions 18 into the substrate 10, and the resulting beak oxide layer 19 has a morphology that is thin in the middle and thick at the edges, resembling two bird beaks. In this embodiment, the two beaks are in contact; in other embodiments, the two beaks may not be in contact.

[0110] Figure 28 This is a top view schematic diagram of the result after removing the hard mask layer, provided in another embodiment of this application. Figure 29 yes Figure 28 A schematic diagram of the cross section in the AA′ direction. Figure 30 This is a top view schematic diagram of the bird's beak after the oxide layer has been removed, according to another embodiment of this application. Figure 31 yes Figure 30 A schematic diagram of the cross-section in the AA′ direction. In step S4, please first refer to... Figure 28 and Figure 29 As shown, the hard mask layer 13 is removed, at which point the field oxide layer 15 is formed in the first region I, the field oxide layer 15 being located above a portion of the active region 11, and the beak oxide layer 19 is formed in the second region II, the beak oxide layer 19 being located above the active region 11. Then please refer to... Figure 30 and Figure 31 As shown, the beak oxide layer 19 is removed, causing the upper surface of the active region 11 within the second region II to bend upwards in the second direction y. It should be noted that the hard mask layer 13 and the beak oxide layer 19 can be removed together, thus reusing existing processes. Removing the beak oxide layer 19 simultaneously with removing the hard mask layer 13 does not add any process steps.

[0111] Because the beak-shaped oxide layer 19 is thin in the middle and thick at the edges, the upper surface of the active region 11 has an upwardly curved surface, meaning the active region 11 is high in the middle and low at the edges. This increases the length of the device channel, thereby simultaneously suppressing threshold voltage drift and increasing the device's drive current, achieving a high-performance, low-power, and high-reliability semiconductor device.

[0112] Figure 32 This is a top view schematic diagram of the gate after its formation, provided in another embodiment of this application. Figure 33 yes Figure 32 A schematic diagram of the cross-section in the AA′ direction. Please refer to... Figure 32 and Figure 33 As shown, after removing the beak oxide layer 19, the method further includes: forming a gate 16 on the substrate 10 in the first region I and the second region II, wherein the gate 16 in the first region I covers a portion of the active region 11 and a portion of the field oxide layer 15, and the gate 16 in the second region II covers a portion of the active region 11. The method further includes: forming source / drain regions 17 in the substrate 10 on both sides of the gate 16.

[0113] In the semiconductor device fabrication method provided in this embodiment, by exposing the isolation regions 18 containing the isolation structures 12 on both sides of the active region in the second direction y within the second region II, and then performing an oxidation process, a bird's beak oxide layer 19 with a thin center and thick edges is formed on the active region 11 in the second region II. After removing the bird's beak oxide layer 19, the upper surface of the active region in the second region II is bent upward in the second direction y, thus forming a surface-bent active region 11. This increases the channel length of the device, thereby simultaneously suppressing threshold voltage drift and increasing the drive current of the device, achieving high performance, low power consumption, and improved reliability. Furthermore, in this application, the isolation regions 18 in the second region II are exposed simultaneously with the field oxide layer region 14 in the first region I, and the bird's beak oxide layer 19 is formed simultaneously with the field oxide layer 15. This does not increase the number of process steps, thus achieving an improvement in CMOS performance without increasing the number of process steps and reducing production costs.

[0114] Figure 34 yes Figure 7 A schematic diagram of a scanning electron microscope in the BB′ direction. Figure 35 yes Figure 20 A schematic diagram of a scanning electron microscope in the BB′ direction, for comparison. Figure 34 and Figure 35 It is understood that the semiconductor device fabrication method provided in this application can form an upwardly curved active region 11.

[0115] Accordingly, this application also provides a semiconductor device fabricated using the semiconductor device fabrication method described above. Please refer to... Figure 23 and Figure 33 As shown, the semiconductor device provided in this application embodiment includes:

[0116] Substrate 10, the substrate 10 including a first region I for forming a DMOS device and a second region II for forming a CMOS device, wherein active regions 11 and isolation structures 12 surrounding the active regions 11 are formed in both the first region I and the second region II; the active regions 11 in the second region II are bent upward; and,

[0117] A field oxide layer 15 is located on the substrate 10 in the first region I.

[0118] Please refer to Figure 22 and Figure 23 As shown, the upper surface of the active region 11 in the second region II is bent upward in the first direction x, thereby increasing the channel width of the device, which can simultaneously suppress threshold voltage drift and increase the drive current of the device, achieving high performance, low power consumption and improved reliability.

[0119] Please refer to Figure 32 and Figure 33 As shown, the upper surface of the active region 11 in the second region II is bent upward in the second direction y, thereby increasing the channel length of the device, which can simultaneously suppress threshold voltage drift and increase the drive current of the device, achieving high performance, low power consumption and improved reliability.

[0120] In one embodiment of this application, a gate 16 and a source / drain region 17 are further included. In the first region I, the gate 16 covers a portion of the substrate 10 and a portion of the field oxide layer 15. In the second region II, the gate 16 covers a portion of the substrate 10. The source / drain region 17 is located in the substrate 10 on both sides of the gate 16 (the gate 16 is on both sides of the second direction y).

[0121] In summary, the semiconductor device and its fabrication method provided in this application firstly provide a substrate, the substrate including a first region for forming a DMOS device and a second region for forming a CMOS device. Both the first and second regions have active regions and isolation structures surrounding the active regions. Then, a hard mask layer is formed on the substrate, exposing a field oxide layer region in the first region where a predetermined field oxide layer is formed, and simultaneously exposing an isolation region in the second region containing a portion of the isolation structure adjacent to the active region. Next, an oxidation process is performed to form a field oxide layer in the field oxide layer region in the first region and a bird's beak oxide layer on the active region in the second region, the bird's beak oxide layer having a thin center and thick edges. Finally, the hard mask layer and the bird's beak oxide layer are removed, causing the upper surface of the active region in the second region to bend upwards. In this application, by exposing the isolation region containing a portion of the isolation structure adjacent to the active region within the second region, an oxidation process is performed to form a bird's beak oxide layer with a thin center and thick edges on the active region within the second region. After removing the bird's beak oxide layer, the upper surface of the active region within the second region bends upward, forming a surface-bent active region. This increases the effective size of the device channel region, thereby simultaneously suppressing threshold voltage drift and increasing the device's drive current, achieving high performance, low power consumption, and improved reliability. Furthermore, this application exposes the isolation region within the second region while simultaneously exposing the field oxide layer region within the first region. Forming the bird's beak oxide layer while forming the field oxide layer does not add process steps, thus achieving performance improvement of the CMOS device without increasing process steps and reducing production costs.

[0122] The above description is merely a description of preferred embodiments of this application and is not intended to limit the scope of this application in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a first region for forming a DMOS device and a second region for forming a CMOS device, wherein an active region and an isolation structure surrounding the active region are formed in both the first region and the second region; A hard mask layer is formed on the substrate, which exposes the field oxide layer region in the first region where a field oxide layer is to be formed, and at the same time exposes the isolation region in the second region where a portion of the isolation structure adjacent to the active region is located; An oxidation process is performed to form a field oxide layer in the field oxide layer region of the first region and a bird's beak oxide layer on the active region of the second region, wherein the bird's beak oxide layer has a morphology that is thin in the middle and thick at the edges; as well as, Remove the hard mask layer and the beak oxide layer to expose the active region with its upper surface curved upwards in the second region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method for forming a hard mask layer on the substrate includes: A hard mask material layer and a photoresist layer are formed on the substrate; The photoresist layer is exposed and developed to form a patterned photoresist layer. Using the patterned photoresist layer as a mask, the hard mask material layer is etched to expose the field oxide region in the first region and the isolation region in the second region; and, Remove the patterned photoresist layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The hard mask layer exposes the isolation areas containing the isolation structures on both sides of the active region in the second region in the first direction, and / or the hard mask layer exposes the isolation areas containing the isolation structures on both sides of the active region in the second region in the second direction, wherein the first direction is perpendicular to the second direction.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The isolation areas exposed on both sides of the active region in the first direction are symmetrical; or / and the isolation areas exposed on both sides of the active region in the second direction are symmetrical.

5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The ratio of the size of the isolation region in the first direction to the size of the active region in the first direction is 10% to 30%; or / and the ratio of the size of the isolation region in the second direction to the size of the active region in the second direction is 10% to 30%.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The distance from the edge of the exposed isolation area near the active region to the active region is 0~1μm.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The hard mask layer comprises a silicon oxide layer and a silicon nitride layer stacked sequentially.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After removing the beak oxide layer, the method further includes: forming a gate on the substrate in the first region and the second region, wherein the gate in the first region covers a portion of the substrate and a portion of the field oxide layer; and forming source / drain regions in the substrate on both sides of the gate.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, The CMOS devices include low-voltage devices or medium-voltage devices.

10. A semiconductor device, characterized in that, include: The substrate includes a first region for forming a DMOS device and a second region for forming a CMOS device, wherein an active region and an isolation structure surrounding the active region are formed in both the first region and the second region; the upper surface of the active region in the second region is bent upward. as well as, A field oxide layer is located on the substrate in the first region.

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