NOR gate device and method for manufacturing the same
By using a three-dimensional arrangement and dual-input port gate integrated NOR gate structure, the problem of layout area compression is solved, realizing a highly integrated NOR gate device with low leakage current and significantly reduced area.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-06-16
AI Technical Summary
The layout area of existing NOR gate devices is difficult to compress, and the physical layout in two-dimensional space limits the improvement of integration density.
By employing a three-dimensional arrangement of a P-type substrate, an N-type substrate, a first P-type doped region, a second P-type doped region, an N-type doped region, a first gate structure, and a second gate structure, and combining a buried gate with a conventional gate, a shared irregular gate NOR gate structure is formed, thereby realizing dual-input port gate integration.
The layout area of the NOR gate is significantly reduced, leakage current is reduced, forming a low-leakage 3D NOR gate device, which occupies 60%~70% less area, and avoids the risk of leakage current during the transition state of the series PMOS pull-up transistor.
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Figure CN122227664A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and in particular to a NOR gate device and its fabrication method. Background Technology
[0002] As integrated circuits continue to develop towards higher integration and smaller size, the demand for the number of logic gates per unit area of chips is increasing. As a core general-purpose logic device in mathematical logic, the layout area of NOR gates directly affects the overall integration density of the chip.
[0003] Currently, NOR gates generally employ a two-dimensional planar structure, with each gate consisting of four independent transistors. Two P-channel MOS transistors (PMOS) are connected in series as pull-up diodes connected to the power supply, and two N-channel MOS transistors (NMOS) are connected in parallel as pull-down diodes connected to ground. A single NOR gate must occupy the entire layout space of four independent transistors, and isolation gaps must be reserved between the transistors to avoid crosstalk between devices. Due to the limitations of the two-dimensional physical layout, even with miniaturization through photolithography or optimization of the planar layout design, the reduction in the layout area of NOR gates remains limited.
[0004] Therefore, how to reduce the layout area of NOR gates becomes a problem that needs to be solved. Summary of the Invention
[0005] To address the aforementioned issues, this application provides a NOR gate device and its fabrication method, which can reduce the layout area of the NOR gate.
[0006] The embodiments of this application disclose the following technical solutions:
[0007] In a first aspect, embodiments of this application provide a NOR gate device, the device comprising: a P-type substrate, an N-type substrate, a first P-type doped region, a second P-type doped region, an N-type doped region, a first gate structure, and a second gate structure;
[0008] The P-type substrate, the first gate structure, and the N-type substrate are arranged sequentially along a first direction; one side of the first gate structure is embedded in the N-type substrate, and the other side is in contact with the sidewall of the P-type substrate; the P-type substrate and the N-type substrate are separated.
[0009] The second gate structure is stacked with the first gate structure along a third direction; the third direction is perpendicular to the plane containing the P-type substrate and the N-type substrate.
[0010] The two N-type doped regions are located at both ends of the P-type substrate near the N-type substrate, and the first gate structure is in contact with the undoped region of the P-type substrate;
[0011] The two first P-type doped regions are disposed on both sides of the first gate structure in the N-type substrate, and are located on the side of the N-type substrate closer to the P-type substrate;
[0012] The two second P-type doped regions are disposed on both sides of the first gate structure in the N-type substrate, and are located on the side of the first gate structure away from the P-type substrate.
[0013] Optionally, the first P-type doped region includes a first lightly doped P-type region and a first heavily doped P-type region; the doping concentration and doping depth of the first heavily doped P-type region are both greater than those of the first lightly doped P-type region.
[0014] The first P-type heavily doped region is located on the side of the first P-type lightly doped region near the edge of the N-type substrate.
[0015] Optionally, the first gate structure includes: three first spacer layers and a first gate;
[0016] The two first spacer layers are respectively disposed at both ends of the portion of the first gate not embedded in the N-type substrate in the second direction, for isolating the first gate from the first P-type doped region and the N-type doped region; the second direction is perpendicular to the first direction and located in the plane where the P-type substrate and the N-type substrate are located;
[0017] A first spacer layer is disposed at one end of the first gate embedded portion of the N-type substrate that contacts the N-type substrate in a first direction.
[0018] Optionally, the second P-type doped region is in contact with the first gate structure, and the second P-type doped region is isolated from the first gate through the first spacer layer.
[0019] Optionally, the first gate structure further includes: a first gate dielectric layer;
[0020] The first gate dielectric layer is located on the first gate sidewall.
[0021] Optionally, the second gate structure includes: a second spacer layer and a second gate;
[0022] Two second spacer layers are disposed at both ends of the second gate in the second direction; the second gate and the first gate are of equal length in the second direction; the second direction is perpendicular to the first direction and is located in the plane containing the P-type substrate and the N-type substrate.
[0023] Optionally, the height of the first gate structure in the third direction is greater than or equal to the height of the P-type substrate and the N-type substrate in the third direction.
[0024] Optionally, the device further includes an insulating barrier located between the first P-type doped region and the N-type doped region.
[0025] Secondly, embodiments of this application provide a method for fabricating a NOR gate device, the method comprising:
[0026] Provide a base;
[0027] A substrate is epitaxially grown on the substrate;
[0028] By etching, trenches are formed that divide the substrate into a first substrate and a second substrate, as well as grooves located on the opposite side of the sidewalls of the first substrate and the second substrate;
[0029] The first substrate is subjected to N-type ion implantation to form an N-type substrate; the second substrate is subjected to P-type ion implantation to form a P-type substrate.
[0030] A first gate structure is fabricated within the trench and the recess; one side of the first gate structure is embedded in the N-type substrate, and the other side is in contact with the sidewall of the P-type substrate.
[0031] A second gate structure is fabricated above the first gate structure, the N-type substrate, and the P-type substrate; the second gate structure and the first gate structure are stacked along a third direction; the third direction is perpendicular to the plane containing the P-type substrate and the N-type substrate;
[0032] N-type ion implantation is performed at both ends of the P-type substrate near the N-type substrate to form an N-type doped region;
[0033] On the side of the N-type substrate close to the P-type substrate, P-type ion implantation is performed on the N-type substrates on both sides of the first gate structure to form a first P-type doped region;
[0034] On the side of the first gate structure away from the P-type substrate, P-type ion implantation is performed on the N-type substrates on both sides of the first gate structure to form a second P-type doped region.
[0035] Optionally, the step of implanting N-type ions at both ends of the P-type substrate near the N-type substrate to form an N-type doped region includes:
[0036] N-type ion implantation is performed at both ends of the P-type substrate near the N-type substrate to form a lightly doped N-type region;
[0037] N-type ion implantation is performed again on the side of the N-type lightly doped region near the edge of the P-type substrate to form an N-type heavily doped region; the doping concentration and doping depth of the N-type heavily doped region are both greater than those of the N-type lightly doped region.
[0038] Compared with the prior art, this application has the following beneficial effects:
[0039] This application provides a NOR gate device, comprising: a P-type substrate, an N-type substrate, a first P-type doped region, a second P-type doped region, an N-type doped region, a first gate structure, and a second gate structure; wherein the P-type substrate, the first gate structure, and the N-type substrate are arranged sequentially along a first direction; one side of the first gate structure is embedded in the N-type substrate, and the other side is in contact with the sidewall of the P-type substrate; the P-type substrate and the N-type substrate are separated; the second gate structure and the first gate structure are stacked along a third direction; the third direction is perpendicular to the plane containing the P-type substrate and the N-type substrate; two N-type doped regions are disposed at both ends of the P-type substrate near the N-type substrate, and the first gate structure is in contact with the undoped region of the P-type substrate; two first P-type doped regions are disposed on both sides of the first gate structure in the N-type substrate, and are located on the side of the N-type substrate near the P-type substrate; two second P-type doped regions are disposed on both sides of the first gate structure in the N-type substrate, and are located on the side of the first gate structure away from the P-type substrate.
[0040] Thus, the P-type substrate, the first gate structure, and the N-type substrate are arranged along the first direction, and the second gate structure is located above the P-type substrate, the first gate structure, and the N-type substrate. The N-type substrate, the first P-type doped region, the second P-type doped region, and the gate structure constitute a PMOS, and the P-type substrate, the N-type doped region, and the gate structure constitute an NMOS. The first gate structure controls the sidewall channel, and the second gate structure controls the surface channel. The combination of the buried gate (first gate structure) and the conventional gate (second gate structure) realizes dual-input port gate integration, forming a NOR gate structure with a shared irregular gate. On the one hand, the buried gate sidewall and the conventional gate bottom realize the combination of carrier surface transport and vertical transport, breaking through the planar layout limitation and significantly compressing the layout area of the NOR gate; on the other hand, the series PMOS pull-up transistor does not have the leakage risk of the transition state, which reduces the leakage current of the NOR gate device, forming a low-leakage 3D NOR gate device. Attached Figure Description
[0041] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 A three-dimensional structural diagram of a NOR gate device provided in an embodiment of this application;
[0043] Figure 2A top cross-sectional view of a NOR gate device provided in an embodiment of this application;
[0044] Figure 3 A side cross-sectional view of a NOR gate device provided in an embodiment of this application;
[0045] Figure 4 An equivalent circuit diagram of a NOR gate is provided for an embodiment of this application;
[0046] Figure 5 A three-dimensional structural diagram of another NOR gate device provided in an embodiment of this application;
[0047] Figure 6 A top cross-sectional view of another NOR gate device provided in an embodiment of this application;
[0048] Figure 7 A top cross-sectional view of another NOR gate device provided in an embodiment of this application;
[0049] Figure 8 A three-dimensional structural diagram of another NOR gate device provided in an embodiment of this application;
[0050] Figure 9 This is a flowchart illustrating a method for fabricating a NOR gate device according to an embodiment of this application.
[0051] Explanation of reference numerals in the attached figures: 100-substrate; 101-first substrate; 102-second substrate; 110-P-type substrate; 120-N-type substrate; 210-first P-type doped region; 211-first P-type lightly doped region; 212-first P-type heavily doped region; 220-second P-type doped region; 221-second P-type lightly doped region; 222-second P-type heavily doped region; 230-N-type doped region; 231-N-type lightly doped region; 232-N-type heavily doped region; 310-first gate structure; 311-first spacer layer; 312-first gate; 313-first gate dielectric layer; 320-second gate structure; 321-second spacer layer; 322-second gate; 400-insulating barrier; 500-buried oxide layer. Detailed Implementation
[0052] The NOR gate device and its fabrication method provided in this application can be used in the field of semiconductor devices. The above is only an example and does not limit the application field of the NOR gate device and its fabrication method provided in this application.
[0053] The terms "first," "second," "third," and "fourth," etc., used in this application specification, claims, and drawings are used to distinguish different objects, not to limit a specific order.
[0054] In the embodiments of this application, the terms "as an example" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design that is described as "as an example" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Specifically, the use of terms such as "as an example" or "for example" is intended to present the relevant concepts in a specific manner.
[0055] The terminology used in the implementation section of this application is for the purpose of explaining specific embodiments of this application only, and is not intended to limit this application.
[0056] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0057] See Figure 1 The figure is a three-dimensional structural diagram of a NOR gate device provided in an embodiment of this application. The NOR gate device includes: a P-type substrate 110, an N-type substrate 120, a first P-type doped region 210, a second P-type doped region 220, an N-type doped region 230, a first gate structure 310, and a second gate structure 320.
[0058] The P-type substrate 110, the first gate structure 310, and the N-type substrate 120 are arranged sequentially along the first direction; one side of the first gate structure 310 is embedded in the N-type substrate 120, and the other side is in contact with the sidewall of the P-type substrate 110; the P-type substrate 110 and the N-type substrate 120 are separated.
[0059] Optionally, the P-type substrate 110 and the N-type substrate 120 can be formed on the substrate by epitaxial growth, such as on the buried oxide layer 500 in the substrate. To ensure that the first gate structure 310 has sufficient control over the sidewall channel, the height of the first gate structure 310 in the third direction can be slightly higher than that of the P-type substrate 110 and the N-type substrate 120, that is, the first gate structure 310 is slightly embedded in the buried oxide layer 500, so that the first gate structure 310 completely covers the sidewalls of the P-type substrate 110 and the N-type substrate 120 in the third direction. The third direction is perpendicular to the plane containing the P-type substrate 110 and the N-type substrate 120.
[0060] To ensure that the buried oxide layer 500 provides sufficient physical support and a stable spatial reference for the NMOS and PMOS transistors, and to insulate the NMOS and PMOS transistors located above the buried oxide layer 500 from the lower portion of the substrate, thus ensuring independent transistor operation, the height of the buried oxide layer 500 in the third-order direction needs to be significantly greater than the height difference between the first gate structure 310 and the substrate. Fluctuations in the height of the buried oxide layer 500 have a relatively small impact on device performance, allowing for a larger process window in production. For example, the height of the buried oxide layer 500 can be 0.75 μm, consistent with the development platform, to maintain compatibility with existing mass production capabilities. In production, the height of the buried oxide layer 600 can fluctuate within the range of 0.75 μm ± 10%.
[0061] The P-type substrate 110 and N-type substrate 120 can be fabricated using a constant-doping ion doping method, meaning the impurity concentration is uniformly distributed throughout the entire region and does not change with depth or lateral position. This avoids potential inhomogeneity caused by concentration fluctuations, ensuring the consistency of the transistor threshold voltage. Furthermore, this can be achieved through a single ion implantation or uniform diffusion, making the fabrication process relatively simple.
[0062] The second gate structure 320 and the first gate structure 310 are stacked along a third direction; the third direction is perpendicular to the plane where the P-type substrate 110 and the N-type substrate 120 are located.
[0063] Two N-type doped regions 230 are respectively disposed at both ends of the P-type substrate 110 near the N-type substrate 120, and the first gate structure 310 is in contact with the undoped region of the P-type substrate 110.
[0064] Two first P-type doped regions 210 are respectively disposed on both sides of the first gate structure 310 in the N-type substrate 120, and are located on the side of the N-type substrate 120 closer to the P-type substrate 110.
[0065] Two second P-type doped regions 220 are respectively disposed on both sides of the first gate structure 310 in the N-type substrate 120, and are located on the side of the first gate structure 310 away from the P-type substrate 110.
[0066] The width of the first P-type doped region 210 in the first direction is smaller than the width of the portion of the first gate structure 310 embedded in the N-type substrate 120, so that there is an undoped region between the first P-type doped region 210 and the second P-type doped region 220 that contacts the sidewall of the first gate structure 310, forming a sidewall channel.
[0067] Thus, the first gate structure 310 contacts the sidewalls of the undoped regions of the P-type substrate 110 and the N-type substrate 120 to control, for example, Figure 2The sidewall channel IN1 shown has the second gate structure 320 in contact with the first gate structure 310, the undoped region of the P-type substrate 110, and the upper surface of the undoped region of the N-type substrate 120, to control... Figure 3 The equivalent circuit diagram of the surface channel IN2 shown is as follows: Figure 4 As shown.
[0068] The height fluctuations of the P-type substrate 110 and N-type substrate 120 in the third-order direction have a relatively small impact on device performance. A larger process window can be configured in production. For example, the center value of the height of the P-type substrate 110 and N-type substrate 120 in the third-order direction can be 0.25 μm, which is consistent with the epitaxial layer thickness of the development platform. In production, its height can be allowed to fluctuate within the range of 0.25 μm ± 10% to be compatible with existing mass production capabilities.
[0069] As an example, the height of the first gate structure 310 in the third-party direction can be greater than or equal to the heights of the P-type substrate 110 and the N-type substrate 120 in the third-party direction. This allows the electric field of the sidewalls of the first gate structure (buried gate) 310 to completely cover the sidewalls of the N-type and P-type channels in the third-party direction, enabling more effective modulation of the carrier concentration within the channels. The height variation of the first gate structure 310 in the third-party direction has a relatively small impact on device performance, allowing for a larger process window in manufacturing. For example, the height of the first gate structure 310 in the third-party direction can be 0.3 μm to match the heights of the P-type substrate 110 and the N-type substrate 120 in the third-party direction. In manufacturing, its height can be allowed to vary within the range of 0.3 μm ± 0.1 μm.
[0070] For example, the height of the P-type substrate 110 and N-type substrate 120 in the third-order direction can be 0.225 μm to provide a smaller vertical stacking height and further optimize area efficiency; or it can be 0.25 μm to match carrier transport requirements and ensure device conduction efficiency; or it can be 0.275 μm to increase silicon material reserves in the channel region and improve the device's current drive capability. The height of the first gate structure 310 in the third-order direction can be 0.2 μm to compress the vertical dimension; or it can be 0.3 μm to balance device size and gate control capability; or it can be 0.4 μm to ensure that the first gate structure 310 completely covers the substrate sidewalls and enhances gate control capability.
[0071] The buried gate independently controls the conduction state of the sidewall channel. When the buried gate input is high (2.5V), the NMOS sidewall channel is turned on and the PMOS sidewall channel is turned off; when the buried gate input is low (-2.5V), the PMOS sidewall channel is turned on and the NMOS sidewall channel is turned off.
[0072] The height of the second gate structure 320 in the third-order direction must be less than the substrate height to avoid excessive thickness of the second gate structure 320, which would increase gate capacitance, reduce switching speed, and prevent substrate stress imbalance leading to wafer breakage during processing. Fluctuations in the height of the second gate structure 320 in the third-order direction have a relatively small impact on device performance, allowing for a larger process window in production. For example, if the substrate height is within the range of 0.25μm ± 10%, the height of the second gate structure 320 can be 0.125μm, consistent with the development platform, to ensure compatibility with existing mass production capabilities. In production, the height of the second gate structure 320 can fluctuate within the range of 0.125μm ± 10%, such as 0.137μm, 0.125μm, or 0.113μm.
[0073] The second gate structure (conventional gate) 320 independently controls the conduction state of the surface channel. When the conventional gate input is high (2.5V), the NMOS surface channel is turned on and the PMOS surface channel is turned off; when the conventional gate input is low (-2.5V), the PMOS surface channel is turned on and the NMOS surface channel is turned off.
[0074] As long as the NMOS in either the surface channel or the sidewall channel is turned on, the overall pull-down transistor is turned on, and the output is pulled to VSS (0V). Only when both PMOS in both channels are turned on, the overall pull-up transistor is turned on, and the output is pulled to VDD (2.5V), thus realizing the OR NOT gate logic function.
[0075] In this embodiment, the two series-connected PMOS transistors are independently controlled by the input signals corresponding to the first gate structure 310 and the second gate structure 320, respectively. The input signal of the first gate structure 310 modulates the sidewall channel PMOS, while the input signal of the second gate structure 320 modulates the surface channel PMOS. When either input is high (2.5V), the corresponding channel PMOS is immediately turned off. The series connection completely disconnects the entire pull-up path, eliminating the risk of leakage during the transition state and creating a low-leakage NOR gate device. Simultaneously, the dual control of the buried gate and the conventional gate strengthens the constraint on channel carriers and optimizes the carrier escape problem under single-gate control.
[0076] Thus, the P-type substrate 110, the first gate structure 310, and the N-type substrate 120 are arranged along a first direction, and the second gate structure 320 is located above the P-type substrate 110, the first gate structure 310, and the N-type substrate 120. The N-type substrate 120, the first P-type doped region 210, the second P-type doped region 220, and the gate structure constitute a PMOS, and the P-type substrate 110, the N-type doped region 230, and the gate structure constitute an NMOS. The first gate structure 310 controls the sidewall channel, and the second gate structure 320 controls the surface channel. The buried gate (first gate structure 310) and the conventional gate (second gate structure 320) are combined to achieve dual-input port gate integration, forming a NOR gate structure with a shared irregular gate. On the one hand, the buried gate sidewall and the conventional gate bottom realize the combination of surface transport and vertical transport of charge carriers, breaking through the planar layout limitation and greatly reducing the layout area of the NOR gate, which can reduce the area occupied by the NOR gate by 60%~70%; on the other hand, the series PMOS pull-up transistor does not have the leakage risk of the transition state, which reduces the leakage of the NOR gate device and forms a low leakage 3D NOR gate device.
[0077] As an example, such as Figure 5 As shown, the first P-type doped region 210 can be a gradient doped region. Specifically, the first P-type doped region 210 includes a first P-type lightly doped region 211 and a first P-type heavily doped region 212; the doping concentration and doping depth of the first P-type heavily doped region 212 are both greater than those of the first P-type lightly doped region 211; the first P-type heavily doped region 212 is located on the side of the first P-type lightly doped region 211 near the edge of the N-type substrate 120.
[0078] Among them, the first P-type highly doped region 212 and the second P-type highly doped region 222 are the main carrier injection regions, which are used to provide sufficient carriers; the first P-type lightly doped region 211 and the second P-type lightly doped region 221 are the transition regions between the highly doped region and the channel, which are used to connect the carrier concentration gradient between the channel and the highly doped region.
[0079] Similarly, the second P-type doped region 220 can also be a gradient-doped region. Specifically, the second P-type doped region 220 includes a second P-type lightly doped region 221 and a second P-type heavily doped region 222; the doping concentration and doping depth of the second P-type heavily doped region 222 are both greater than those of the second P-type lightly doped region 221; the second P-type heavily doped region 222 is located on the side of the second P-type lightly doped region 221 near the edge of the N-type substrate 120.
[0080] Similarly, the N-type doped region 230 can also be a gradient-doped region. Specifically, the N-type doped region 230 includes a lightly doped N-type region 231 and a heavily doped N-type region 232; the doping concentration and doping depth of the heavily doped N-type region 232 are both greater than those of the lightly doped N-type region 231; the heavily doped N-type region 232 is located on the side of the lightly doped N-type region 231 near the edge of the P-type substrate 110.
[0081] For example, the highly doped region (i.e., the source / drain region, SD) can be selected from 3e20cm. -3 ~5e20cm -3 High peak doping concentrations, such as a doping concentration of 4e20cm. -3 This ensures that the highly doped region provides sufficient electron or hole carriers for the device; the lightly doped region (LDD) can use 1e19cm -3 ~3e19cm -3 Low to medium peak doping concentrations, such as a doping concentration of 2e19cm. -3 This creates a smooth concentration gradient between the channel, lightly doped region, and heavily doped region. This reduces the migration resistance of charge carriers caused by abrupt concentration changes during transport, allowing charge carriers to be efficiently injected into the channel from the heavily doped region through the lightly doped region.
[0082] The doping concentration in the heavily doped and lightly doped regions affects the logic stability of the device. To ensure high consistency in the fabricated devices, a smaller process window can be set for the doping concentration in the heavily doped and lightly doped regions, such as controlling the doping concentration to fluctuate within ±5% of the corresponding center value. For example, the doping concentration in the heavily doped region can be selected from 4e20cm. -3 Within ±5%, for example, it can be 3.8e20cm. -3 4e20cm -3 Or 4.2e20cm -3 To balance low on-current and low impurity diffusion risk, the doping concentration in the low-doped region can be selected from 2e19cm. -3 Within ±5%, for example, it can be 1.9e19cm. -3 2e19cm -3 Or 2.1e19cm -3 This is done to match the doping concentration in the highly doped region and smooth the concentration gradient.
[0083] The doping depth of the heavily doped region is greater than that of the lightly doped region. Heavier doping reduces the bulk resistance of the source / drain regions, facilitating the formation of ohmic contacts between the metal and semiconductor. Lightly doped regions serve as current transition channels between the channel and source / drain regions, reducing carrier losses during transport and improving the transmission efficiency of pull-down current in NMOS and pull-up current in PMOS. The doping depth of the heavily and lightly doped regions affects the logic stability of the device. To ensure high consistency in the fabricated devices, a smaller process window can be set for the doping depth of the heavily and lightly doped regions, such as controlling the doping depth to fluctuate within ±5% of the corresponding center value.
[0084] For example, the doping depth of the highly doped region can be in the range of 0.25 μm ± 5%, such as 0.238 μm, 0.25 μm or 0.262 μm, to match the substrate thickness and ensure effective contact between the source / drain region and the channel; the doping depth of the lightly doped region can be in the range of 0.05 μm ± 5%, such as 0.048 μm, 0.05 μm or 0.052 μm, to match the doping depth of the highly doped region and optimize the electric field distribution.
[0085] Gradient doping design is performed on the first P-type doped region 210, the second P-type doped region 220 and the N-type doped region 230. By gradient transition of doping concentration and doping depth, the gate's control capability over the channel can be enhanced, avoiding increased leakage current or logic misjudgment caused by short-channel effect, and improving gate control accuracy.
[0086] See Figure 6 The figure is a top cross-sectional view of another NOR gate device provided in an embodiment of this application, wherein the first gate structure 310 includes three first spacer layers 311 and a first gate 312.
[0087] Two first spacer layers 311 are respectively disposed at both ends of the portion of the first gate 312 not embedded in the N-type substrate 120 in the second direction, for isolating the first gate 312 from the first P-type doped region 210 and the N-type doped region 230; another first spacer layer 311 is disposed at the end of the first gate 312 that contacts the N-type substrate 120 in the first direction. Thus, the first spacer layer 311 can be used to block the electrical connection between the first gate 312 and the source / drain regions, isolating the parasitic leakage current between the first gate 312 and the source / drain regions. The second direction is perpendicular to the first direction and located in the plane containing the P-type substrate 110 and the N-type substrate 120.
[0088] For example, the second lightly doped P-type region 221 in the second P-type doped region 220 is in contact with the first gate structure 310, and the second P-type doped region 220 is isolated from the first gate 312 by the first spacer layer 311. This avoids a short circuit between the gate and the source / drain regions, and also gradients the doping concentration between the gate and the source / drain regions, mitigating the electric field strength, suppressing the hot carrier effect at its source, and reducing gate oxide tunneling leakage.
[0089] The length of the first gate 312 in the second direction needs to be matched with the distance between two doped regions of the same conductivity type to determine the switching characteristics of the device. For example, the length of the first gate 312 in the second direction can be selected from the range of 0.3 μm ± 0.1 μm. For instance, the length of the first gate 312 in the second direction can be 0.2 μm to reduce channel resistance and improve switching speed by shortening the gate length; or the length of the first gate 312 in the second direction can be 0.4 μm to suppress short-channel effects by increasing the gate length; or the length of the first gate 312 in the second direction can be 0.3 μm to balance switching speed and short-channel effects.
[0090] The first spacer layer 311 is used to prevent the first gate 312 from directly contacting the source and drain, thus preventing a short circuit. Its length in the direction perpendicular to the contact surface of the first gate 312 matches the distance between two adjacent P-type doped regions and the length of the first gate 312. For example, the length of the first spacer layer 311 can be selected from the range of 0.15 μm ± 0.05 μm. For instance, the length of the first spacer layer 311 can be 0.1 μm, 0.15 μm, or 0.2 μm.
[0091] like Figure 7 As shown, this figure is a top cross-sectional view of another NOR gate device provided in the embodiment of this application. The first gate structure 310 may also include a first gate dielectric layer 313. The first gate dielectric layer 313 is located on the sidewall of the first gate 312 and is used to isolate the first gate 312 from the sidewall channel, prevent direct current conduction between the two, and avoid short circuit due to direct physical contact between the first gate 312 and the sidewall channel.
[0092] The thinner the first gate dielectric layer 313, the larger the gate capacitance, the stronger the drive current, and the faster the switching speed. However, if the first gate dielectric layer 313 is too thin, it will cause gate tunneling leakage. In one embodiment, the thickness of the first gate dielectric layer 313 in the first direction can fluctuate within the range of 5nm ± 0.2nm to balance the requirements of fast drive and low leakage.
[0093] The width of the first gate 312 in the first direction is matched with the current conduction capability, for example, it can be selected from the range of 0.6μm±0.1μm; the width of the first P-type doped region 210 and the N-type doped region 230 in the first direction is constrained by the channel length, for example, it can fluctuate within the range of 0.1μm±5% during production.
[0094] See Figure 8 The figure is a three-dimensional structural diagram of another NOR gate device provided in the embodiment of this application, wherein the second gate structure 320 includes a second spacer layer 321 and a second gate 322.
[0095] Two second spacer layers 321 are disposed at both ends of the second gate 322 in the second direction.
[0096] The second gate 322 is located at a position corresponding to the undoped region on the upper surface of the P-type substrate 110 and the N-type substrate 120. The second spacer layer 321 is in contact with the first P-type doped region 210, the second P-type doped region 220 and the N-type doped region 230. The second spacer layer 321 is used to block the electrical connection between the second gate 322 and the highly doped source / drain region and to isolate the parasitic leakage current between the second gate 322 and the source / drain region.
[0097] The length of the second gate 322 in the second direction needs to match the distance between the two doped regions of the same conductivity type in the second direction to determine the switching characteristics of the device. In one embodiment, the length of the second gate 322 in the second direction can be equal to the length of the first gate 312 in the second direction. For example, if the length of the first gate 312 is 0.3 μm, then the length of the second gate 322 is also 0.3 μm.
[0098] The second spacer layer 321 is used to prevent the second gate 322 from directly contacting the source / drain, thus preventing a short circuit. Its length in the second direction matches the distance between two doped regions of the same conductivity type in the second direction and the length of the second gate 322. Exemplarily, the length of the second spacer layer 321 in the second direction can be selected from the range of 0.15 μm ± 0.05 μm. For example, the length of the second spacer layer 321 in the second direction can be 0.1 μm, 0.15 μm, or 0.2 μm.
[0099] The second gate structure 320 may also include a second gate dielectric layer, which is located at the bottom of the second gate 322 and is used to isolate the second gate 322 from the surface channel, prevent direct current conduction between the two, and avoid short circuit due to direct physical contact between the second gate 322 and the surface channel.
[0100] The thinner the second gate dielectric layer, the larger the gate capacitance, the stronger the drive current, and the faster the switching speed. However, an excessively thin second gate dielectric layer can lead to gate tunneling leakage. In one embodiment, the thickness of the second gate dielectric layer in the first direction can fluctuate within the range of 5nm ± 0.2nm to balance the requirements of fast drive and low leakage.
[0101] The width of the second gate 322 in the first direction can be equal to the sum of the widths of the P-type substrate 110, the first gate structure 310, and the N-type substrate 120 in the first direction. For example, the width of the second gate 322 can be 2.3 μm.
[0102] Furthermore, the NOR gate device provided in this application embodiment also includes an insulating isolation wall 400. The insulating isolation wall 400 is located between the first P-type doped region 210 and the N-type doped region 230.
[0103] See Figure 9 The figure is a flowchart of a method for fabricating a NOR gate device according to an embodiment of this application. The method includes:
[0104] S901: Provides a substrate.
[0105] As an example, the substrate may include, but is not limited to, the buried oxide layer 500. The buried oxide layer 500 is used to provide physical support and a stable space reference for the NMOS and PMOS, and to insulate the NMOS and PMOS located above the buried oxide layer 500 from the lower part of the substrate.
[0106] S902: Epitaxial growth of substrate 100 on a substrate.
[0107] For example, such as Figure 9 As shown in (a), a Si substrate 100 can be epitaxially grown above the buried oxide layer 500.
[0108] S903: By etching, a trench is formed that divides the substrate 100 into a first substrate 101 and a second substrate 102, and a groove is located on the opposite side of the sidewalls of the first substrate 101 and the second substrate 102.
[0109] Specifically, etching can be used to divide the substrate 100 corresponding to a single NOR gate device into two parts, namely a first substrate 101 and a second substrate 102, and grooves can be etched on the opposite sidewalls of the first substrate 101 and the second substrate 102, such as... Figure 9 As shown in (b).
[0110] S904: Perform N-type ion implantation on the first substrate to form an N-type substrate 120; perform P-type ion implantation on the second substrate to form a P-type substrate 110.
[0111] Specifically, by using a constant-doping ion doping method, ions of different conductivity types can be implanted into the first substrate 101 and the second substrate 102 to obtain a P-type substrate 110 and an N-type substrate 120, respectively. Figure 9 As shown in (d).
[0112] PMOS and NMOS have different carrier types, resulting in a natural difference in mobility. NMOS uses electrons as carriers, while PMOS uses holes. The mobility of holes is only 1 / 3 to 1 / 2 that of electrons. If the doping concentrations of the P-type substrate 110 and the N-type substrate 120 are the same, the NMOS drive current will be greater than the PMOS drive current, leading to faster pull-down and slower pull-up during logic transitions, resulting in output signal distortion. To compensate for the difference in carrier mobility and ensure dual-input logic synchronization, the doping concentration of the P-type substrate 110 can be appropriately increased to reduce the NMOS drive current. For example, the doping concentration of the P-type substrate 110 can be 2e18cm⁻¹. -3 In this solution, the turn-off effect is enhanced by using a series PMOS pull-up transistor. The doping concentration of the N-type substrate 120 does not need to be excessively high to meet the low leakage current requirement. The doping concentration of the N-type substrate 120 can be appropriately reduced to increase the PMOS drive current; for example, the doping concentration of the N-type substrate 120 can be 1e18cm⁻¹. -3 .
[0113] Ion implantation energy affects the logic stability of devices. A smaller process window can be set, for example, the process window can be set to ±5% of the center value.
[0114] For example, to avoid ion implantation into the trenches and recesses between the first substrate 101 and the second substrate 102 during ion implantation, shallow trench isolation deposition can be performed in the trenches and recesses before ion implantation, filling the trenches and recesses with an insulating oxide 01, such as silicon oxide. Figure 9 As shown in (c).
[0115] S905: The first gate structure 310 is fabricated in the trench and recess.
[0116] One side of the first gate structure 310 is embedded in the N-type substrate 120, and the other side is in contact with the sidewall of the P-type substrate 110.
[0117] Specifically, the insulating oxide 01 deposited in the trench can be etched first to obtain the first gate trench and the insulating isolation wall 400; then, an insulating material, such as silicon nitride, is deposited in the gate trench and the recess; subsequently, the insulating material is etched to obtain the second gate trench and three first spacer layers 311, wherein two of the first spacer layers 311 are respectively disposed at both ends of the portion of the first gate 312 not embedded in the N-type substrate 120 in the second direction, for isolating the first gate 312 from the first P-type doped region 210 and the N-type doped region 230; the other first spacer layer 311 is disposed at the end of the portion of the first gate 312 embedded in the N-type substrate 120 that contacts the N-type substrate 120 in the first direction; finally, the second gate trench is filled with a gate material, such as polysilicon, to form the first gate 312, such as... Figure 9 As shown in (e), a first gate structure 310 comprising a first spacer layer 311 and a first gate 312 is thus obtained.
[0118] For example, after obtaining the second gate trench and the first spacer layer 311, a first gate dielectric layer 313 located on the sidewall of the trench can be deposited first, and then gate material can be filled in the second gate trench to form the first gate 312.
[0119] S906: A second gate structure 320 is fabricated over the first gate structure 310, the N-type substrate 120, and the P-type substrate 110.
[0120] The second gate structure 320 and the first gate structure 310 are stacked along a third direction; the second direction is perpendicular to the first direction, and the third direction is perpendicular to the plane containing the first and second directions.
[0121] Specifically, a gate material, such as polysilicon, can be deposited first over the first gate structure 310, the P-type substrate 110, and the N-type substrate 120 to form a gate material layer; then, the gate material layer is etched to form a second gate 322 located above the undoped regions of the first gate structure 310, the P-type substrate 110, and the N-type substrate 120. Figure 9 As shown in (f); finally, a second spacer layer 321 is deposited at both ends of the second gate 322 in the second direction, as shown in (f). Figure 9 As shown in (g), a second gate structure 320 including a second spacer layer 321 and a second gate 322 is obtained.
[0122] For example, before depositing the gate material, a second gate dielectric layer can be deposited over the undoped regions of the first gate structure 310, the P-type substrate 110, and the N-type substrate 120 to isolate the second gate 322 from the surface channel.
[0123] S907: N-type ion implantation is performed at both ends of the P-type substrate 110 near the N-type substrate 120 to form an N-type doped region 230; P-type ion implantation is performed on the N-type substrate 120 on both sides of the first gate structure 310 near the P-type substrate 110 to form a first P-type doped region 210; P-type ion implantation is performed on the N-type substrate 120 on both sides of the first gate structure 310 away from the P-type substrate 110 to form a second P-type doped region 220.
[0124] Optionally, P-type ion implantation with a low doping concentration and shallow doping depth can be performed on the N-type substrate 120 near the P-type substrate 110 to form a first lightly doped P-type region 211; on the side of the first gate structure 310 away from the P-type substrate 110, P-type ion implantation with a low doping concentration and shallow doping depth can be performed on the N-type substrate 120 to form a second lightly doped P-type region 221; and N-type ion implantation with a low doping concentration and shallow doping depth can be performed at both ends of the P-type substrate 110 near the N-type substrate 120 to form a lightly doped N-type region 231, such as... Figure 9 As shown in (h).
[0125] Then, in the first lightly doped P-type region 211, near the edge of the N-type substrate 120, a higher concentration and deeper P-type ion implantation is performed again to form the first heavily doped P-type region 212; in the central region of the second lightly doped P-type region 221, a higher concentration and deeper P-type ion implantation is performed again to form the second heavily doped P-type region 222; in the N-type lightly doped region 231, near the edge of the P-type substrate 110, a higher concentration and deeper N-type ion implantation is performed again to form the heavily doped N-type region 232, as shown below. Figure 9 As shown in (i).
[0126] Among them, the doping concentration and doping depth of the first P-type highly doped region 212 are both greater than those of the first P-type lightly doped region 211; the doping concentration and doping depth of the second P-type highly doped region 222 are both greater than those of the second P-type lightly doped region 221; and the doping concentration and doping depth of the N-type highly doped region 232 are both greater than those of the N-type lightly doped region 231.
[0127] Thus, the P-type substrate 110, the first gate structure 310, and the N-type substrate 120 are arranged along a first direction, and the second gate structure 320 is located above the P-type substrate 110, the first gate structure 310, and the N-type substrate 120. The N-type substrate 120, the first P-type doped region 210, the second P-type doped region 220, and the gate structure constitute a PMOS, and the P-type substrate 110, the N-type doped region 230, and the gate structure constitute an NMOS. The first gate structure 310 controls the sidewall channel, and the second gate structure 320 controls the surface channel. The buried gate (first gate structure 310) and the conventional gate (second gate structure 320) are combined to achieve dual-input port gate integration, forming a NOR gate structure with a shared irregular gate. On the one hand, the buried gate sidewall and the conventional gate bottom realize the combination of surface transport and vertical transport of charge carriers, breaking through the planar layout limitation and greatly reducing the layout area of the NOR gate, which can reduce the area occupied by the NOR gate by 60%~70%; on the other hand, the series PMOS pull-up transistor does not have the leakage risk of the transition state, which reduces the leakage of the NOR gate device and forms a low leakage 3D NOR gate device.
[0128] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the structural embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the structural embodiments. The method embodiments described above are merely illustrative, and some or all of the steps can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement them without creative effort.
[0129] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A NOR gate device, characterized in that, The device includes: a P-type substrate, an N-type substrate, a first P-type doped region, a second P-type doped region, an N-type doped region, a first gate structure, and a second gate structure; The P-type substrate, the first gate structure, and the N-type substrate are arranged sequentially along a first direction; one side of the first gate structure is embedded in the N-type substrate, and the other side is in contact with the sidewall of the P-type substrate; the P-type substrate and the N-type substrate are separated. The second gate structure is stacked with the first gate structure along a third direction; the third direction is perpendicular to the plane containing the P-type substrate and the N-type substrate. The two N-type doped regions are located at both ends of the P-type substrate near the N-type substrate, and the first gate structure is in contact with the undoped region of the P-type substrate; The two first P-type doped regions are disposed on both sides of the first gate structure in the N-type substrate, and are located on the side of the N-type substrate closer to the P-type substrate; The two second P-type doped regions are disposed on both sides of the first gate structure in the N-type substrate, and are located on the side of the first gate structure away from the P-type substrate.
2. The device according to claim 1, characterized in that, The first P-type doped region includes a first lightly doped P-type region and a first heavily doped P-type region; the doping concentration and doping depth of the first heavily doped P-type region are both greater than those of the first lightly doped P-type region. The first P-type heavily doped region is located on the side of the first P-type lightly doped region near the edge of the N-type substrate.
3. The device according to claim 1, characterized in that, The first gate structure includes: three first spacer layers and a first gate; The two first spacer layers are respectively disposed at both ends of the portion of the first gate not embedded in the N-type substrate in the second direction, for isolating the first gate from the first P-type doped region and the N-type doped region; the second direction is perpendicular to the first direction and located in the plane where the P-type substrate and the N-type substrate are located; A first spacer layer is disposed at one end of the first gate embedded portion of the N-type substrate that contacts the N-type substrate in a first direction.
4. The device according to claim 3, characterized in that, The second P-type doped region is in contact with the first gate structure, and the second P-type doped region is isolated from the first gate through the first spacer layer.
5. The device according to claim 3, characterized in that, The first gate structure further includes: a first gate dielectric layer; The first gate dielectric layer is located on the first gate sidewall.
6. The device according to claim 3, characterized in that, The second gate structure includes: a second spacer layer and a second gate; Two second spacer layers are disposed at both ends of the second gate in the second direction; the second gate and the first gate are of equal length in the second direction; the second direction is perpendicular to the first direction and is located in the plane containing the P-type substrate and the N-type substrate.
7. The device according to claim 1, characterized in that, The height of the first gate structure in the third direction is greater than or equal to the height of the P-type substrate and the N-type substrate in the third direction.
8. The device according to claim 1, characterized in that, The device further includes an insulating barrier wall located between the first P-type doped region and the N-type doped region.
9. A method for fabricating a NOR gate device, characterized in that, The method includes: Provide a base; A substrate is epitaxially grown on the substrate; By etching, trenches are formed that divide the substrate into a first substrate and a second substrate, as well as grooves located on the opposite side of the sidewalls of the first substrate and the second substrate; The first substrate is subjected to N-type ion implantation to form an N-type substrate; the second substrate is subjected to P-type ion implantation to form a P-type substrate. A first gate structure is fabricated within the trench and the recess; one side of the first gate structure is embedded in the N-type substrate, and the other side is in contact with the sidewall of the P-type substrate. A second gate structure is fabricated above the first gate structure, the N-type substrate, and the P-type substrate; the second gate structure and the first gate structure are stacked along a third direction; the third direction is perpendicular to the plane containing the P-type substrate and the N-type substrate; N-type ion implantation is performed at both ends of the P-type substrate near the N-type substrate to form an N-type doped region; On the side of the N-type substrate close to the P-type substrate, P-type ion implantation is performed on the N-type substrates on both sides of the first gate structure to form a first P-type doped region; On the side of the first gate structure away from the P-type substrate, P-type ion implantation is performed on the N-type substrates on both sides of the first gate structure to form a second P-type doped region.
10. The method according to claim 9, characterized in that, The step of implanting N-type ions at both ends of the P-type substrate near the N-type substrate to form N-type doped regions includes: N-type ion implantation is performed at both ends of the P-type substrate near the N-type substrate to form a lightly doped N-type region; N-type ion implantation is performed again on the side of the N-type lightly doped region near the edge of the P-type substrate to form an N-type heavily doped region; the doping concentration and doping depth of the N-type heavily doped region are both greater than those of the N-type lightly doped region.