Integrated circuit structure with fin isolation regions continuous with gate cut plug

Abstract

Integrated circuit structures with fin isolation regions continuous with gate cut plug are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin above a first sub-fin. A gate structure is above the vertical stack of horizontal nanowires or the fin and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not above a channel structure, but on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate cut plug is continuous with the dielectric structure.

Description

[0001] This application is a divisional application. The original application was filed with the China Patent Office on January 13, 2025, with application number 202510046100.6 and the invention title "Integrated Circuit Structure Having a Fin-like Isolation Region Continuous with a Gate Cut-out Plug". Background Technology

[0002] For decades, the scaling of features in integrated circuits has been a driving force behind the booming semiconductor industry. Scaling to increasingly smaller features allows for an increase in the density of functional units on the limited chip area of ​​a semiconductor chip. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a single chip, facilitating the creation of products with greater capacity. However, the pursuit of greater capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important.

[0003] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent due to the continuous shrinking of device dimensions. In conventional processes, tri-gate transistors are typically fabricated on bulk silicon substrates or silicon-on-insulator (SiI) substrates. In some instances, bulk silicon substrates are preferred due to their low cost and because they enable less complex tri-gate fabrication processes. On the other hand, maintaining improved mobility and short-channel control as microelectronic device dimensions scale down to below the 10-nanometer (nm) node presents challenges in device fabrication. Nanowires used to fabricate devices offer improved short-channel control.

[0004] However, scaling up multi-gate and nanowire transistors has not been without consequences. As the size of these fundamental building blocks of microelectronic circuits decreases, and as the number of fundamental building blocks fabricated in a given area increases, the limitations of the photolithography processes used to pattern these building blocks have become increasingly unbearable. In particular, there may be a trade-off between the minimum size (critical size) of a feature patterned in a semiconductor stack and the spacing between such features. Attached Figure Description

[0005] Figure 1A-1F The diagram shows top-down oblique cross-sectional views of various operations in a method of fabricating an integrated circuit structure having a fin-isolated region constrained by a gate notch, according to an embodiment of the present disclosure.

[0006] Figure 1G-1J (a) a top-down oblique cross-sectional view and (b) a corresponding top-down plan view are shown in the embodiments of the present disclosure of various operations in a method of fabricating an integrated circuit structure having a fin isolation region continuous with a gate cut-out plug.

[0007] Figure 1KA cross-sectional view of an integrated circuit structure having a fin-isolated region according to an embodiment of the present disclosure is shown.

[0008] Figure 2A A cross-sectional view of an integrated circuit structure having fins and a metal front gate dielectric plug according to an embodiment of the present disclosure is shown.

[0009] Figure 2B A cross-sectional view of an integrated circuit structure having fins and a notched metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0010] Figure 3A A cross-sectional view of an integrated circuit structure having nanowires and a metal front gate dielectric plug according to an embodiment of the present disclosure is shown.

[0011] Figure 3B A cross-sectional view of an integrated circuit structure having nanowires and notched metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0012] Figure 4A A cross-sectional view of an integrated circuit structure having nanowires and a metal front gate dielectric plug according to an embodiment of the present disclosure is shown.

[0013] Figure 4B A cross-sectional view of an integrated circuit structure having nanowires and notched metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0014] Figures 5A-5C A plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown.

[0015] Figures 6A-6C Cross-sectional views of comparative integrated circuit structures according to embodiments of the present disclosure are shown.

[0016] Figures 7A-7J Cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure according to embodiments of the present disclosure are shown.

[0017] Figure 8 A cross-sectional view along the gate line of a non-planar integrated circuit structure according to an embodiment of the present disclosure is shown.

[0018] Figure 9 Cross-sectional views taken through nanowires and fins are shown of a non-endcap architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture (right side (b)) according to embodiments of the present disclosure.

[0019] Figure 10Cross-sectional views are shown of various operations in a method for fabricating a self-aligned gate end cap (SAGE) structure with a gate full-around device, according to an embodiment of the present disclosure.

[0020] Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown.

[0021] Figure 11B An embodiment according to this disclosure is shown. Figure 11A The source or drain diagram of a cross section taken along the a-a' axis of a nanowire-based integrated circuit structure.

[0022] Figure 11C An embodiment according to this disclosure is shown. Figure 11A Interface channel diagram of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0023] Figure 12 A computing device according to one embodiment of the present disclosure is shown.

[0024] Figure 13 An interpolator including one or more embodiments of the present disclosure is shown. Detailed Implementation

[0025] An integrated circuit structure having a finned isolation region continuous with a gate cut-out plug is described, as well as a method for fabricating an integrated circuit structure having a finned isolation region continuous with a gate cut-out plug. In the following description, numerous specific details, such as specific integration and material systems, are set forth in order to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure can be practiced without these specific details. In other instances, known features, such as integrated circuit design layouts, are not described in detail so as not to unnecessarily obscure embodiments of this disclosure. Furthermore, it should be understood that the various embodiments illustrated in the figures are illustrative representations and are not necessarily drawn to scale.

[0026] Some terms may also be used in the description below for reference only, and therefore these terms are not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientations in the referenced figures. Terms such as “front,” “back,” “rear,” and “side” describe the orientation and / or position of portions of a component within a consistent but arbitrary frame of reference, which is made clear by reference to the text describing the component in question and the associated figures. Such terms may include words specifically mentioned above, their derivatives, and words with similar meanings.

[0027] The embodiments described herein are applicable to front-end process (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL generally encompasses all processes up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0028] The embodiments described herein pertain to back-end process (BEOL) semiconductor processing and structures. BEOL is the second part of IC manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected using wiring (e.g., one or more metallization layers) on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding sites for chip-to-package connections. During the manufacturing phase of the BEOL, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL.

[0029] The embodiments described below can be applied to FEOL processing and structures, BEOL processing and structures, or both FEOL processing and structures and BEOL processing and structures. Specifically, although exemplary processing schemes can be shown using FEOL processing schemes, this approach can also be applied to BEOL processing. Similarly, although exemplary processing schemes can be shown using BEOL processing schemes, this approach can also be applied to FEOL processing.

[0030] One or more embodiments described herein relate to a fin trimmed isolation (FTI) structure with a metal gate cutout (MGC) ladder. One or more embodiments described herein relate to an integrated circuit structure with a fin isolation region formed after metal gate processing, which may be referred to as a post-replacement gate fin trimmed isolation (FTI). One or more embodiments described herein relate to a gate-all-around device with a fin isolation region continuous with the gate cutout plug. It should be understood that, unless otherwise indicated, references to nanowires herein may refer to nanowires or nanoribbons, or even nanosheets. One or more embodiments described herein relate to a FinFET structure with a fin isolation region continuous with the gate cutout plug.

[0031] To provide context, fin trimming isolation (FTI) processes become increasingly complex as gate pitch and fin (or wire stack) pitch decrease. A standard FTI process involves the fabrication of a gate plug and the underlying channel structure. The plug can negatively interfere with the metal gate process.

[0032] According to one or more embodiments, the FTI opening is backfilled with a dielectric material after the metal gate processing. Embodiments can be implemented to provide a process flow with fewer processing operations and / or reduce the negative impact on the metal gate processing. Embodiments can be implemented to ensure that the FTI structure has a gate notch around the FTI region. In embodiments, isotropic etching is used to remove the metal gate, and then the fins / bands are removed, followed by dielectric filling. This process can have a smaller impact on the gate height.

[0033] As an example of a post-replacement gate fin trimming isolation (FTI) process, Figure 1A-1F The illustration shows top-down oblique cross-sectional views of various operations in a method of fabricating an integrated circuit structure having fin isolation regions constrained by gate notches, according to embodiments of the present disclosure. It should be understood that although described in association with a stack of nanowires (or nanoribbons or nanosheets), embodiments may also cover semiconductor fins, for example, where a semiconductor fin on top of a sub-fin replaces a stack of nanowires on top of the sub-fin.

[0034] refer to Figure 1A The initial structure 100 includes sub-fins 104 that extend from a substrate, such as silicon sub-fins extending from a silicon substrate. Sub-fins 104 protrude through a shallow trench isolation (STI) structure 106, such as a silicon oxide structure. An assembly of nanowires 108 is positioned above a corresponding one of the sub-fins 104. Each assembly of nanowires 108 may be referred to as a vertical arrangement of horizontally stacked nanowires, such as a vertical arrangement of horizontally stacked silicon nanowires. A corresponding gate stack, such as a gate dielectric layer 110 / gate electrode 112, is positioned above each of the nanowires 108. The gate stack is, for example, a gate stack comprising a high-k gate dielectric layer 112 and a gate electrode 110, the gate electrode 110 comprising one or more conductive work function layers and conductive filler material. Dielectric spacers 114, such as silicon nitride spacers, are positioned along the sides of the gate stacks 110 / 112 and may be referred to as gate spacers. Conductive trench contacts 116 are located between the gate spacers 114 of the corresponding gate stacks. The conductive trench contact 116 may be located in one or more epitaxial source or drain structures (not shown, but depicted on) Figure 1F It extends over the dielectric region 118 and, as depicted, may have a dielectric cap 120 thereon.

[0035] Refer again Figure 1AThe gate cutout is laterally adjacent to the gate structure 110 / 112 and has a dielectric gate cutout plug 122 therein (e.g., a gate cutout plug described below). In an embodiment, the initial structure 100 represents the structure after forming trench contacts, replacing the gate to form a permanent gate stack 110 / 112, and forming the gate cutout and gate cutout plug (in this case, the final example of the gate cutout). This structure may be referred to as a pixel structure because the dielectric gate cutout plug 122 extends through multiple alternating gate and trench contact structures, effectively isolating such cells at this stage.

[0036] refer to Figure 1B ,exist Figure 1A A photoresist layer or stack 124 is formed on the structure 100. The photoresist layer or stack 124 is formed to have openings 126 therein, for example, openings in locations where fin trimming isolation processes are to be performed.

[0037] refer to Figure 1C An etching process is performed through opening 126 to etch trench 128. The etching removes the intermediate gate electrode 110, exposing the gate dielectric layer 112. Trench 128 is constrained by gate notch plug 122.

[0038] refer to Figure 1D The photoresist layer or stack 124 is removed. A protective helmet 129, such as a titanium helmet, is formed on the resulting structure. An etching process is performed through an opening in the helmet 129. The etching removes the nanowires 108 beneath the opening and etches them into the corresponding sub-fins. The etching forms etched nanowire portions 108A. As depicted, the etching may also cause the corresponding sub-fins 104 to be recessed to form etched sub-fins 104A. In an embodiment, the protective helmet 129 protects the gate spacer 114 and the gate cut-out plug 122 during etching.

[0039] refer to Figure 1E By filling with dielectric structure 130 Figure 1D The integrated circuit structure 150 is formed by cavities in the structure, and the dielectric structure 130 may be referred to as a fin-trimmed isolation structure. In an embodiment, as depicted, the dielectric structure 130 does not have an associated lower channel structure (e.g., fins, nanowire stacks, etc.), while each of the remaining gate structures 110 / 112 has a corresponding lower channel structure (e.g., nanowire 108 stacks).

[0040] refer to Figure 1F Together, they depict integrated circuit structure 150 and structure 159, a rotating view representing structure 150. In rotating view 159, epitaxial source or drain structure 132, such as epitaxial silicon germanium or epitaxial silicon source or drain structure, is visible.

[0041] Refer again Figure 1F When the back side is exposed, a hard mask or protective layer can be formed over the front side of the structure. The structure then undergoes back-side processing. For example, the back side can be planarized, for instance, for electrical coupling to back-side contacts.

[0042] By referring again Figure 1F According to embodiments of this disclosure, integrated circuit structures 150 / 159 include a vertical stack of horizontal nanowires 108 above a first sub-fin 104. Gate structures 110 / 112 are above the vertical stack of horizontal nanowires 108 and on the first sub-fin 104. A dielectric structure 130 is laterally spaced from the gate structures 110 / 112. The dielectric structure 130 is not above the channel structure but is on the second sub-fin 104A. A gate notch is located between the gate structures 110 / 112 and the dielectric structure 130.

[0043] In an embodiment, as depicted, the integrated circuit structure 150 / 159 further includes a dielectric gate cut-out plug 122 in the gate cut-out. In another embodiment, the integrated circuit structure 150 / 159 further includes a second gate structure 110 / 112 on a vertical stack of horizontal nanowires 108 and on a third sub-fin 104, the second gate structure 110 / 112 being laterally spaced from the dielectric structure 130 (e.g., in a direction opposite to the gate structure). As depicted, the second gate cut-out is between the second gate structure 110 / 112 and the dielectric structure 130, and the second dielectric gate cut-out plug 122 is located within the second gate cut-out.

[0044] In one embodiment, as depicted, the second sub-fin 104A has a top surface located below the top surface of the first sub-fin 104. In another embodiment, as depicted, the integrated circuit structure 150 / 159 further includes an epitaxial source or drain structure 132 at the end of a vertically stacked body of the horizontal nanowire 108.

[0045] It should be understood that, regardless of whether they are formed of the same or different materials, the dielectric structure 130 and the dielectric gate cutout plug 122 that are in contact with each other are discontinuous due to dielectric filling being performed at different stages of the process flow. In another aspect, according to one or more embodiments, the dielectric structure and one or more adjacent dielectric gate cutout plugs are continuous, for example, due to dielectric filling being performed simultaneously in the same process. The resulting structure may be referred to as a fin trimmed isolation (FTI) structure including metal gate cutout (MGC) ladder-like features.

[0046] To provide context, pixel structures are typically fabricated using a grid mask. In one embodiment, an FTI pattern is incorporated into such a pixel mask to create an FTI ladder. In one embodiment, a single pixel metal gate notch is etched to create the pixel notch and the FTI. The MGC / FTI region is then filled together with a dielectric. In this embodiment, there is no interface / gap between the pixel notch and the FTI, and the FTI is self-aligned to the pixel notch. The FTI can be self-aligned to the pixel notch and constrained by the pixel notch.

[0047] As an example processing solution Figure 1G-1J (a) a top-down oblique cross-sectional view and (b) a corresponding top-down plan view are shown in the embodiments of the present disclosure of various operations in a method of fabricating an integrated circuit structure having a fin isolation region continuous with a gate cut-out plug. Figure 1K A cross-sectional view of an integrated circuit structure having fin isolation regions according to an embodiment of the present disclosure is shown. It should be understood that although described in association with a stack of nanowires (or nanoribbons or nanosheets), embodiments may also cover semiconductor fins, for example, where a semiconductor fin on top of a sub-fin replaces a stack of nanowires on top of the sub-fin.

[0048] refer to Figure 1G The starting structure 160 includes a sub-fin 162, a trench isolation structure 164, a nanowire stack 166, a common gate stack including a high-k gate dielectric layer 168 and a metal gate electrode 170, an insulating gate cap layer 172, a dielectric gate spacer 174, a conductive trench contact 178, and an optional liner 176.

[0049] refer to Figure 1H The insulating gate cap layer 172 is removed to expose the metal gate electrode 170, and a gate structure 180 / 182, including, for example, a silicon nitride layer 180 and an overlying mask 182, is formed on the resulting structure. The region 184 of the gate structure 180 / 182 that will eventually form the FTI structure is removed.

[0050] refer to Figure 1IThe gate structures 180 / 182 are used as masks during a non-selective etching process to pattern the metal gate electrode 170, leaving a patterned metal gate electrode 170A and a cavity in the region 184 where the gate electrode is completely removed. Additionally, a high-k gate dielectric layer 168 is patterned to form a patterned high-k gate dielectric layer 168A; the trench isolation structure 164 and sub-fins 162 exposed by region 184 are patterned to form a patterned isolation structure 164A and a patterned sub-fin 162A; the gate spacer 174 is patterned to form a patterned gate spacer 174A; and the conductive trench contact 178 is patterned to form a patterned conductive trench contact 178A. Additionally, the nanowire 166 is removed from region 184, effectively leaving the region where the channel structure has been removed. The mask 182 is also removed.

[0051] refer to Figure 1J , Figure 1I The structure undergoes a dielectric filling process, such as a silicon oxide or silicon nitride dielectric filling process, and then the resulting structure is planarized to form structure 190. Planarization forms an insulating gate cap layer 180A from the silicon nitride layer 180, and forms a dielectric gate cut-out plug 186 and an FTI dielectric structure 188 from the dielectric filler. In an embodiment, as depicted, the dielectric gate cut-out plug 186 and the FTI dielectric structure 188 are continuous; for example, there are no seams between the structures.

[0052] Figure 1K Will Figure 1J Structure 190 is shown as a cross-sectional view taken along the fin cut (a) and the gate cut (b), with the features previously marked. The right-hand figure (b) also depicts the epitaxial source or drain structure 192.

[0053] On the other hand, to reduce cell height in future or scaled-up technology nodes, both the gate end cap and gate notch sizes need to be reduced. Gate notches that pre-fill the gate metal can limit the effective end cap available for the work function and may become a challenge to metal-filling capabilities in tighter spaces. Any end-to-end misregistration of the gate can exacerbate defects, resulting in even smaller end cap space. It should be understood that either the dielectric gate notch / gate plug structure described below can be adapted to combine... Figure 1F The described integrated circuit structure 150 / 159 and / or combination Figure 1J and Figure 1K The described integrated circuit structure 190, or more generally, is used for Figure 1A-1F and / or Figure 1G-1K The dielectric gate cut-out plug and the fin-shaped isolation region continuous with such gate cut-out plug.

[0054] According to one or more embodiments of this disclosure, the problems summarized above are addressed by performing a metal gate grooving process after the gate dielectric and work function metal deposition and patterning are completed.

[0055] Advantages of implementing the methods described herein can include the so-called "plug-last" approach, which results in the gate dielectric layer (e.g., a high-k gate dielectric layer) not being deposited on the gate notch plug sidewalls, thus effectively saving additional space for work function metal deposition. Conversely, in the so-called conventional "plug-first" approach, the metal gate fill material can be squeezed between the plug and the fin. The space for metal filling can be narrower due to plug misregistration in later methods and can lead to voids during metal filling. In the embodiments described herein, using the "plug-last" approach, work function metal deposition can be seamless (e.g., without voids). However, both approaches are applicable to the embodiments described herein.

[0056] According to one or more embodiments of this disclosure, the integrated circuit structure has a clean interface between the gate-cut plug dielectric and the gate metal. It should be understood that many embodiments may benefit from the methods described herein, such as the plugging final method. For example, the following is combined with... Figure 2B The metal gate cutout on a FinFET device is described. Metal gate cutout schemes can be implemented for gate all-around (GAA) devices, as illustrated below. Figure 3B and Figure 4B Described. Additionally, the metal gate notch and plug formation can appear different depending on the input structure. For example, the plug can land on a shallow trench isolation (STI) structure, such as in combination with... Figure 2B and Figure 3B The described, or may land on a prefabricated gate wall made of dielectric, for example, by combining Figure 4B The described metal gate notching method can be selective for the gate spacer dielectric, for example, by combining... Figure 5B and Figure 6B The description, or the fact that the gate spacer material may not be selective, for example, combined with Figure 5C and Figure 6C Described. Non-selective metal gate notch embodiments may require alternating contact metal schemes to accommodate a dielectric plug between the epitaxial source / drain. Plug etching selectivity for the epitaxial source / drain material is optional. However, in one embodiment, if the epitaxial source / drain is exposed to plug etching (e.g., due to device size), the etching can anisotropically trim the source / drain, as described below. Figure 5C Described. This method can be implemented to achieve a compact end cap spacing.

[0057] A dielectric gate cut-out plug can be fabricated for FinFET devices. As a comparative example, Figure 2A A cross-sectional view of an integrated circuit structure having fins and a metal front gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 2B A cross-sectional view of an integrated circuit structure having fins and a notched metal gate dielectric plug according to an embodiment of the present disclosure is shown.

[0058] refer to Figure 2A The integrated circuit structure 200 includes a fin 202 having a portion protruding above a shallow trench isolation (STI) structure 204. A gate dielectric material layer 206, such as a high-k gate dielectric layer, is above the protruding portion of the fin 202 and above the STI structure 204. It should be understood that, although not depicted, an oxide portion of the fin 202 may be between the protruding portion of the fin 202 and the gate dielectric material layer 206, and may be included together with the gate dielectric material layer 206 to form a gate dielectric structure. A conductive gate layer 208, such as a work function metal layer, is above the gate dielectric material layer 206, and, as depicted, may be directly on the gate dielectric material layer 206. A conductive gate fill material 210 is above the conductive gate layer 208, and, as depicted, may be directly on the conductive gate layer 208. A dielectric gate cap 212 is on the conductive gate fill material 210. The dielectric gate cutout plug 214 is laterally spaced from the fin 202 and is located on the STI structure 204. The gate dielectric material layer 206 and the conductive gate layer 208 are located along the side of the dielectric gate cutout plug 214.

[0059] refer to Figure 2B The integrated circuit structure 250 includes a fin 252 having a portion protruding above a shallow trench isolation (STI) structure 254. A gate dielectric material layer 256, such as a high-k gate dielectric layer, is above the protruding portion of the fin 252 and above the STI structure 254. It should be understood that, although not depicted, an oxide portion of the fin 252 may be between the protruding portion of the fin 252 and the gate dielectric material layer 256, and may be included together with the gate dielectric material layer 256 to form a gate dielectric structure. A conductive gate layer 258, such as a work function metal layer, is above the gate dielectric material layer 256, and, as depicted, may be directly on the gate dielectric material layer 256. A conductive gate fill material 260 is above the conductive gate layer 258, and, as depicted, may be directly on the conductive gate layer 258. A dielectric gate cap 262 is on the conductive gate fill material 260.

[0060] In one embodiment, the dielectric gate cutout plug 264 is horizontally spaced from the fin 252 and is on, but does not penetrate, the STI structure 254. As used throughout the disclosure, a dielectric plug referred to as "on, but not through" the STI structure can refer to a dielectric plug landing on the top or uppermost surface of the STI, or it can refer to a plug extending into the STI but not penetrating it. In other embodiments, the plug described herein may extend completely through or penetrate the STI.

[0061] In this embodiment, the gate dielectric material layer 256 and the conductive gate layer 258 do not run along the sides of the dielectric gate cutout plug 264. Instead, the conductive gate fill material 260 contacts the sidewalls of the dielectric gate cutout plug 264. Therefore, the region between the dielectric gate cutout plug 264 and the fin 252 comprises only one layer of gate dielectric material layer 256 and only one layer of conductive gate layer 258, which alleviates the space constraints in this compact region of structure 250. Alleviating space constraints can improve metal filling and / or facilitate the patterning of multiple VTs.

[0062] Refer again Figure 2B In one embodiment, the dielectric gate notch plug 264 is formed after the gate dielectric material layer 256, the conductive gate layer 258, and the conductive gate fill material 260 are formed. Therefore, the gate dielectric material layer 256 and the conductive gate layer 258 are not formed along the sidewalls of the dielectric gate notch plug 264. In one embodiment, as depicted, the dielectric gate notch plug 264 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 262. In another embodiment not depicted, the dielectric gate cap 262 is not included, and the dielectric gate notch plug 264 has an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 260, for example, along plane 280.

[0063] Dielectric gate cutout plugs can be fabricated for nanowire devices. As a comparative example, Figure 3A A cross-sectional view of an integrated circuit structure having nanowires and a metal front gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 3B A cross-sectional view of an integrated circuit structure having nanowires and notched metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0064] refer to Figure 3AThe integrated circuit structure 300 includes a sub-fin 302 having a portion protruding above a shallow trench isolation (STI) structure 304. A plurality of horizontally stacked nanowires 305 are on the sub-fin 302. A gate dielectric material layer 306, such as a high-k gate dielectric layer, is on the protruding portion of the sub-fin 302, on the STI structure 304, and surrounding the horizontally stacked nanowires 305. It should be understood that, although not depicted, oxidized portions of the sub-fin 302 and the horizontally stacked nanowires 305 may be between the protruding portion of the sub-fin 302 and the gate dielectric material layer 306, and between the horizontally stacked nanowires 305 and the gate dielectric material layer 306, and may be included together with the gate dielectric material layer 306 to form a gate dielectric structure. A conductive gate layer 308, such as a work function metal layer, is on the gate dielectric material layer 306, and, as depicted, may be directly on the gate dielectric material layer 306. A conductive gate filler 310 is on top of the conductive gate layer 308, and as depicted, may be directly on the conductive gate layer 308. A dielectric gate cap 312 is on the conductive gate filler 310. A dielectric gate notch plug 314 is horizontally spaced from the sub-fins 302 and a plurality of horizontally stacked nanowires 305, and is on the STI structure 304. A gate dielectric material layer 306 and a conductive gate layer 308 are along the sidewalls of the dielectric gate notch plug 314.

[0065] refer to Figure 3BThe integrated circuit structure 350 includes a sub-fin 352 having a portion protruding above a shallow trench isolation (STI) structure 354. Multiple horizontally stacked nanowires 355 are on the sub-fin 352. A gate dielectric material layer 356, such as a high-k gate dielectric layer, is on the protruding portion of the sub-fin 352, on the STI structure 354, and surrounding the horizontally stacked nanowires 355. It should be understood that, although not depicted, oxidized portions of the sub-fin 352 may be between the protruding portion of the sub-fin 352 and the gate dielectric material layer 356, and between the horizontally stacked nanowires 355 and the gate dielectric material layer 356, and may be included together with the gate dielectric material layer 356 to form a gate dielectric structure. A conductive gate layer 358, such as a work function metal layer, is on the gate dielectric material layer 356, and as depicted, may be directly on the gate dielectric material layer 356. A conductive gate filler 360 is on top of the conductive gate layer 358 and, as depicted, can be directly on the conductive gate layer 358. A dielectric gate cap 362 is on the conductive gate filler 360. A dielectric gate notch plug 364 is laterally spaced from the sub-fins 352 and the plurality of horizontally stacked nanowires 355, and is on the STI structure 354, but does not penetrate the STI structure 354. However, the gate dielectric material layer 356 and the conductive gate layer 358 do not run along the sides of the dielectric gate notch plug 364. Instead, the conductive gate filler 360 contacts the sides of the dielectric gate notch plug 364. Therefore, the region between the dielectric gate notch plug 364 and the combination of the sub-fins 352 and the plurality of horizontally stacked nanowires 355 comprises only one layer of gate dielectric material layer 356 and only one layer of conductive gate layer 358, which alleviates the space constraints in this compact region of structure 350.

[0066] Refer again Figure 3B In one embodiment, a dielectric gate notch plug 364 is formed after the gate dielectric material layer 356, the conductive gate layer 358, and the conductive gate fill material 360 are formed. Therefore, the gate dielectric material layer 356 and the conductive gate layer 358 are not formed along the sidewalls of the dielectric gate notch plug 364. In one embodiment, as depicted, the dielectric gate notch plug 364 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 362. In another embodiment not depicted, the dielectric gate cap 362 is not included, and the dielectric gate notch plug 364 has an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 360, for example, along plane 380.

[0067] A dielectric gate cutout plug can be fabricated on the gate end cap wall of a nanowire device. As a comparative example, Figure 4A A cross-sectional view of an integrated circuit structure having nanowires and a metal front gate dielectric plug according to an embodiment of the present disclosure is shown. Figure 4B A cross-sectional view of an integrated circuit structure having nanowires and notched metal gate dielectric plugs according to an embodiment of the present disclosure is shown.

[0068] refer to Figure 4A The integrated circuit structure 400 includes a sub-fin 402 having a portion protruding above a shallow trench isolation (STI) structure 404. A plurality of horizontally stacked nanowires 405 are situated above the sub-fin 402. A gate end-cap structure 403, such as a self-aligned gate end-cap structure, is situated on the STI structure 404 and laterally spaced from the sub-fin 402 and the plurality of horizontally stacked nanowires 405. A gate dielectric material layer 406, such as a high-k gate dielectric layer, is situated above the protruding portion of the sub-fin 402, above the STI structure 404, along the side of the gate end-cap structure 403, and surrounding the horizontally stacked nanowires 405. It should be understood that, although not shown, the oxidized portions of the sub-fins 402 and the horizontally stacked nanowires 405 may be included between the protruding portions of the sub-fins 402 and the gate dielectric material layer 406, and between the horizontally stacked nanowires 405 and the gate dielectric material layer 406, and may be included together with the gate dielectric material layer 406 to form a gate dielectric structure. A conductive gate layer 408, such as a work function metal layer, is on the gate dielectric material layer 406, and as depicted, may be directly on the gate dielectric material layer 406. A conductive gate fill material 410 is on the conductive gate layer 408, and as depicted, may be directly on the conductive gate layer 408. A dielectric gate cap 412 is on the conductive gate fill material 410. A dielectric gate notch plug 414 is on the gate cap structure 403. The gate dielectric material layer 406 and the conductive gate layer 408 are along the sides of the dielectric gate notch plug 414.

[0069] refer to Figure 4BThe integrated circuit structure 450 includes a sub-fin 452 having a portion protruding above a shallow trench isolation (STI) structure 454. A plurality of horizontally stacked nanowires 455 are situated above the sub-fin 452. A gate end-cap structure 453, such as a self-aligned gate end-cap structure, is situated on the STI structure 454 but does not penetrate it, and is laterally spaced from the sub-fin 452 and the plurality of horizontally stacked nanowires 455. A gate dielectric material layer 456, such as a high-k gate dielectric layer, is situated above the protruding portion of the sub-fin 452, above the STI structure 454, along the side of the gate end-cap structure 453, and surrounding the horizontally stacked nanowires 455. It should be understood that, although not depicted, the oxidized portion of the sub-fin 452 may be between the protruding portion of the sub-fin 452 and the gate dielectric material layer 456, and between the horizontally stacked nanowires 455 and the gate dielectric material layer 456, and may be included together with the gate dielectric material layer 456 to form a gate dielectric structure. A conductive gate layer 458, such as a work function metal layer, is on the gate dielectric material layer 456, and as depicted, may be directly on the gate dielectric material layer 456. A conductive gate fill material 460 is on the conductive gate layer 458, and as depicted, may be directly on the conductive gate layer 458. A dielectric gate cap 462 is on the conductive gate fill material 460. A dielectric gate notch plug 464 is on the gate cap structure 453. However, the gate dielectric material layer 456 and the conductive gate layer 458 are not along the sides of the dielectric gate notch plug 464. Instead, the conductive gate filling material 460 makes side contact with the dielectric gate cutout plug 464.

[0070] refer to Figure 4B In one embodiment, a dielectric gate notch plug 464 is formed after the gate dielectric material layer 456, the conductive gate layer 458, and the conductive gate fill material 460 are formed. Therefore, the gate dielectric material layer 456 and the conductive gate layer 458 are not formed along the sidewalls of the dielectric gate notch plug 464. In one embodiment, as depicted, the dielectric gate notch plug 464 has an uppermost surface coplanar with the uppermost surface of the dielectric gate cap 462. In another embodiment not depicted, the dielectric gate cap 462 is not included, and the dielectric gate notch plug 464 has an uppermost surface coplanar with the uppermost surface of the conductive gate fill material 460, for example, along plane 480.

[0071] In another aspect, selective or non-selective versions of the metal gate notch can be implemented. As an example, Figures 5A-5C A plan view of a comparative integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 5A Representing the conventional "plug-first" method, it shows two gate cutout plugs in adjacent gates. Figure 5BThis represents a selective metal gate notching method, which illustrates two gate notch plugs in adjacent gates. Figure 5C This represents a non-selective metal gate notching method, which illustrates a long gate notch plug spanning multiple gates.

[0072] refer to Figure 5A The integrated circuit structure 500 includes gate lines and power or drain contacts 518 between dielectric spacers 517. Each gate line includes a gate dielectric material layer 506, a conductive gate layer 508 such as a work function metal layer, and a conductive gate fill material 510. A dielectric gate notch plug 514 can disconnect a portion of the corresponding gate line. The dielectric gate notch plug 514 contacts the conductive gate layer 508 but not the gate dielectric material layer 506 or the conductive gate fill material 510. Figure 5A The floor plan can correspond to Figure 2A , Figure 3A or Figure 4A The structure. It should be understood that, although referred to above as power supply or drain contact 518, at an earlier stage of the process or in other locations in the integrated circuit structure, a occupier or dielectric plug may be located in the position of power supply or drain contact 518.

[0073] refer to Figure 5B The integrated circuit structure 550 includes gate lines and power or drain contacts 568 between dielectric spacers 567. Each gate line includes a gate dielectric material layer 556, a conductive gate layer 558 such as a work function metal layer, and a conductive gate fill material 560. A dielectric gate notch plug 564 can disconnect a portion of the corresponding gate line. The dielectric gate notch plug 564 is in contact with the conductive gate fill material 560. Figure 5B The floor plan can correspond to Figure 2B , Figure 3B or Figure 4B The structure. It should be understood that, although referred to above as power supply or drain contact 568, in an earlier stage of the process or in other locations in the integrated circuit structure, a occupier or dielectric plug may be located in the position of power supply or drain contact 568.

[0074] refer to Figure 5CThe integrated circuit structure 570 includes gate lines and power or drain contacts 588 between dielectric spacers 587. Each gate line includes a gate dielectric material layer 576, a conductive gate layer 578 such as a work function metal layer, and a conductive gate fill material 580. A single dielectric gate cut-out plug 584 can disconnect a portion of the gate line and can extend through the dielectric spacers 587, and even partially or completely into one or more of the power or drain contacts 588. The dielectric gate cut-out plug 584 contacts the conductive gate fill material 580. Figure 5C The floor plan can correspond to Figure 2B , Figure 3B or Figure 4B The structure.

[0075] Refer again Figure 5C It should be understood that although referred to above as power source or drain contact 588, a placeholder dielectric or dielectric plug may be present in the location of power source or drain contact 588 at an earlier stage of the process or in other locations within the integrated circuit structure. In embodiments, the etching used to form the opening in which a single dielectric gate cut-out plug 584 is ultimately formed is referred to as non-selective etching. Where power source or drain contact 588 has already been formed, non-selective etching may etch into the conductive material of power source or drain contact 588. In other embodiments, where a placeholder dielectric or dielectric plug is present in the location of power source or drain contact 588, non-selective etching may etch into the placeholder dielectric or dielectric plug. In both cases, non-selective etching may etch through the epitaxial semiconductor material formed beneath the location of power source or drain contact 588 in the source or drain region, and may separate the epitaxial semiconductor material. When a conductive power electrode or drain contact 588 has already been formed, the epitaxial semiconductor material of the source or drain region may include a silicide portion.

[0076] Figures 6A-6C Cross-sectional views of comparative integrated circuit structures according to embodiments of the present disclosure are shown. Figure 6A This represents the conventional "plug first" method. Figure 6B This represents the selective metal gate grooving method. Figure 6C This represents a non-selective metal gate cutting method.

[0077] refer to Figure 6A The integrated circuit structure 600 includes a dielectric gate cut-out plug 614 between dielectric spacers 617 and a power supply or drain contact portion 618. Figure 6A The cross-sectional view can be corresponding to Figure 2A , Figure 3A , Figure 4A or Figure 5A An orthogonal diagram of the structure.

[0078] refer to Figure 6B The integrated circuit structure 650 includes a dielectric gate cut-out plug 664 between dielectric spacers 667 and a power supply or drain contact 668. Figure 6B The cross-sectional view can be corresponding to Figure 2B , Figure 3B , Figure 4B or Figure 5B An orthogonal diagram of the structure.

[0079] refer to Figure 6C The integrated circuit structure 670 includes a single dielectric gate cutout plug 684 between conductive power or drain contacts 688. The dashed box 690 illustrates... Figure 6B In this case, the corresponding discrete gate cut-out plug, such as gate cut-out plug 664, will be aligned to the desired position. Dashed box 692 shows the position where... Figure 6B In this case, the non-embedded gate or source contact 668 will be aligned at the desired location. The area between dashed boxes 690 and 692 illustrates the position where... Figure 6B In this case, the location where the dielectric spacer 667 will be located. Figure 6C The cross-sectional view can be corresponding to Figure 2B , Figure 3B , Figure 4B or Figure 5C An orthogonal diagram of the structure.

[0080] In the embodiments, the metal work function can be: (a) the same metal system in NMOS and PMOS, (b) different metal systems between NMOS and PMOS, and / or (c) a single material or a multilayer material (e.g., W, TiN, TiXAlyCz, TaN, Mo, MoN). In the embodiments, the metal notch etching chemical includes a chlorine- or fluorine-containing etchant with possible additional carbon- or silicon-containing components to provide passivation.

[0081] It should be understood that the embodiments described herein may also include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials including but not limited to Si and SiGe. For example, group III-V materials may be used.

[0082] It should be understood that, in certain embodiments, nanowires or nanoribbons or sacrificial intercalary layers may be composed of silicon. As used throughout, silicon layer can be used to describe silicon materials composed of, if not all, but a very large amount of silicon. However, it should be understood that, in practice, 100% pure Si may be difficult to form, and therefore may include minute percentages of carbon, germanium, or tin. Such impurities may be included as unavoidable impurities or components during Si deposition, or may “contaminate” Si during diffusion during post-deposition processing. Therefore, embodiments of silicon layers described herein may include silicon layers containing relatively small amounts (e.g., “impurity” levels) of non-Si atoms or types such as Ge, C, or Sn. It should be understood that silicon layers described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0083] It should be understood that, in certain embodiments, the nanowires or nanoribbons or sacrificial intercalator may be composed of silicon-germanium. As used throughout, a silicon-germanium layer can be used to describe a silicon-germanium material composed of a significant portion (e.g., at least 5% of both) of silicon and germanium. In some embodiments, the amount of germanium is greater than the amount of silicon. In a particular embodiment, the silicon-germanium layer comprises approximately 60% germanium and approximately 40% silicon (Si). 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon-germanium layer comprises approximately 30% germanium and approximately 70% silicon (Si). 70 Ge 30 It should be understood that, in practice, 100% pure silicon-germanium (commonly referred to as SiGe) may be difficult to form, and therefore may include a small percentage of carbon or tin. Such impurities can be included as unavoidable impurities or components during SiGe deposition, or can “contaminate” SiGe during diffusion during post-deposition processing. Therefore, the embodiments for silicon-germanium layers described herein may include silicon-germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge and non-Si atoms or types such as carbon or tin. It should be understood that the silicon-germanium layers described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0084] It should be understood that, in certain embodiments, the nanowires or nanoribbons or sacrificial intercalary layers may be composed of germanium. As used throughout, germanium layer can be used to describe germanium materials composed of, if not entirely, a very large amount of germanium. However, it should be understood that, in practice, 100% pure Ge may be difficult to form, and therefore may include minute percentages of carbon, silicon, or tin. Such impurities may be included as unavoidable impurities or components during Ge deposition, or may “contaminate” Ge during diffusion during post-deposition processing. Therefore, embodiments of germanium layers described herein may include germanium layers containing relatively small amounts (e.g., “impurity” levels) of non-Ge atoms or types such as Si, C, or Sn. It should be understood that germanium layers described herein may be undoped or may be doped with dopant atoms such as boron, phosphorus, or arsenic.

[0085] In another aspect, the integrated circuit structure described herein can also undergo a back-side exposure fabrication method for the front-side structure. In some exemplary embodiments, the exposure of the back side of a transistor or other device structure requires wafer-level back-side processing. In contrast to conventional TSV-type techniques, the back-side exposure of transistors described herein can be performed at the density of device cells, and even within sub-regions of the device. Furthermore, such back-side exposure of transistors can be performed to remove substantially all of the donor substrate on which the device layer is disposed during the front-side device processing. Therefore, since the thickness of the semiconductor in the device cell can be only tens or hundreds of nanometers after the back-side exposure of the transistor, micrometer-deep TSVs become unnecessary.

[0086] The exposure techniques described in this paper enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer used in front fabrication, exposed from the back, and reused in back fabrication. The treatment of both the front and exposed back of the device structure can address several challenges associated with 3D IC fabrication when relying primarily on front processing.

[0087] The method of exposing the back side of the transistor can be used, for example, to remove at least a portion of the carrier layer and intercalary layer of a donor-host substrate assembly. The process flow begins at the input of the donor-host substrate assembly. The thickness of the carrier layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any polishing and / or dry / wet etching process known to be suitable for the composition of the carrier layer can be used. For example, in the case where the carrier layer is a group IV semiconductor (e.g., silicon), a CMP polishing slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can also be used.

[0088] In some embodiments, prior to the above, the carrier layer is cracked along a fracture surface substantially parallel to the intercalary layer. A large portion of the carrier layer can be removed as a bulk using a cracking or fracturing process, thereby reducing the polishing or etching time required to remove the carrier layer. For example, for a carrier layer thickness of 400-900 μm, 100-700 μm can be cracked using any uniform-thickness implantation known to promote wafer-level fracturing. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted into the carrier layer to produce a uniform target depth of fracture surface. Following this cracking process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched to completely remove it. Alternatively, for cases where the carrier layer does not fracture, a larger thickness of the carrier layer can be removed using grinding, polishing, and / or etching operations.

[0089] Next, the exposure of the intermediate layer is detected. Detection is used to identify the point where the back surface of the donor substrate advances to near the device layer. Any endpoint detection technique known to be suitable for detecting the transition between the materials used for the carrier layer and the intermediate layer can be practiced. In some embodiments, one or more endpoint criteria are based on detecting changes in light absorption or light emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are associated with changes in light absorption or light emission of byproducts during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with carrier layer etching byproducts can vary depending on the different compositions of the carrier layer and the intermediate layer. In other embodiments, the endpoint criteria are associated with changes in the mass of material in the byproducts of polishing or etching the back surface of the donor substrate. For example, byproducts can be sampled using a quadrupole mass spectrometer, and changes in mass can be associated with different compositions of the carrier layer and the intermediate layer. In another exemplary embodiment, the endpoint criteria are associated with changes in the frictional force between the back surface of the donor substrate and the polished surface in contact with the back surface of the donor substrate.

[0090] For cases where the removal process is selective relative to the carrier layer over the intercalary layer, the detection of the intercalary layer can be enhanced because inhomogeneities in the carrier removal process can be mitigated by the difference in etching rates between the carrier and intercalary layers. If the grinding, polishing, and / or etching operations remove the intercalary layer at a rate sufficiently lower than that used to remove the carrier layer, detection can even be skipped. Without using endpoint criteria, grinding, polishing, and / or etching operations of a predetermined fixed duration can be stopped on the intercalary layer material if the thickness of the intercalary layer is sufficient to satisfy etching selectivity. In some examples, the carrier etching rate:intercalary layer etching rate is 3:1 to 10:1, or more.

[0091] After exposing the intercalary layer, at least a portion of it can be removed. For example, one or more component layers of the intercalary layer can be removed. The thickness of the intercalary layer can be uniformly removed, for example, by polishing. Alternatively, the thickness of the intercalary layer can be removed using a mask or uniform-thickness etching process. This process can use the same polishing or etching process used for thinning the carrier, or it can be a different process with different process parameters. For example, in cases where the intercalary layer provides an etching stop for the carrier removal process, subsequent operations can use different polishing or etching processes that facilitate the removal of the intercalary layer without removing the device layer. For cases where the thickness of the intercalary layer is less than a few hundred nanometers, the removal process can be relatively slow, optimized for cross-wafer uniformity, and subject to more precise control than that used for removing the carrier layer. The CMP process used can, for example, employ a polishing slurry that provides very high selectivity (e.g., 100:1-300:1, or more) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO), which surrounds the device layer and is embedded within the intercalary layer, for example, as electrical isolation between adjacent device regions.

[0092] For embodiments that expose the device layer by completely removing the intervening layer, the backside processing can begin on the exposed backside of the device layer or a specific device region therein. In some embodiments, the backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer disposed between the intervening layer and the device region (e.g., source or drain region) previously fabricated in the device layer.

[0093] In some embodiments where the back face of the carrier layer, intermediary layer, or device layer is recessed using wet and / or plasma etching, this etching can be patterned etching or material-selective etching, which imparts significant non-planarity or morphology to the back face surface of the device layer. As further described below, patterning can be within a device cell (i.e., “intra-cell” patterning) or across device cells (i.e., “inter-cell” patterning). In some patterned etching embodiments, at least a portion of the thickness of the intermediary layer is used as a hard mask for patterning the back face device layer. Therefore, the mask etching process can begin with the corresponding mask device layer etching.

[0094] The processing scheme described above can produce a donor-body substrate assembly including an IC device that has exposed the back side of an intermediary layer, the back side of a device layer, and / or the back side and / or front side metallization of one or more semiconductor regions within the device layer. Additional back side processing of any of these exposed regions can then be performed during downstream processing.

[0095] The following describes various apparatuses and processing methods that can be used to fabricate devices that can be integrated with fin isolation regions continuous with gate cut-out plugs. It should be understood that exemplary embodiments do not necessarily require all the features described, or may include more features than described. For example, a nanowire release process can be performed by replacing the gate trench. Examples of such a release process are described below. Additionally, in another aspect, back-end (BE) interconnect scaling can cause lower performance and higher manufacturing costs due to patterning complexity. Embodiments described herein can be implemented to achieve front and back interconnect integration for nanowire transistors or fin transistors. Embodiments described herein can provide methods to achieve relatively wide interconnect pitches. The result can be improved product performance and reduced patterning costs. Embodiments can be implemented to achieve robust functionality of scaled nanowire or nanoribbon transistors with low power and high performance.

[0096] One or more embodiments described herein are for oriented dual epitaxial (EPI) connections of nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depths. In the embodiments, the integrated circuit structure is fabricated by forming source-drain openings filled with SD epitaxial portions of the nanowire / nanoribbon transistor. The remainder of the openings is filled with a conductive material. Deep trench formation on one of the source or drain sides enables direct contact to the back-side interconnect stage.

[0097] This is an exemplary process flow for fabricating a gate-all-around device for a gate-all-around integrated circuit structure. Figures 7A-7J Cross-sectional views of various operations in a method of fabricating a gate-all-around integrated circuit structure according to embodiments of the present disclosure are shown.

[0098] refer to Figure 7A A method of fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 704 and nanowires 706 above fins 702, such as silicon fins. The nanowires 706 may be referred to as vertically arranged nanowires. As depicted, a protective cap 708 may be formed above the alternating sacrificial layers 704 and nanowires 706. Also as depicted, a relaxation buffer layer 752 and a defect modification layer 750 may be formed below the alternating sacrificial layers 704 and nanowires 706.

[0099] refer to Figure 7B A gate stack 710 is formed on the vertical arrangement of horizontal nanowires 706. Then, the vertically arranged portion of the horizontal nanowires 706 is released by removing a portion of the sacrificial layer 704 to provide, for example... Figure 7C The recessed sacrificial layer 704' and cavity 712 are depicted in the image.

[0100] It should be understood that the fabrication can be completed without first performing the deep etching and asymmetric contact treatments described below. Figure 7C The structure. In both cases (e.g., with or without asymmetric contact processing), in embodiments, the fabrication process involves the use of a process scheme to provide a gate-surround integrated circuit structure with an epitaxial block, which may be a vertically discrete source or drain structure.

[0101] refer to Figure 7D An upper gate spacer 714 is formed at the sidewall of the gate structure 710. A cavity spacer 716 is formed in the cavity 712 below the upper gate spacer 714. Then, optionally, deep trench contact etching is performed to form a trench 718 and a recessed nanowire 706'. As depicted, a patterned relaxation buffer layer 752' and a patterned defect modification layer 750' may also be present.

[0102] Then, as Figure 7E As depicted, sacrificial material 720 is formed in trench 718. In other process options, an isolated trench bottom or a silicon trench bottom can be used.

[0103] refer to Figure 7F A first epitaxial source or drain structure (e.g., left-side feature 722) is formed at a first end of the vertically arranged horizontal nanowire 706'. A second epitaxial source or drain structure (e.g., right-side feature 722) is formed at a second end of the vertically arranged horizontal nanowire 706'. In embodiments, as depicted, the epitaxial source or drain structure 722 is a vertically discrete source or drain structure and may be referred to as an epitaxial block.

[0104] Then, as Figure 7G As depicted, an interlayer dielectric (ILD) material 724 is formed on the sides of the gate electrode 710 and the adjacent source or drain structure 722. (Reference) Figure 7H The gate replacement process is used to form the permanent gate dielectric 728 and the permanent gate electrode 726. Then, as... Figure 7I As depicted, ILD material 724 is removed. Then, sacrificial material 720 is removed from one of the source and drain locations (e.g., the right side) to form trench 732, but sacrificial material 720 is not removed from the other source and drain location to form trench 730.

[0105] refer to Figure 7JA first conductive contact structure 734 is formed, which is coupled to a first epitaxial source or drain structure (e.g., left-side feature 722). A second conductive contact structure 736 is formed, which is coupled to a second epitaxial source or drain structure (e.g., right-side feature 722). The second conductive contact structure 736 is formed deeper along the fin 702 than the first conductive contact structure 734. In the embodiment, although not in Figure 7J As depicted, the method also includes forming an exposed surface of a second conductive contact structure 736 at the bottom of the fin 702. The conductive contact portion may include a contact resistance reduction layer and a main contact electrode layer, wherein examples may include Ti, Ni, Co (for the former, and W, Ru, Co for the latter).

[0106] In one embodiment, as depicted, the second conductive contact structure 736 is deeper along the fin 702 than the first conductive contact structure 734. In one such embodiment, as depicted, the first conductive contact structure 734 is not along the fin 702. In another such embodiment, not depicted, the first conductive contact structure 734 is partially along the fin 702.

[0107] In one embodiment, the second conductive contact structure 736 extends along the entire fin 702. In another embodiment, although not depicted, the second conductive contact structure 736 has an exposed surface at the bottom of the fin 702 when the bottom of the fin 702 is exposed via a back substrate removal process.

[0108] In the embodiments, it is possible to manufacture Figure 7J The structure, or Figures 7A-7J The related structures include a fin-isolated region that is continuous with the gate cutout plug, an example of which is described above.

[0109] It should be understood that the structure obtained from the above exemplary processing scheme can be used in the same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of the completed device, Figure 8 A cross-sectional view along the gate line of a non-planar integrated circuit structure according to an embodiment of the present disclosure is shown.

[0110] refer to Figure 8The semiconductor structure or device 800 includes a nonplanar active region within a trench isolation region 806 (e.g., a fin structure including a protruding fin portion 804 and a sub-fin region 805). In embodiments, the nonplanar active region is not a solid fin, but is divided into nanowires (e.g., nanowires 804A and 804B) above the sub-fin region 805, as indicated by dashed lines. In both cases, for ease of description of the nonplanar integrated circuit structure 800, the nonplanar active region 804 is hereinafter referred to as the protruding fin portion. In embodiments, as depicted, the sub-fin region 805 also includes a relaxation buffer layer 842 and a defect modification layer 840.

[0111] Gate line 808 is disposed over a protrusion 804 of the non-planar active region (including, where applicable, the area surrounding nanowires 804A and 804B) and a portion of the trench isolation region 806. As shown, gate line 808 includes a gate electrode 850 and a gate dielectric layer 852. In one embodiment, gate line 808 may also include a dielectric cap layer 854. From this view, gate contact 814 and the overlying gate contact via 816, together with the overlying metal interconnect 860, are all disposed within the interlayer dielectric stack or layer 870. Figure 8 From another perspective, it can also be seen that in one embodiment, the gate contact 814 is disposed above the trench isolation region 806, but not above the non-planar active region. In another embodiment, the gate contact 814 is disposed above the non-planar active region.

[0112] In this embodiment, the semiconductor structure or device 800 is a non-planar device, such as, but not limited to, a FIN-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In this embodiment, the corresponding semiconductor channel region is composed of, or formed within, a three-dimensional body. In one such embodiment, the gate electrode stack of the gate line 808 surrounds at least the top surface and a pair of sidewalls of the three-dimensional body.

[0113] As also Figure 8 As depicted, in one embodiment, interface 880 exists between the protruding fin portion 804 and the sub-fin region 805. Interface 880 may be a transition region between the doped sub-fin region 805 and the lightly doped or undoped upper fin portion 804. In one such embodiment, each fin is approximately 10 nanometers wide or narrower, and sub-fin dopant is optionally provided from an adjacent solid-state doped layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

[0114] Although not in Figure 8As depicted, but to be understood, the source or drain region of the protruding fin portion 804, or the source or drain region adjacent to the protruding fin portion 804, is on both sides of the gate line 808, i.e., inside and outside the page. In one embodiment, the material of the protruding fin portion 804 at the source or drain location is removed and replaced, for example, by epitaxial deposition, with another semiconductor material to form an epitaxial source or drain structure. The source or drain region may extend below the height of the dielectric layer of the trench isolation region 806, i.e., into the sub-fin region 805. According to embodiments of this disclosure, the heavily doped sub-fin region, i.e., the doped portion of the fin below the interface 808, suppresses source-to-drain leakage through this portion of the bulk semiconductor fin. In embodiments, as described above... Figure 7J The described source and drain regions have associated asymmetric source and drain contact structures.

[0115] Refer again Figure 8 In the embodiments, the fins 804 / 805 (and possibly the nanowires 804A and 804B) consist of a crystalline silicon-germanium layer that may be doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, gallium or combinations thereof.

[0116] In embodiments, trench isolation region 806, and the trench isolation region (trench isolation structure or trench isolation layer) described throughout the text, may be composed of materials suitable for ultimately electrically isolating portions of a permanent gate structure from the underlying bulk substrate, or facilitating the isolation of portions of a permanent gate structure from the underlying bulk substrate, or isolating isolated active regions such as isolated fin active regions formed within the underlying bulk substrate. For example, in one embodiment, trench isolation region 806 is composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0117] Gate line 808 may be composed of a gate electrode stack including a gate dielectric layer 852 and a gate electrode layer 850. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate, and the gate dielectric layer is composed of a high-k material. For example, in one embodiment, the gate dielectric layer 852 is composed of materials such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, zinc lead niobate, or combinations thereof. Furthermore, a portion of the gate dielectric layer 852 may include a layer of natural oxide formed from the top few layers of the substrate fin 804. In an embodiment, the gate dielectric layer 852 consists of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 852 consists of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some embodiments, the gate dielectric portion is a "U"-shaped structure, comprising a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0118] In one embodiment, the gate electrode layer 850 is composed of a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode layer 850 is composed of a non-work function filling material formed above the metal work function setting layer. Depending on whether the transistor will be a PMOS transistor or an NMOS transistor, the gate electrode layer 850 may be composed of a P-type work function metal or an N-type work function metal. In some embodiments, the gate electrode layer 850 may be composed of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers, and at least one metal layer is a conductive filling layer. For PMOS transistors, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer will enable the formation of a PMOS gate electrode having a work function between approximately 4.9 eV and approximately 5.2 eV. For NMOS transistors, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode having a work function between approximately 3.9 eV and approximately 4.2 eV. In some embodiments, the gate electrode may be formed of a "U"-shaped structure, including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another embodiment, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and does not include the sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments of this disclosure, the gate electrode may be formed of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may be formed of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0119] The spacers associated with the gate electrode stack can be composed of materials suitable for ultimately electrically isolating, or contributing to, adjacent conductive contacts such as self-aligned contacts, the permanent gate structure. For example, in one embodiment, the spacers are composed of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0120] The gate contact 814 and the overlying gate contact via 816 may be made of a conductive material. In embodiments, one or more of the contacts or vias may be made of a metal. The metal may be a pure metal, such as tungsten, nickel, or cobalt, or it may be an alloy, such as a metal-metal alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0121] In an embodiment (though not shown), a contact pattern is formed that is substantially perfectly aligned to the existing gate pattern 808, while eliminating the use of photolithography steps with very tight registration budgets. In an embodiment, the contact pattern is a vertically symmetrical contact pattern, or, as in combination... Figure 7J The described asymmetric contact pattern. In other embodiments, all contacts are front-facing connected and not asymmetric. In one such embodiment, the self-aligned method achieves the creation of contact openings using inherently highly selective wet etching (e.g., compared to conventional dry or plasma etching). In embodiments, the contact pattern is formed by utilizing existing gate patterns in conjunction with contact plug lithography operations. In one such embodiment, the method eliminates the need for lithography operations that are critical in other cases for creating contact patterns, as used in conventional methods. In embodiments, the trench contact mesh is not patterned separately but formed between polysilicon (gate) lines. For example, in one such embodiment, the trench contact mesh is formed after the gate grid patterning but before the gate grid notch.

[0122] In an embodiment, providing structure 800 involves fabricating a gate stack body structure 808 using a gate replacement process. In this approach, a dummy gate material, such as a columnar material of polysilicon or silicon nitride, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, rather than in an earlier process. In an embodiment, the dummy gate is removed using a dry etching or wet etching process. In one embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a dry etching process including the use of SF6. In another embodiment, the dummy gate is composed of polysilicon or amorphous silicon and is removed using a wet etching process including the use of an aqueous solution of NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is composed of silicon nitride and is removed using a wet etching process including an aqueous solution of phosphoric acid.

[0123] Refer again Figure 8 In one embodiment, the semiconductor structure or device 800 is arranged with the gate contacts placed over an isolation region. This arrangement can be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure in which the gate electrode is formed over the active region (e.g., over the fin 805) and in the same layer as the trench contact via.

[0124] In the embodiments, it is possible to manufacture Figure 8 The structure includes a fin-isolated region that is continuous with the gate cutout plug, an example of which is described above.

[0125] It should be understood that not all aspects of the processes described above are required to fall within the spirit and scope of the embodiments of this disclosure. Similarly, the processes described herein can be used to fabricate one or more semiconductor devices. A semiconductor device can be a transistor or similar device. For example, in embodiments, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic cells or memory, or a bipolar transistor. Likewise, in embodiments, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, a separate access dual-gate device, or a FIN-FET. One or more embodiments can be particularly useful for fabricating semiconductor devices at sub-10 nanometer (nm) technology nodes.

[0126] In embodiments, as used throughout this description, the interlayer dielectric (ILD) material comprises or includes a layer of dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material can be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

[0127] In embodiments, as used throughout this description, the metal wire or interconnect material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper wires and structures that may or may not include a barrier layer between copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect may include a barrier layer (e.g., a layer comprising one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, an interconnect may be a single layer of material or may be formed from several layers including a conductive liner and a filler layer. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect. In embodiments, the interconnect is composed of a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. Interconnects are sometimes also referred to in the art as traces, wires, lines, metals, or simply interconnects.

[0128] In embodiments, as used throughout this description, the hard mask material, cap layer, or plug is composed of a dielectric material different from the interlayer dielectric material. In one embodiment, different hard mask, cap, or plug materials can be used in different regions to provide different growth or etching selectivity relative to each other and relative to the underlying dielectric and metal layers. In some embodiments, the hard mask layer, cap, or plug layer comprises a silicon nitride (e.g., silicon nitride) layer or a silicon oxide layer, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Depending on the specific implementation, other hard mask, cap, or plug layers known in the art may be used. The hard mask, cap, or plug layer can be formed by CVD, PVD, or other deposition methods.

[0129] In the embodiments, as used throughout this description, lithography operations are performed using a 193 nm immersion lithography machine (i193), EUV, and / or EBDW lithography. Positive or negative tone resists can be used. In one embodiment, the lithographic mask is a three-layer mask consisting of a topography masking portion, an antireflective coating (ARC) layer, and a photoresist layer. In a particular embodiment of this type, the topography masking portion is a carbon hard mask (CHM) layer, and the antireflective coating layer is a silicon ARC layer.

[0130] In another aspect, one or more embodiments target adjacent semiconductor structures or devices separated by a self-aligned gate end cap (SAGE) structure. Specific embodiments may target the integration of multiple width (multi-Wsi) nanowires and nanoribbons within a SAGE architecture and separated by SAGE walls. In embodiments, the nanowires / nanoribbons are integrated with multiple Wsi within a portion of the SAGE architecture in a front-end process flow. This process flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality for next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be embedded (e.g., removing portions of the nanowires and then performing source or drain (S / D) growth).

[0131] To provide further context, the advantages of the self-aligned gate end cap (SAGE) architecture can include achieving higher layout density, and, in particular, scaling of diffusion to diffusion spacing. For illustrative comparison, Figure 9 Cross-sectional views taken through nanowires and fins are shown of a non-endcap architecture (left side (a)) and a self-aligned gate endcap (SAGE) architecture (right side (b)) according to embodiments of the present disclosure.

[0132] refer to Figure 9On the left side (a), the integrated circuit structure 900 includes a substrate 902 with fins 904 protruding from the substrate 902 to an extent 906 above an isolation structure 908, which laterally surrounds the lower portion of the fins 904. As depicted, the upper portion of the fins may include a relaxation buffer layer 922 and a defect modification layer 920. Corresponding nanowires 905 are on top of the fins 904. A gate structure may be formed on the integrated circuit structure 900 to fabricate a device. However, discontinuities in such a gate structure can be accommodated by increasing the spacing between the fin 904 / nanowire 905 pairs.

[0133] In comparison, reference Figure 9 On the right side (b), the integrated circuit structure 950 includes a substrate 952 having fins 954 protruding from the substrate 952 to an extent 956 above an isolation structure 958, which laterally surrounds a lower portion of the fins 954. As depicted, the upper portion of the fins may include a relaxation buffer layer 972 and a defect modification layer 970. Corresponding nanowires 955 are above the fins 954. Isolation SAGE walls 960 (as depicted, which may include a hard mask thereon) are included within the isolation structure 952 and between adjacent pairs of fins 954 / nanowires 955. The distance between the isolation SAGE wall 960 and the nearest pair of fins 954 / nanowires 955 defines a gate cap spacing 962. A gate structure may be formed above the integrated circuit structure 900, between the isolation SAGE walls, to fabricate a device. Discontinuities in this gate structure are imposed by the isolation SAGE walls. Because the isolation SAGE wall 960 is self-aligned, limitations from conventional methods can be minimized to achieve more aggressive diffusion to the diffusion interval. Furthermore, because the gate structure includes discontinuities at all locations, individual gate structure portions can be layered via local interconnects formed on the isolation SAGE wall 960. In embodiments, as depicted, each SAGE wall 960 includes a lower dielectric portion and a dielectric cap on the lower dielectric portion. According to embodiments of this disclosure, for use with… Figure 9 The fabrication process of the associated structure involves the use of process solutions to provide a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0134] In the embodiments, it is possible to manufacture Figure 9 The structure of part (a) includes a fin-isolated region continuous with the gate cutout plug, an example of which has been described above. In embodiments, it can be fabricated Figure 9 Part (b) has a structure that includes a fin-isolated region that is continuous with the gate cutout plug, an example of which is described above.

[0135] The self-aligned gate end cap (SAGE) processing scheme involves the formation of gate / trench contact end caps that are self-aligned to the fins without requiring additional length to handle mask misregistration. Therefore, embodiments can be implemented to achieve a reduction in transistor layout area. The embodiments described herein may relate to the fabrication of gate end cap isolation structures, which may also be referred to as gate walls, isolated gate walls, or self-aligned gate end cap (SAGE) walls.

[0136] In an exemplary processing scheme for a structure having SAGE walls that separate adjacent devices, Figure 10 Cross-sectional views are shown of various operations in a method for fabricating a self-aligned gate end cap (SAGE) structure with a gate full-around device, according to an embodiment of the present disclosure.

[0137] refer to Figure 10 Part (a) of the initial structure includes a nanowire patterned stack 1004 over a substrate 1002. A photolithographically patterned stack 1006 is formed over the nanowire patterned stack 1004. As depicted, the nanowire patterned stack 1004 includes alternating sacrificial layers 1010 and nanowire layers 1012, which may be over a relaxation buffer layer 1082 and a defect modification layer 1080. A protective mask 1014 is located between the nanowire patterned stack 1004 and the photolithographically patterned stack 1006. In one embodiment, the photolithographically patterned stack 1006 is a three-layer mask consisting of a topography masking portion 1020, an antireflective coating (ARC) layer 1022, and a photoresist layer 1024. In this particular embodiment, the topography masking portion 1020 is a carbon hard mask (CHM) layer, and the antireflective coating layer 1022 is a silicon ARC layer.

[0138] refer to Figure 10 Part (b) involves photolithographically patterning the stack of part (a) and then etching it to provide an etched structure including a patterned substrate 1002 and trenches 1030.

[0139] refer to Figure 10 Parts (c) and (b) have an isolation layer 1040 and a SAGE material 1042 formed in the trench 1030. The structure is then planarized to leave a patterned topographic masking layer 1020' as the exposed upper layer.

[0140] refer to Figure 10 The portion (d) is such that the isolation layer 1040 is recessed below the upper surface of the patterned substrate 1002 to, for example, define the protruding fin portion and provide the trench isolation structure 1041 below the SAGE wall 1042.

[0141] refer to Figure 10In part (e), at least in the channel region, the sacrificial layer 1010 is removed to release nanowires 1012A and 1012B. During the formation of... Figure 10 Following the structure of part (e), a gate stack can be formed around nanowire 1012B or nanowire 1012A, over the protruding fins of substrate 1002, and between the SAGE wall 1042. In one embodiment, the remainder of the protective mask 1014 is removed before forming the gate stack. In another embodiment, the remainder of the protective mask 1014 is retained as an insulating fin cap, which is an artifact of the processing scheme.

[0142] Refer again Figure 10 Part (e) depicts a channel view, wherein the source or drain regions are located inside and outside the page. In an embodiment, the channel region including nanowire 1012B has a smaller width than the channel region including nanowire 1012A. Therefore, in an embodiment, the integrated circuit structure includes multiple width (multi-Wsi) nanowires. Although the structures of 1012B and 1012A can be distinguished as nanowires and nanoribbons, respectively, both structures are generally referred to herein as nanowires. It should also be understood that references or depictions of fin / nanowire pairs throughout the document can refer to fins and one or more overlay nanowires (e.g., Figure 10 The structure of two overlaid nanowires is shown. According to embodiments of this disclosure, it is used with... Figure 10 The fabrication process of the associated structure involves the use of process solutions to provide a gate-all-around integrated circuit structure with an epitaxial source or drain structure.

[0143] In the embodiments, it is possible to manufacture Figure 10 The structure of part (e) includes a fin-isolated region that is continuous with the gate cut-out plug, an example of which is described above.

[0144] In embodiments, as described throughout, the self-aligned gate end-cap (SAGE) isolation structure may be composed of one or more materials suitable for ultimately electrically isolating portions of a permanent gate structure from each other, or contributing to their isolation. Exemplary materials or combinations of materials include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or combinations of materials include multilayer stacks having a lower portion of silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a material with a higher dielectric constant, such as hafnium oxide.

[0145] To highlight the exemplary integrated circuit structure with three vertically arranged nanowires, Figure 11A A three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to an embodiment of the present disclosure is shown. Figure 11B It shows Figure 11A The source or drain diagram of a cross section taken along the a-a' axis of a nanowire-based integrated circuit structure. Figure 11C It shows Figure 11A A cross-sectional channel diagram of a nanowire-based integrated circuit structure taken along the b-b' axis.

[0146] refer to Figure 11A The integrated circuit structure 1100 includes one or more vertically stacked nanowires (set of 1104) above a substrate 1102. In embodiments, as depicted, a relaxation buffer layer 1102C, a defect modification layer 1102B, and a lower substrate portion 1102A are included in the substrate 1102, as depicted. Optional fins formed from the substrate 1102 below the bottommost nanowire are not depicted for illustrative purposes due to the emphasis on the nanowire portion. The embodiments herein pertain to both single-wire and multi-wire devices. As an example, a three-nanowire-based device having nanowires 1104A, 1104B, and 1104C is shown for illustrative purposes. For ease of description, nanowire 1104A is used as an example, where the description focuses on one nanowire. It should be understood that in describing the properties of a single nanowire, embodiments based on multiple nanowires may have the same or substantially the same properties for each nanowire.

[0147] Each nanowire in nanowire 1104 includes a channel region 1106. The channel region 1106 has a length (L). Reference Figure 11C The channel region also has a perimeter (Pc) orthogonal to its length (L). (See reference) Figure 11A and Figure 11C Both, the gate electrode stack 1108 surrounds the entire perimeter (Pc) of each channel region in the channel regions 1106. The gate electrode stack 1108 includes a gate electrode and a gate dielectric layer between the channel regions 1106 and the gate electrode (not shown). In embodiments, the channel regions are discrete because they are completely surrounded by the gate electrode stack 1108 without any intermediary material such as a lower substrate material or an overlying channel fabrication material. Accordingly, in embodiments having multiple nanowires 1104, the channel regions 1106 of the nanowires are also discrete relative to each other.

[0148] refer to Figure 11A and Figure 11BBoth, the integrated circuit structure 1100 includes a pair of non-discrete source or drain regions 1110 / 1112. The pair of non-discrete source or drain regions 1110 / 1112 are on either side of a channel region 1106 of multiple vertically stacked nanowires 1104. Furthermore, the pair of non-discrete source or drain regions 1110 / 1112 are adjacent to the channel region 1106 of the multiple vertically stacked nanowires 1104. In one such embodiment (not depicted), the pair of non-discrete source or drain regions 1110 / 1112 are directly perpendicularly adjacent to the channel region 1106 because epitaxial growth occurs on and between nanowire portions extending beyond the channel region 1106, wherein the nanowire ends are shown within the source or drain structure. In another embodiment, as... Figure 11A As depicted, a pair of non-discrete source or drain regions 1110 / 1112 are indirectly perpendicularly adjacent to the channel region 1106 because they are formed at the ends of the nanowires and not between the nanowires.

[0149] In embodiments, as depicted, the source or drain regions 1110 / 1112 are non-discrete because there are no individual and discrete source or drain regions for each channel region 1106 of the nanowire 1104. Accordingly, in embodiments with multiple nanowires 1104, the source or drain regions 1110 / 1112 of the nanowires are integral or monolithic source or drain regions for each nanowire, rather than discrete. That is, the non-discrete source or drain regions 1110 / 1112 are monolithic in the sense that a single monolithic feature is used as the source or drain region for multiple (in this case, 3) nanowires 1104, and more specifically, for the source or drain region for more than one discrete channel region 1106. In one embodiment, as in Figure 11B As depicted, from a cross-sectional view orthogonal to the length of the discrete channel region 1106, each of the pair of non-discrete source or drain regions 1110 / 1112 is approximately rectangular in shape, having a bottom tapered portion and a top vertex portion. However, in other embodiments, the source or drain regions 1110 / 1112 of the nanowire are relatively large but discrete non-vertically fused epitaxial structures, such as those combined with… Figures 7A-7J The block being described.

[0150] According to embodiments of this disclosure, and as Figure 11A and Figure 11B As depicted, the integrated circuit structure 1100 also includes a pair of contacts 1114, each contact 1114 on one of a pair of non-discrete source or drain regions 1110 / 1112. In one such embodiment, each contact 1114 completely surrounds the corresponding non-discrete source or drain region 1110 / 1112 in a vertical sense. In another aspect, as... Figure 11B As depicted, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 may not be in contact with the contact portion 1114, and therefore, the contact portion 1114 only partially surrounds the non-discrete source or drain regions 1110 / 1112. In a comparative embodiment not depicted, the entire perimeter of the non-discrete source or drain regions 1110 / 1112 (e.g., truncated along the a-a' axis) is surrounded by the contact portion 1114.

[0151] Refer again Figure 11A In one embodiment, the integrated circuit structure 1100 further includes a pair of spacers 1116. As depicted, the outer portions of the pair of spacers 1116 may overlap with portions of the non-discrete source or drain regions 1110 / 1112, providing "embedded" portions of the non-discrete source or drain regions 1110 / 1112 located beneath the pair of spacers 1116. Also as depicted, the embedded portions of the non-discrete source or drain regions 1110 / 1112 may not extend entirely beneath the pair of spacers 1116.

[0152] Substrate 1102 may be composed of materials suitable for fabricating integrated circuit structures. In one embodiment, substrate 1102 comprises a lower bulk substrate composed of a single crystal of a material, which may include, but is not limited to, silicon, germanium, silicon-germanium, germanium-tin, silicon-germanium-tin, or group III-V compound semiconductor materials. An upper insulating layer composed of a material that may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride is on the lower bulk substrate. Thus, structure 1100 can be fabricated from an initial insulator-on-semiconductor substrate. Alternatively, structure 1100 is formed directly from the bulk substrate, and local oxidation is used to form an electrically insulating portion instead of the aforementioned upper insulating layer. In another alternative embodiment, structure 1100 is formed directly from the bulk substrate, and doping is used to form electrically isolated active regions thereon, such as nanowires. In one such embodiment, the first nanowire (i.e., closest to the substrate) is in the form of an Ω-FET type structure.

[0153] In embodiments, as described below, the nanowire 1104 can be the size of a wire or strip and can have square or rounded corners. In embodiments, the nanowire 1104 is composed of a material such as, but not limited to, silicon, germanium, or combinations thereof. In one such embodiment, the nanowire is single-crystal. For example, for silicon nanowire 1104, the single-crystal nanowire can be based on a (100) global orientation, for example, having a z-direction of <100> As described below, other orientations may also be considered. In the embodiments, the size of the nanowire 1104 is nanoscale when viewed from a cross-sectional perspective. For example, in a specific embodiment, the minimum size of the nanowire 1104 is less than approximately 20 nanometers. In the embodiments, particularly in the channel region 1106, the nanowire 1104 is composed of a strained material.

[0154] refer to Figure 11C In this embodiment, each channel region 1106 has a width (Wc) and a height (Hc), which are approximately the same. That is, in both cases, the channel region 1106 is approximately square in cross-sectional profile, or if it is rounded, it is approximately circular in cross-sectional profile. In another aspect, the width and height of the channel regions do not need to be the same, for example, in the case of nanoribbons as described throughout the text.

[0155] In embodiments, as described throughout, the integrated circuit structure includes non-planar devices, such as, but not limited to, finFETs or tri-gate devices having corresponding one or more overlaid nanowire structures. In such embodiments, the corresponding semiconductor channel region comprises or is formed within a three-dimensional body having one or more discrete nanowire channel portions overlaid on the three-dimensional body. In one such embodiment, the gate structure surrounds at least the top surface and a pair of sidewalls of the three-dimensional body, and also surrounds each of the one or more discrete nanowire channel portions.

[0156] In the embodiments, it is possible to manufacture Figure 11A-11C The structure includes a fin-isolated region that is continuous with the gate cutout plug, an example of which is described above.

[0157] In embodiments, as described throughout, the underlying substrate may be composed of a semiconductor material capable of undergoing manufacturing processes and in which charge can migrate. In embodiments, the substrate is a bulk substrate composed of crystalline silicon, a silicon / germanium, or a germanium layer, doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof to form active regions. In one embodiment, the silicon atom concentration in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate comprises an epitaxial layer grown on top of a crystalline substrate (distinct from the crystalline substrate), for example, a silicon epitaxial layer grown on top of a boron-doped bulk silicon single-crystal substrate. The bulk substrate may alternatively be composed of group III-V materials. In embodiments, the bulk substrate is composed of group III-V materials, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or combinations thereof. In one embodiment, the bulk substrate is composed of a group III-V material, and the charge carrier dopant impurity atoms are atoms such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0158] The embodiments disclosed herein can be used to manufacture a wide variety of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, etc. In other embodiments, semiconductor memory can be manufactured. Furthermore, integrated circuits or other microelectronic devices can be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), mobile phones, personal electronic products, etc. Integrated circuits can be coupled to buses and other components in the system. For example, a processor can be coupled to memory, chipsets, etc., via one or more buses. Each of the processor, memory, and chipset can potentially be manufactured using the methods disclosed herein.

[0159] Figure 12 A computing device 1200 according to one embodiment of the present disclosure is shown. The computing device 1200 houses a board 1202. The board 1202 may include multiple components, including but not limited to a processor 1204 and at least one communication chip 1206. The processor 1204 is physically and electrically coupled to the board 1202. In some embodiments, at least one communication chip 1206 is also physically and electrically coupled to the board 1202. In other embodiments, the communication chip 1206 is part of the processor 1204.

[0160] Depending on its application, computing device 1200 may include other components that may or may not be physically and electrically coupled to board 1202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (e.g., hard disk drive, optical disc (CD), digital multifunction disc (DVD), etc.).

[0161] Communication chip 1206 implements wireless communication for transmitting data to or from computing device 1200. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data via modulated electromagnetic radiation through a non-solid medium. This term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not. Communication chip 1206 may implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and higher. Computing device 1200 may include a plurality of communication chips 1206. For example, the first communication chip 1206 can be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and the second communication chip 1206 can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others.

[0162] The processor 1204 of the computing device 1200 includes an integrated circuit die packaged within the processor 1204. The integrated circuit die of the processor 1204 may include one or more structures, such as an integrated circuit structure having a fin-isolated region continuous with a gate cut-out plug constructed according to embodiments of the present disclosure. The term "processor" may refer to any means or part of a means of processing electronic data from registers and / or memory to transform such electronic data into other electronic data that can be stored in registers and / or memory.

[0163] The communication chip 1206 also includes an integrated circuit die packaged within the communication chip 1206. The integrated circuit die of the communication chip 1206 may include one or more structures, such as an integrated circuit structure having a fin-isolated region continuous with a gate cut-out plug constructed according to embodiments of the present disclosure.

[0164] In other embodiments, another component housed within the computing device 1200 may include an integrated circuit die comprising one or more structures, such as an integrated circuit structure having a fin-isolated region continuous with a gate cut-out plug constructed according to embodiments of the present disclosure.

[0165] In various embodiments, the computing device 1200 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other embodiments, the computing device 1200 may be any other electronic device that processes data.

[0166] Figure 13 An interpolator 1300, including one or more embodiments of the present disclosure, is illustrated. The interpolator 1300 is an intermediary substrate for bridging a first substrate 1302 to a second substrate 1304. The first substrate 1302 may be, for example, an integrated circuit die. The second substrate 1304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interpolator 1300 is to extend a connection over a wider spacing or to reroute a connection to a different connection. For example, the interpolator 1300 may couple an integrated circuit die to a ball grid array (BGA) 1306, which may then be coupled to the second substrate 1304. In some embodiments, the first and second substrates 1302 / 1304 are attached to opposite sides of the interpolator 1300. In other embodiments, the first and second substrates 1302 / 1304 are attached to the same side of the interpolator 1300. And in other embodiments, three or more substrates are interconnected via the interpolator 1300.

[0167] The interposer 1300 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymeric material such as polyimide. In other embodiments, the interposer 1300 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials.

[0168] The interposer 1300 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1312. The interposer 1300 may also include embedded devices 1314, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1300. According to embodiments of this disclosure, the devices or processes disclosed herein can be used in the fabrication of the interposer 1300 or in the fabrication of components included in the interposer 1300.

[0169] Therefore, embodiments of this disclosure include an integrated circuit structure having a fin isolation region continuous with a gate cut-out plug, and a method for fabricating an integrated circuit structure having a fin isolation region continuous with a gate cut-out plug.

[0170] The above description of the embodiments illustrated in this disclosure, including the content described in the abstract, is not intended to be exhaustive or to limit this disclosure to its exact forms. Although specific embodiments and examples of this disclosure have been described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of this disclosure.

[0171] These modifications can be made to the disclosure based on the specific embodiments described above. The terminology used in the following claims should not be construed as limiting this disclosure to the specific embodiments described in the specification and claims. Rather, the scope of this disclosure is determined entirely by the following claims, which will be interpreted according to the established principles of claim interpretation.

[0172] Example Embodiment 1: An integrated circuit structure includes a vertical stack of horizontal nanowires above a first sub-fin. A gate structure is above the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced from the gate structure. The dielectric structure is not above a channel structure but is on a second sub-fin. A gate notch is located between the gate structure and the dielectric structure. A dielectric gate notch plug is inserted into the gate notch. The dielectric gate notch plug is continuous with the dielectric structure.

[0173] Example 2: The integrated circuit structure of Example 1, wherein the dielectric gate cut-out plug has an uppermost surface at the same level as the uppermost surface of the dielectric structure.

[0174] Example 3: The integrated circuit structure of Example 1 or 2 further includes a second gate structure on a second vertical stack of horizontal nanowires and on a third sub-fin, the second gate structure being laterally spaced from the dielectric structure. A second gate notch is formed between the second gate structure and the dielectric structure, and the second dielectric gate notch is inserted into the second gate notch. The second dielectric gate notch is continuous with the dielectric structure.

[0175] Example 4: An integrated circuit structure of Example 1, 2 or 3, wherein the second sub-fin has a top surface located below the top surface of the first sub-fin.

[0176] Example 5: The integrated circuit structure of Example 1, 2, 3 or 4 further includes an epitaxial source or drain structure at the end of a vertically stacked body of horizontal nanowires.

[0177] Example Embodiment 6: An integrated circuit structure includes a fin on top of a first sub-fin. A gate structure is on top of the fin. A dielectric structure is laterally spaced from the gate structure. The dielectric structure is not on top of a channel structure, but on a second sub-fin. A gate notch is between the gate structure and the dielectric structure. A dielectric gate notch plug is inserted into the gate notch. The dielectric gate notch plug is continuous with the dielectric structure.

[0178] Example 7: The integrated circuit structure of Example 6, wherein the dielectric gate cut-out plug has an uppermost surface at the same level as the uppermost surface of the dielectric structure.

[0179] Example Embodiment 8: The integrated circuit structure of Example Embodiment 6 or 7 further includes a second gate structure located above the second fin, the second fin being above the third sub-fin, and the second gate structure being laterally spaced from the dielectric structure. A second gate notch is formed between the second gate structure and the dielectric structure, and the second dielectric gate notch is inserted into the second gate notch. The second dielectric gate notch is continuous with the dielectric structure.

[0180] Example 9: An integrated circuit structure of Example 6, 7 or 8, wherein the second sub-fin has a top surface located below the top surface of the first sub-fin.

[0181] Example 10: The integrated circuit structure of Example 6, 7, 8 or 9 further includes an epitaxial source or drain structure at the end of the fin.

[0182] Example 11: A computing device includes a board and components coupled to the board. The components include an integrated circuit structure comprising a vertical stack or fin of horizontal nanowires above a first sub-fin. A gate structure is above the vertical stack or fin of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced from the gate structure. The dielectric structure is not above a channel structure but is on a second sub-fin. A gate notch is between the gate structure and the dielectric structure. A dielectric gate notch plug is inserted into the gate notch. The dielectric gate notch plug is continuous with the dielectric structure.

[0183] Example 12: The computing device of Example 11 includes a vertical stack of horizontal nanowires.

[0184] Example 13: The computing device of Example 11 or 12 includes fins.

[0185] Example 14: The computing device of Example 11, 12 or 13 further includes a memory coupled to the board.

[0186] Example 15: The computing device of Example 11, 12, 13 or 14 further includes a communication chip coupled to the board.

[0187] Example 16: The computing device of Example 11, 12, 13, 14 or 15 further includes a battery coupled to a plate.

[0188] Example 17: The computing device of Example 11, 12, 13, 14, 15 or 16 further includes a camera coupled to the board.

[0189] Example 18: The computing device of Example 11, 12, 13, 14, 15, 16 or 17 further includes a display coupled to the board.

[0190] Example 19: A computing device of Example 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0191] Example 20: A computing device of Example 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the components are selected from the group consisting of a processor, a communication chip and a digital signal processor.

Claims

1. An integrated circuit structure, comprising: The first fin is located above the first sub-fin; A trench isolation structure is adjacent to the first sub-fin; A first gate dielectric layer is located on the first fin, and the first gate dielectric layer is located on the trench isolation structure; The first gate electrode is located above the first gate dielectric layer; The first dielectric gate cut-out plug is laterally spaced from the first fin, and the first dielectric gate cut-out plug is in contact with the first gate electrode; The fin-trimmed isolation structure is laterally adjacent to the first dielectric gate cut-out plug and the trench isolation structure, and the fin-trimmed isolation structure has a bottom surface located below the top surface of the trench isolation structure; The second dielectric gate cut-out plug is laterally adjacent to the fin-shaped trimmed isolation structure; The second fin is located above the second sub-fin. The second fin is laterally spaced from the second dielectric gate cut-out plug, and the second sub-fin is adjacent to the trench isolation structure. The first dielectric gate cut-out plug is laterally located between the first fin and the fin trimming isolation structure. The fin trimming isolation structure is laterally located between the first dielectric gate cut-out plug and the second dielectric gate cut-out plug. The second dielectric gate cut-out plug is laterally located between the fin trimming isolation structure and the second fin. A second gate dielectric layer is located above the second fin and on the trench isolation structure; and The second gate electrode is located above the second gate dielectric layer, and the second gate electrode is in contact with the second dielectric gate notch plug.

2. The integrated circuit structure according to claim 1, further comprising: The third sub-fin is located below the fin trimming and isolation structure.

3. The integrated circuit structure according to claim 1, wherein, The fin trimming isolation structure has an uppermost surface that is at the same level as the uppermost surface of the first dielectric gate cut-out plug.

4. The integrated circuit structure according to claim 3, wherein, The second dielectric gate notch plug has an uppermost surface that is at the same level as the uppermost surface of the fin trimmed isolation structure.

5. The integrated circuit structure according to claim 1, wherein, Along a direction orthogonal to the direction from the first fin to the second fin, the widths of both the first dielectric gate cutout plug and the second dielectric gate cutout plug are greater than the width of the fin trimming isolation structure.

6. The integrated circuit structure according to claim 1, wherein, Along the direction from the first fin to the second fin, the widths of both the first dielectric gate cutout plug and the second dielectric gate cutout plug are smaller than the width of the fin trimming isolation structure.

7. The integrated circuit structure according to claim 1, wherein, There is no intermediate fin between the first fin and the second fin.

8. The integrated circuit structure according to claim 1, wherein, The first dielectric gate notch plug and the second dielectric gate notch plug are in contact with the fin trimming and isolation structure.

9. An integrated circuit structure, comprising: The first fin is located above the first sub-fin; A trench isolation structure is adjacent to the first sub-fin; A first gate dielectric layer is located on the first fin, and the first gate dielectric layer is located on the trench isolation structure; The first gate electrode is located above the first gate dielectric layer; The first dielectric gate cut-out plug is laterally spaced from the first fin, and the first dielectric gate cut-out plug is in contact with the first gate electrode; The fin-shaped trimmed isolation structure is laterally adjacent to the first dielectric gate cut-out plug and the trench isolation structure; The second dielectric gate cut-out plug is laterally adjacent to the fin-shaped trimmed isolation structure; The second fin is located above the second sub-fin. The second fin is laterally spaced from the second dielectric gate cut-out plug, and the second sub-fin is adjacent to the trench isolation structure. The first dielectric gate cut-out plug is laterally located between the first fin and the fin trimming isolation structure. The fin trimming isolation structure is laterally located between the first dielectric gate cut-out plug and the second dielectric gate cut-out plug. The second dielectric gate cut-out plug is laterally located between the fin trimming isolation structure and the second fin. A second gate dielectric layer is located above the second fin and on the trench isolation structure; and The second gate electrode is located above the second gate dielectric layer, and the second gate electrode is in contact with the second dielectric gate notch plug.

10. The integrated circuit structure according to claim 9, wherein, The fin trimming isolation structure has an uppermost surface that is at the same level as the uppermost surface of the first dielectric gate cut-out plug.

11. The integrated circuit structure according to claim 10, wherein, The second dielectric gate notch plug has an uppermost surface that is at the same level as the uppermost surface of the fin trimmed isolation structure.

12. The integrated circuit structure according to claim 9, wherein, Along the direction of the first fin, the widths of the first dielectric gate cutout plug and the second dielectric gate cutout plug are both greater than the width of the fin trimming isolation structure.

13. The integrated circuit structure according to claim 9, wherein, The first dielectric gate notch plug and the second dielectric gate notch plug are in contact with the fin trimming and isolation structure.

14. The integrated circuit structure according to claim 9, wherein, The first dielectric gate cutout plug and the second dielectric gate cutout plug extend deeper into the trench isolation structure than the fin trimmed isolation structure.

15. A method for manufacturing an integrated circuit structure, the method comprising: The first fin is formed on top of the first sub-fin; A groove isolation structure is formed adjacent to the first sub-fin; A first gate dielectric layer is formed on the first fin, and the first gate dielectric layer is also formed on the trench isolation structure. A first gate electrode is formed on the first gate dielectric layer; A first dielectric gate cutout plug is formed that is laterally spaced from the first fin, and the first dielectric gate cutout plug is in contact with the first gate electrode; A fin-trimmed isolation structure is formed that is laterally adjacent to the first dielectric gate cut-out plug and the trench isolation structure, the fin-trimmed isolation structure having a bottom surface located below the top surface of the trench isolation structure; A second dielectric gate cut-out plug is formed that is laterally adjacent to the fin-shaped trimmed isolation structure; A second fin is formed on top of the second sub-fin, the second fin being laterally spaced from the second dielectric gate cut-out plug, and the second sub-fin being adjacent to the trench isolation structure. The first dielectric gate cut-out plug is laterally located between the first fin and the fin trimming isolation structure, the fin trimming isolation structure is laterally located between the first dielectric gate cut-out plug and the second dielectric gate cut-out plug, and the second dielectric gate cut-out plug is laterally located between the fin trimming isolation structure and the second fin. A second gate dielectric layer is formed on the second fin and on the trench isolation structure; as well as A second gate electrode is formed on the second gate dielectric layer, and the second gate electrode is in contact with the second dielectric gate notch plug.

16. The method of claim 15, further comprising: A third sub-fin is formed below the fin trimming and isolation structure.

17. The method according to claim 15, wherein, The fin trimming isolation structure has an uppermost surface at the same level as the uppermost surface of the first dielectric gate cutout plug, and wherein the second dielectric gate cutout plug has an uppermost surface at the same level as the uppermost surface of the fin trimming isolation structure.

18. The method according to claim 15, wherein, Along a direction orthogonal to the direction from the first fin to the second fin, the widths of both the first dielectric gate cutout plug and the second dielectric gate cutout plug are greater than the width of the fin trimming isolation structure.

19. The method according to claim 15, wherein, There is no intermediate fin between the first fin and the second fin.

20. The method of claim 15, wherein, The first dielectric gate notch plug and the second dielectric gate notch plug are in contact with the fin trimming and isolation structure.

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