SEMICONDUCTOR DEVICE

Abstract

Semiconductor device, comprising: Semiconductor wires (22) arranged vertically above one another, each of which has a channel region; a source / drain epitaxy layer (80B) connected to the semiconductor wires; and a gate structure (108B) formed around the semiconductor wires (22), wherein: the semiconductor wires (22) made of Si 1-x Ge x are manufactured, where 0.45 ≤ x ≤ 0.55, wherein a conducting cross-section of the semiconductor wires (22) has a bone shape, where the semiconductor device is a p-channel field-effect transistor.

Description

GENERAL STATE OF THE ART

[0001] While the semiconductor industry has made progress in nanometer-scale process nodes in the pursuit of higher packing density, higher performance, and lower costs, challenges in manufacturing and design have led to the development of three-dimensional designs, such as a multi-gate field-effect transistor (FET), including a fin-type FET (Fin-FET) and a gate-all-around (GAA) FET. In a Fin-FET, a gate electrode is adjacent to three sides of a channel region with a gate dielectric layer sandwiched between them. Because the gate structure surrounds (encloses) the fin on three sides, the transistor essentially has three gates that control the current through the fin or channel region. Unfortunately, the fourth side, the bottom of the channel, is located far from the gate electrode and is therefore not under precise gate control.In contrast, in a GAA-FET, all side faces of the channel region are surrounded by the gate electrode, allowing for more complete channel depletion and resulting in fewer short-channel effects due to a steeper subthreshold current oscillation (SS) and lower drain-induced junction reduction (DIBL). While transistor dimensions are continuously being reduced to technology nodes below 10 to 15 nm, further improvements to the GAA-FET are needed.

[0002] US 2015 / 0053928 A1 discloses semiconductor assemblies and methods for fabricating such semiconductor assemblies. For example, one or more silicon and silicon-germanium stacks are used to form PMOS transistors with germanium nanowire channels and NMOS transistors with silicon nanowire channels. In one example, a first silicon and silicon-germanium stack is oxidized to convert silicon into silicon oxide regions. These are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon-germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors with germanium nanowire channels and NMOS transistors with silicon nanowire channels are fabricated in a single manufacturing process.

[0003] US 2017 / 0077232 A1 discloses: A method for fabricating a semiconductor device comprises the epitaxial growth of a plurality of silicon layers and pressure-stressed silicon germanium (SiGe) layers on a substrate in a stacked configuration, wherein the silicon layers and the pressure-stressed SiGe layers are stacked alternately on top of each other, starting with a silicon layer at one bottom of the stacked configuration, structuring the stacked configuration to a first width, selectively removing a portion of each of the silicon layers in the stacked configuration to reduce the silicon layers to a second width that is smaller than the first width, and forming an oxide layer on the pressure-stressed SiGe layers of the stacked configuration, wherein the formation of the oxide layer comprises the complete oxidation of the silicon layers.so that parts of the oxide layer are formed in place of each fully oxidized silicon layer, and the removal of part of the oxide layer while retaining at least part of the parts of the oxide layer that were formed in place of each fully oxidized silicon layer, wherein the compression-stressed SiGe layers are anchored to each other and a compressive stress is applied in each of the compression-stressed SiGe layers.

[0004] US 2017 / 0117360 A1 discloses a method for fabricating nanowires. In this process, multiple epitaxial layers are formed on a substrate, with the layers alternating between high- and low-Ge material concentrations. The layers are then structured to form ribs. The ribs are etched to create depressions in the low-Ge layers, forming pillars between the high-Ge layers. The pillars are converted into dielectric pillars. A conformal material is formed in the depressions and on the dielectric pillars. The high-Ge layers are compacted to form hexagonal, faceted Ge wires. The facets are exposed to form the nanowires.

[0005] US 2017 / 0104062 A1 describes techniques for fabricating stacked SiGe nanowires via a condensation process without parasitic Ge nanowires as an unwanted byproduct. A method for fabricating SiGe nanowires includes the following steps: forming a stack of alternating Si and SiGe layers on a wafer; structuring the lamellae in the stack; selectively thinning the SiGe layers in the lamellae so that the Si and SiGe layers give the lamellae an hourglass shape; embedding the lamellae in an oxide material; and annealing the lamellae under conditions sufficient to diffuse Ge from the SiGe layers in the lamellae into the Si layers in the lamellae, thus forming the SiGe nanowires. A FET device and a method for its fabrication are also provided.

[0006] DE 10 2017 124 774 A1 describes a semiconductor device with channel layers arranged over a substrate, a source / drain region arranged over the substrate, a gate dielectric layer arranged on and surrounding each of the channel layers, and a gate electrode layer arranged on the gate dielectric layer and surrounding each of the channel layers. Each of the channel layers contains a semiconductor wire consisting of a core region and one or more cladding regions. The core region has an approximately square cross-section, and a first cladding region of one or more cladding regions forms a first cladding region of an approximately rhombus-shaped cross-section around the core region and is connected to an adjacent first cladding region corresponding to an adjacent semiconductor wire.

[0007] US 2017 / 0104061 A1 discloses transistor structures and methods for fabricating transistor structures. The transistor structures comprise alternating layers of a first and a second epitaxial material. In some embodiments, either the first or the second epitaxial material can be removed for an n-type or a p-type transistor. A bottom layer of the first and second epitaxial materials can be removed, and the sidewalls of the first and second epitaxial materials can be indented or recessed.

[0008] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the usual practice in the industry, various features are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may be arbitrarily enlarged or reduced for the clarity of the discussion. Fig. Figure 1 shows a view of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. Fig. Figure 2 shows a view of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. Fig. Figure 3 shows a view of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. Fig. Figure 4 shows a view of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. Fig. Figure 5 shows a view of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 6A, Fig. 6B, Fig. 6C and Fig. Figure 6D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 7A, Fig. 7B, Fig. 7C and Fig. Figure 7D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 8A, Fig. 8B, Fig. 8C and Fig. Figure 8D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 9A, Fig. 9B, Fig. 9C and Fig. Figure 9D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 10A, Fig. 10B, Fig. 10C and Fig. Figure 10D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 11A, Fig. 11B, Fig. 11C and Fig. Figure 11D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 12A, Fig. 12B, Fig. 12C and Fig. Figure 12D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 13A, Fig. 13B, Fig. 13C and Fig. Figure 13D shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 14A, Fig. 14B, Fig. 14C, Fig. 14D and Fig. Figure 14E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 15A, Fig. 15B, Fig. 15C, Fig. 15D and Fig. Figure 15E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 16A, Fig. 16B, Fig. 16C, Fig. 16D and Fig. Figure 16E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 17A, Fig. 17B, Fig. 17C, Fig. 17D and Fig. Figure 17E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 18A, Fig. 18B, Fig. 18C, Fig. 18D and Fig. Figure 18E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D and Fig. Figure 19E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 20A, Fig. 20B, Fig. 20C, Fig. 20D and Fig. Figure 20E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D and Fig. Figure 21E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 22A, Fig. 22B, Fig. 22C, Fig. 22D and Fig. Figure 22E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 23A, Fig. 23B, Fig. 23C, Fig. 23D and Fig. Figure 23E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 24A, Fig. 24B, Fig. 24C, Fig. 24D and Fig. Figure 24E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 25A, Fig. 25B, Fig. 25°C, Fig. 25D and Fig. Figure 25E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 26A, Fig. 26B, Fig. 26C, Fig. 26D and Fig. Figure 26E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 27A, Fig. 27B, Fig. 27C, Fig. 27D and Fig. Figure 27E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 28A, Fig. 28B, Fig. 28°C, Fig. 28D and Fig. Figure 28E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 29A, Fig. 29B, Fig. 29C, Fig. 29D and Fig. Figure 29E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 30A, Fig. 30B, Fig. 30°C Fig. 30D and Fig. Figure 30E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 31A, Fig. 31B, Fig. 31C, Fig. 31D and Fig. Figure 31E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 32A, Fig. 32B, Fig. 32C, Fig. 32D and Fig. Figure 32E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 33A, Fig. 33B and Fig. Figure 33C shows various views of a GAA-FET device according to embodiments of the present disclosure. The Fig. 34A, Fig. 34B, Fig. 34C, Fig. 34D and Fig. Figure 34E shows various views of a GAA-FET device according to embodiments of the present disclosure. The Fig. 35A, Fig. 35B, Fig. 35°C Fig. 35D and Fig. Figure 35E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 36A, Fig. 36B, Fig. 36C, Fig. 36D and Fig. Figure 36E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. The Fig. 37A, Fig. 37B, Fig. 37C, Fig. 37D and Fig. Figure 37E shows different views of one of the different stages of a sequential manufacturing process for a GAA-FET device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples to implement various features of different embodiments of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples. For instance, the dimensions of elements may depend on process conditions and / or desired properties of the device. Furthermore, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features, such that the first and second features may not be in direct contact.For the sake of simplicity and clarity, various features may be drawn arbitrarily at different scales.

[0011] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to facilitate discussion and to describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. These spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, various orientations of the device during its use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Furthermore, the term "made of" may mean either "comprising" or "consisting of."In the present revelation, the expression “one of A, B and C” means “A, B and / or C” (A, B, C, A and B, A and C, B and C or A, B and C) and does not mean one element of A, one element of B and one element of C, unless otherwise described.

[0012] In the following embodiments, materials, configurations, dimensions, operations and / or processes of one embodiment may be used in another embodiment unless otherwise described, and a detailed description thereof may be omitted.

[0013] Over the past 10 years, high-mobility channel materials and device architectures have been studied to extend the lifetime of Moore's Law. Pure Ge and SiGe with a high Ge concentration are promising candidates for such materials due to their material properties of higher intrinsic hole and electron mobility. For well-tempered device scaling to Lg < 12 nm, nanowire or nanosheet structures are employed to provide improved short-channel control. Therefore, Ge or SiGe nanowire devices are considered promising and potential candidates for further miniaturization of logic device applications.

[0014] To fabricate a GAA FET with Si-, SiGe-, or Ge-based channels (semiconductor wires), a stacked layer of Si and SiGe or SiGe and Ge is formed over a substrate. The stacked layer is structured into a fin structure, and one of the layers is removed during a gate exchange process to expose the channels. Generally, Si is used for an n-channel GAA FET, and SiGe or Ge is used for a p-channel GAA FET. In the case of a SiGe p-channel GAA FET, a higher Ge concentration can increase the transistor performance.

[0015] When forming a stacked layer of Si and SiGe to fabricate both n-channel and p-channel GAA FETs, the SiGe layer with a higher Ge concentration can cause some problems. For example, if the Ge concentration is approximately 50 atomic percent in the SiGe layer, the lattice mismatch between Si and SiGe becomes large, and the critical thickness of a Si layer epitaxially formed on the SiGe layer would be small, which can reduce the performance of the n-channel GAA FET with Si channels. Conversely, if the Ge concentration in the SiGe layer is only approximately 30 to 40 atomic percent, the performance of the p-channel GAA FET with SiGe channels may be insufficient. Although it is possible to fabricate differently stacked layers for an n-channel GAA FET and a p-channel FET, the process costs would increase.

[0016] In the present disclosure, a semiconductor device is specified to solve the problems as described above.

[0017] The Fig. Figures 1 to 32E show a sequential process for manufacturing a GAA-FET device according to an embodiment of the present disclosure. It is understood, however, that additional operations before, during, and after the operations described by the Fig. Figures 1 to 32E show that the following may be provided for, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The sequence of operations / processes may be interchangeable.

[0018] As shown in Fig. 1. Doping ions (dopants) 12 are implanted into a silicon substrate 10 to form a trough region. The ion implantation is performed to prevent penetration. In some embodiments, the substrate 10 comprises a single-crystal semiconductor layer over at least one surface area. The substrate 10 can comprise a single-crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In one embodiment, the substrate 10 is made of crystalline Si.

[0019] The substrate 10 can comprise one or more buffer layers (not shown) in its surface region. The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source / drain regions. The buffer layers can be formed from epitaxially grown single-crystal semiconductor materials such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In a particular embodiment, the substrate 10 comprises silicon-germanium (SiGe) buffer layers that are epitaxially grown on the silicon substrate 10. The Ge concentration of the SiGe buffer layers can increase from 30 atomic percent germanium for the lowest buffer layer to 70 atomic percent germanium for the uppermost buffer layer. Substrate 10 can comprise different regions that have been suitably doped with dopants (e.g. type p or n).The dopants 12 are, for example, boron (BF2) for an n-Fin-FET and phosphorus for a p-Fin-FET.

[0020] As shown in Fig. 2 Stacked semiconductor layers are formed on substrate 10. The stacked semiconductor layers comprise the first semiconductor layers 20 and the second semiconductor layers 25. Furthermore, a mask layer 15 is formed over the stacked layers. The first semiconductor layers 20 and the second semiconductor layers 25 are made of materials with different lattice constants and can comprise one or more layers of Si, Ge, SiGe, GeSn, SiGeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or InP.

[0021] In some embodiments, the first semiconductor layers 20 and the second semiconductor layers 25 are made of Si, a Si compound, SiGe, Ge, or a Ge compound. In certain embodiments, the first semiconductor layers 20 are Si1-x Ge x , where 0.35 ≤ x ≤ 0.45, and the second semiconductor layers 25 are Si. In other embodiments, the second semiconductor layers 25 are made of Si 1-y Ge y manufactured where y is equal to or less than approximately 0.2 and x > y.

[0022] In Fig. In the diagram, five layers of the first semiconductor layer 20 and five layers of the second semiconductor layer 25 are arranged. However, the number of layers is not limited to five and can be as small as 1 (each layer), and in some embodiments, 2 to 20 layers of each of the first and second semiconductor layers are formed. By adjusting the number of stacked layers, the drive current of the GAA-FET device can be adjusted.

[0023] The first semiconductor layers 20 and the second semiconductor layers 25 are formed epitaxially over the substrate 10. The thickness of the first semiconductor layers 20 can be equal to or less than that of the second semiconductor layers 25 and ranges from approximately 2 nm to approximately 10 nm in some embodiments and from approximately 3 nm to approximately 5 nm in other embodiments. The thickness of the second semiconductor layers 25 ranges from approximately 5 nm to approximately 20 nm in some embodiments and from approximately 7.5 nm to approximately 12.5 nm in other embodiments. The thickness of each of the first and second semiconductor layers can be the same or can vary.

[0024] In some embodiments, the lower first semiconductor layer (the layer closest to substrate 10) is thicker than the remaining first semiconductor layers. The thickness of the lower first semiconductor layer ranges from approximately 10 nm to approximately 50 nm in some embodiments, or from 20 nm to 40 nm in other embodiments.

[0025] In some embodiments, the mask layer 15 comprises a first mask layer 15A and a second mask layer 15B. The first mask layer 15A is a pad oxide layer made of silicon oxide, which can be formed by thermo-oxidation. The second mask layer 15B is made of silicon nitride (SiN), which is formed by chemical vapor deposition (CVD), including low-pressure kinetic plasma-assisted deposition (LPCVD) and plasma-enhanced kinetic plasma-assisted deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable process. The mask layer 15 is structured into a mask structure using structuring operations, including photolithography and etching.

[0026] Next, as shown in Fig. 3 the stacked layers of the first and second semiconductor layers 20, 25 are structured using the structured mask layer, thereby forming the stacked layers in fin structures 30 that extend in the Y direction and are arranged along the X direction.

[0027] The fin structures 30 can be structured by any suitable method. For example, the fin structures can be structured using one or more photolithography processes, including dual-structuring or multi-structuring processes. In general, dual-structuring or multi-structuring processes combine photolithography and self-alignment processes, which makes it possible to produce structures that, for example, have spacings that are smaller than what is otherwise achievable using a single direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacing elements are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed and the remaining spacers or thorns can then be used to structure the fin structures.

[0028] In Fig. Figure 3 shows two fin structures 30 arranged in the X-direction. However, the number of fin structures is not limited to this and can be as few as one and as few as three or more. In some embodiments, one or more dummy fin structures are formed on both sides of the fin structures 30 to improve the structural accuracy during the structuring operations. As shown in Figure 3. Fig. 3 The fin structures 30 have upper sections formed by the stacked semiconductor layers 20, 25 and the trough sections 11, which correspond to the lower fin structure.

[0029] The width W1 of the upper section of the fin structure 30 along the X-direction ranges from approximately 5 nm to approximately 30 nm in some embodiments and from approximately 7.5 nm to approximately 15 nm in other embodiments. The height H1 along the Z-direction of the fin structure 30 ranges from approximately 50 nm to approximately 200 nm.

[0030] After the fin structure is formed, an insulating material layer 41, including one or more insulating material layers, is formed over the substrate such that the fin structures are completely embedded in the insulating layer 41. The insulating material for the insulating layer 41 can include silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), or a low-k dielectric formed by LPCVD (low-pressure chemical vapor deposition), plasma-CVD, or flowable CVD. An annealing operation can be performed after the formation of the insulating layer 41. Next, a planarization operation, such as a chemical-mechanical polishing (CMP) process and / or a back-etching process, is performed such that the top surface of the uppermost second semiconductor layer 25 is separated from the insulating material layer 41 as shown in Figure 1. Fig. 4 is exposed.

[0031] In some embodiments, one or more fin lining layers 35 are formed before the insulating material layer 41 is formed over the structure of Fig. 3 formed, as it is in Fig. Figure 4 shows the lining layer 35 being made of SiN or a silicon nitride-based material (e.g., SiON, SiCN, or SiOCN). In some embodiments, the fin lining layers 35 comprise a first fin lining layer 35A formed over the substrate 10 and side surfaces of the lower fin structures 11, and a second fin lining layer 35B formed on top of the first fin lining layer 35A. In some embodiments, each lining layer has a thickness between approximately 1 nm and approximately 20 nm. In some embodiments, the first fin lining layer 35A comprises silicon oxide and has a thickness between approximately 0.5 nm and approximately 5 nm, and the second fin lining layer 35B comprises silicon nitride and has a thickness between approximately 0.5 nm and approximately 5 nm.The fin lining layers 35 can be deposited by one or more processes such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), although any acceptable process may be used.

[0032] Then, as shown in Fig. 5. The insulating material layer 41 is recessed to form an insulating layer 40, thus exposing the upper sections of the fin structures 30. This process electrically isolates the fin structures 30 from one another through the insulating layer 40, a process also known as shallow trench insulation (STI). In the embodiment shown in Fig. In step 5, the insulating material layer 41 is omitted until the very lowest first semiconductor layer 20 is exposed. In other embodiments, the upper section of the well layer 11 is also partially exposed. The first semiconductor layers 20 are sacrificial layers that are subsequently partially removed, and the second semiconductor layers 25 are then formed in channel layers of a GAA-FET.

[0033] In the Fig. 6A to 13D are, as explained below, the "A" figures (e.g., the Fig. 6A, Fig. 7A, ... 13A) perspective views, the “B” figures (e.g. the Fig. 6B, Fig. 7B, ... 13B) Cross-sectional views along the X-direction according to the line X1-X1 of Fig. 6A, the “C” figures (e.g. the Fig. 6C, Fig. 7C, ... 13C) Cross-sectional views along the Y-direction according to the line Y1-Y1 of Fig. 6A (intersecting the fin structure 30A) and the “D” figures (e.g. the Fig. 6D, Fig. 7D, ... 13D) Cross-sectional views along the Y-direction according to the line Y2-Y2 of Fig. 6A (cutting the fin structure 30B).

[0034] The Fig. Figures 6A to 6D show the structure after the upper sections of the fin structures 30 have been exposed. Fig. 6A is essentially the same as Fig. 5. As shown in the Fig. In sections 6A to 6D, a first fin structure 30A and a second fin structure 30B are arranged above the lower fin structures 11A and 11B, respectively. In some embodiments, the first fin structure 30A is for an n-channel FET and the second fin structure 30B is for a p-channel FET. In other embodiments, the first and second fin structures are for the same type of FET.

[0035] Then, as shown, in the Fig. 7A-7A a first protective layer 42 over the structure, which is in the Fig. Figures 6A to 6D show the first protective layer 42. In some embodiments, the first protective layer 42 comprises silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof, formed by CVD (including LPCVD and PECVD), PVD, ALD, or another suitable process. In certain embodiments, the first protective layer 42 is made of silicon nitride.

[0036] Then, as shown, in the Fig. 8A to 8D the first protective layer 42 is structured using one or more lithography and etching processes to expose the second fin structure 30B and its surroundings.

[0037] Next, as shown, in the Fig. 9A-9D an oxidation film 44 over the structure that is in the Fig. Figures 7A to 7D are shown. In some embodiments, the oxide film 44 comprises silicon oxide formed by CVD including LPCVD and PECVD, PVD, ALD or another suitable process.

[0038] Subsequently, a thermal process is carried out to oxidize the first semiconductor layers 20. In some embodiments, the thermal process is carried out in an oxidizing environment including O₂ and / or O₃. In certain embodiments, the thermal process is carried out at a temperature in the range of approximately 800 °C to approximately 1000 °C. During the thermal process to oxidize the first semiconductor layer 20, which is made of SiGe, Si atoms in the SiGe become increasingly trapped in the oxide layer, while Ge atoms in the SiGe are concentrated in non-oxidized regions of the first semiconductor layers 20 (a SiGe compaction process). In particular, the selective oxidation of face-to-face Si atoms in a SiO₂-rich oxide layer during the SiGe compaction process results.Meanwhile, surface Ge atoms are not only forced into the SiGe layer, but also diffuse out into the upper and lower Si layers due to a high heat balance. The combined SiGe compaction and diffusion processes result in a redistribution of Ge concentration within a SiGe bulk layer and a Ge-diffused Si layer. The resulting Ge distribution profile after compaction determines the SiGe conductivity shape, as described below (e.g., bone shape).

[0039] Therefore, the non-oxidized sections 22 of the first semiconductor layers exhibit a higher Ge concentration than the first semiconductor layers 20 before the SiGe densification process. In some embodiments, the Ge concentration after the SiGe densification process in the densified first semiconductor layer 22 is in the range of approximately 45 atomic percent to approximately 55 atomic percent (Si). 1-z Ge z, where 0.45 ≤ z ≤ 0.55). During the compaction process, the thickness of the first semiconductor layers 20 also increases. During the compaction process, the second semiconductor layers 25, which are made of Si, are also slightly oxidized. The amount of oxidation of the first semiconductor layers 20 is greater than the amount of oxidation of the second semiconductor layers 25.

[0040] In other embodiments, the compaction process is carried out without the formation of the oxidation film 44.

[0041] After the compaction process, the oxidation film 44 and the oxidized sections of the second fin structures 30B are removed by a suitable etching process such as wet etching, as described in the Fig. Figures 11A to 11D are shown. In some embodiments, the compaction process is repeated two or more times to achieve a desired Ge concentration in the compacted first semiconductor layer 22.

[0042] After the compaction process, in some embodiments the width of the compacted first semiconductor layers 22 is smaller than the thickness of the compacted first semiconductor layers 22.

[0043] In other embodiments, the width of the densified first semiconductor layers 22 is greater than the thickness of the densified first semiconductor layers 22.

[0044] Subsequently, the first protective layer 42 is applied using one or more etching processes as shown in the Fig. 12A to 12D away.

[0045] After the first protective layer 42 has been removed, a sacrificial gate dielectric layer 52 is applied as shown in the Fig. 13A to 13D. The sacrificial gate dielectric layer 52 comprises one or more layers of insulating material, such as a silicon oxide-based material. In one embodiment, silicon oxide formed by CVD is used. The thickness of the sacrificial gate dielectric layer 52 ranges from approximately 1 nm to approximately 5 nm in some embodiments.

[0046] In the Fig. 14A to 32E are the “A” figures (e.g., as explained below). Fig. 14A, Fig. 15A, ... 32A) perspective views that include “B” figures (e.g. Fig. 14B, Fig. 15B, ... 32B) Cross-sectional views along the X-direction according to the line X1-X1 of Fig. 14A (cutting a gate region), the “C” figures (e.g. Fig. 14C, Fig. 15C, ... 32C) Cross-sectional views along the X-direction according to the line X2-X2 of Fig. 14A (cutting a source / drain region), the “D” figures (e.g. Fig. 14D, Fig. 15D, ... 32.) Cross-sectional views along the Y-direction according to the line Y1-Y1 of Fig. 32A (intersecting the fin structure 30A) and the “E” figures (e.g. Fig. 14E, Fig. 14E, ... 32E) Cross-sectional views along the Y-direction according to the line Y2-Y2 of Fig. 14A (cutting the fin structure 30B).

[0047] The Fig. Figures 14A to 14E illustrate a structure after a sacrificial gate structure 50 is formed over the exposed fin structures 30A and 30B. The sacrificial gate structure 50 comprises a sacrificial gate electrode 54 and the sacrificial gate dielectric layer 52. The sacrificial gate structure 50 is formed over a section of the fin structures that is intended to be a channel region. The sacrificial gate structure 50 defines the channel region of the GAA-FET.

[0048] The sacrificial gate structure 50 is formed by first depositing the sacrificial gate dielectric layer 52 over the entire surface of the fin structures 30A and 30B. A sacrificial gate electrode layer is then deposited over the entire surface of the sacrificial gate dielectric layer and over the fin structures 30, so that the fin structures 30 are completely embedded in the sacrificial gate electrode layer. The sacrificial gate electrode layer comprises silicon, such as polycrystalline silicon or amorphous silicon. The thickness of the sacrificial gate electrode layer ranges from approximately 100 nm to approximately 200 nm in some embodiments. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization process. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or another suitable process.Subsequently, a mask layer 56 is formed over the sacrificial gate electrode layer. The mask layer 56 comprises one or more layers of a SiN layer and a silicon oxide layer.

[0049] Then a structuring operation is performed on the mask layer and the sacrificial gate electrode layer is incorporated into the sacrificial gate structure 50 as shown in the Fig. 14A to 14E are structured. The sacrificial gate structure comprises the sacrificial gate dielectric layer 52, the sacrificial gate electrode layer 54 (e.g., polysilicon), and the mask layer 56. By structuring the sacrificial gate structure, the stacked layers of the first and second semiconductor layers are partially exposed on opposite sides of the sacrificial gate structure, creating source / drain (S / D) regions as shown in the Fig. 14A to 14E are defined. In this revelation, a source and a drain are used interchangeably, and their structures are essentially the same. In the Fig. In 14A to 14E, a sacrificial gate structure 50 is formed, but the number of sacrificial gate structures is not limited to one. In some embodiments, two or more sacrificial gate structures are arranged in the Y direction. In certain embodiments, one or more dummy sacrificial gate structures are formed on both sides of the sacrificial gate structures to improve structural accuracy.

[0050] After the sacrificial gate structure 50 is formed, a cover layer 53 made of an insulating material for gate sidewall spacer elements 55 is applied using CVD or other suitable methods as shown in the Fig. 15A to 15E are formed conformally. The cover layer 53 is deposited in a conformal manner such that it is formed to have substantially the same thickness on vertical surfaces, such as the side walls, horizontal surfaces, and the top of the sacrificial gate structure. In some embodiments, the cover layer 53 is deposited to a thickness in the range of approximately 2 nm to approximately 10 nm. In some embodiments, the insulating material of the cover layer 53 is a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN, and combinations thereof. In certain embodiments, the insulating material is one of SiOC, SiCON, and SiCN.

[0051] Furthermore, as shown in the Fig. Gate sidewall spacer elements 55 are formed on opposite sidewalls of the sacrificial gate structures by anisotropic etching in embodiments 16A to 16E. After the cover layer 53 is formed, anisotropic etching is performed on the cover layer 53 using, for example, reactive ion etching (RIE). During the anisotropic etching process, most of the insulating material is removed from horizontal surfaces, leaving the dielectric spacer layer on vertical surfaces such as the sidewalls of the sacrificial gate structures and the sidewalls of the exposed fin structures. The mask layer 56 can be exposed from the sidewall spacer elements. In some embodiments, an isotropic etching process can then be performed to remove the insulating material from the upper portions of the S / D region of the exposed fin structures 30.

[0052] Subsequently, a second protective layer 57 is formed to cover the region corresponding to the second fin structure 30B (for a p-channel region), as shown in the Fig. 17A to 17E.

[0053] In some embodiments, the second protective layer 57 comprises a silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof, formed by CVD (including LPCVD and PECVD), PVD, ALD, or another suitable process. In certain embodiments, the second protective layer 57 is produced from silicon nitride. After a top layer is formed, the second protective layer 57 is formed using one or more lithography and etching processes.

[0054] The first semiconductor layers 20 in the S / D region of the first fin structure 30A are then removed. Furthermore, the first semiconductor layers 20 are horizontally recessed (etched) such that edges of the first semiconductor layers 20 are located substantially below the gate sidewall spacer elements 55. In some embodiments, end sections (edges) of the first semiconductor layers 20 have a concave shape, such as a V-shape or a U-shape. The depth of recession of the first semiconductor layers 20 from the plane including a gate sidewall spacer element 55 is in the range of approximately 5 nm to approximately 10 nm. Etching of the second semiconductor layer 20 involves wet etching and / or dry etching. A wet etchant such as an ammonium hydroxide (NH4OH) solution can be used to selectively etch the first semiconductor layers 20.

[0055] Next, a dielectric layer is formed and one or more etching processes are carried out to deposit internal dielectric spacer elements 62 onto end faces of the recessed first semiconductor layers 20 as shown in the Fig. 18A to 18E. In some embodiments, the inner dielectric spacers 62 comprise a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN and combinations thereof, and differ from the material of the gate sidewall spacers 55. In certain embodiments, the inner dielectric spacers 62 are made of silicon nitride. The dielectric layer can be formed using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. In certain embodiments, the etching is isotropic etching. The maximum thickness along the Y-direction of the inner dielectric spacers 62 is in the range of approximately 0.5 nm to approximately 5 nm in some embodiments.

[0056] Then, as shown, in the Fig. From 19A to 19E, a first source / drain (S / D) epitaxial layer 80A is formed, which surrounds the second semiconductor layer 25 in the S / D region. The first S / D epitaxial layer 80A comprises one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET. The first S / D epitaxial layer 80A is formed by an epitaxial growth process using CVD, ALD, or molecular beam epitaxy (MBE). After the first S / D epitaxial layer 80A is formed, the second protective layer 57 is removed.

[0057] Subsequently, a third protective layer 59 is formed to cover the region corresponding to the first fin structure 30A (for an n-channel region), as shown in the Fig. 20A to 20E. In some embodiments, the third protective layer 59 comprises silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof, formed by CVD (including LPCVD and PECVD), PVD, ALD, or another suitable process. In certain embodiments, the third protective layer 59 is produced from silicon nitride. After a top layer is formed, the third protective layer 59 is formed using one or more lithography and etching processes.

[0058] The second semiconductor layers 25 are then removed in the S / D region of the second fin structure 30B. Furthermore, the second semiconductor layers 25 are horizontally recessed (etched) such that edges of the second semiconductor layers 25 are located substantially below the gate sidewall spacer elements 55. In some embodiments, end sections (edges) of the second semiconductor layers 25 have a concave shape, such as a V-shape or a U-shape. The depth of recession of the second semiconductor layers 25 from the plane, including a gate sidewall spacer element 55, is in the range of approximately 5 nm to approximately 10 nm. Etching of the second semiconductor layer 25 includes wet etching and / or dry etching. A wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, can be used to selectively etch the second semiconductor layers 25.

[0059] Next, a dielectric layer is formed and one or more etching processes are carried out to deposit internal dielectric spacer elements 64 onto end faces of the recessed second semiconductor layers 25 as shown in the Fig. 21A to 21E. In some embodiments, the inner dielectric spacers 64 comprise a silicon nitride-based material, such as SiN, SiON, SiOCN, or SiCN and combinations thereof, and differ from the material of the gate sidewall spacers 55. In certain embodiments, the inner dielectric spacers 64 are made of silicon nitride. The dielectric layer can be formed using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. In certain embodiments, the etching is isotropic. The maximum thickness along the Y-direction of the inner dielectric spacers 64 is in the range of approximately 0.5 nm to approximately 5 nm in some embodiments.

[0060] Then, as shown, in the Fig. From 22A to 22E, a second source / drain (S / D) epitaxial layer 80B is formed, which surrounds the thickened first semiconductor layer 22 in the S / D region. The second S / D epitaxial layer 80B comprises one or more layers of Si, SiGe, and SiGeP for a p-channel FET. The second S / D epitaxial layer 80B is formed by an epitaxial growth process using CVD, ALD, or molecular beam epitaxy (MBE). As shown in the Fig. From 22A to 22E, a portion of the dielectric layer remains between the second S / D epitaxic layer and the lower fin structure 11B. After the second S / D epitaxic layer 80B is formed, the third protective layer 59 is formed as shown in the Fig. 23A to 23E away.

[0061] Subsequently, a lining layer 85 is formed, followed by an intermediate dielectric (ILD) layer 90 as shown in the Fig. 24A to 24E are formed. The lining layer 85 is made from a silicon nitride-based material such as silicon nitride and acts as a contact etch stop layer (CESL) in the subsequent etching operations. The materials for the ILD layer 90 include compounds containing Si, O, C and / or H, such as silicon dioxide, SiCOH and SiOC. Organic materials such as polymers can be used for the ILD layer 90. After the ILD layer 90 is formed, a planarization process such as CMP is performed so that the sacrificial gate electrode layer 54, as shown in the Fig. 24A to 24E will be exposed.

[0062] Then, as shown in the Fig. Steps 25A to 25E remove the sacrificial gate electrode layer 54 and the sacrificial gate dielectric layer 52, exposing a channel region of the fin structures. The ILD layer 90 protects the first and second S / D epitaxy layers 80A and 80B during the removal of the sacrificial gate structure. The sacrificial gate structure can be removed using plasma dry etching and / or wet etching. If the sacrificial gate electrode layer 54 is polysilicon and the ILD layer 90 is silicon dioxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode layer 54. The sacrificial gate dielectric layer 52 is then removed using plasma dry etching and / or wet etching.

[0063] Subsequently, a fourth protective layer 87 is formed to cover the region corresponding to the first fin structure 30A (for the n-channel region), as shown in the Fig. 26A to 26E. Fig. Figure 26A is a perspective view exposing the channel region. In some embodiments, the fourth protective layer 87 comprises silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof, formed by an overlay deposition process, such as CVD (including LPCVD and PECVD), PVD, ALD, or another suitable process. In certain embodiments, the fourth protective layer 87 is fabricated from silicon nitride. After an overlay layer is formed, the fourth protective layer 87 is formed using one or more lithography and etching operations.

[0064] After the fourth protective layer 87 is formed, the first semiconductor layers 20 in the channel region of the first fin structure 30A are removed, leaving semiconductor wires of the second semiconductor layers 25 as shown in the Fig. 27A to 27E will be formed.

[0065] The first semiconductor layers 20 can be removed or etched using an etchant that can selectively etch the first semiconductor layers 20. Etching the first semiconductor layer 20 includes wet etching and / or dry etching. A wet etchant such as an ammonium hydroxide (NH4OH) solution can be used to selectively etch the first semiconductor layers 20.

[0066] Then the fourth protective layer 87 is removed and a fifth protective layer 89 is formed to cover the region corresponding to the first fin structure 30A (for the n-channel region), as shown in the Fig. 28A to 28E. In some embodiments, the fifth protective layer 89 comprises silicon nitride-based material, such as silicon nitride, SiON, SiOCN, or SiCN, and combinations thereof, formed by an overlay deposition process, such as CVD including LPCVD and PECVD, PVD, ALD, or another suitable process. In certain embodiments, the fifth protective layer 89 is produced from silicon nitride. After an overlay layer is formed, the fifth protective layer 89 is formed using one or more lithography and etching processes.

[0067] After the fifth protective layer 89 is formed, the second semiconductor layers 25 in the channel region of the second fin structure 30B are removed, leaving semiconductor wires of the densified first semiconductor layers 22 as shown in the Fig. 29A to 29E will be formed.

[0068] The second semiconductor layers 25 can be removed or etched using an etchant that can selectively etch the second semiconductor layers 25. Etching the second semiconductor layers 25 includes wet etching and / or dry etching. A wet etchant such as a TMAH solution can be used to selectively etch the second semiconductor layers 25. Then the fifth protective layer 89 is removed as shown in the Fig. 30A to 30E away.

[0069] After the wires of the dense first semiconductor layers 22 are formed, a gate dielectric layer 104 is formed around the wires of the second semiconductor layer 25 in the first fin structure 30A and the wires of the dense first semiconductor layer 22 in the second fin structure 30B as shown in the Fig. 31A to 31E. In some embodiments, the gate dielectric layer 104 comprises one or more layers of a dielectric, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric, and / or combinations thereof. Examples of high-k dielectric materials include HfO₂, HfSiO₂, HfSiON₄, HfTaO, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide aluminum oxide (HfO₂-Al₂O₃) alloy, other suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, an intermediate layer 102 is formed between the channel layers and the gate dielectric layer 104. The gate dielectric layer 104 can be formed by CVD, ALD, or any suitable method.In one embodiment, the gate dielectric layer 104 is formed using a highly conformal deposition process such as ALD to ensure the formation of a gate dielectric layer with a uniform thickness around each channel layer. The thickness of the gate dielectric layer 104 ranges from approximately 1 nm to approximately 6 nm in one embodiment.

[0070] Furthermore, a gate electrode layer 108 is placed over the gate dielectric layer 104 as shown in the Fig. 32A to 32E. The gate electrode layer 108 is formed over the gate dielectric layer 104 to surround each channel layer in some embodiments. The gate electrode 108 comprises one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 108 can be formed by CVD, ALD, electroplating, or another suitable process. The gate electrode layer is also deposited over the top surface of the ILD layer 90. The gate dielectric layer and the gate electrode layer formed over the ILD layer 90 are then planarized using, for example, CMP until the ILD layer 90 is exposed.

[0071] In certain embodiments, one or more output function matching layers 106 are arranged between the gate dielectric layer 104 and the gate electrode layer 108. The output function matching layers 106 are made of a conductive material such as a single layer of TiN, TaN, TaAlC, TiC, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC, or a multiple layer of two or more of these materials. For the n-channel FET, one or more of TaN, TaAlC, TiN, TiC, Co, TiAl, HfTi, TiSi, and TaSi are used as the output function matching layer. The output function matching layer 106 can be formed by ALD, PVD, CVD, electron beam evaporation, or another suitable process. Furthermore, the output work matching layer 106 can be formed separately for the n-channel FET and the p-channel FET, which can use different metal layers.

[0072] It is understood that the GAA-FETs undergo further CMOS processes to form various features such as contacts / vias, coupling structure metal layers, dielectric layers, passivation layers, etc.

[0073] Fig. 33A is an enlarged view of Fig. 32B. An n-channel GAA FET is formed over the first fin structure 30A, and a p-channel GAA FET is formed over the second fin structure 30B. Each channel of the n-channel GAA FET (the first channel) is made of Si (the first semiconductor layer 25), and each channel of the p-channel GAA FET (the second channel) is made of SiGe, the Ge concentration of which is increased during fabrication processes as described above (densified second semiconductor layer 22) in some embodiments. In certain embodiments, the second channels of the p-channel GAA FET are made of Si 1-z Ge z , where 0.40 ≤ z ≤ 0.50.

[0074] In some embodiments, the thickness H11 of the first channel is in the range of approximately 5 nm to approximately 10 nm, the space S11 between adjacent channels is in the range of approximately 5 nm to approximately 10 nm, and the width W11 is in the range of approximately 3 nm to approximately 8 nm. In some embodiments, the thickness H21 of the second channel is in the range of approximately 5 nm to approximately 10 nm, the space S21 between adjacent channels is in the range of approximately 5 nm to approximately 10 nm, and the width W21 is in the range of approximately 3 nm to approximately 8 nm. In certain embodiments, H11 ≥ 5 nm ≥ S11 and H21 ≥ 5 nm ≥ S21. Furthermore, in some embodiments, W11 ≥ W21 ≥ 3 nm. In certain embodiments, W21 < H21. In certain embodiments, S11 < H21 and H11 > S21, while S11+H11 is essentially the same as S21+H21.The thickness, width, and volume are measured at the center of each channel in the XY cross-section.

[0075] As shown in Fig. In some embodiments, the cross-section of the first channels (25) in 33A has a rectangular shape with rounded corners. In other embodiments, the cross-section of the first channels has an oval shape or a square shape with rounded corners. In some embodiments, the cross-section of the second channels (22) has a rectangular shape with rounded corners, an oval shape, or a square shape with rounded corners. In other embodiments, as shown in the Fig. 33B and Fig. 33C the cross-section of the second channels (22) has a bone shape or a spool (or coil) shape. In Fig. 33B are two sides concave and in Fig. 33C has four concave sides. As described above, a post-annealing process is performed, i.e., a SiGe compaction process that increases the Ge concentration within the SiGe layer and also causes Ge diffusion into the Si layers for a p-channel FET. The Si bulk layer near the SiGe interface has a Ge impurity, such as 20 to 30% Ge; the Si surface layer near the SiGe interface has a higher Ge concentration, such as 30 to 40% Ge, due to the compaction and diffusion effects; and the SiGe bulk layer has the highest Ge concentration, such as 40 to 50%, after the compaction process. The resulting Ge distribution influences the SiGe conduction profile. Since the etch rate for the SiGe region is high with a lower Ge concentration, the SiGe wire becomes bone-shaped.

[0076] The Fig. Figures 34A-34E show cross-sectional views of various GAA-FETs according to embodiments of the present disclosure. Fig. In 33A, a gate structure is shared by an n-channel GAA-FET and a p-channel GAA-FET. In other embodiments, as described in the Fig. 34A and Fig. As shown in Figure 34B, separate gate structures 108A and 108B are provided accordingly for an n-channel GAA-FET and a p-channel GAA-FET, while the n-channel GAA-FET and the p-channel GAA-FET are provided over the same substrate.

[0077] In some embodiments, various p-channel FETs are also used as shown in the Fig. 34C to 34E on the same substrate together with the GAA-FETs that are in the Fig. 32A, Fig. 34A and / or 34B are shown, provided for. Fig. 34C is a channel of a semiconductor fin 25A that projects continuously from the lower fin structure 11. In Fig. In 34D, a channel comprises a stacked structure of the first semiconductor layers 20 and the second semiconductor layers 25. This structure can be formed without performing a compaction process and without removing the second semiconductor layers from the channel region. Fig. 34E comprises a channel consisting of a stacked structure of densified first semiconductor layers 20 and second semiconductor layers 25. This structure can be formed by performing a densification process without removing the second semiconductor layers from the channel region. The in Fig. The FET shown in 34C can be an n-FET.

[0078] In some embodiments, the GAA-FETs that are in Fig. Figure 32A shows a CMOS device and is used for a core region of a semiconductor device comprising FETs formed by the minimum design rules. In some embodiments, the FETs that are in the Fig. Figures 34C to 34E are shown, used for the I / O region of the semiconductor device.

[0079] The Fig. Figures 35A to 37E show a sequential process for manufacturing a GAA-FET device according to a further embodiment of the present disclosure. It is understood, however, that additional operations before, during, and after the processes described by the Fig. Figures 35A to 37E show that the following may be provided for, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The sequence of operations / processes may be interchangeable.

[0080] After the structure, which is in the Fig. As shown in 16A to 16E, the S / D regions of the fin structures 30A and 30B are formed downwards equal to or below the upper surface of the insulating insulating layer 40 using dry etching and / or wet etching as shown in the Fig. 35A to 35E are omitted. In this stage, end sections of the stacked layer of the first and second semiconductor layers 20, 25 under the sacrificial gate structure have essentially flat sides, which are connected to the sidewall spacer elements 55 as shown in the Fig. 35D and Fig. 35E are aligned. In some embodiments, the end sections of the stacked layer of the first and second semiconductor layers 20, 25 are slightly horizontally etched.

[0081] Subsequently, using the same or similar processes as in the preceding embodiments, a first S / D epitaxic layer 80A and a second S / D epitaxic layer 80B are produced as shown in the Fig. 36A-36E are formed. The first S / D epitaxic layer 80A and the second S / D epitaxic layer 80B are formed separately as described above.

[0082] Then, using the same or similar processes as in the preceding embodiments, a gate structure including a gate dielectric layer 104 and a gate electrode layer 108 is produced as shown in the Fig. 37A to 37E formed.

[0083] It is understood that the GAA-FETs undergo further CMOS processes to form various features such as contacts / vias, coupling structure metal layers, dielectric layers, passivation layers, etc.

[0084] The various embodiments or examples described herein offer several advantages over existing technology. In the present disclosure, for example, SiGe layers in a Si / SiGe stacked layer initially exhibit a relatively low Ge concentration in order to mitigate lattice mismatch between Si and SiGe. Therefore, it is possible to increase the thickness of Si epitaxy layers formed on the SiGe layers. Furthermore, by employing a Ge compaction process to increase the subsequent Ge concentration, it is possible to improve the performance of the SiGe p-channel GAA FET.

[0085] It is understood that not all advantages have necessarily been described herein, that no specific advantage is required for all embodiments or examples, and that other embodiments or examples may offer different advantages.

[0086] According to one aspect of the present disclosure, a semiconductor device comprises semiconductor wires arranged perpendicularly, each semiconductor device having a channel region, a source / drain epitaxial layer associated with the semiconductor wires, and a gate structure formed around the semiconductor wires. The semiconductor wires are made of Si 1-x Ge xmanufactured, wherein 0.45 ≤ x ≤ 0.55. In one or more of the preceding and following embodiments, the width of the semiconductor wires is less than the thickness of the semiconductor wires. In one or more of the preceding and following embodiments, the thickness of the semiconductor wires is greater than the space between adjacent semiconductor wires. In one or more of the preceding and following embodiments, a cross-section of the semiconductor wires has a bone shape or a spool shape. In one or more of the preceding and following embodiments, the semiconductor device is a p-channel field-effect transistor. In one or more of the preceding and following embodiments, the source / drain epitaxy layer envelops source / drain regions of the semiconductor wires.In one or more of the preceding and following embodiments, the semiconductor device further comprises inner dielectric spacers arranged between the gate structure and the source / drain epitaxy layer. In one or more of the preceding and following embodiments, the semiconductor device further comprises gate sidewall spacers made of a different material than the inner dielectric spacers. In one or more of the preceding and following embodiments, the material of the inner dielectric spacers is silicon nitride. In one or more of the preceding and following embodiments, the material of the sidewall spacers is one of SiOC, SiCON, and SiCN.

[0087] According to another aspect of the present disclosure, a semiconductor device comprises an n-channel field-effect transistor (FET) and a p-channel FET. The n-channel FET comprises first semiconductor wires arranged perpendicularly, each having a channel region, and a first source / drain epitaxial layer connected to the first semiconductor wires. The p-channel FET comprises second semiconductor wires arranged perpendicularly, each having a channel region, and a second source / drain epitaxial layer connected to the second semiconductor wires. The second semiconductor wires are made of Si 1-x Ge x manufactured, where 0.45 ≤ x, and the first semiconductor wires are made of Si or Si 1-y Ge- y manufactured, where 0 < y ≤ 0.2. In one or more of the preceding and following embodiments, the second semiconductor wires are made of Si 1-x Ge xmanufactured, where 0.45 ≤ x ≤ 0.55, and the first semiconductor wires are made of Si. In one or more of the preceding and following embodiments, the width of the second semiconductor wires is less than the width of the first semiconductor wires. In one or more of the preceding and following embodiments, the width of the second semiconductor wires is less than the thickness of the first semiconductor wires and the thickness of the second semiconductor wires. In one or more of the preceding and following embodiments, the first source / drain epitaxic layer envelops source / drain regions of the first semiconductor wires, and the second source / drain epitaxic layer envelops source / drain regions of the second semiconductor wires. In one or more of the preceding and following embodiments, the first source / drain epitaxic layer is formed on end faces of the first semiconductor wires.In one or more of the preceding and following embodiments, a cross-section of the second semiconductor wires has a bone-like or spool-like shape. In one or more of the preceding and following embodiments, a cross-section of the first semiconductor wires has a rectangular shape with rounded corners and an oval shape. In one or more of the preceding and following embodiments, the semiconductor device further comprises a gate electrode layer formed around the first semiconductor wires and the second semiconductor wires.

[0088] According to another aspect of the present disclosure, a semiconductor device comprises a first p-channel field-effect transistor (FET) and a second p-channel FET. The first p-channel FET comprises first semiconductor wires arranged perpendicularly, each of which has a channel region, a first source / drain epitaxial layer connected to the first semiconductor wires, and a first gate structure formed around the first semiconductor wires. The second p-channel FET comprises second semiconductor wires and third semiconductor wires stacked alternately, each of which has a channel region, a second source / drain epitaxial layer connected to the second and third semiconductor wires, and a second gate structure formed around the second semiconductor wires. The first and second semiconductor wires are made of Si 1-x Ge x manufactured, where 0.45 ≤ x, and the third semiconductor wires are made of Si or Si1-y Ge y manufactured, where 0 < y ≤ 0.2.

Claims

[1] Semiconductor device comprising: Semiconductor wires (22) arranged vertically above one another, each of which has a channel region; a source / drain epitaxy layer (80B) connected to the semiconductor wires; and a gate structure (108B) formed around the semiconductor wires (22), wherein: the semiconductor wires (22) made of Si 1-x Ge x are manufactured, where 0.45 ≤ x ≤ 0.55, wherein a conducting cross-section of the semiconductor wires (22) has a bone shape, where the semiconductor device is a p-channel field-effect transistor. [2] Semiconductor device according to claim 1, wherein a width (W21) of the semiconductor wires (22) is smaller than a thickness (H21) of the semiconductor wires (22). [3] Semiconductor device according to claim 1 or 2, wherein a thickness (H21) of the semiconductor wires (22) is greater than a space (S21) between adjacent semiconductor wires (22). [4] Semiconductor device according to one of the preceding claims, wherein the source / drain epitaxy layer (80B) wraps around source / drain regions of the semiconductor wires (22). [5] Semiconductor device according to any one of the preceding claims, further comprising: internal dielectric spacer elements (62, 64) that are arranged between the gate structure (108B) and the source / drain epitaxy layer (80B). [6] Semiconductor device according to claim 5, further comprising: Gate sidewall spacer elements (55) which are made of a different material than the inner dielectric spacer elements (62, 64). [7] Semiconductor device according to claim 6, wherein the material of the inner dielectric spacer elements (62, 64) is silicon nitride, and the material of the gate sidewall spacer elements (55) is one of SiOC, SiCON and SiCN. [8] comprising a semiconductor device: an n-channel FET; and a p-channel FET, where the n-channel FET includes: - first semiconductor wires (25) arranged vertically above one another, each of which has a channel region; and - a first source / drain epitaxy layer (80A) connected to the first semiconductor wires (25), the p-channel FET includes: - second semiconductor wires (22) arranged perpendicularly above one another, each of which has a channel region; and - a second source / drain epitaxy layer (80B) connected to the second semiconductor wires (22), wherein the second semiconductor wires (22) are made of Si1-x Ge x are manufactured, where 0.45 ≤ x, wherein the first semiconductor wires (25) are made of Si or Si 1-y Ge y are manufactured, where 0 < y ≤ 0.2, and wherein a conduction cross-section of the second semiconductor wires (22) has a bone shape. [9] Semiconductor device according to claim 8, wherein the second semiconductor wires (22) are made of Si 1-x Ge x are manufactured, where 0.45 ≤ x ≤ 0.55, wherein the first semiconductor wires (25) are made of Si. [10] Semiconductor device according to claim 8 or 9, wherein a width (W21) of the second semiconductor wires (22) is smaller than a width (W11) of the first semiconductor wires (25). [11] Semiconductor device according to one of claims 8 to 10, wherein a width (W21) of the second semiconductor wires (22) is smaller than a thickness (H11) of the first semiconductor wires (25) and a thickness (H21) of the second semiconductor wires (22). [12] Semiconductor device according to any one of claims 8 to 11, wherein the first source / drain epitaxy layer (80A) wraps around the source / drain regions of the first semiconductor wires (25), wherein the second source / drain epitaxy layer (80B) wraps around source / drain regions of the second semiconductor wires (22). [13] Semiconductor device according to one of claims 8 to 11, wherein the first source / drain epitaxy layer (80A) is formed on end faces of the first semiconductor wires (25). [14] Semiconductor device according to any one of claims 8 to 13, wherein a conductor cross-section of the first semiconductor wires (25) has a rectangular shape with rounded corners or an oval shape. [15] comprising a semiconductor device: a first p-channel FET; and a second p-channel FET, the first p-channel FET features: - first semiconductor wires (22) arranged vertically above one another, each of which has a channel region; - a first source / drain epitaxy layer (80B) connected to the first semiconductor wires (22); and - a first gate structure (108B) formed around the first semiconductor wires (22), the second p-channel FET features: - second semiconductor wires (22) and third semiconductor wires (25) stacked alternately, each of which has a channel region; - a second source / drain epitaxy layer (80B) connected to the second (22) and third (25) semiconductor wires; and - a second gate structure (108B) formed around the second (22) and third (25) semiconductor wires, wherein the first semiconductor wires (22) and the second semiconductor wires (22) are made of Si 1-x Ge x are manufactured, where 0.45 ≤ x, wherein the third semiconductor wires (25) are made of Si or Si 1-y Ge y are manufactured, where 0 < y ≤ 0.2, wherein a conduction cross-section of the first semiconductor wires (22) and the second semiconductor wires (22) each has a bone shape.

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