Method for power consumption optimization of conditional branches, computer device, medium, product
By analyzing program addresses and creating initial entries, loop jump branches are filtered out, and invalid access to L2CBP is prevented, thus solving the power consumption problem when L1BTB is hit and achieving power optimization and performance preservation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2026-03-17
- Publication Date
- 2026-06-19
AI Technical Summary
In the existing technology, the L2CBP access is initiated every time the L1BTB hits a conditional branch, resulting in high power consumption and insufficient accuracy of L1CBP prediction results, leading to pipeline bubbles and delays.
By analyzing the program address, an initial entry is created, and loop jump branches with the same prediction direction for L1CBP and L2CBP are filtered out. Their continuous jump patterns are recorded, and the startup of L2CBP is automatically prevented after L1BTB is hit. Power consumption is optimized using a lightweight loop branch filter.
It effectively reduces the power consumption of branch prediction, ensures that the prediction accuracy is not affected, saves power consumption, and improves the energy efficiency of the processor.
Smart Images
Figure CN122240186A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, and more particularly to a power consumption optimization method for conditional branching, a computer device, a medium, and a product. Background Technology
[0002] The development trend of modern high-performance commercial processors is towards deeper pipelines, faster clock frequencies, and lower power consumption. For branch prediction, the requirement is to improve prediction accuracy while simultaneously increasing prediction speed as much as possible. This has led to the emergence of multi-stage hybrid predictor architectures. In many applications, conditional branches constitute a significant portion of the code, thus direction predictors are being designed to be increasingly larger, and the algorithms becoming increasingly complex.
[0003] In existing technologies, L1BTB+L1CBP is generally used as the first-stage hybrid predictor, and L2BTB+L2CBP (implemented using SRAM) is used as the second-stage hybrid predictor with a larger capacity. In order to ensure the prediction accuracy of conditional branches, for conditional branches hit by L1BTB, the result of L1CBP is needed to provide the predicted target address and jump direction. At the same time, due to the characteristics of L1CBP itself, such as small capacity, simple algorithm and fast speed, the prediction result cannot be guaranteed to be 100% accurate. Moreover, if the prediction direction given by L1CBP is wrong, it will bring more pipeline bubbles and delays. Therefore, after each conditional branch hit by L1BTB, L2CBP is unconditionally started to confirm the output result of L1CBP. Due to the characteristics of L2CBP itself, such as large capacity and slow speed, it takes multiple cycles to produce a result. Therefore, frequent L2CBP access leads to a lot of power consumption. Summary of the Invention
[0004] In view of this, embodiments of the present disclosure provide a power consumption optimization method, computer device, medium, and product for conditional branching, which can solve the problem of high power consumption caused by L2CBP access being initiated every time a conditional branch is hit in the prior art.
[0005] In a first aspect, embodiments of this disclosure provide a power consumption optimization method for conditional branching, including: Analyze the program address to obtain the target address; The branch type of the target address is a conditional branch, and the prediction direction given by the two-level hybrid predictor is a jump. An initial entry is created based on the target address. The initial entry includes a flag bit, a counter, a usable quantity, and a valid bit. In response to the reappearance of the target address, the initial entry is updated until a preset condition is met, and the target entry is obtained. In response to the target entry acquisition signal and the signal that the target address reappears after the target entry is acquired, the startup of the second-level conditional branch predictor after the first-level branch target buffer hits the target address is automatically prevented according to the target entry.
[0006] Secondly, this disclosure also provides a computer device, which adopts the following technical solution: The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the power optimization method of any of the conditional branches described above.
[0007] Thirdly, embodiments of this disclosure also provide a computer-readable storage medium storing computer instructions; the computer instructions are used to cause a computer to execute the power optimization method of any of the conditional branches described above.
[0008] Fourthly, embodiments of this disclosure also provide a computer program product, including a computer program / instructions that, when executed by a processor, implement the steps of any of the methods described above.
[0009] The power consumption optimization method for conditional branches disclosed in this application first analyzes the program address to obtain the target address and filters out those loop jump branches whose prediction directions (L1CBP and L2CBP) are consistent. Second, an initial entry is created based on the target address. In response to the target address reappearing, the initial entry is updated until a preset condition is met, and the target entry is obtained. By recording the continuous jump patterns of branches, the program's runtime behavior is automatically learned, and only branches that repeatedly and stably exhibit the same jump behavior are ultimately optimized. Then, in response to the target entry acquisition signal and the signal that the target address reappears after the target entry is obtained, the startup of the second-level conditional branch predictor after the first-level branch target buffer hits the target address is automatically prevented. In this application, the first-level prediction result corresponding to the filtered conditional branches already has high reliability and can therefore be directly used as the final prediction result. Preventing the startup of the second-level predictor does not affect the final prediction accuracy, ensuring performance is not compromised while saving power and significantly reducing prediction power consumption.
[0010] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description
[0011] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0012] Figure 1 A flowchart illustrating the power consumption optimization method for conditional branches provided in this embodiment of the disclosure.
[0013] Figure 2 This is a flowchart illustrating the method for obtaining a target address provided in an embodiment of this disclosure.
[0014] Figure 3 This is a schematic diagram illustrating the configuration of a circulating branch filter provided in an embodiment of this disclosure.
[0015] Figure 4 A flowchart illustrating the method for obtaining target entries provided in this embodiment of the disclosure.
[0016] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present disclosure. Detailed Implementation
[0017] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0018] It should be understood that the following specific examples illustrate the implementation of this disclosure, and those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0019] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.
[0020] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0021] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.
[0022] Reference Figure 1 This application discloses a power consumption optimization method for conditional branching, including: S100 analyzes the program address to obtain the target address.
[0023] The branch type of the target address is a conditional branch and the prediction direction given by the two-level hybrid predictor is a jump. The two-level hybrid predictor includes a first-level hybrid predictor and a second-level hybrid predictor. The first-level hybrid predictor includes a first-level branch target buffer (L1BTB) and a first-level conditional branch predictor (L1CBP). The second-level hybrid predictor includes a second-level branch target buffer (L2BTB) and a second-level conditional branch predictor (L2CBP).
[0024] S200, Create an initial entry based on the target address.
[0025] The initial entries include a tag, a counter, a usable quantity, and a valid bit; each program address corresponds to a set of target entries.
[0026] S300, in response to the reappearance of the target address signal, updates the initial entry until the preset conditions are met and the target entry is obtained.
[0027] By using S100-S300, those cyclic jump branches whose prediction directions are consistent with those of L1CBP and L2CBP can be effectively filtered out. The first-level prediction results corresponding to these branches already have high reliability.
[0028] S400, in response to the target entry acquisition signal and the signal that the target address reappears after the target entry is acquired, automatically prevents the start of the second-level conditional branch predictor (L2CBP) after the first-level branch target buffer (L1BTB) hits the target address, based on the target entry.
[0029] Specifically, refer to Figure 2 The specific methods for obtaining the S100 target address include: S110, if the initial program address accesses the first-level branch target buffer and meets the first preset condition, the first-level prediction result is obtained through the first-level conditional branch predictor.
[0030] Specifically, the current program address A in the program instruction stream is obtained. When the first-level branch target buffer (L1BTB) is accessed and hit at the initial program address A, the branch type corresponding to the hit entry is obtained. If the branch type is a conditional branch, the first-level conditional branch predictor (L1CBP) is started to obtain the prediction direction of the corresponding branch and recorded as the first prediction direction.
[0031] Furthermore, if a hit is found in L1BTB and the hit entry indicates that the branch type corresponding to the current program address A is a conditional branch, then the first-level conditional branch predictor (L1CBP) is started to predict the direction.
[0032] S120, if the first-level prediction direction is a jump and the jump address is the initial program address, start accessing the second-level conditional branch predictor and obtain the second-level prediction result.
[0033] The first-level prediction result and the second-level prediction result each include the corresponding prediction direction and jump address. In this step, the second-level conditional branch predictor (L2CBP) is started only when the prediction result of L1CBP is a jump and the predicted jump address given by L1CBP is equal to the current program address A, so as to perform a second prediction on the direction of the conditional branch.
[0034] During program execution, the subsequent processing flow is initiated if and only if the initial program address A is accessed and the first and second conditions are met. The first condition is that L1BTB hits this address after accessing L1BTB, and the hit L1BTB branch type is a conditional branch. The second condition is that the predicted direction given by L1CBP is a jump, and the jump address is the initial program address A. The subsequent processing flow includes at least: initiating access to L2CBP, and determining the final branch direction based on the predicted directions of L1CBP and L2CBP.
[0035] S130, if the second-level prediction result is consistent with the first-level prediction result, record the initial program address as the target address.
[0036] Specifically, when the direction given by L2CBP is the same as that of L1CBP, both being jumps, the final branch prediction direction is determined to be a jump, and the initial program address A is recorded as the target address. The condition corresponding to this step can be considered as a third condition; the initial program address will only be recorded as the target address if it meets all three conditions mentioned above.
[0037] This embodiment can optimize power consumption for a large number of loop jump branches in the program. After accurately filtering out the loop jump branches that meet the conditions, they can be accurately identified in subsequent execution, thereby obtaining the correct prediction result through L1CBP and preventing the start of L2CBP.
[0038] For S200, an initial entry is created based on the target address, including: S210, hash the target address to obtain the tag.
[0039] In a CPU's Branch Target Buffer (BTB) or similar structure, the Tag field is used to uniquely identify a branch instruction address to avoid collisions. Since the branch instruction address (let's call it A) has a large number of bits, while the Tag field has a limited number of bits, a hash algorithm is usually used to map address A to a shorter Tag value a.
[0040] Suppose the target address A has M bits (e.g., 32 or 64 bits), and the Tag field requires K bits (K is usually much smaller than M). A suitable hashing method is Fold-XOR, which mixes all bits of address A into K bits. Specifically, the binary representation of address A is divided into several segments of length K bits (from least significant bit to most significant bit). If the last segment is less than K bits, it is padded with 0s up to K bits in the most significant bits. All segments are then XORed, and the result is the K-bit Tag value a.
[0041] S220, configured with Useful and Valid bits both 0, and Counter set to 1.
[0042] Reference Figure 3 Furthermore, all entries can be stored in the loop branch filter. For example, the initial entry Aa for target address A represents an entry with A as address and a as tag (e.g., Tag 1); the initial entry Bb for target address B represents an entry with B as address and b as tag (e.g., Tag 2)... In this embodiment, each target address corresponds to a set of initial entries, that is, a new set of initial entries is created every time a target address that meets the conditions is identified.
[0043] Among them, the recurrent branch filter is a small hardware component, much smaller than the second-stage predictor itself. It achieves significant dynamic power savings with a small area and low static power consumption, ensuring a high return on investment.
[0044] Reference Figure 4 The method of S300, which "updates the initial entry in response to the reappearance of the target address signal until the preset conditions are met, and obtains the target entry," specifically includes: S310, in response to the target address reappearing with a signal, updates the counter by incrementing the first value.
[0045] Among them, the number of times the target address reappears is the same as the increment count; S320: When the incremented counter reaches the preset upper limit threshold, obtain the target counter and update the usable quantity and the valid bit is 1, indicating that the updated entry corresponding to this target address is available.
[0046] Specifically, the program continues to execute. Whenever it encounters a program address A and meets the above conditions to be recorded as a target address, the counter in the initial entry Aa is incremented by a first value. In this embodiment, the first value is preferably 1, until the counter is incremented to the maximum value (i.e., the preset upper limit threshold).
[0047] Furthermore, if program address A satisfies only the first and second conditions but not the third condition before the counter reaches its maximum value (e.g., 62), the usable quantity can be set to 1, and the counter remains unchanged. For example, if condition 1 is satisfied but condition 2 is not satisfied on the 32nd occurrence, then the counter is 31, and the usable quantity (useful) is set to 1. During program execution, other program addresses will also be updated according to the above logic.
[0048] Furthermore, during the update of initial entries, if the target address of the initial entry is redirected (i.e., a BTB prediction error) or deleted from the first-level branch target buffer (L1BTB), the initial entry corresponding to the target address is deleted. For example, if address C is redirected, then the corresponding entry Cc needs to be invalidated; if address D is kicked out of L1BTB, then the corresponding entry Dd needs to be invalidated.
[0049] For example, when the CPU fetches an instruction, the Branch Targeting (BTB) checks if the address of this instruction is in its recorded branch instruction list. If it is (BTB hit): the BTB immediately tells the CPU that this is a branch instruction and predicts that it will jump to address X, just like last time. In this way, the CPU can fetch instructions from address X before actually calculating the branch result, keeping the pipeline full and avoiding pauses. If it is not (BTB miss), that is, the BTB has no prediction information, the CPU will usually assume that this is a non-jump sequential branch or wait for the branch result to be calculated.
[0050] The S400's "responding to the target entry acquisition signal and the signal that the target address reappears after the target entry is acquired, automatically preventing the L2CBP from starting after the L1BTB hits the target address" specifically includes: S410, after obtaining the target entry, responds to the signal that the target address reappears, obtains the current counter value in the corresponding target entry, and determines the target value.
[0051] Wherein, the target value = the current counter value in the corresponding target entry - 1.
[0052] Specifically, a monitoring counter is constructed with an initial value of 0. When the target address reappears, the current counter value in the target entry corresponding to the target address is obtained, for example, 63. At this time, the reappearance of the target address indicates that after the new entry is hit, the current L2CBP has been blocked once. At this time, the number of times the blocking has occurred (1) needs to be subtracted to get 62, and this value is assigned to the monitoring counter, that is, the monitoring counter is updated, and the current monitoring counter is 62.
[0053] In this step, after all target entries are created, for any recurring initial program address, it is determined whether it exists in the target entry. If it does, it means that the recurring initial program address hits the target entry. Then, the current counter value in the corresponding target entry is obtained and the target value is determined, which is preferred as the value of the monitoring counter.
[0054] S420 automatically prevents the start of the second-level conditional branch predictor (L2CBP) by using a gated clock after the target value is not 0 and the first-level branch target buffer (L1BTB) is hit, and decrements the target value by a second value.
[0055] In this step, all values in the corresponding target entry remain unchanged as the standard for subsequent analysis. The second value is preferably 1, meaning that when the target address reappears, the monitoring counter is decremented by 1, and the second-level conditional branch predictor (L2CBP) is automatically prevented from starting after the first-level branch target buffer (L1BTB) is hit via a gated clock.
[0056] This step allows L2CBP to be prevented from starting and the monitoring counter to be updated automatically when the target address reappears, without needing to query the loop branch filter, thus saving time.
[0057] Furthermore, it also includes: updating the target value based on the number of times the target address reappears; when the target value is 0, decrementing the counter value in the target entry corresponding to the target address by a second value and assigning it to the target value, and preventing the start of the second-level conditional branch predictor (L2CBP) after the first-level branch target buffer (L1BTB) is hit.
[0058] In this embodiment, when the value of the monitoring counter is 0, the startup of the second-level conditional branch predictor (L2CBP) after the first-level branch target buffer (L1BTB) is hit is prevented, and the loop branch filter needs to be queried to update the value of the monitoring counter; if the value of the monitoring counter is 0 and the loop branch filter is not hit, the filter does not prevent access to L2CBP.
[0059] Assume all target entries include address A and address B, meaning the loop branch filter contains both types of information. For example, the counter value in the target entry corresponding to address A is 63, and the counter value in the target entry corresponding to address B is 3.
[0060] When the corresponding loop is executed after the target entry is created (assuming it is executed 100 times), the information in the loop branch filter can effectively prevent invalid access to L2CBP by address A and address B, which can prevent 100 × (63 + 31) = 9400 accesses to L2CBP.
[0061] The first-level hybrid predictor in this application focuses on fast response, while the second-level hybrid predictor focuses on high-accuracy verification. The first-level hybrid predictor includes a first-level branch-target buffer (L1BTB) and a first-level conditional branch predictor (L1CBP), typically employing high-speed structures such as perceptron predictors, capable of completing preliminary predictions within a single cycle and quickly providing branch direction (taken / not taken) and target address. The second-level hybrid predictor includes a second-level branch-target buffer (L2BTB) and a second-level conditional branch predictor (L2CBP), often employing complex structures such as TAGE predictors, capturing long-cycle branch patterns through multi-level global history tables, but with higher latency, and is used to double-check the prediction results of the first-level hybrid predictor.
[0062] Because TAGE has high accuracy, but its algorithm is complex and requires a large number of entries, it needs to be implemented using dozens of SRAM chips, resulting in high power consumption per L2CBP access. This application uses a small-capacity component (100~300 bits) to configure optimal parameters for a loop branch filter based on program behavior to gate L2CBP access, with significant results. As long as a loop is captured in the program, the resulting power consumption benefit is positive; the more loop jumps and loop branches, the better the benefit.
[0063] The power optimization method for conditional branches disclosed in this application can identify those loop branches where the L1CBP prediction direction and L2CBP direction are consistent. When L1CBP hits these loop branches each time, it avoids initiating L2CBP access every time. By preventing these invalid L2CBP accesses in advance, the power overhead of branch prediction is effectively reduced. The essence of this method is to replace simple always-on operation with intelligent management. Complex circuits are shut down when branch behavior is highly predictable, and full-function prediction is enabled when behavior is complex and unpredictable. This on-demand allocation of computing resources achieves considerable power savings with almost no impact on IPC (instructions per clock cycle). The entire solution is completed autonomously in hardware, without software or compiler intervention. It can dynamically adapt to the branch characteristics of different applications and even different stages of the same program, exhibiting strong versatility. The reduction in processor power consumption directly means less heat generation, potentially allowing for higher sustained operating frequencies (under thermal design power constraints) or reserving more power budget for other computing units on the chip (such as GPUs and AI accelerators), thereby improving the overall system energy efficiency.
[0064] This application identifies multiple invalid accesses to L2CBP within various loop blocks during program execution, thereby training a conditional branch filter. Based on the information from the conditional branch filter, L2CBP access is promptly blocked. The power optimization method for conditional branching disclosed in this application is a highly refined microarchitecture power optimization technique. By cleverly utilizing the locality and predictability of branch behavior, and through a lightweight learning and filtering mechanism, it intelligently shuts down high-power modules that are unnecessary to operate at specific times, significantly reducing power consumption.
[0065] A computer device according to embodiments of the present disclosure includes a memory and a processor. The memory is used to store non-transitory computer-readable instructions. Specifically, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc.
[0066] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the computer device to perform desired functions. In one embodiment of this disclosure, the processor is used to execute computer-readable instructions stored in the memory, causing the computer device to perform all or part of the power optimization methods of the conditional branches of the foregoing embodiments of this disclosure.
[0067] Those skilled in the art will understand that, in order to solve the technical problem of how to achieve a good user experience, this embodiment may also include well-known structures such as communication buses and interfaces, and these well-known structures should also be included within the protection scope of this disclosure.
[0068] like Figure 5 This is a schematic diagram of a computer device provided for an embodiment of the present disclosure. It illustrates a structural schematic diagram suitable for implementing the computer device in the embodiments of the present disclosure. Figure 5 The computer device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.
[0069] like Figure 5As shown, a computer device may include a processor (such as a central processing unit, graphics processing unit, etc.), which can perform various appropriate actions and processes based on programs stored in read-only memory (ROM) or programs loaded from storage devices into random access memory (RAM). The RAM also stores various programs and data required for the operation of the computer device. The processor, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.
[0070] Typically, the following devices can be connected to the I / O interface: input devices, such as sensors or visual information acquisition devices; output devices, such as displays; storage devices, such as magnetic tapes or hard drives; and communication devices. Communication devices allow the computer device to communicate wirelessly or wiredly with other devices (such as edge computing devices) to exchange data. Although Figure 5 A computer apparatus with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or included alternatively.
[0071] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from ROM. When the computer program is executed by a processor, all or part of the steps of the power optimization method of the conditional branches of embodiments of this disclosure are performed.
[0072] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.
[0073] A computer-readable storage medium according to embodiments of the present disclosure stores non-transitory computer-readable instructions. When these non-transitory computer-readable instructions are executed by a processor, all or part of the steps of the power consumption optimization methods for conditional branches in the foregoing embodiments of the present disclosure are performed.
[0074] The aforementioned computer-readable storage media include, but are not limited to: optical storage media (e.g., CD-ROM and DVD), magneto-optical storage media (e.g., MO), magnetic storage media (e.g., magnetic tape or portable hard drive), media with built-in rewritable non-volatile memory (e.g., memory card), and media with built-in ROM (e.g., ROM cartridge).
[0075] For a detailed description of this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.
[0076] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.
[0077] In this disclosure, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The block diagrams of devices, apparatuses, devices, and systems involved in this disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc., are open-ended terms meaning "including but not limited to," and are used interchangeably with them. The terms "or" and "and" as used herein refer to the terms "and / or," and are used interchangeably with them unless the context clearly indicates otherwise. The term "such as" as used herein refers to the phrase "such as but not limited to," and is used interchangeably with it.
[0078] Additionally, as used herein, the "or" used in a list of items beginning with "at least one" indicates a separate list, such that a list of, for example, "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not imply that the described example is preferred or better than other examples.
[0079] It should also be noted that in the systems and methods of this disclosure, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered as equivalent solutions to this disclosure.
[0080] Various changes, substitutions, and modifications can be made to the technology described herein without departing from the teachings defined by the appended claims. Furthermore, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufactures, events, means, methods, or actions that perform substantially the same function or achieve substantially the same result as the corresponding aspects described herein can be utilized. Therefore, the appended claims include such processes, machines, manufactures, events, means, methods, or actions within their scope.
[0081] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.
[0082] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.
Claims
1. A power consumption optimization method for conditional branching, characterized in that, include: Analyze the program address to obtain the target address; The branch type of the target address is a conditional branch, and the prediction direction given by the two-level hybrid predictor is a jump. An initial entry is created based on the target address. The initial entry includes a flag bit, a counter, a usable quantity, and a valid bit. In response to the reappearance of the target address, the initial entry is updated until a preset condition is met, and the target entry is obtained. In response to the target entry acquisition signal and the signal that the target address reappears after the target entry is acquired, the startup of the second-level conditional branch predictor is automatically prevented after the first-level branch target buffer hits the target address, based on the target entry.
2. The power consumption optimization method for conditional branching according to claim 1, characterized in that, The step of analyzing the program address to obtain the target address includes: If the initial program address accesses the first-level branch target buffer and meets the first preset condition, the first-level prediction result is obtained through the first-level conditional branch predictor. If the first-level prediction direction is a jump and the jump address is the initial program address, the access to the second-level conditional branch predictor is initiated, and the second-level prediction result is obtained; If the second-level prediction result is consistent with the first-level prediction result, the initial program address is recorded as the target address.
3. The power consumption optimization method for conditional branching according to claim 2, characterized in that, If the initial program address accesses the first-level branch target buffer and satisfies the first preset condition, the first prediction direction is obtained through the first-level conditional branch predictor, including: When the first-level branch target buffer is accessed and hit at the initial program address, the branch type corresponding to the hit entry is obtained; If the branch type is a conditional branch, start the first-level conditional branch predictor to obtain the prediction direction of the corresponding branch, and record it as the first prediction direction.
4. The power consumption optimization method for conditional branching according to claim 2, characterized in that, The step of creating an initial entry based on the target address includes: The target address is hashed to obtain a flag bit; The initial usable quantity and valid bits are both set to 0, and the initial counter is set to 1.
5. The power consumption optimization method for conditional branching according to claim 1, characterized in that, The step of updating the initial entry in response to the reappearance of the target address until a preset condition is met to obtain the target entry includes: In response to the reappearance of the signal at the target address, the counter is updated by incrementing the first value; The target address appears again the same number of times as the incrementing number; When the incremented counter reaches the preset upper limit threshold, the target counter is obtained, and the usable quantity and the valid bit are updated to 1. The flag bit, the valid bit, the updated counter, and the updated usable quantity constitute the target entry.
6. The power consumption optimization method for conditional branching according to claim 5, characterized in that, During the process of updating the initial entry, if the target address of the initial entry is redirected or deleted from the first-level branch target buffer, the initial entry corresponding to the target address is deleted.
7. The power consumption optimization method for conditional branching according to claim 1, characterized in that, The step of automatically preventing the activation of the second-level conditional branch predictor after the first-level branch target buffer is hit, in response to the target entry acquisition signal and the signal that the target address reappears after the target entry is acquired, includes: After obtaining the target entry, in response to the signal that the target address reappears, the counter value in the corresponding target entry is obtained, and the target value is determined; After the target value is not 0 and the first-level branch target buffer is hit, the second-level conditional branch predictor is automatically prevented from starting by the gating clock, and the target value is decremented by a second value.
8. The power consumption optimization method for conditional branching according to claim 7, characterized in that, Also includes: The target value is updated based on the number of times the target address reappears after the target entry is obtained; When the target value is 0, the counter value in the target entry corresponding to the target address is decremented by a second value and assigned to the target value, and the start of the second-level conditional branch predictor is prevented after the first-level branch target buffer is hit.
9. A computer device, characterized in that, The computer device includes: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the power optimization method of the conditional branch as described in any one of claims 1-8.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions; the computer instructions are used to cause the computer to perform the power optimization method of the conditional branch as described in any one of claims 1-8.
11. A computer program product comprising computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the method according to any one of claims 1-8.