Data transmission circuit and application

Abstract

This invention provides a data transmission circuit and its application, including a synchronous transmission channel connected between a first bidirectional data port and a second bidirectional data port and connected to a clock signal input terminal, for transmitting data at regular intervals in response to a received clock signal; an asynchronous transmission channel connected between the first bidirectional data port and the second bidirectional data port and connected in parallel with the synchronous transmission channel, for directly transmitting data; a mode control module connected to a mode control signal input terminal, for selectively activating the synchronous transmission channel and the asynchronous transmission channel in response to a received mode control signal; and a direction control module connected to the direction control signal terminal, for controlling the data transmission direction in response to a received direction control signal. This invention integrates synchronous, asynchronous, and bidirectional transmission functions into a single circuit unit, avoiding the need for multiple complex IP modules and effectively improving the flexibility and adaptability of the data transmission circuit.

Description

Technical Field

[0001] This invention belongs to the field of electrical digital data processing technology, and specifically relates to a data transmission circuit and its application. Background Technology

[0002] Currently, the demand for computing power in fields such as artificial intelligence continues to rise, posing significant challenges to single-chip system solutions in terms of performance improvement and yield control. To address this, the industry is turning to chip-to-chip integration technology, which integrates multiple small chips into a single package through high-density interconnects. In this architecture, the underlying chip responsible for interconnection needs to build an efficient data exchange network for the upper-layer computing chips.

[0003] On-chip interconnect networks can be divided into two types: message signaling level and line level. Among them, line-level networks are crucial in scenarios with high real-time requirements due to their simple structure and extremely low latency. As the core component of this network, the multi-channel data transceiver must have flexible bidirectional data transmission capabilities.

[0004] However, achieving such bidirectional data transmission, especially data paths for different operating modes, usually relies on complex circuit combinations or dedicated IP modules, which leads to many problems such as high design costs, large chip area and power consumption. Summary of the Invention

[0005] The purpose of this invention is to provide a data transmission circuit and application that integrates synchronous transmission, asynchronous transmission, and bidirectional transmission into a single circuit unit. It achieves hardware-level dynamic configuration of transmission mode and data flow direction through different control signals, avoiding the need for multiple complex IP modules and effectively improving the flexibility and adaptability of the data transmission circuit.

[0006] To solve the above-mentioned technical problems, the present invention provides a data transmission circuit, comprising:

[0007] The first bidirectional data port is used for sending and receiving data; The second bidirectional data port is used for sending and receiving data; Clock signal input terminal, used to receive clock signals; The mode control signal input terminal is used to receive mode control signals; The direction control signal terminal is used to receive direction control signals; A synchronous transmission channel is connected between the first bidirectional data port and the second bidirectional data port and is connected to the clock signal input terminal to transmit data in response to the clock signal at regular intervals. An asynchronous transmission channel is connected between the first bidirectional data port and the second bidirectional data port, and is connected in parallel with the synchronous transmission channel to directly transmit data; A mode control module, connected to the mode control signal access terminal, is used to selectively turn on the synchronous transmission channel and the asynchronous transmission channel in response to the mode control signal; A direction control module is connected to the direction control signal access terminal to control the transmission direction of data between the first bidirectional data port and the second bidirectional data port in response to the direction control signal.

[0008] In one embodiment of the present invention, the synchronous transmission channel includes at least one trigger, the clock terminal of the trigger being connected to the clock signal input terminal to trigger data transmission in response to the clock signal.

[0009] In one embodiment of the present invention, the asynchronous transmission channel includes a first transmission gate, one end of which is connected to the first bidirectional data port, and the other end is directly connected to the second bidirectional data port.

[0010] In one embodiment of the present invention, the mode control module includes a second transmission gate, which is connected in series between the data output terminal of the trigger and an internal node; The first transmission gate is connected between the first bidirectional data port and the second bidirectional data port.

[0011] In one embodiment of the present invention, the mode control module further includes a first inverter, the input terminal of the first inverter is connected to the mode control signal input terminal, and its output terminal is connected to the second transmission gate and the first transmission gate, for providing a mode control signal that is inverted from the mode control signal.

[0012] In one embodiment of the present invention, the direction control module includes a first direction submodule, a third transmission gate and a fourth transmission gate of the first direction submodule, the output terminals of the third transmission gate and the fourth transmission gate are both connected to the trigger; the input terminal of the third transmission gate is connected to the second bidirectional data port, and the input terminal of the fourth transmission gate is connected to the first bidirectional data port.

[0013] In one embodiment of the present invention, the direction control module further includes a second direction submodule; The inputs of the fifth and sixth transmission gates are connected to the data output of the internal node or the trigger; the output of the fifth transmission gate is connected to the second bidirectional data port, and the output of the sixth transmission gate is connected to the first bidirectional data port.

[0014] In one embodiment of the present invention, a second inverter and a third inverter are further included for inverting the direction control signal; The input terminal of the second inverter is connected to the direction control signal input terminal; The input terminal of the third inverter is connected to the output terminal of the second inverter, and the output terminal of the third inverter is connected to the third transmission gate, the fourth transmission gate, the fifth transmission gate, and the sixth transmission gate.

[0015] The present invention also provides a chip system, comprising: Packaging substrate; Multiple chips are interconnected and integrated on the packaging substrate, and at least one of the multiple chips integrates a data transmission circuit as provided by the present invention as described in any one of the above-mentioned embodiments.

[0016] The present invention also provides an electronic device comprising the chip system described above.

[0017] By adopting the above technical solution, this invention, as an example, has the following advantages and positive effects: This invention integrates synchronous, asynchronous, and bidirectional transmission into a single circuit unit. It achieves dynamic hardware-level configuration of transmission modes and data flow direction through different control signals, avoiding the need for multiple complex IP modules. This significantly improves the flexibility and adaptability of the data transmission circuit. Mode and direction switching are both accomplished by pure hardware inverters and transmission gates, resulting in short switching times without software intervention. This meets the extremely low latency requirements of high-performance chip interconnects. The dual-mode coexistence design allows a single circuit unit to flexibly adapt to the timing requirements and topologies of different protocols, broadening its application and achieving an overall improvement in data transmission efficiency and energy efficiency. Furthermore, the circuit unit structure of this invention is compact, significantly reducing the number of transistors. Both static and dynamic power consumption are effectively reduced, effectively decreasing chip area and overall power consumption, and significantly lowering design complexity. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A schematic diagram of the data transmission circuit provided in an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of the asynchronous transmission route of the data transmission circuit provided in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram of the synchronous transmission route of the data transmission circuit provided in an embodiment of the present invention.

[0022] Figure 4 This is a schematic diagram of the synchronous transmission route of the data transmission circuit provided in an embodiment of the present invention.

[0023] Explanation of reference numerals in the attached figures The system includes a data transmission circuit 100, a mode control module 110, a first direction submodule 120, and a second direction submodule 130. Detailed Implementation

[0024] The technical solutions disclosed in this invention will be described in detail below with reference to specific embodiments.

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0027] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0028] like Figure 1 As shown, the present invention provides a data transmission circuit with features including but not limited to dual transmission modes, bidirectional data transmission, high integration, flexible configuration, and low latency. As a basic physical layer unit of the interconnect network between cores, it can flexibly configure the data transmission direction and mode according to the interconnection requirements of the interconnect network, which is beneficial to significantly improve data throughput efficiency, reduce communication latency, and simplify system design and layout wiring complexity. It is especially suitable for high-performance computing, artificial intelligence training and inference, cloud servers, edge computing and other application fields with strict requirements for area, power consumption and real-time performance.

[0029] The data transmission circuit provided by this invention can be applied to integrated chips, communication and network processing chips, automotive electronics and autonomous driving chips, IoT and mobile device chips, etc. Specifically, the data transmission circuit provided by this invention can be applied to integrated chips, such as high-end AI acceleration chips, high-performance computing CPUs / GPUs, large FPGAs, etc. As the basic physical layer unit of the inter-chip interconnection network, the data transmission circuit provided by this invention is responsible for realizing flexible and controllable data transmission.

[0030] Specifically, the data transmission circuit provided by this invention is applied to communication and network processing chips, such as high-speed Ethernet switching chips, optical communication DSP chips, 5G baseband chips, and network processors. The data transmission circuit provided by this invention establishes a high-speed data flow exchange network between multiple processing engines or coprocessors within the chip. Synchronous mode is used to process data packets that require timing, while asynchronous mode is used to transmit high-priority interrupt or control information requiring low latency.

[0031] Specifically, for example, the data transmission circuit provided by this invention is used in scenarios of high-bandwidth memory stack (such as HBM) communication, such as AI chips and graphics processors that integrate HBM, to realize bidirectional data channels in the interface PHY layer, and can freely switch between synchronous and asynchronous transmission according to the operation mode.

[0032] like Figure 1 As shown, the data transmission circuit 100 provided by the present invention includes a first bidirectional data port, a second bidirectional data port, a clock signal input terminal, a mode control signal input terminal, a direction control signal terminal, a synchronous transmission channel, an asynchronous transmission channel, a mode control module 110, and a direction control module (specifically including a first direction submodule 120 and a second direction submodule 130).

[0033] The first bidirectional data port A serves as the core interface for data exchange with the outside world, and can dynamically act as either a data sender or receiver based on the internal configuration of the data transmission circuit. In some implementations, in asynchronous transmission mode, the direction of data flow through the first bidirectional data port A is determined by the external data transmission circuit connected to that port; while in synchronous transmission mode, the direction of data flow is determined by the direction control module within the data transmission circuit provided by this invention.

[0034] The second bidirectional data port B and the first bidirectional data port A have the same properties. In this invention, data transmission has two directions. One direction is that data flows from the first bidirectional data port A to the second bidirectional data port B, and the other direction is that data flows from the second bidirectional data port B to the first bidirectional data port A.

[0035] like Figure 1As shown, the clock signal input terminal CK is used to receive the input clock signal. In some embodiments, this clock signal originates from an internal global clock network, phase-locked loop, or other clock generation and distribution data transmission circuitry. In some embodiments, the clock signal input terminal CK has high impedance to minimize the load on the clock network. Figure 1 As shown, the clock signal input terminal CK is set on the illustrated flip-flop D1, and the clock signal input terminal CK is connected to its clock pin. Flip-flop D1, as part of the synchronous transmission channel, has a Q terminal and a D terminal, where the Q terminal is the data output of the D flip-flop, and the D terminal is the data input of the D flip-flop. When in synchronous transmission mode, flip-flop D1 responds to the input clock signal, latching the input data (e.g., logic 0 or 1) at each valid edge of the clock signal (e.g., the rising edge) and outputting it from the Q terminal.

[0036] like Figure 1 As shown, the mode control signal input terminal M_SEL is used to receive the mode control signal, which may originate from the system's configuration register, microcontroller, or other control logic. In some embodiments, the mode control signal includes a first mode control signal and a second mode control signal. The first mode control signal is low (e.g., logic 0), indicating that the data transmission circuit provided by this invention is configured in asynchronous transmission mode; the second mode control signal is high (e.g., logic 1), indicating that the data transmission circuit provided by this invention is configured in synchronous transmission mode.

[0037] like Figure 1 As shown, the direction control signal input terminal (denoted as D_SEL_PAD) is used to receive the direction control signal (denoted as D_SEL). This direction control signal may originate from the routing controller, programmable configuration register, central processing core, or protocol state machine of the on-chip interconnect network. When the mode control signal is the second mode control signal, the data transmission circuit provided by this invention is configured to determine the flow direction of data between the first bidirectional data port A and the second bidirectional data port B through the direction control signal. In some embodiments, the direction control signal includes a first direction control signal and a second direction control signal, wherein the first direction control signal is high (e.g., logic 1), and the data flow direction is from the first bidirectional data port A to the second bidirectional data port B; the second direction control signal is low (e.g., logic 0), and the direction is from the second bidirectional data port B to the first bidirectional data port A.

[0038] Through the above-described configuration, the data transmission circuit provided by this invention possesses a complete external interactive interface. By using direction control signals and mode control signals, the operating mode and data flow direction of the data transmission circuit can be dynamically and quickly switched at the hardware level. This achieves the integration of multiple functions into a single data transmission circuit structure, avoiding the need to use multiple complex IPs, greatly improving the flexibility and adaptability of the data transmission circuit, and effectively reducing area occupation and overall power consumption.

[0039] In some embodiments of the present invention, the mode control module is connected to the mode control signal input terminal M_SEL to respond to the received mode control signal and mutually exclusively select the synchronous transmission channel or the asynchronous transmission channel in the form of a hardware data transmission circuit, thereby realizing a fundamental switch of the operating mode of the data transmission circuit.

[0040] Specifically, combined Figure 1 As shown, the mode control module 110 includes a first transmission gate T1 and a second transmission gate T2. The first transmission gate T1, as previously described, constitutes the main body of the asynchronous transmission channel, with its two ends connected to the first bidirectional data port A and the second bidirectional data port B, respectively. The second transmission gate T2 is connected in series on the synchronous transmission channel, specifically between the data output terminal Q of trigger D1 and the intermediate node X inside the data transmission circuit. Node X is the necessary path for data flow to the subsequent direction control module (specifically referring to the fifth transmission gate T5 or the sixth transmission gate T6 included in the direction control module). Therefore, the conduction and deactivation of the second transmission gate T2 determine whether the data after passing through trigger D1 can continue to be transmitted.

[0041] In some embodiments of the present invention, the mode control module further includes a first inverter I1, the input of which is connected to the mode control signal input M_SEL to receive the original mode control signal; its output generates an inverted signal (e.g., denoted as M_SEL_N) that is completely opposite to the logic level of M_SEL. The conduction and de-conduction of the second transmission gate T2 and the first transmission gate T1 are controlled collaboratively by the mode control signal and its inverted signal M_SEL_N, a pair of complementary signals. In a specific embodiment, the control logic is as follows: the mode control signal controls one control terminal of the first transmission gate T1, and the M_SEL_N signal controls the other control terminal of the first transmission gate T1; the control terminal connection of the second transmission gate T2 is opposite to that of the first transmission gate T1, and is controlled by the M_SEL_N signal and the mode control signal respectively.

[0042] When the mode control signal is at the first level (e.g., logic 0), its inverted signal M_SEL_N is logic 1. At this time, the conduction condition of the first transmission gate T1 is met, T1 conducts, and the data transmission circuit is configured in asynchronous transmission mode. Simultaneously, this level prevents the conduction condition of the second transmission gate T2 from being met, T2 is turned off, thus completely cutting off the synchronous transmission path and isolating the output of flip-flop D1. Conversely, when the mode control signal is at the second level (e.g., logic 1), M_SEL_N is logic 0. At this time, the control logic flips, the second transmission gate T2 meets the conduction condition and turns on, and the synchronous transmission path is open; the first transmission gate T1 is turned off because the conduction condition is not met, and the asynchronous transmission path is disabled.

[0043] The above configuration offers benefits including, but not limited to, the following: First, it provides flexible and reliable mode switching, achieving mutual exclusion control of the two paths. The rapid switching eliminates cycle delays in instruction fetching, decoding, and execution caused by software intervention, meeting the stringent real-time requirements of high-performance interconnects. Second, the dual-mode bidirectional structure provided by this invention is simple and compact, saving chip area and power consumption. Furthermore, it ensures the reliability of the transmission gate's switching state, avoiding the risk of competition from simultaneous conduction of different data transmission circuit channels or data interruption problems from simultaneous shutdown, thereby improving the overall reliability and stability of the data transmission circuit.

[0044] In some embodiments of the present invention, an asynchronous transmission channel is connected between the first bidirectional data port and the second bidirectional data port for direct data transmission. For example... Figure 1 and Figure 2 As shown, the asynchronous transmission channel includes a first transmission gate T1. One end of the first transmission gate T1 is connected to the first bidirectional data port A, and the other end is directly connected to the second bidirectional data port B, thereby establishing a direct connection path between port A and port B. When the mode control signal is the first mode control signal, the data transmission circuit provided by this invention is configured in asynchronous transmission mode. At this time, the first transmission gate T1 is turned on, while the second transmission gate T2 is turned off. Under this configuration, data can only move in the transmission path formed by the first bidirectional data port A, the first transmission gate T1, and the second bidirectional data port B. This transmission path has low transmission latency, depending on the on-resistance and parasitic capacitance of the transmission gate itself. This mode is suitable for, for example, building bidirectional buses or signal links requiring low latency where the direction is dynamically controlled by a higher-level protocol.

[0045] In some embodiments of the present invention, in asynchronous transmission mode, the direction of data flow is determined in real time by the driving state of the external data transmission circuit applied to the first bidirectional data port A and the second bidirectional data port B. For example, when the external data transmission circuit drives the first bidirectional data port A and the second bidirectional data port B is in a high-impedance state, data flows from A to B; conversely, data flows from B to A. It is worth noting that although the direction control module is physically present in the data transmission circuit, in asynchronous transmission mode, the direction of data flow is determined by the external drive, and the state of the direction control signal (D_SEL) and the transmission gates (T3, T4, T5, T6) controlled by it does not affect the logical connectivity of the data path.

[0046] It should be noted that in the above embodiments, the first transmission gate T1 plays a dual role: on the one hand, it is the core component of the asynchronous transmission channel, with its two ends directly connected to the first bidirectional data port A and the second bidirectional data port B, in order to establish a direct data path in the asynchronous transmission mode; on the other hand, it is also a key component of the controlled switch network in the mode control module, and together with the second transmission gate T2 and the first inverter I1, it forms a mutually exclusive gating structure driven by the mode control signal.

[0047] Physically, the first transmission gate T1 is a single, independent transmission gate device; logically, from the perspective of the data path, it belongs to the asynchronous transmission channel, and from the perspective of control, it belongs to the mode control module. These two aspects are not contradictory, but rather functional descriptions of the same hardware resource from different dimensions. Those skilled in the art should understand that this module definition method based on functional division aims to clearly explain the working principle and signal flow of the data transmission circuit, and should not be interpreted as a repetitive limitation or logical contradiction regarding the attribution of components.

[0048] like Figure 3 and Figure 4 As shown, in some embodiments of the present invention, a synchronous transmission channel is connected between the first bidirectional data port A and the second bidirectional data port B, and is connected to the clock signal input terminal CK, for performing timed data transmission with strict timing relationships in response to the received clock signal. The synchronous transmission channel includes at least one trigger. For example... Figure 1 As shown, in a specific embodiment of the present invention, a D flip-flop D1 is used. The D flip-flop has been described previously and will not be repeated here. By setting the flip-flop, the data stream transmission in synchronous transmission mode is synchronized with the clock signal, thereby ensuring the reliability and correctness of data exchange.

[0049] In some embodiments of the present invention, the data input terminal D of the trigger D1 is connected to an internal node Y, which is jointly connected by the output terminals of the third transmission gate T3 and the fourth transmission gate T4 in the direction control module; its data output terminal Q is connected to an internal node X, which is jointly connected by the input terminals of the fifth transmission gate T5 and the sixth transmission gate T6 in the direction control module, through the second transmission gate T2. This connection method makes the trigger D1 the core register unit in the synchronous transmission path.

[0050] When the data transmission circuit provided by this invention operates in synchronous transmission mode, at each valid edge of the clock signal CK, according to the configuration of the direction control signal D_SEL, data from a designated source port (e.g., A or B) is selected by the direction control module and sent to the D input of flip-flop D1. When the CK edge arrives, the data is captured and latched by D1. Subsequently, the latched data is output from the Q terminal of D1, and through the conducting second transmission gate T2, it is again guided by the direction control module to the designated target port (e.g., B or A). The entire process proceeds in rhythm with the clock signal, realizing the synchronization, storage, and forwarding of data from source to destination.

[0051] It should be noted that this invention does not limit the specific implementation type of the flip-flop. Although the accompanying drawings show a rising-edge triggered D flip-flop, those skilled in the art can use falling-edge triggered D flip-flops, flip-flops with enable terminals, or other sequential logic units with similar data latching functions to achieve the same synchronous transmission function, all of which fall within the scope of protection of this invention. The design of the synchronous transmission channel provides a clock-controlled, bidirectional data transmission path with register capability, suitable for data exchange scenarios that need to be synchronized with the system clock domain. It is the foundation for building a reliable, high-performance interconnection network. Variations in its specific implementation components should not constitute a limitation of this invention, nor affect its implementation.

[0052] like Figure 1 As shown, in some embodiments of the present invention, the direction control module is connected to the direction control signal input terminal (denoted as D_SEL_PAD) to control the transmission direction of data between the first bidirectional data port A and the second bidirectional data port B in response to the received direction control signal, in synchronous transmission mode. The direction control module is responsible for data input selection and output allocation through two sets of complementary control switch networks. Specifically, in conjunction with... Figure 1As shown, the direction control module includes a first direction submodule 120, which includes a third transmission gate T3 and a fourth transmission gate T4. The input of the third transmission gate T3 is connected to the second bidirectional data port B, and its control is achieved by direction control signals D_SEL and D_SEL_b (D_SEL_b originates from the second inverter I2) sent from the direction control signal terminal D_SEL_PAD. The input of the fourth transmission gate T4 is connected to the first bidirectional data port A, and its control is achieved by complementary direction control signals D_SEL_b and D_SEL_bb (D_SEL_bb originates from the third inverter I3, and D_SEL_b originates from the second inverter I2). The outputs of the third transmission gate T3 and the fourth transmission gate T4 are jointly connected to the data input D of the trigger D1. The first direction submodule 120 is used to select and guide data from the data port specified by D_SEL (e.g., A or B) to the data input D of the synchronous transmission channel.

[0053] like Figure 1 As shown, in some embodiments of the present invention, the direction control module further includes a second direction submodule 130, which includes a fifth transmission gate T5 and a sixth transmission gate T6. The inputs of the fifth transmission gate T5 and the sixth transmission gate T6 are connected to an internal node X, which is connected to the output of the second transmission gate T2 and carries the data synchronized by flip-flop D1. The output of the fifth transmission gate T5 is connected to the second bidirectional data port B, and the output of the sixth transmission gate T6 is connected to the first bidirectional data port A. The present invention does not limit the specific implementation type of the transmission gates; they can be analog switches implemented based on CMOS, NMOS, or other processes. Their core function is to provide bidirectional conduction and shutdown control with essentially no voltage attenuation. Changes in the specific implementation components should not constitute a limitation of the present invention, nor affect the implementation of the present invention. The direction control module is used to allocate and drive data from the output (Q) of the synchronous transmission channel to a designated target port.

[0054] like Figure 1 As shown, in some embodiments of the present invention, the second direction submodule 130 of the direction control module further includes an inverter chain for generating complementary control signals. The inverter chain is composed of a second inverter I2 and a third inverter I3 cascaded together to convert a single direction control signal D_SEL into two complementary control signals with determined phases, thereby realizing the switching control of four transmission gates T3, T4, T5, and T6.

[0055] It is worth noting that this invention does not limit the specific implementation process of the aforementioned inverters, including the first inverter I1 belonging to the mode control module, and the second inverter I2 and third inverter I3 belonging to the direction control module. They can adopt standard CMOS inverters, Schmitt trigger inverters, or other circuit structures with inverting logic functions. Any equivalent circuit structure that can generate a pair of complementary control signals and drive the subsequent transmission gate network does not depart from the protection scope of this invention.

[0056] Specifically, in combination Figure 1 As shown, the input terminal of the second inverter I2 is connected to the direction control signal input terminal (denoted as D_SEL_PAD) to receive the original direction control signal (denoted as D_SEL). The second inverter I2 generates an inverted signal of this signal at its output terminal, denoted as D_SEL_b. This signal D_SEL_b serves as an independent direction control signal, transmitted to the subsequent transmission gate control terminal; on the other hand, it also serves as the input signal of the third inverter I3.

[0057] The input of the third inverter I3 is connected to the output of the second inverter I2, i.e., it receives the D_SEL_b signal. The third inverter I3 performs a second inversion on the D_SEL_b signal, generating a signal at its output that has the same logic as the original direction control signal, but has been shaped and buffered by two stages of inverters, denoted as D_SEL_bb. It should be noted that D_SEL_bb, driven by two stages of inverters, has improved load-carrying capacity, edge steepness, and anti-interference ability, and can reliably drive multiple subsequent parallel transmission gate control terminals, thereby ensuring rapid and stable switching action.

[0058] Specifically, when the data transmission circuit provided by this invention is configured in synchronous transmission mode (e.g., the second mode control signal, logic 1), and the direction control signal is specified as transmission from port A to port B (e.g., the direction control signal is the first direction control signal, logic 1), such as Figure 2 As shown in the highlighted path, the direction control module turns on the fourth transmission gate T4 and the fifth transmission gate T5, while turning off the third transmission gate T3 and the sixth transmission gate T6. At this time, the synchronous data transmission path established and activated by the direction control module is as follows: Data is transmitted from the first bidirectional data port A to the turned-on fourth transmission gate T4, then to the data input D of flip-flop D1, latched at the valid edge of clock CK, and then to the data output Q of flip-flop D1, then to the turned-on second transmission gate T2, then to the internal node X, then to the turned-on fifth transmission gate T5, and finally to the second bidirectional data port B. This completes the timed data transmission process in synchronous transmission mode from the first bidirectional data port A to the second bidirectional data port B.

[0059] Conversely, when the direction control signal is specified as transmission from port B to port A (e.g., the direction control signal is the second direction control signal, with logic 0), the complementary control signal flips, causing the third transmission gate T3 and the sixth transmission gate T6 to conduct, while the fourth transmission gate T4 and the fifth transmission gate T5 are turned off. At this time, the synchronous transmission data path established and activated by the direction control module is as follows: the data from the second bidirectional data port B is transmitted to the conducting third transmission gate T3, then to the data input D of flip-flop D1, latched on the valid edge of clock CK, transmitted to the data output Q of flip-flop D1, then to the conducting second transmission gate T2, then to the internal node X, then to the conducting sixth transmission gate T6, and finally to the first bidirectional data port A. This completes the data timing transmission process in the synchronous transmission mode from the second bidirectional data port B to the first bidirectional data port A. The direction control module utilizes a transmission gate network and complementary signal control logic to achieve reconfigurable and rapid hardware guidance of the synchronous data stream direction. Working in conjunction with the mode control module, it constitutes the core mechanism for the flexible, efficient, and reliable data interconnection of the data transmission circuit of this invention.

[0060] In summary, the data transmission circuit provided by this invention achieves benefits including, but not limited to, the following: By dividing multiple transmission gates into different switching groups for control, the selection of data input terminals (e.g., executed by the third transmission gate T3 / fourth transmission gate T4) and the allocation of data output terminals (e.g., executed by the fifth transmission gate T5 / sixth transmission gate T6) are kept synchronized. This avoids path conflicts or data latching errors that may be caused by timing deviations in control signals, effectively improving the reliability and robustness of the data transmission circuit. Multiple transmission gates distributed at different positions along the data path are manipulated by external direction control signals, simplifying the complexity of the chip's external interface and control logic. Mode switching and direction switching are completed by pure hardware inverters in conjunction with the transmission gates, resulting in short switching times without software intervention, meeting the requirements of high-performance chip interconnects for extremely low latency.

[0061] The present invention further provides a chip system. The chip system includes a packaging substrate and multiple chips. The multiple chips are integrated on or within the packaging substrate using advanced packaging technologies (e.g., 3D stacking, 2.5D adapter boards, embedded bridge chips, system-in-package, etc.), establishing a high-speed, high-density interconnect network among them. At least one of the multiple chips integrates the data transmission circuit described in any of the foregoing embodiments; or, the at least one chip is a multi-chip integrated circuit, comprising multiple chips, and the data transmission circuit is integrated within at least one of the multiple chips, serving as a physical layer transceiver unit for inter-chip interconnection, deployed on the data path at the chip boundary to achieve synchronous or asynchronous, unidirectional or bidirectional data transmission between different chips.

[0062] Specifically, the chip system can be a heterogeneous integrated processor system, including various functional chips such as computing chips, memory chips, and interface chips. For example, in one embodiment, the chip system is a central processing unit (CPU) or graphics processing unit (GPU) system based on a chip-neck architecture, comprising a computing chip packaged with multiple computing chips and at least one cache coherent interconnect chip. The cache coherent interconnect chip integrates multiple data transmission circuits to establish low-latency, high-bandwidth data paths between multiple computing chips. In another embodiment, the chip system is a high-bandwidth memory (HBM) system, comprising a memory chip stacked with multiple memory chips and a logic control chip. The logic control chip integrates the data transmission circuits for high-speed data exchange with the processor chip. In yet another embodiment, the chip system is an interface bridging chip system conforming to common chip-neck interconnect standards (such as UCIe, BoW, etc.), which integrates the data transmission circuits to achieve protocol adaptation and data forwarding between different process nodes and different functional chips.

[0063] It should be noted that this invention does not limit the specific functional type, integration method, or number of chips in the chip system. Any chip system product containing at least one chip or granular component integrating the data transmission circuit falls within the protection scope of this invention. The data transmission circuit, with its high integration, fast hardware switching, low latency, and low power consumption, can significantly improve data throughput efficiency, reduce communication latency, and simplify system design and layout / routing complexity in chip-level and granular-level interconnection scenarios. It is particularly suitable for applications with stringent requirements for area, power consumption, and real-time performance, such as high-performance computing, artificial intelligence training and inference, cloud servers, and edge computing.

[0064] The present invention further provides an electronic device comprising the chip system described in any of the foregoing embodiments. By employing a chip system integrating the data transmission circuit, the electronic device achieves an overall improvement in data transmission efficiency and energy efficiency at the chip, board, and system levels.

[0065] Specifically, the electronic device can be various forms of computing or communication equipment. For example, in one embodiment, the electronic device is a data center server, whose processor or accelerator card integrates the chip-integrated chip. Utilizing the low-latency characteristics of the data transmission circuit, the communication overhead between chips is significantly reduced, improving overall computing power utilization. In another embodiment, the electronic device is an artificial intelligence training server or inference device, comprising multiple parallel computing accelerator chips. These chips exchange data at high frequency through an interconnection network integrating the data transmission circuit, thereby accelerating model training and inference processes. In yet another embodiment, the electronic device is an autonomous driving domain controller, whose internally integrated chip-integrated chip is responsible for processing high real-time data from multiple sensors. The asynchronous transmission mode of the data transmission circuit can meet the requirements for extremely fast response to sensor interruption signals, while the synchronous transmission mode ensures the deterministic timing of data processing. Furthermore, the electronic device may also include, but is not limited to, high-performance mobile terminals, network communication devices, edge computing nodes, industrial control computers, medical imaging equipment, etc. Any electronic device incorporating the chip-integrated chip described in this invention falls within the protection scope of this invention.

[0066] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0067] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A data transmission circuit, characterized in that, include: The first bidirectional data port is used for sending and receiving data; The second bidirectional data port is used for sending and receiving data; Clock signal input terminal, used to receive clock signals; The mode control signal input terminal is used to receive mode control signals; The direction control signal terminal is used to receive direction control signals; A synchronous transmission channel is connected between the first bidirectional data port and the second bidirectional data port, and is connected to the clock signal input terminal, in order to transmit data in timed response to the clock signal; An asynchronous transmission channel is connected between the first bidirectional data port and the second bidirectional data port, and is connected in parallel with the synchronous transmission channel to directly transmit data; A mode control module, connected to the mode control signal access terminal, is used to selectively turn on the synchronous transmission channel and the asynchronous transmission channel in response to the mode control signal; A direction control module, connected to the direction control signal terminal, is used to control the transmission direction of data between the first bidirectional data port and the second bidirectional data port in response to the direction control signal.

2. The data transmission circuit according to claim 1, characterized in that: The synchronous transmission channel includes at least one trigger, the clock terminal of which is connected to the clock signal input terminal to trigger data transmission in response to the clock signal.

3. The data transmission circuit according to claim 1, characterized in that: The asynchronous transmission channel includes a first transmission gate, one end of which is connected to the first bidirectional data port, and the other end is directly connected to the second bidirectional data port.

4. The data transmission circuit according to claim 1, characterized in that: The mode control module includes a second transmission gate, which is connected in series between the data output terminal of the trigger and an internal node; The first transmission gate is connected between the first bidirectional data port and the second bidirectional data port.

5. The data transmission circuit according to claim 4, characterized in that: The mode control module further includes a first inverter, the input of which is connected to the mode control signal input, and its output is connected to the second transmission gate and the first transmission gate, for providing a mode control signal that is inverted from the mode control signal.

6. The data transmission circuit according to claim 1, characterized in that: The direction control module includes a first direction submodule, a third transmission gate and a fourth transmission gate of the first direction submodule, the output terminals of the third transmission gate and the fourth transmission gate are both connected to the trigger; the input terminal of the third transmission gate is connected to the second bidirectional data port, and the input terminal of the fourth transmission gate is connected to the first bidirectional data port.

7. The data transmission circuit according to claim 6, characterized in that: The direction control module also includes a second direction sub-module; The inputs of the fifth and sixth transmission gates are connected to the data output of the internal node or the trigger; the output of the fifth transmission gate is connected to the second bidirectional data port, and the output of the sixth transmission gate is connected to the first bidirectional data port.

8. The data transmission circuit according to claim 7, characterized in that: It also includes a second inverter and a third inverter for inverting the direction control signal; The input terminal of the second inverter is connected to the direction control signal input terminal; The input terminal of the third inverter is connected to the output terminal of the second inverter, and the output terminal of the third inverter is connected to the third transmission gate, the fourth transmission gate, the fifth transmission gate, and the sixth transmission gate.

9. A chip system, characterized in that, include: Packaging substrate; Multiple chips are interconnected and integrated on the packaging substrate, wherein at least one of the multiple chips integrates a data transmission circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Including the chip system as described in claim 9.

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