Semiconductor pattern matching method and system considering photolithography process deformation

Abstract

The application belongs to the technical field of integrated circuits, and provides a semiconductor pattern matching method and system considering photoetching process deformation, adopting a divide-and-conquer strategy: firstly, unified preprocessing and standardization are performed on layout data; then, for regular patterns, precise matching is realized by directly comparing normalized geometric features; for irregular patterns, firstly, simplification is performed through a recursive simplification algorithm, then, curvature segmentation, grid alignment and region merging are performed to reconstruct orthogonal topological structures, finally, tolerance matching is realized by threshold comparison through fusing multiple features such as contour proximity, track similarity and shape distribution features into comprehensive similarity. The application can effectively shield normal deformation within a process allowable range, identify real defects such as bridging and open circuit, and efficiently and accurately perform automatic matching on all types of patterns after processing, thereby improving the efficiency of OPC verification and mask detection.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and particularly relates to a semiconductor pattern matching method and system that takes into account the deformation of photolithography process. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] As semiconductor manufacturing processes continue to advance to the nanometer node, the optical proximity effect (OPE) in photolithography becomes increasingly pronounced. To ensure the quality of photolithography imaging, optical proximity correction (OPC) must be performed on the original design pattern. However, the pattern formed after OPC processing and actual exposure and development on the wafer often differs significantly from the original semiconductor design pattern. For example, right angles in the original design will appear as rounded corners on the wafer, and straight edges will exhibit wavy edges due to standing wave effects or photoresist properties.

[0004] Currently, pattern matching techniques addressing these differences are mainly divided into two categories. One is pixel-based image template matching, which is computationally intensive and highly sensitive to noise in scanning electron microscope images. The other is rigid matching based on vertex coordinates, which requires a one-to-one correspondence between the vertices of the target semiconductor pattern and the template pattern. However, in real-world scenarios, a designed rectangle may become a smooth closed curve composed of hundreds of discrete points after actual photolithography. Existing vertex matching methods may misjudge these normal deformations caused by photolithography physical effects as defects, or infinitely relax the threshold to tolerate deformation, leading to missed detection of critical defects. Summary of the Invention

[0005] To address at least one of the technical problems mentioned above, this invention provides a semiconductor pattern matching method and system that takes into account photolithography deformation. Under the premise of strictly controlling geometric deformation errors, it can restore irregular actual photolithography patterns to the original design topology and minimize redundant data. This enables high-precision and high-efficiency processing of universal matching of regular and irregular deformed patterns, avoiding the omission of critical defects.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A first aspect of the present invention provides a semiconductor pattern matching method that takes into account photolithography process deformation, comprising the following steps: Acquire the actual semiconductor pattern contour data after photolithography and the corresponding original design layout data, and preprocess the pattern contour data; The preprocessed semiconductor pattern contour data is classified to determine the type of the actual semiconductor pattern. For regular semiconductor patterns, a similarity score is obtained by directly comparing the geometric properties of the regular semiconductor pattern and the original design layout; For irregular shapes, a recursive simplification algorithm is used to simplify the irregular semiconductor shape to obtain the main shape outline of the semiconductor shape. Based on the main shape outline, regularization reconstruction is performed to obtain a regularized semiconductor shape. The similarity is calculated based on the multi-dimensional features of the extracted regularized semiconductor shape and the original design layout to obtain a similarity score. The similarity score is compared with a preset threshold for a specific process. If the score is higher than the threshold, it is judged as a normal process deviation; otherwise, it is judged as a potential defect.

[0007] Furthermore, preprocessing of the graphic contour data includes: The multi-line coordinate strings of the actual semiconductor pattern outline data after photolithography and the corresponding original design layout data are parsed and converted into standard structured polygon coordinate strings. For each polygon, find its bottom leftmost vertex as the starting point, set the coordinates of the starting point to zero, and convert the coordinates of all other vertices of the polygon to coordinates relative to the starting point. Calculate the area of ​​the polygons, determine the orientation of their vertices based on the sign of the area, and then adjust all polygons to a clockwise direction. Detect and remove three or more collinear vertices, keeping only the two endpoints of the line segment, thus obtaining the effective geometric topology of the polygon.

[0008] Furthermore, the preprocessed semiconductor pattern contour data is classified, including: If the included angle between all adjacent boundary vectors of the semiconductor pattern falls within the range of or If the semiconductor pattern falls within the preset tolerance range, it is determined that the semiconductor pattern has orthogonal topological features and is classified as a regular pattern. The preset angle tolerance threshold; If at least one set of adjacent boundary vectors in a semiconductor pattern has an angle that exceeds the preset tolerance range, or contains non-linear curved boundaries, then the semiconductor pattern is determined to contain non-orthogonal geometric features and is classified as an irregular pattern.

[0009] Furthermore, for regular semiconductor patterns, the similarity scoring formula is obtained by comparing the geometric attributes of the regular semiconductor pattern and the original design layout: , , in, This indicates the overall similarity score. For semiconductor regular patterns and original design layouts i Similarity sub-scores for geometric features For the first i Each geometric feature has a pre-defined weight. These are the characteristic values ​​of regular semiconductor patterns. These are the corresponding feature values ​​of the original design layout. The total number of dimensions of the geometric features being compared.

[0010] Furthermore, for irregular shapes, the simplification of irregular semiconductor shapes using a recursive simplification algorithm includes: Calculate the perpendicular distance from any point in the contour coordinate sequence to the line connecting the first and last vertices; Find the maximum value among all vertical distances and its corresponding dividing points; judge and preset tolerance parameters If the relationship, Less than or equal to If the current segment is sufficiently simplified, only the first and last vertices of the current segment are retained. like Greater than Then Using the corresponding dividing points as boundaries, the outline is segmented and the simplification process is recursively executed; Connect all the retained feature points in their original order to form a simplified contour after filtering out edge roughness.

[0011] Furthermore, the process of regularizing and reconstructing based on the main shape contour to obtain a regularized semiconductor pattern includes: Set a corner threshold and perform curvature segmentation on the simplified main shape contour. By adjusting the preset corner threshold, corners with significant changes in direction can be identified, and the contour can be divided into multiple line segments that are approximately straight. Project the segmented line segments onto the nearest horizontal or vertical direction and align them to the grid. Set an overlap threshold, extract axis-aligned rectangles from the aligned line segments, and merge adjacent rectangles that overlap more than the overlap threshold to reconstruct the regularized body of the graphic. Set a grouping tolerance threshold, group line segments that are close in position and in the same direction, calculate the average position of each group as the principal coordinate, and align all line segments in the group to this principal coordinate to obtain grouped clustering. After deduplication, a regularized semiconductor pattern is obtained.

[0012] Furthermore, when calculating the similarity based on the multi-dimensional features of the extracted regularized semiconductor pattern and the original design layout, the calculation includes converting the calculated contour proximity, trajectory similarity and shape spatial distribution difference into normalized feature sub-scores with a value range of (0,1] through a negative exponential mapping function, assigning preset weights to each feature, and obtaining the final comprehensive similarity score by weighted summation.

[0013] A second aspect of the present invention provides a semiconductor patterning system that takes into account photolithography process deformation, comprising: The data preprocessing module is used to acquire the actual semiconductor pattern contour data after photolithography and the corresponding original design layout data, and to preprocess the pattern contour data. The image classification module is used to classify the preprocessed semiconductor image contour data and determine the type of the actual semiconductor image. The regular pattern matching module is used to obtain a similarity score for regular semiconductor patterns by directly comparing the geometric properties of the regular semiconductor pattern and the original design layout. The irregular shape matching module is used to simplify irregular semiconductor shapes using a recursive simplification algorithm to obtain the main shape contour of the semiconductor shape. Based on the main shape contour, regularization reconstruction is performed to obtain a regularized semiconductor shape. The similarity is calculated based on the multi-dimensional features of the extracted regularized semiconductor shape and the original design layout to obtain a similarity score. The defect detection module compares the similarity score with a preset threshold for a specific process. If the score is higher than the threshold, it is determined to be a normal process deviation; otherwise, it is determined to be a potential defect.

[0014] A third aspect of the present invention provides a computer-readable storage medium.

[0015] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps in the semiconductor pattern matching method taking into account photolithography process deformation as described above.

[0016] A fourth aspect of the present invention provides a computer device.

[0017] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the program, implements the steps of the semiconductor pattern matching method taking into account photolithography process deformation as described above.

[0018] Compared with the prior art, the beneficial effects of the present invention are: This invention achieves comprehensive matching of all types of regular and irregular graphics through a divide-and-conquer strategy. For irregular graphics deformed by photolithography, a recursive simplification algorithm with threshold control is used to filter out minor jitter caused by electron beam measurement noise and photoresist edge roughness, while retaining the main topological skeleton of the graphics. Then, smooth corners caused by photolithography rounded corner effects are identified, and the deformed measured contours are restored to a fitted design graphic containing right-angle features. This can effectively shield normal deformations within the allowable range of the process, identify real defects such as bridging and open circuits, and perform automated matching of all types of processed graphics efficiently and accurately, improving the efficiency of OPC verification and mask inspection.

[0019] Advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0020] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0021] Figure 1 This is a flowchart of a semiconductor pattern matching method considering photolithography deformation provided in an embodiment of the present invention; Figure 2 This is the original outline of an actual graphic after OPC correction provided in an embodiment of the present invention; Figure 3 This is the result after applying the recursive simplification algorithm and extracting the rectangular outline, as provided in the embodiments of the present invention; Figure 4 This is the result of curvature segmentation of the graphic provided in the embodiments of the present invention; Figure 5 This is a graphic generated after grouping and clustering line segments, as provided in the embodiments of the present invention. Figure 6 This is a comparison between the actual graphic after OPC correction and the regularized graphic provided in the embodiments of the present invention. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0024] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0025] To address the technical challenge in integrated circuit manufacturing and photomask inspection where nonlinear deformation between the actual wafer pattern and the original design pattern occurs due to optical proximity effect and process fluctuations, leading to matching failures and missed detection of critical defects, this invention proposes a method to read the original layout data and the actual processed graphic data, perform coordinate normalization and orientation unification to form a unified graphic representation; classify the preprocessed graphics, and for graphics conforming to regular graphic characteristics, perform precise matching by comparing their standardized geometric attributes; for irregular graphics deformed by optical effects, sequentially perform graphic simplification, regularization reconstruction, multi-dimensional feature extraction, and similarity calculation, and finally achieve tolerance matching by comparing the comprehensive similarity score with a preset threshold.

[0026] By employing a divide-and-conquer strategy, comprehensive matching of all types of regular and irregular graphics was achieved. For irregular graphics deformed by photolithography effects, a recursive simplification algorithm with threshold control was used to filter out minor jitter caused by electron beam measurement noise and photoresist edge roughness, while retaining the main topological skeleton of the graphics. Then, smooth corners caused by photolithography rounding effects were identified, and the deformed measured contours were restored to a fitted design graphic containing right-angle features. Contour proximity, trajectory similarity, and shape distribution features between the reconstructed graphic and the original design graphic were extracted, and a comprehensive similarity score was calculated through weighted fusion. Finally, the comprehensive similarity score was compared with a threshold preset for a specific process. If the score was higher than the threshold, it was determined to be a normal process deviation, and the match was successful; otherwise, it was marked as a potential defect, avoiding missed defect detection.

[0027] Example 1 like Figure 1 As shown, this embodiment provides a semiconductor pattern matching method that takes into account photolithography process deformation, including the following steps: Step 1: Obtain the actual semiconductor pattern contour data after photolithography or etching and the corresponding original design layout data, and preprocess the pattern contour data; In this embodiment, the preprocessing of the actual semiconductor graphic contour data includes coordinate normalization and orientation unification to form a unified graphic representation, specifically including the following processes: Based on the coordinate sequence in the original design layout data and the actual semiconductor pattern outline data, the original multi-line coordinate string is parsed and converted into a standard structured polygon coordinate string; For each polygon, find its bottom leftmost vertex as the starting point, set the coordinates of the starting point to zero, and convert the coordinates of all other vertices of the polygon to coordinates relative to the starting point. Calculate the area of ​​the polygons, determine the orientation of their vertices based on the sign of the area, and then adjust all polygons to a clockwise direction. Detect and remove three or more collinear vertices, keeping only the two endpoints of the line segment, thus obtaining the effective geometric topology of the polygon.

[0028] Step 2: Classify the preprocessed semiconductor pattern contour data to determine the type of pattern; In this embodiment, if the included angle between all adjacent boundary vectors of the semiconductor pattern falls within the range of... or Within the preset tolerance range (where If the preset angle tolerance threshold is 5° in this embodiment, then the semiconductor pattern is determined to have orthogonal topological features and is classified as a regular pattern. If at least one set of adjacent boundary vectors in a semiconductor pattern has an angle that exceeds the preset tolerance range, or contains non-linear curved boundaries, then the semiconductor pattern is determined to contain non-orthogonal geometric features and is classified as an irregular pattern.

[0029] Step 3: For regular shapes, a similarity score is obtained by directly comparing the geometric properties of the semiconductor regular shape and the original design layout; for irregular shapes, shape simplification, regularization reconstruction, multi-dimensional feature extraction and similarity calculation are performed in sequence. In this embodiment, by adopting a divide-and-conquer strategy, fast matching is used for the vast majority of regular graphics, while deep reconstruction is performed only for complex deformed graphics, which greatly improves the processing efficiency of the entire chip data.

[0030] Specifically, the steps include the following: Step 301: For regular patterns, obtain a similarity score by directly comparing the geometric properties of the semiconductor regular pattern and the original design layout; In this embodiment, the geometric properties being compared include geometric features such as coordinates, area, and side length.

[0031] Let the characteristic value of a regular semiconductor pattern be... The corresponding characteristic value of the original design layout is .like Then the similarity sub-score of this feature If the score is 1.0, then the similarity sub-score for the feature is calculated based on the normalized absolute difference between the two, as shown in the following formula: , A weight set is preset for each of the geometric features. The final comprehensive similarity score is obtained by weighted summation of the similarity sub-scores of each feature and their corresponding weights, using the following formula: , For semiconductor regular patterns and original design layouts i Similarity sub-scores for geometric features For the first i Each geometric feature has a pre-defined weight. The total number of dimensions of the geometric features being compared.

[0032] Step 302: For irregular shapes, perform shape simplification, regularization reconstruction, multi-dimensional feature extraction and similarity calculation in sequence; Specifically, the steps include the following: Step 3021: For irregular shapes, the irregular semiconductor shapes are simplified by a recursive simplification algorithm to obtain the main shape outline of the semiconductor shapes; For irregular shapes deformed by photolithography, a recursive simplification algorithm is first used, with the epsilon parameter set to control the degree of simplification, significantly reducing the number of vertices while preserving the main shape outline; for example... Figure 2 As shown, it is the original outline of an irregular shape; For the recursive simplification algorithm, first define the vertical distance calculation function. Used to calculate any point in a contour coordinate sequence. From the starting point and the end point The perpendicular distance of the line segment SE is calculated using the following formula: , Define a recursive simplification function ,in, For the input ordered sequence of coordinate points , The preset tolerance parameters, The number of coordinate points; The processing logic satisfies the following mathematical relationship: , when When the value is less than 3, directly output the original sequence: ; when When ≥ 3, set the starting point and the ending point ; Calculate all intermediate points (1 < i < n) to the perpendicular distance of the line segment SE, and find the maximum perpendicular distance and its corresponding splitting point : , , Traverse all intermediate points between the starting and ending points, calculate the perpendicular distance of each point to the line connecting the starting and ending points; record the point with the maximum perpendicular distance and its distance value ; According to the maximum distance and the tolerance parameter relationship, The output of is defined as follows: Case A: If ≤ , it is considered that the current segment has been sufficiently simplified, and the output is: , Case B: If > , take this maximum distance point as the splitting point, divide the contour into left and right segments, and repeat this screening and simplification process for each segment, and the output is: , Among them, represents the subsequence on the left side of the splitting point; represents the subsequence on the right side of the splitting point; the operator means to connect the two simplified sequences in the original order and remove duplicates for the repeated splitting points .

[0033] For example, set the preset tolerance parameter , corresponding to the allowable edge roughness of the process. Assume that a sequence of edge points affected by the lithography standing wave effect is collected , and its line connecting the starting and ending points is . Calculate the perpendicular distance from the intermediate point (5, 10.12) to the line is 0.12, and the distance of the point (10, 9.95) is 0.05. Since the maximum perpendicular distance , the system determines that the undulation of this segment is noise and directly outputs the simplified starting and ending points {(0, 10), (15, 10)}, thus removing the edge jitter.

[0034] Finally, connect all the remaining feature points in the original order to form a simplified polygon contour.

[0035] The above technical solution filters out minute jitters caused by electron beam measurement noise and photoresist edge roughness, while preserving the main topological skeleton of the pattern.

[0036] Step 3022: Based on the main shape contour, perform regularization reconstruction to obtain regularized semiconductor patterns; Specifically, the steps include the following: Set the corner threshold angle_threshold to perform curvature segmentation on the simplified main shape contour. By adjusting the preset corner threshold, corners with obvious changes in direction are identified, and the contour is divided into multiple line segments that are approximately straight. Project the segmented line segments onto the nearest horizontal or vertical direction and align them to the grid, such as... Figure 3 The image shows the result after applying the recursive simplification algorithm and performing grid alignment; Set an overlap threshold (overlap_threshold), extract axis-aligned rectangles from the aligned line segments, and merge adjacent rectangles with an overlap exceeding overlap_threshold to reconstruct the regularized body of the graphic; for example... Figure 4 As shown, this is the result of reconstructing the regularized subject from the recursively simplified graph; A position grouping tolerance threshold, epsilon, is set to control the strictness of coordinate alignment. The specific calculation and determination process is as follows: First, cluster the data by calculating the first absolute deviation between adjacent coordinates. Extract the endpoints of all line segments and separate their X and Y coordinates, constructing independent one-dimensional coordinate sequences for each, and then deduplicate and sort them in ascending order. Traverse the sorted coordinate sequences and calculate the first absolute deviation between the current coordinate and the last coordinate in its cluster, using the following formula: .in, The coordinates of the current traversal. This is the coordinate of the last position within the current cluster group. If the first absolute deviation... If the two coordinates are close, the current coordinate is added to the current cluster group; otherwise, a new cluster group is created starting from the current coordinate. Secondly, calculate the principal coordinates of the cluster groups. After obtaining the grouping results, calculate the arithmetic mean of all coordinates within each cluster group, and use this as the representative principal coordinate of that group; Finally, the second absolute deviation between the original coordinates and the principal coordinates is calculated for alignment mapping. For each original endpoint coordinate of the graphic contour, the second absolute deviation between it and each principal coordinate is calculated iteratively, using the following formula: .in, These are the original endpoint coordinates. Let be the principal coordinates of a certain cluster group. From all calculated results, select the one with the second smallest absolute deviation that satisfies... The target principal coordinates are then used to directly align and map the original endpoint coordinates to these target principal coordinates. For example... Figure 5 As shown, it is a graph drawn after using a recursive simplification algorithm and performing line segment grouping and clustering.

[0037] Subsequently, the endpoint coordinate sequence after the above mapping and alignment process is deduplicated to ensure that the reconstructed graphic is a closed polygon. For example... Figure 6 The image shown is a comparison between the original image and the regularized image.

[0038] The above scheme can adapt to the deformation characteristics of different process nodes, and the algorithm can be reused simply by adjusting the simplified tolerance and mesh alignment parameters.

[0039] Step 3023: Calculate the similarity score based on the multi-dimensional features of the extracted regularized semiconductor pattern and the original design layout. Traverse all the graphics and extract basic geometric features, edge features, angle features and spatial features from the regularized graphics to obtain the shape attributes, edge uniformity, angle distribution and spatial location information of the graphics. The proximity of contours is calculated and defined as the maximum value of the nearest distance from any point between two contours to the other contour. It is used to measure how close the contours are.

[0040] Contour proximity measures the degree of closeness between the edges of two graphic contours. Let the set of points contained in the regularized graphic contour be... The original design layout's outline point set is .

[0041] First, calculate the point set. Point set First one-way proximity distance : , in,‖ || represents a contour point and The Euclidean distance between them. Similarly, calculate the point set. Point set Second one-way proximity distance The maximum value of the two is extracted as the final bidirectional profile extreme value proximity. : , Trajectory similarity is calculated by using a dynamic programming algorithm to determine the minimum coupling distance between two contour sequences, which measures the similarity of their orientations. To overcome comparison errors caused by inconsistent feature point counts, a recursive state transition model is employed to calculate the minimum coupling distance between the two contour sequences. Let the vertex sequences extracted sequentially from the two graphic contours be... and Construct a dimension as × The cumulative distance matrix, whose state elements are... ( , ) represents a subset of the sequence. and The minimum cumulative alignment error between them is calculated using the following formula for the state transition: , in, This represents the Euclidean distance between the currently traversed sequence of node pairs. The cumulative distance matrix is ​​calculated recursively from the starting point to the ending point using the above formula, and the last element of the matrix is ​​extracted. ( , Trajectory similarity between two contour sequences traj .

[0042] The shape distribution features are calculated by constructing a relative vector distribution histogram of contour points to characterize the shape context. A multi-dimensional relative spatial vector distribution histogram is constructed to characterize the global shape features of the pattern. For any reference point on the semiconductor pattern contour... Calculate all remaining contour points Relative to this reference point polar diameter With polar angle The calculation results are then mapped to a predefined log-polar coordinate system space grid. Statistical values ​​of partition characteristics of each grid The calculation formula is: , in, ( ) represents the th logarithmic polar coordinate system. Each spatial grid partition The parentheses (·) represent an indicator function (value 1 when the spatial attribution condition within the parentheses is met, otherwise value 0). Finally, based on the distribution histograms generated by the two figures, the shape space distribution difference is obtained by calculating the absolute difference distance between the histograms. .

[0043] After normalizing the extracted features, they are merged into a comprehensive similarity score. This process is repeated to obtain the final comprehensive similarity score. First, the various absolute difference characteristics calculated above are... Transformed into a normalized feature score with a range of (0,1] using a negative exponential mapping function: , in, For corresponding features The preset sensitivity attenuation coefficient is then used. Subsequently, preset weights are assigned to each feature. The final comprehensive similarity score is obtained by weighted summation: , in, This represents the total number of extracted features. The closer the overall similarity score is to 1, the better the overall geometric shape and spatial position of the two graphics match.

[0044] Through the simplification-reconstruction mechanism described above, the present invention can effectively shield normal rounded corner deformation and edge roughness interference in semiconductor processes, significantly reducing the false alarm rate in OPC verification.

[0045] Step 4: Compare the similarity calculation results with the threshold preset for the specific process.

[0046] Specifically, the specific process types include different semiconductor technology nodes (e.g., 28nm, 14nm, or 5nm process nodes) and different layout structure levels. Since different semiconductor technology nodes and layout structure levels have significantly different tolerances to lithographic proximity effects and dimensional deviations, the preset similarity threshold is configured independently based on the corresponding specific process type. If the score is higher than the threshold, it is determined to be a normal process deviation; otherwise, it is determined to have a potential defect.

[0047] This invention effectively shields normal deformations within the allowable range of the process, identifies genuine defects such as bridging and open circuits, and efficiently and accurately performs automated matching of all types of processed patterns, improving the efficiency of OPC verification and mask inspection. It solves the problem of difficulty in accurately matching the actual wafer pattern with the original design layout due to optical proximity effects and process fluctuations during photolithography and etching processes, which result in rounded corners and rough edges.

[0048] Example 2 This embodiment provides a semiconductor pattern matching system that takes into account photolithography process deformation, including: The data preprocessing module is used to acquire the actual semiconductor pattern contour data after photolithography and the corresponding original design layout data, and to preprocess the pattern contour data. The image classification module is used to classify the preprocessed semiconductor image contour data and determine the type of the actual semiconductor image. The regular pattern matching module is used to obtain a similarity score for regular semiconductor patterns by directly comparing the geometric properties of the regular semiconductor pattern and the original design layout. The irregular shape matching module is used to simplify irregular semiconductor shapes using a recursive simplification algorithm to obtain the main shape contour of the semiconductor shape. Based on the main shape contour, regularization reconstruction is performed to obtain a regularized semiconductor shape. The similarity is calculated based on the multi-dimensional features of the extracted regularized semiconductor shape and the original design layout to obtain a similarity score. The defect detection module compares the similarity score with a preset threshold for a specific process. If the score is higher than the threshold, it is determined to be a normal process deviation; otherwise, it is determined to be a potential defect.

[0049] It should be noted that the specific implementation of the semiconductor pattern matching system considering photolithography process deformation in this embodiment of the invention is similar to the specific implementation of the semiconductor pattern matching method considering photolithography process deformation in this embodiment of the invention. Please refer to the description in the method section for details. To reduce redundancy, it will not be repeated here.

[0050] Example 3 This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the semiconductor pattern matching method considering photolithography process deformation as described above.

[0051] Example 4 This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps in the semiconductor pattern matching method that takes into account photolithography process deformation as described above.

[0052] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage and optical storage) containing computer-usable program code.

[0053] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0054] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0055] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0056] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0057] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor pattern matching method considering photolithography deformation, characterized in that, Includes the following steps: Acquire the actual semiconductor pattern contour data after photolithography and the corresponding original design layout data, and preprocess the pattern contour data; The preprocessed semiconductor pattern contour data is classified to determine the type of the actual semiconductor pattern. For regular semiconductor patterns, a similarity score is obtained by directly comparing the geometric properties of the regular semiconductor pattern and the original design layout; For irregular shapes, a recursive simplification algorithm is used to simplify the irregular semiconductor shape to obtain the main shape outline of the semiconductor shape. Based on the main shape outline, regularization reconstruction is performed to obtain a regularized semiconductor shape. The similarity is calculated based on the multi-dimensional features of the extracted regularized semiconductor shape and the original design layout to obtain a similarity score. The similarity score is compared with a preset threshold for a specific process. If the score is higher than the threshold, it is judged as a normal process deviation; otherwise, it is judged as a potential defect. For irregular shapes, the step of simplifying irregular semiconductor shapes using a recursive simplification algorithm includes: Calculate the perpendicular distance from any point in the contour coordinate sequence to the line connecting the first and last vertices; Find the maximum value among all vertical distances and its corresponding dividing points; judge and preset tolerance parameters If the relationship, Less than or equal to If the current segment is sufficiently simplified, only the first and last vertices of the current segment are retained. like Greater than Then Using the corresponding dividing points as boundaries, the outline is segmented and the simplification process is recursively executed; Connect all the retained feature points in their original order to form a simplified contour after filtering out edge roughness.

2. The semiconductor pattern matching method considering photolithography deformation as described in claim 1, characterized in that, Preprocessing of graphic contour data includes: The multi-line coordinate strings of the actual semiconductor pattern outline data after photolithography and the corresponding original design layout data are parsed and converted into standard structured polygon coordinate strings. For each polygon, find its bottom leftmost vertex as the starting point, set the coordinates of the starting point to zero, and convert the coordinates of all other vertices of the polygon to coordinates relative to the starting point. Calculate the area of ​​the polygons, determine the orientation of their vertices based on the sign of the area, and then adjust all polygons to a clockwise direction. Detect and remove three or more collinear vertices, keeping only the two endpoints of the line segment, thus obtaining the effective geometric topology of the polygon.

3. The semiconductor pattern matching method considering photolithography deformation as described in claim 1, characterized in that, The preprocessed semiconductor pattern contour data is classified, including: If the included angle between all adjacent boundary vectors of the semiconductor pattern falls within the range of or If the semiconductor pattern falls within the preset tolerance range, it is determined that the semiconductor pattern has orthogonal topological features and is classified as a regular pattern. The preset angle tolerance threshold; If at least one set of adjacent boundary vectors in a semiconductor pattern has an angle that exceeds the preset tolerance range, or contains non-linear curved boundaries, then the semiconductor pattern is determined to contain non-orthogonal geometric features and is classified as an irregular pattern.

4. The semiconductor pattern matching method considering photolithography deformation as described in claim 1, characterized in that, For regular semiconductor patterns, the similarity scoring formula is obtained by comparing the geometric attributes of the regular semiconductor pattern and the original design layout: ， ， in, This indicates the overall similarity score. For semiconductor regular patterns and original design layouts i Similarity sub-scores for geometric features For the first i Each geometric feature has a pre-defined weight. These are the characteristic values ​​of regular semiconductor patterns. These are the corresponding feature values ​​of the original design layout. The total number of dimensions of the geometric features being compared.

5. The semiconductor pattern matching method considering photolithography deformation as described in claim 1, characterized in that, The process of regularizing and reconstructing based on the main shape contour to obtain regularized semiconductor patterns includes: Set a corner threshold and perform curvature segmentation on the simplified main shape contour. By adjusting the preset corner threshold, corners with significant changes in direction can be identified, and the contour can be divided into multiple line segments that are approximately straight. Project the segmented line segments onto the nearest horizontal or vertical direction and align them to the grid. Set an overlap threshold, extract axis-aligned rectangles from the aligned line segments, and merge adjacent rectangles that overlap more than the overlap threshold to reconstruct the regularized body of the graphic. Set a grouping tolerance threshold, group line segments that are close in position and in the same direction, calculate the average position of each group as the principal coordinate, and align all line segments in the group to this principal coordinate to obtain grouped clustering. After deduplication, a regularized semiconductor pattern is obtained.

6. The semiconductor pattern matching method considering photolithography deformation as described in claim 1, characterized in that, When calculating the similarity based on the multi-dimensional features of the extracted regularized semiconductor graphics and the original design layout, the calculation includes converting the calculated contour proximity, trajectory similarity and shape spatial distribution difference into normalized feature sub-scores with a value range of (0,1] through a negative exponential mapping function, assigning preset weights to each feature, and obtaining the final comprehensive similarity score by weighted summation.

7. A semiconductor pattern matching system considering photolithography deformation, characterized in that, include: The data preprocessing module is used to acquire the actual semiconductor pattern contour data after photolithography and the corresponding original design layout data, and to preprocess the pattern contour data. The image classification module is used to classify the preprocessed semiconductor image contour data and determine the type of the actual semiconductor image. The regular pattern matching module is used to obtain a similarity score for regular semiconductor patterns by directly comparing the geometric properties of the regular semiconductor pattern and the original design layout. The irregular shape matching module is used to simplify irregular semiconductor shapes using a recursive simplification algorithm to obtain the main shape contour of the semiconductor shape. Based on the main shape contour, regularization reconstruction is performed to obtain a regularized semiconductor shape. The similarity is calculated based on the multi-dimensional features of the extracted regularized semiconductor shape and the original design layout to obtain a similarity score. The defect detection module compares the similarity score with a preset threshold for a specific process. If the score is higher than the threshold, it is determined to be a normal process deviation; otherwise, it is determined to be a potential defect. For irregular shapes, the step of simplifying irregular semiconductor shapes using a recursive simplification algorithm includes: Calculate the perpendicular distance from any point in the contour coordinate sequence to the line connecting the first and last vertices; Find the maximum value among all vertical distances and its corresponding dividing points; judge and preset tolerance parameters If the relationship, Less than or equal to If the current segment is sufficiently simplified, only the first and last vertices of the current segment are retained. like Greater than Then Using the corresponding dividing points as boundaries, the outline is segmented and the simplification process is recursively executed; Connect all the retained feature points in their original order to form a simplified contour after filtering out edge roughness.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the program is executed by the processor, it implements the steps in the semiconductor pattern matching method that takes into account photolithography process deformation as described in any one of claims 1-6.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps in the semiconductor pattern matching method considering photolithography process deformation as described in any one of claims 1-6.

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