A multi-channel inductive load pulse driving circuit and inductive load driving method

Abstract

This invention relates to the field of MOSFET driver circuit design technology, and discloses a multi-channel inductive load pulse drive circuit, including a microcontroller unit. The control signal output by the microcontroller unit is hardware-level interlocked via a logic gate distribution network module. A high-power TVS transient circuit is located between the power supply and the H-bridge, using an ultra-fast recovery diode for unidirectional blocking and utilizing transient voltage suppression diodes to directionally discharge high-voltage flyback energy. This invention also discloses four timing modes for driving inductive loads, including a 10Hz fixed-frequency reference steady-state mode, a wideband random frequency dithering mode, a channel-interleaved delay output step polling mode, and a 7.83Hz ultra-low frequency fixed-frequency mode. This invention solves the defects of high-power transistor shoot-through burnout and thermal breakdown, effectively eliminates mechanical resonance and material fatigue caused by fixed-frequency testing, and greatly improves the safety, stability, and data accuracy of industrial extreme condition simulation.

Description

Technical Field

[0001] This invention belongs to the field of MOSFET drive circuit design technology, specifically relating to a multi-channel inductive load pulse drive circuit and an inductive load drive method. Background Technology

[0002] In applications such as industrial automation measurement and control, electromagnetic actuator testing, and specific frequency band environment simulation, test systems are typically required to continuously and frequently drive high-current inductive loads (such as pure copper electromagnetic test coils) to complete extreme condition simulation and performance evaluation of the test object.

[0003] In existing inductive load driving and testing systems, the most common implementation in the industry typically uses a microcontroller unit (MCU) as the control core. The MCU is directly connected to or connected to a high-speed gate driver chip via basic physical logic control circuitry. The gate driver chip then controls a full-bridge (H-bridge) or half-bridge topology composed of power metal-oxide-semiconductor field-effect transistors (MOSFETs). In this conventional approach, the MCU primarily outputs a fixed-frequency pulse-width modulation (PWM) wave through its internally configured timer to directly drive the inductive load for forward magnetization and reverse demagnetization. At the physical electrical connection level, existing traditional test benches typically use standard screw-locking terminals to carry the large drive current output by the system. However, the above-mentioned existing technologies have at least the following technical drawbacks under actual high-frequency continuous operation conditions:

[0004] 1. Lack of physical isolation and short-circuit protection mechanisms: The topology of MCU direct-connect driver stage is extremely fragile. Once the MCU software crashes, the program runs away, or initialization fails, it is very easy to output incorrect PWM timing, causing the upper and lower arms of the H bridge to conduct simultaneously (shoot-through short circuit), instantly burning out expensive high-power transistors.

[0005] 2. Single frequency can easily lead to material fatigue: Traditional drives usually operate at a fixed frequency or mechanical linear frequency sweep. During long-term continuous testing, the device under test or the inductive load itself is very prone to "mechanical fatigue" and "fixed frequency resonance", which will lead to distorted test data and even damage to the physical structure.

[0006] 3. Lack of redundancy in power failure flyback impact: When an inductive load switches off at high speed, it will generate a high voltage flyback impact with extremely high dE / dt. Traditional designs lack a targeted transient high-power absorption channel, which can easily cause thermal breakdown of components.

[0007] 4. Inefficient and unreliable industrial connections: Traditional screw terminals are prone to loosening under the high-frequency vibration environment of industrial test benches, and do not have the ability to quickly troubleshoot and blindly replace on-site. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a multi-channel inductive load pulse driving circuit and an inductive load driving method, which combines hardware-level logic gate dead-time locking with firmware multi-dimensional random frequency dithering algorithm to solve the H-bridge shoot-through burnout defect and eliminate test resonance.

[0009] To solve the above-mentioned technical problems, the present invention provides a multi-channel inductive load pulse driving circuit, including: a power supply module, a microcontroller unit, a high-current connection module, and at least one channel of inductive load pulse driving module. The inductive load pulse driving module includes a logic gate allocation network module, a pre-driver stage, an H-bridge power transistor array, and a high-power TVS transient circuit.

[0010] The microcontroller unit, logic gate distribution network module, pre-driver stage, and H-bridge power transistor array are electrically connected in sequence. The output of the H-bridge power transistor array is electrically connected to the terminal inductive load through a high-current connection module. The high-power TVS transient circuit is located between the external DC power bus and the H-bridge power transistor array, including an ultra-fast recovery diode D4 and a transient voltage suppression diode D3. The ultra-fast recovery diode D4 is connected in series between the external DC power bus and the H-bridge power transistor array, and the transient voltage suppression diode D3 is connected in parallel between the H-bridge power transistor array and system ground.

[0011] The external DC power supply is electrically connected to the front-end driver stage, and the external DC power supply is also electrically connected to the microcontroller unit and the logic gate distribution network module after being stepped down by the power supply module.

[0012] As an improvement to the multi-channel inductive load pulse driving circuit of the present invention:

[0013] The microcontroller unit includes an STM32 chip U1 and a crystal oscillator Y1. The crystal oscillator Y1 is connected in parallel between pins 5 and 6 of the STM32 chip U1 and grounded through capacitors C1 and C2 respectively. Pins 29 to 32 of the STM32 chip U1 are PWM signal output terminals, pins 14 to 17 are Pol signal output terminals, pins 24, 36, 48 and 9 are all electrically connected to the output terminal of the power module, pin 13 is a floating ADC pin, pin 18 is electrically connected to the first external button, and pin 19 is electrically connected to the second external button.

[0014] As a further improvement to the multi-channel inductive load pulse driving circuit of the present invention:

[0015] The logic gate allocation network module includes a logic gate chip IC9. Pin 14 of the logic gate chip IC9 is electrically connected to the output terminal of the power supply module, pin 7 is grounded, and pins 13 and 10 are electrically connected to the low-side input terminal and high-side input terminal of the pre-driver stage, respectively. Pin 1 of the logic gate chip IC9 is connected to pins 9 and 12, and pin 4 is connected to pin 11. Pins 2 and 3 of the logic gate chip IC9 are shorted together and electrically connected to the PWM signal output terminal of the STM32 chip U1. Pins 5, 6, and 8 are shorted together and electrically connected to the Pol signal output terminal of the STM32 chip U1.

[0016] The logic gate chip IC9 is a logic chip that internally contains NOR gate topology.

[0017] As a further improvement to the multi-channel inductive load pulse driving circuit of the present invention:

[0018] The front-end driver stage includes a first half-bridge driver chip IC1 and a second half-bridge driver chip IC2. Pin 3 of both the first half-bridge driver chip IC1 and the second half-bridge driver chip IC2 is electrically connected to an external DC power bus, and pin 4 is grounded. A capacitor C7 is connected in parallel between pin 8 and pin 6 of both the first half-bridge driver chip IC1 and the second half-bridge driver chip IC2. Pin 7 is the high-side output terminal, and pin 5 is the low-side output terminal, and is electrically connected to the H-bridge power transistor array.

[0019] Pin 1 of the first half-bridge driver chip IC1 is electrically connected to pin 10 of the logic gate chip IC9, and pin 2 is electrically connected to pin 13 of the logic gate chip IC9; pin 8 of the first half-bridge driver chip IC1 is electrically connected to the cathode of diode D1, and the anode of diode D1 is electrically connected to the external DC power supply bus.

[0020] Pin 1 of the second half-bridge driver chip IC2 is electrically connected to pin 13 of the logic gate chip IC9, and pin 2 is electrically connected to pin 10 of the logic gate chip IC9; pin 8 of the second half-bridge driver chip IC2 is electrically connected to the cathode of diode D2, and the anode of diode D2 is electrically connected to the external DC power supply bus input. At the same time, a capacitor C10 is connected in parallel between the anode of diode D2 and the system ground.

[0021] As a further improvement to the multi-channel inductive load pulse driving circuit of the present invention:

[0022] The H-bridge power transistor array includes power transistors Q1, Q2, Q3, and Q4. Pin 2 of power transistors Q1 and Q3 is electrically connected to a high-power TVS transient circuit. Pin 3 of power transistor Q1 is connected to pin 2 of power transistor Q2, forming the midpoint A of the first bridge arm. Pin 3 of power transistor Q3 is connected to pin 2 of power transistor Q4, forming the midpoint B of the second bridge arm. Both the midpoint A of the first bridge arm and the midpoint B of the second bridge arm are electrically connected to a high-current connection module.

[0023] Pin 1 of power transistor Q1 and pin 1 of power transistor Q2 are each electrically connected to the high-side output terminal and low-side output terminal of the first half-bridge driver chip IC1 respectively through a gate resistor; pin 1 of power transistor Q3 and pin 1 of power transistor Q4 are each electrically connected to the high-side output terminal and low-side output terminal of the second half-bridge driver chip IC2 respectively through a gate resistor.

[0024] As a further improvement to the multi-channel inductive load pulse driving circuit of the present invention:

[0025] The anode of the ultrafast recovery diode D4 in the high-power TVS transient circuit is electrically connected to the external DC power bus, and a filter capacitor C9 is connected in parallel between the anode and the system ground. The cathode of the ultrafast recovery diode D4 is electrically connected to pin 2 of power transistor Q1, pin 2 of power transistor Q3, and the cathode of transient voltage suppression diode D3, respectively. The anode of transient voltage suppression diode D3 is connected to the system ground.

[0026] This invention also provides a method for driving an inductive load using a multi-channel inductive load pulse driving circuit:

[0027] Step S1: The microcontroller reads the noise floor data of the floating ADC pin and uses the noise floor data as the initial random number seed for the true random number generation algorithm.

[0028] Step S2: The microcontroller selects one of the following modes based on the preset mode flag: reference steady-state mode, wideband random frequency dithering mode, step polling mode, and ultra-low frequency fixed frequency mode, and outputs a pulse width modulation signal and a polarity reversal signal.

[0029] Step S3: The pulse width modulation signal and the polarity reversal signal are subjected to forced physical interlocking through the logic gate distribution network module to output a safety control signal. Then, after being amplified by the pre-driver stage, the signal controls the turn-on and turn-off of the H-bridge power transistor array. The flyback energy generated by the inductive load is discharged through the transient voltage suppression diode D3.

[0030] As an improvement to the inductive load driving method of the present invention:

[0031] The specific operations of the output pulse width modulation signal and polarity reversal signal in step S2 are as follows:

[0032] (1) When the mode flag is set to Mode1, the reference steady-state mode is selected:

[0033] The microcontroller synchronously outputs pulse width modulation signals and polarity reversal signals based on fixed frequency and preset duty cycle intensity to the inductive load pulse drive modules of channels CH1 to CH4.

[0034] (2) When the mode flag is Mode2, select the wideband random dithering mode:

[0035] Within a preset time period, the microcontroller dynamically generates a random target frequency using a true random number generation algorithm, and synchronously outputs a pulse width modulation signal and a polarity reversal signal based on the random target frequency and preset duty cycle intensity to the inductive load pulse drive modules of channels CH1 to CH4.

[0036] (3) When the mode flag is Mode3, select the step polling mode:

[0037] Based on the current frequency and preset duty cycle intensity, the microcontroller outputs pulse width modulation signals and polarity reversal signals to the inductive load pulse drive modules of channels CH1 to CH4 in sequence according to the curing time cycle.

[0038] (4) When the mode flag is Mode4, the ultra-low frequency fixed-frequency mode is selected:

[0039] The microcontroller synchronously outputs pulse width modulation signals and polarity reversal signals based on a specific extremely low frequency and a preset duty cycle intensity to the inductive load pulse drive modules of channels CH1 to CH4.

[0040] As a further improvement to the inductive load driving method of the present invention:

[0041] The process of discharging the flyback energy through the transient voltage suppression diode D3 is as follows:

[0042] At the instant that power transistors Q1 to Q4 are turned off, the flyback high voltage generated by the inductive load is blocked by the unidirectional blocking effect of the ultrafast recovery diode D4, preventing it from flowing back into the external DC power supply; at the same time, when the flyback high voltage exceeds the avalanche breakdown threshold of the transient voltage suppressor diode D3, the transient voltage suppressor diode D3 turns on, forming a discharge loop from the bus node to the system ground.

[0043] The bus node is the common electrical connection terminal between the ultrafast recovery diode D4 and the H-bridge power transistor array.

[0044] As a further improvement to the inductive load driving method of the present invention:

[0045] The method for presetting the mode flag is as follows:

[0046] Based on the number of times the first button is triggered, the mode flag is cyclically switched between Mode 1, Mode 2, Mode 3 and Mode 4;

[0047] The method for presetting the duty cycle intensity is as follows:

[0048] Based on the number of times the second button is triggered, the duty cycle intensity is cycled between 20%, 40%, 60%, 80%, and 100%.

[0049] The fixed frequency is 10Hz;

[0050] The range of the random target frequency is set to 1Hz to 50Hz;

[0051] The preset time period is set to 3 to 5 minutes;

[0052] The curing time period is set to 800 milliseconds;

[0053] The specific extremely low frequency is set to 7.83 Hz.

[0054] The beneficial effects of this invention are mainly reflected in:

[0055] 1. This invention adds a logic gate allocation network module between the microcontroller unit and the front-end driver stage, performing hardware-level Boolean logic interlocking on pulse width modulation signals and polarity reversal signals to ensure that the upper and lower transistors of the same bridge arm will not be at a high level simultaneously under any software abnormality. This fundamentally eliminates the H-bridge shoot-through / short-circuit defect caused by program crashes or system freezes in the main control chip, greatly improving the safety and reliability of high-power transistors.

[0056] 2. The wideband random frequency dithering control method of this invention enables the system to continuously output dynamically changing frequency pulses to the inductive load, completely interrupting the inherent physical resonance state of the device under test under long-term testing. This wideband random frequency dithering mode effectively avoids material mechanical fatigue caused by a single fixed frequency, significantly improving the data authenticity of extreme condition simulation tests.

[0057] 3. This invention configures a transient circuit at the input of the H-bridge power transistor array, consisting of an ultrafast recovery diode and a high-power transient voltage suppressor (TVS) diode. The ultrafast recovery diode is responsible for unidirectionally blocking the high voltage generated during power-off from flowing back to the front-end bus, while the TVS diode constructs a low-impedance loop to instantaneously absorb the flyback energy during polarity reversal. This physical redundancy design effectively suppresses the transient impact of extremely high voltage change rates on the system, completely eliminating thermal breakdown damage to the underlying power components.

[0058] 4. This invention employs a foolproof magnetic spring pin interface supporting 5A transient high current as the physical connection medium between the output of the H-bridge power transistor array and the terminal inductive load. This quick-release architecture has excellent vibration resistance, effectively overcoming the problem of traditional screw terminals easily loosening under high-frequency vibration conditions in industrial applications. Attached Figure Description

[0059] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0060] Figure 1 This is a schematic diagram of a multi-channel inductive load pulse drive circuit;

[0061] Figure 2 This is a circuit diagram of the power module;

[0062] Figure 3 This is a circuit diagram of the microcontroller unit;

[0063] Figure 4 This is a circuit diagram of an inductive load pulse drive module.

[0064] Figure 5 This is a schematic flowchart of the inductive load driving method of the present invention;

[0065] Figure 6 The waveform of the PWM signal with a nominal output frequency of 31Hz in wideband random dithering mode is shown in the figure.

[0066] Figure 7 This is a waveform diagram of the PWM signal with a nominal output frequency of 18Hz in wideband random dithering mode according to the present invention;

[0067] Figure 8 The waveform of the PWM signal with a nominal output frequency of 49Hz in the wideband random dithering mode of this invention is shown.

[0068] Figure 9 This is a waveform diagram of the PWM signal with a nominal output frequency of 19Hz in wideband random dithering mode according to the present invention;

[0069] Figure 10 This is a waveform diagram of the PWM signal with a nominal output frequency of 10Hz in wideband random frequency dithering mode according to the present invention;

[0070] Figure 11 This is a continuous impulse waveform diagram of the transient circuit terminal voltage of a high-power TVS under high dE / dt flyback operating conditions with a driving frequency of 1Hz.

[0071] Figure 12This is a continuous impulse waveform diagram of the transient circuit terminal voltage of a high-power TVS under high dE / dt flyback operating conditions with a driving frequency of 10Hz.

[0072] Figure 13 This is a continuous impulse waveform diagram of the transient circuit terminal voltage of a high-power TVS under high dE / dt flyback operating conditions with a driving frequency of 25Hz.

[0073] Figure 14 This is a continuous impulse waveform diagram of the transient circuit terminal voltage of a high-power TVS under high dE / dt flyback operating conditions with a driving frequency of 50Hz.

[0074] Figure 15 for Figure 14 A magnified view of a portion of the image. Detailed Implementation

[0075] The present invention will be further described below with reference to specific embodiments, but the scope of protection of the present invention is not limited thereto:

[0076] Example 1: A multi-channel inductive load pulse driving circuit and inductive load driving method, employing a combination of hardware-level logic gate dead-time locking and firmware multi-dimensional random frequency dithering algorithm, completely solves the fatal defect of H-bridge shoot-through burnout from the bottom layer and eliminates test resonance. It also provides a physical quick-release architecture supporting 5A-level high-current transient pulses, achieving ultimate industrial-grade safety and stability.

[0077] Multi-channel inductive load pulse drive circuit, such as Figure 1-4 As shown, it mainly includes a power supply module, a microcontroller unit (MCU), a four-channel inductive load pulse drive module, and a high-current connection module.

[0078] The power module includes a power chip PS1 (UA78M33CDCYRG3), filter capacitors C3 (2200uF), C5 (100nF), C6 (2200uF), and C26 (2.2uF), such as... Figure 2As shown. Pin 1 (INPUT) of the power supply chip PS1 is electrically connected to the external DC power bus to input a 12V external DC power supply. Pin 1 (INPUT) is also connected to system ground (GND) through capacitor C26 (2.2uF). Pin 3 (OUTPUT) serves as the 3.3V output terminal to output a 3.3V DC power supply, and pin 4 (COMMON_2) is connected to system ground (GND). A filter capacitor C6 (2200uF) is connected in parallel between the 12V input terminal and system ground (GND); filter capacitors C3 (2200uF) and C5 (2.2uF) are connected in parallel between the 3.3V output terminal and system ground (GND). The power supply pins of the microcontroller unit U1 and the logic gate chip IC9 are connected to the 3.3V output terminal respectively.

[0079] The external 12V DC input serves two purposes: firstly, as a high-voltage power bus directly powering the subsequent pre-driver stage and high-power TVS transient circuit; and secondly, by stepping down to 3.3V through the power module, it provides digital logic power to the microcontroller unit and logic gate distribution network module.

[0080] The microcontroller unit (MCU) serves as the core control of the entire system, generating and outputting four sets of pulse width modulation signals (PWM1, PWM2, PWM3, and PWM4) and polarity reversal signals (Pol1, Pol2, Pol3, and Pol4), corresponding to the control signals output through four channels (CH1 ~ CH4). The MCU includes the main control chip, crystal oscillator Y1 (selected as ECS-80-12-30Q-D5-TR), and capacitors C1 and C2 (both 20pF), as follows... Figure 3As shown. The main control chip includes, but is not limited to, STM32 series microcontrollers, digital signal processors (DSPs), industrial-grade host computers, or Raspberry Pi devices that directly output low-level timing information via a bus. In this embodiment, an STM32 chip U1 (using the STM32F103C8T6 chip) is preferred. A crystal oscillator Y1 is connected in parallel between pin 5 (PD0) and pin 6 (PD1) of the STM32 chip U1, and the two pins are grounded through capacitors C1 and C2 respectively. The PWM signal output terminal (pins 29 (PA8) ~ 32 (PA11)) of the STM32 chip U1 outputs four pulse width modulation signals (PWM1, PWM2, PWM3, and PWM4), and the Pol signal output terminal (pins 14 (PA4) ~ 17 (PA7)) outputs four polarity inversion signals (Pol1, Pol2, Pol3, and Pol4), which are used as control signals input to the four channels (CH1-CH4). Pins 24 (VDD), 36 (VDD), 48 (VDD), and 9 (VDDA) of the STM32 chip U1 are connected to the 3.3V output of the power module, while pins 23 (VSS) and 8 (VSSA) are grounded. Pin 7 (NRST) of the STM32 chip U1 serves as the reset pin for inputting the Reset signal, and pins 44 (BOOT0) and 20 (PB2) serve as boot pins for inputting the Boot 0 and Boot 1 signals, respectively. Pin 13 (PA3) of the STM32 chip U1 serves as a floating ADC pin for inputting the Floating ADC signal. Pin 18 (PB0) of the STM32 chip U1 is electrically connected to the first external button (Button 1), and pin 19 (PB1) is electrically connected to the second external button (Button 2). The STM32 chip U1 cycles through the active mode flag between Mode 1 and Mode 4 based on the interrupt signal generated by the first button (Button 1), and cycles through the current duty cycle intensity between 20%, 40%, 60%, 80%, and 100% based on the interrupt signal generated by the second button (Button 2).

[0081] Four inductive load pulse drive modules are located after the microcontroller unit, meaning one inductive load pulse drive module is provided for each channel. Each inductive load pulse drive module includes a logic gate distribution network, H-Bridge Drivers, an H-bridge power transistor array, and a high-power TVS transient circuit. The logic gate distribution network module uses Boolean logic operations (such as NOR logic) to force physical interlocking of the input control signals, ensuring that the control signals of the upper and lower transistors on the same bridge arm will not be at a high level simultaneously under any abnormal software state. The safety control signal, after logic interlocking, outputs a large current pulse to the terminal inductive load through the H-bridge driver and H-bridge power transistor array. During load polarity reversal, the high-power TVS transient circuit absorbs the flyback energy generated by the inductive load. The circuit of the inductive load pulse drive module is as follows: Figure 4 As shown, specifically:

[0082] The logic gate allocation network module receives signals output from the microcontroller unit and performs polarity inversion logic processing to prevent bridge arm shoot-through. In this embodiment, the 74VHC02FT chip is preferentially used as the logic gate chip IC9. For the logic gate allocation network module of each channel, pin 14 (VCC) of the logic gate chip IC9 is electrically connected to the 3.3V output terminal of the power supply module, and pin 7 (GND) is grounded. The logic output pins 13 (4Y) and 10 (3Y) of the logic gate chip IC9 are used as the input signals of the low-side input terminal and the high-side input terminal of the pre-amplifier driver stage, respectively. Pin 1 (1Y) of the logic gate chip IC9 is electrically connected to pin 9 (3B) and pin 12 (4B), and pin 4 (2Y) is electrically connected to pin 11 (4A).

[0083] Pins 2 (1A) and 3 (1B) of logic gate chip IC9 are shorted together and electrically connected to the PWM signal output terminal of the corresponding channel of STM32 chip U1. Pins 5 (2A), 6 (2B), and 8 (3A) of logic gate chip IC9 are shorted together and electrically connected to the Pol signal output terminal of STM32 chip U1. Specifically:

[0084] For the logic gate IC9 of channel CH1, pins 2 (1A) and 3 (1B) are electrically connected to pin 29 (PA8) of STM32 chip U1 for inputting pulse width modulation signal (PWM1), and pins 5 (2A), 6 (2B) and 8 (3A) of the logic gate IC9 of channel CH1 are electrically connected to pin 14 (PA4) of STM32 chip U1 for inputting polarity reversal signal (Pol1).

[0085] For channel CH2, pins 2 (1A) and 3 (1B) of the logic gate IC9 are electrically connected to pin 30 (PA9) of the STM32 chip U1 for inputting pulse width modulation signal (PWM2). Pins 5 (2A), 6 (2B) and 8 (3A) of the logic gate IC9 of channel CH2 are electrically connected to pin 15 (PA5) of the STM32 chip U1 for inputting polarity reversal signal (Pol2).

[0086] For the logic gate IC9 of channel CH3, pins 2 (1A) and 3 (1B) are electrically connected to pin 31 (PA10) of STM32 chip U1 for inputting pulse width modulation signal (PWM3), and pins 5 (2A), 6 (2B) and 8 (3A) of the logic gate IC9 of channel CH3 are electrically connected to pin 16 (PA6) of STM32 chip U1 for inputting polarity reversal signal (Pol3).

[0087] For the logic gate IC9 of channel CH4, pins 2 (1A) and 3 (1B) are electrically connected to pin 32 (PA11) of STM32 chip U1 for inputting pulse width modulation signal (PWM4), and pins 5 (2A), 6 (2B) and 8 (3A) of the logic gate IC9 of channel CH4 are electrically connected to pin 17 (PA7) of STM32 chip U1 for inputting polarity reversal signal (Pol4).

[0088] In a conventional full-bridge circuit, if the firmware in the microcontroller unit crashes or malfunctions and simultaneously outputs two high-level signals, the H-bridge will instantly short-circuit and burn out. Current conventional improvements include using optocouplers for physical isolation. However, in this invention, the logic gate chip IC9 is a logic chip with an internal NOR gate topology. The Pol signals input to pins 5 (2A) and 6 (2B) of the logic gate chip IC9, and the PWM signals input to pins 2 (1A) and 3 (1B), are clamped by the hardware gate circuits within the logic gate chip IC9. This ensures that the outputs of pins 13 (4Y) and 10 (3Y) are always mutually exclusive, thus completely locking out the possibility of simultaneous conduction of the upper and lower transistors on the same half-bridge at the physical level. Simultaneously, the logic gate chip IC9 decodes and compresses the full-bridge, which originally required four independent pins for MCU control, into control with only two pins (one PWM + one Pol). This combination of anti-passthrough protection and port compression decoding cannot be achieved simply by replacing isolation devices. The interlocking mechanism of the logic gate chip IC9 in this invention does not depend on the instruction cycle or register state of the microcontroller unit, but is forcibly determined by the logic bottom line of the internal physical transistor topology of the NOR gate (74VHC02FT). The technical effect is that it not only provides a conventional switching dead time, but also provides low-level short-circuit redundancy with no delay under extreme industrial conditions such as hardware-level crashes and pin level loss at the main control level.

[0089] The pre-driver stage receives the output safety control signal from the logic gate allocation network module, amplifies the voltage level through an internal level conversion module, and outputs a high-speed gate drive signal. In this embodiment, the pre-driver stage includes a first half-bridge driver chip IC1 and a second half-bridge driver chip, preferably using an independent half-bridge driver chip UCC27712DR as the first half-bridge driver chip IC1 and the second half-bridge driver chip IC2. Pin 3 (VDD) of the first half-bridge driver chip IC1 is connected to the 12V input, pin 4 (COM) is grounded, and pin 8 (HB) is connected to the cathode of diode D1 (BYG20J). The anode of diode D1 is connected to the external +12V DC bus input. A capacitor C7 (2.2uF) is connected in parallel between pin 8 (HB) and pin 6 (HS) of the first half-bridge driver chip IC1. Pin 1 (LI) of the low-side input terminal of the first half-bridge driver chip IC1 is connected to pin 10 (3Y) of the logic gate chip IC9, and pin 2 (HI) of the high-side input terminal is connected to pin 13 (4Y) of the logic gate chip IC9. Pin 7 (HO) of the first half-bridge driver chip IC1 is the high-side output terminal, and pin 5 (LO) is the low-side output terminal, both of which are connected to the H-bridge power transistor array.

[0090] Pin 3 (VDD) of the second half-bridge driver chip IC2 is connected to the 12V input, pin 4 (COM) is grounded, and pin 8 is connected to the cathode of diode D2 (BYG20J). The anode of diode D2 is connected to the external +12V DC bus input, and a capacitor C10 (2.2uF) is connected in parallel between the anode of diode D2 and system ground (GND). A capacitor C8 (2.2uF) is connected in parallel between pin 8 (HB) and pin 6 (HS) of the second half-bridge driver chip IC2. Pin 1 (LI) of the low-side input of the second half-bridge driver chip IC2 is connected to pin 13 (4Y) of the logic gate chip IC9, and pin 2 (HI) of the high-side input is connected to pin 10 (3Y) of the logic gate chip IC9. Pin 7 (HO) of the second half-bridge driver chip IC2 is the high-side output, and pin 5 (LO) is the low-side output, both of which are connected to the H-bridge power transistor array.

[0091] The H-bridge power transistor array employs a full-bridge driver circuit driven by four MOSFETs to receive control signals from the pre-driver stage. Through the full-bridge (H-Bridge) topology, it chops and inverts the input bus DC voltage, ultimately outputting a high-current pulse to drive the terminal test inductive load. In this embodiment, IPB60R060P7ATMA1 type N-channel power MOSFETs are preferably used as power transistors Q1-Q4.

[0092] Pin 2 (drain) of power transistors Q1 and Q3 are electrically connected to a high-power TVS transient circuit for input protection of 12V. Pin 3 (source) of power transistor Q1 is connected to pin 2 (drain) of power transistor Q2, forming the output at midpoint A of the first bridge arm; pin 3 (source) of power transistor Q3 is connected to pin 2 (drain) of power transistor Q4, forming the midpoint B of the second bridge arm. Midpoints A and B of the first and second bridge arms together serve as the physical output terminals of this channel, electrically connected to the high-current connection module as the connection interface for terminating inductive loads. Pin 3 (source) of power transistors Q2 and Q4 are electrically connected to system ground (GND).

[0093] The gate of power transistor Q1 is electrically connected to the high-side output terminal (pin 7 (HO)) of the first half-bridge driver chip IC1 through the gate resistor R1 (5.1Ω), and the gate of power transistor Q2 is connected to the low-side output terminal (pin 5 (LO)) of the first half-bridge driver chip IC1 through the gate resistor R2 (5.1Ω).

[0094] Pin 1 (gate) of power transistor Q3 is electrically connected to the high-side output terminal (pin 7 (HO)) of the second half-bridge driver chip IC2 through gate resistor R3 (5.1Ω), and pin 1 (gate) of power transistor Q4 is electrically connected to the low-side output terminal (pin 5 (LO)) of the second half-bridge driver chip IC2 through gate resistor R4 (5.1Ω).

[0095] A high-power TVS transient circuit is located between the external DC power bus and the H-bridge power transistor array bus. It includes an ultra-fast recovery diode D4 (STTH5R06B) connected in series with the H-bridge power transistor array and a transient voltage suppressor diode D3 (TVS, preferably SMCJ150A) connected in parallel with the H-bridge power transistor array. This blocks the high-voltage flyback power supply and absorbs the high-voltage flyback potential generated during polarity switching of the inductive load. In this embodiment, the external +12V DC power bus is not directly connected to the H-bridge power transistor array, but is electrically connected to the anode of the ultra-fast recovery diode D4 (STTH5R06B) (i.e., pins 1 (NC) and 3 (A)). A filter capacitor C9 (2.2uF) is connected in parallel between the anode of the ultra-fast recovery diode D4 (STTH5R06B) and system ground (GND). The cathode (pin 2) of the ultrafast recovery diode D4 is connected to pin 2 (drain) of power transistor Q1 and pin 2 (drain) of power transistor Q3, respectively. At this connection, the cathode of the ultrafast recovery diode D4 and the common electrical connection terminal between the H-bridge power transistor array form a protected bus node (i.e., the H-bridge input terminal), used to output protected DC 12V to the subsequent stage. The cathode (pin 2) of the transient voltage suppressor diode D3 is connected in parallel at the bus node, that is, electrically connected to the cathode (pin 2) of the ultrafast recovery diode D4. The anode (pin 1) of the transient voltage suppressor diode D3 is connected to system ground (GND), thus constructing a directional discharge loop from the bus node to system ground (GND). The flyback high voltage of the inductive load at the moment of power failure will be blocked by the ultrafast recovery diode D4 and directionally absorbed by the transient voltage suppressor diode D3.

[0096] The output terminals of the four channels of the inductive load pulse drive module (midpoint A of the first bridge arm and midpoint B of the second bridge arm) are all electrically connected to the high current connection module. In this embodiment, it is preferred to use a foolproof magnetic pogo pin interface that can withstand 5A transient current for electrical connection. Alternatively, an industrial aviation plug or a quick push-pull self-locking connector can be used.

[0097] A method for driving an inductive load using a multi-channel inductive load pulse driving circuit according to the present invention, such as... Figure 5 As shown, the specific process is as follows:

[0098] Step 1: System initialization and random number generation:

[0099] After the system is powered on or reset, the microcontroller unit directly reads the noise floor data of the preset floating analog-to-digital converter (ADC) pin. This noise floor data is used as the initial random number seed (Seed RNG) for the true random number generation algorithm.

[0100] Step 2, Timer Configuration:

[0101] The microcontroller initializes the internal timer (TIM1) and starts the default output state of the output channels of all inductive load pulse drive modules. Initially, timing mode 1 (reference steady state mode) is the default startup mode. After starting timing mode 1, the main loop is entered.

[0102] Step 3, Main loop listener:

[0103] The system enters the core main loop, and the microcontroller unit monitors the input of the first button (Button 1) and the second button (Button 2) in real time:

[0104] (1) Timing mode listening: Listen to the trigger signal of the first button (Button 1), and update the active mode flag bit (Mode 1 - Mode 4) in a loop between timing mode 1 and timing mode 4 according to the number of triggers.

[0105] (2) Duty cycle monitoring: Monitor the trigger signal of the second button (Button 2), and cycle through five preset duty cycle intensities (20%, 40%, 60%, 80%, 100%) according to the number of triggers, and update and lock it to the current duty cycle intensity.

[0106] Step 4, Dynamic Timing Trigger:

[0107] Based on the monitored mode flag and duty cycle strength, the microcontroller executes one of the following four timing modes to drive the inductive load:

[0108] (1) When the mode flag is Mode1, timing mode 1 (reference steady-state mode) is selected:

[0109] The microcontroller's internal timer's automatic reload register (ARR) is overwritten to a fixed frequency of 10Hz. The current preset duty cycle intensity is extracted and overwritten to the capture / compare register CCRx (where x represents channel CH1, CH2, CH3, or CH4). Then, the microcontroller synchronously outputs pulse width modulation signals (PWM1, PWM2, PWM3, and PWM4) with fixed frequency and preset duty cycle intensity, as well as polarity reversal signals (Pol1, Pol2, Pol3, and Pol4) to all inductive load pulse drive modules to establish a benchmark test condition.

[0110] In timing mode 1, unless interrupted by the first button (Button 1), the microcontroller is in an infinite loop output state, and the system continues to operate at a locked fixed frequency.

[0111] (2) When the mode flag is Mode2, select timing mode 2 (wideband random jitter mode):

[0112] The current preset duty cycle intensity is extracted and overwritten to the capture / compare register CCRx. Using the initial random number seed (Seed RNG) generated in step 1, the microcontroller dynamically and regenerates a random target frequency within the frequency range of 1Hz to 50Hz every preset time period of 3 to 5 minutes using a true random number generation algorithm. The microcontroller overwrites the newly generated random target frequency in the current period into the automatic reload register (ARR) of the internal timer. For example, during the random generation period (T=4 minutes), the ARR is continuously output with a fixed random number (e.g., F=32Hz). After these 4 minutes, the microcontroller rereads the ADC noise floor to generate a new random frequency.

[0113] Then, pulse width modulation signals (PWM1, PWM2, PWM3 and PWM4) with random target frequencies and preset duty cycle strengths, as well as polarity reversal signals (Pol1, Pol2, Pol3 and Pol4), are synchronously output to all inductive load pulse drive modules.

[0114] In this mode, the present invention utilizes the noise floor of the floating analog-to-digital converter pin to generate a true random number seed, dynamically generates a wideband random pulse signal within a frequency range of 1Hz to 50Hz according to a preset time period, and overwrites the random target frequency of the internal timer. This multi-dimensional random frequency dithering algorithm enables the system to continuously output dynamically changing frequency pulses to the inductive load, completely breaking the inherent physical resonance state of the device under test under long-term testing, aiming to avoid high-power switching losses caused by frequent frequency switching.

[0115] (3) When the mode flag is Mode3, select timing mode 3 (step polling mode):

[0116] The microcontroller maintains the current frequency and preset duty cycle intensity (i.e., keeps the capture / compare register CCRx and the auto-reload register ARR unchanged) and drives the four channels using an interleaved delay start strategy: First, the microcontroller outputs a pulse width modulation signal (PWM1) and a polarity reversal signal (Pol1) to the inductive load pulse drive module of channel CH1. Then, the microcontroller executes an 800-millisecond (ms) delay, and while maintaining the operation of the already started channel, outputs a pulse width modulation signal (PWM2) and a polarity reversal signal (Pol2) to the inductive load pulse drive module of channel CH2, and so on. The signal output of subsequent channels CH3 and CH4 is started sequentially every 800 ms until all four channels are running simultaneously in a superimposed state. Ultimately, by setting a fixed 800-millisecond (ms) start time difference between adjacent channels, the microcontroller creates a staggered start sequence for multiple inductive loads on the macroscopic time axis. This staggered delayed start strategy effectively avoids the superposition of external 12V DC bus surge current and transient voltage drop caused by the simultaneous power-on of high-current inductive loads on four channels, thereby improving the system power supply stability.

[0117] In both timing modes 2 and 3, the interrupt switching mode can be triggered by pressing the first button (Button 1).

[0118] (4) When the mode flag is Mode4, timing mode 4 (ultra-low frequency fixed frequency mode) is selected:

[0119] The microcontroller locks a specific extremely low frequency (specifically 7.83Hz) and directly overwrites it into the automatic reload register (ARR) of the internal timer. Based on the current preset duty cycle strength setting (i.e., the automatic reload register ARR remains unchanged), it synchronously outputs fixed-period pulse width modulation signals (PWM1, PWM2, PWM3, and PWM4) and polarity reversal signals (Pol1, Pol2, Pol3, and Pol4) to all inductive load pulse drive modules to perform specific simulation tests on environmental immunity.

[0120] In timing mode 4, unless interrupted by the first button (Button 1), the microcontroller is in an infinite loop output state, and the system continues to operate at a specific extremely low frequency.

[0121] Step 4: Hardware Cascade Drive and High-Voltage Flyback Protection:

[0122] (1) After the pulse width modulation signals (PWM1, PWM2, PWM3 and PWM4) and polarity reversal signals (Pol1, Pol2, Pol3 and Pol4) enter an inductive load pulse drive module, the signals are first subjected to forced physical interlocking by the logic gate distribution network module and then the safety control signal is output. Then, the front drive stage amplifies the safety control signal through the internal level conversion module and applies it to the gate of the power transistors Q1 to Q4 in the H-bridge power transistor array, controlling the corresponding power transistors to turn on and off at the nanosecond level, thereby completing the chopping and inverting control of the bus DC voltage;

[0123] (2) The external 12V DC bus first flows through the ultra-fast recovery diode D4 in the high-power TVS transient circuit to establish a protected internal power supply bus node. During the forward drive cycle, the bus current flows in from the drain of the power transistor Q1 and out from the source, positively injecting into the terminal inductive load, and then flows in from the drain of the power transistor Q4 and out from the source, finally flowing into the system ground (GND) to complete the positive magnetization energy storage of the inductive load; during the reverse drive cycle, the bus current alternately flows along the path of the power transistor Q3, the inductive load (reverse), the power transistor Q2 and the system ground to complete the reverse magnetization.

[0124] (3) During the polarity reversal dead zone of the inductive load or at the moment of power failure, all four power transistors Q1-Q4 of the H-bridge are turned off instantaneously. Since the inductor current inside the inductive load cannot change abruptly, a flyback high voltage spike with an extremely high voltage change rate is instantaneously generated across the inductive load. When this flyback high voltage attempts to flow back to the power supply, it is blocked by the unidirectional physical blocking effect of the ultra-fast recovery diode D4 and cannot flow back to the external 12V DC bus. At the same time, the flyback high voltage quickly exceeds the avalanche breakdown threshold of the unidirectional transient voltage suppression diode D3 connected in parallel at the bus node, causing the unidirectional transient voltage suppression diode D3 to instantly enter the conduction state, constructing a high-speed discharge closed-loop circuit from the bus node system ground (GND), thereby strictly clamping the voltage across the H-bridge bus within the safe withstand voltage range of the power transistors Q1-Q4, completely eliminating the risk of component thermal breakdown damage caused by transient high voltage backflow.

[0125] experiment:

[0126] I. Experimental Objective

[0127] The experiment was conducted to verify the electromagnetic drive stability of the system under extreme random frequency dithering conditions, and the effectiveness of the high-power TVS transient circuit in absorbing flyback energy and providing physical explosion protection under high dE / dt flyback conditions.

[0128] II. Experiment 1: Verification of Timing Pattern 2 (Wideband Random Dithering Pattern)

[0129] The noise floor of the floating ADC pin (PA3) of the STM32 chip U1 during operation is collected as a random number seed to trigger the generation of a PWM drive signal. A logic analyzer is used to capture the continuous output waveform, as shown in the attached figure. Figures 6 to 10 The duty cycle of the PWM output signal is strictly locked at a preset 50% (measured value 49.95% - 49.99%). However, its output frequency exhibits highly discrete random jumps within a very short time. The attached figure clearly records the instantaneous frequency of the continuous jumps: 31Hz. Figure 6 ), 18Hz Figure 7 ), 49Hz Figure 8 ), 19Hz Figure 9 ), 10Hz Figure 10 ).

[0130] Experiments have shown that the firmware random frequency dithering algorithm of this system can successfully break the fixed mechanical resonance frequency, achieving the expected anti-material fatigue effect.

[0131] III. Experiment 2: Physical clamping verification of high dE / dt excitation spikes

[0132] The industry-standard SPICE simulation environment was used. A regulated 12V DC voltage was applied to the system input. Extreme drive conditions were set: a 2.0mH inductive load was driven by forcing the MOSFET to turn on and off rapidly using an ideal square wave (simulating extremely high dE / dt). Simultaneously, an SMCJ150A TVS transient suppression diode was connected in parallel at the H-bridge input (i.e., the system bus node).

[0133] Under continuous high-frequency impacts at different frequencies (1Hz, 10Hz, 25Hz, 50Hz) (e.g.) Figures 11 to 15 The system maintains a stable output pulse train throughout. Most importantly, as clearly observed in the microsecond-level magnified field of view in Figure 15, when the MOSFET is momentarily turned off, the fatal flyback voltage spike of several hundred volts generated by the inductive load is successfully intercepted by the TVS clamping network at approximately 176V-180V. A classic "flat-top clamping effect" is formed at the top of the waveform, the voltage stops surging and safely falls back after energy dissipation.

[0134] Simulation results strongly demonstrate that even under high-intensity back shocks up to 50Hz, the high-power TVS transient circuit designed in this invention can suppress the fatal flyback high voltage below the safety threshold, completely eliminating the risk of power component breakdown, and the physical explosion-proof redundancy design is extremely reliable.

[0135] Finally, it should be noted that the above examples are merely some specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments and many variations are possible. All variations that can be directly derived or conceived by those skilled in the art from the disclosure of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A multi-channel inductive load pulse driving circuit, characterized in that: It includes a power supply module, a microcontroller unit, a high-current connection module, and an inductive load pulse drive module with at least one channel. The inductive load pulse drive module includes a logic gate distribution network module, a pre-driver stage, an H-bridge power transistor array, and a high-power TVS transient circuit. The microcontroller unit, logic gate distribution network module, pre-driver stage, and H-bridge power transistor array are electrically connected in sequence. The output of the H-bridge power transistor array is electrically connected to the terminal inductive load through a high-current connection module. The high-power TVS transient circuit is located between the external DC power bus and the H-bridge power transistor array, including an ultra-fast recovery diode D4 and a transient voltage suppression diode D3. The ultra-fast recovery diode D4 is connected in series between the external DC power bus and the H-bridge power transistor array, and the transient voltage suppression diode D3 is connected in parallel between the H-bridge power transistor array and system ground. The external DC power supply is electrically connected to the front-end driver stage, and the external DC power supply is also electrically connected to the microcontroller unit and the logic gate distribution network module after being stepped down by the power supply module.

2. The multi-channel inductive load pulse driving circuit according to claim 1, characterized in that: The microcontroller unit includes an STM32 chip U1 and a crystal oscillator Y1. The crystal oscillator Y1 is connected in parallel between pins 5 and 6 of the STM32 chip U1 and grounded through capacitors C1 and C2 respectively. Pins 29 to 32 of the STM32 chip U1 are PWM signal output terminals, pins 14 to 17 are Pol signal output terminals, pins 24, 36, 48 and 9 are all electrically connected to the output terminal of the power module, pin 13 is a floating ADC pin, pin 18 is electrically connected to the first external button, and pin 19 is electrically connected to the second external button.

3. The multi-channel inductive load pulse driving circuit according to claim 2, characterized in that: The logic gate allocation network module includes a logic gate chip IC9. Pin 14 of the logic gate chip IC9 is electrically connected to the output terminal of the power supply module, pin 7 is grounded, and pins 13 and 10 are electrically connected to the low-side input terminal and high-side input terminal of the pre-driver stage, respectively. Pin 1 of the logic gate chip IC9 is connected to pins 9 and 12, and pin 4 is connected to pin 11. Pins 2 and 3 of the logic gate chip IC9 are shorted together and electrically connected to the PWM signal output terminal of the STM32 chip U1. Pins 5, 6, and 8 are shorted together and electrically connected to the Pol signal output terminal of the STM32 chip U1. The logic gate chip IC9 is a logic chip that internally contains NOR gate topology.

4. The multi-channel inductive load pulse drive circuit according to claim 3, characterized in that: The front-end driver stage includes a first half-bridge driver chip IC1 and a second half-bridge driver chip IC2. Pin 3 of both the first half-bridge driver chip IC1 and the second half-bridge driver chip IC2 is electrically connected to an external DC power bus, and pin 4 is grounded. A capacitor C7 is connected in parallel between pin 8 and pin 6 of both the first half-bridge driver chip IC1 and the second half-bridge driver chip IC2. Pin 7 is the high-side output terminal, and pin 5 is the low-side output terminal, and is electrically connected to the H-bridge power transistor array. Pin 1 of the first half-bridge driver chip IC1 is electrically connected to pin 10 of the logic gate chip IC9, and pin 2 is electrically connected to pin 13 of the logic gate chip IC9; pin 8 of the first half-bridge driver chip IC1 is electrically connected to the cathode of diode D1, and the anode of diode D1 is electrically connected to the external DC power supply bus. Pin 1 of the second half-bridge driver chip IC2 is electrically connected to pin 13 of the logic gate chip IC9, and pin 2 is electrically connected to pin 10 of the logic gate chip IC9; pin 8 of the second half-bridge driver chip IC2 is electrically connected to the cathode of diode D2, and the anode of diode D2 is electrically connected to the external DC power supply bus input. At the same time, a capacitor C10 is connected in parallel between the anode of diode D2 and the system ground.

5. A multi-channel inductive load pulse drive circuit according to claim 4, characterized in that: The H-bridge power transistor array includes power transistors Q1, Q2, Q3, and Q4. Pin 2 of power transistors Q1 and Q3 is electrically connected to a high-power TVS transient circuit. Pin 3 of power transistor Q1 is connected to pin 2 of power transistor Q2, forming the midpoint A of the first bridge arm. Pin 3 of power transistor Q3 is connected to pin 2 of power transistor Q4, forming the midpoint B of the second bridge arm. Both the midpoint A of the first bridge arm and the midpoint B of the second bridge arm are electrically connected to a high-current connection module. Pin 1 of power transistor Q1 and pin 1 of power transistor Q2 are each electrically connected to the high-side output terminal and low-side output terminal of the first half-bridge driver chip IC1 respectively through a gate resistor; pin 1 of power transistor Q3 and pin 1 of power transistor Q4 are each electrically connected to the high-side output terminal and low-side output terminal of the second half-bridge driver chip IC2 respectively through a gate resistor.

6. The multi-channel inductive load pulse driving circuit according to claim 5, characterized in that: The anode of the ultrafast recovery diode D4 in the high-power TVS transient circuit is electrically connected to the external DC power bus, and a filter capacitor C9 is connected in parallel between the anode and the system ground. The cathode of the ultrafast recovery diode D4 is electrically connected to pin 2 of power transistor Q1, pin 2 of power transistor Q3, and the cathode of transient voltage suppression diode D3, respectively. The anode of transient voltage suppression diode D3 is connected to the system ground.

7. A method for driving an inductive load using a multi-channel inductive load pulse driving circuit as described in any one of claims 1-6, characterized in that: Step S1: The microcontroller reads the noise floor data of the floating ADC pin and uses the noise floor data as the initial random number seed for the true random number generation algorithm. Step S2: The microcontroller selects one of the following modes based on the preset mode flag: reference steady-state mode, wideband random frequency dithering mode, step polling mode, and ultra-low frequency fixed frequency mode, and outputs a pulse width modulation signal and a polarity reversal signal. Step S3: The pulse width modulation signal and the polarity reversal signal are subjected to forced physical interlocking through the logic gate distribution network module to output a safety control signal. Then, after being amplified by the pre-driver stage, the signal controls the turn-on and turn-off of the H-bridge power transistor array. The flyback energy generated by the inductive load is discharged through the transient voltage suppression diode D3.

8. The method for driving an inductive load according to claim 7, characterized in that: The specific operations of the output pulse width modulation signal and polarity reversal signal in step S2 are as follows: (1) When the mode flag is set to Mode1, the reference steady-state mode is selected: The microcontroller synchronously outputs pulse width modulation signals and polarity reversal signals based on fixed frequency and preset duty cycle intensity to the inductive load pulse drive modules of channels CH1 to CH4. (2) When the mode flag is Mode2, select the wideband random dithering mode: Within a preset time period, the microcontroller dynamically generates a random target frequency using a true random number generation algorithm, and synchronously outputs a pulse width modulation signal and a polarity reversal signal based on the random target frequency and preset duty cycle intensity to the inductive load pulse drive modules of channels CH1 to CH4. (3) When the mode flag is Mode3, select the step polling mode: Based on the current frequency and preset duty cycle intensity, the microcontroller outputs pulse width modulation signals and polarity reversal signals to the inductive load pulse drive modules of channels CH1 to CH4 in sequence according to the curing time cycle. (4) When the mode flag is Mode4, the ultra-low frequency fixed-frequency mode is selected: The microcontroller synchronously outputs pulse width modulation signals and polarity reversal signals based on a specific extremely low frequency and a preset duty cycle intensity to the inductive load pulse drive modules of channels CH1 to CH4.

9. The method for driving an inductive load according to claim 8, characterized in that: The process of discharging the flyback energy through the transient voltage suppression diode D3 is as follows: At the instant that power transistors Q1 to Q4 are turned off, the flyback high voltage generated by the inductive load is blocked by the unidirectional blocking effect of the ultrafast recovery diode D4, preventing it from flowing back into the external DC power supply; at the same time, when the flyback high voltage exceeds the avalanche breakdown threshold of the transient voltage suppressor diode D3, the transient voltage suppressor diode D3 turns on, forming a discharge loop from the bus node to the system ground. The bus node is the common electrical connection terminal between the ultrafast recovery diode D4 and the H-bridge power transistor array.

10. The method for driving an inductive load according to claim 9, characterized in that: The method for presetting the mode flag is as follows: Based on the number of times the first button is triggered, the mode flag is cyclically switched between Mode 1, Mode 2, Mode 3 and Mode 4; The method for presetting the duty cycle intensity is as follows: Based on the number of times the second button is triggered, the duty cycle intensity is cycled between 20%, 40%, 60%, 80%, and 100%. The fixed frequency is 10Hz; The range of the random target frequency is set to 1Hz to 50Hz; The preset time period is set to 3 to 5 minutes; The curing time period is set to 800 milliseconds; The specific extremely low frequency is set to 7.83 Hz.

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