Multilevel inverter circuit, energy storage inverter and photovoltaic system
By combining a series DC source with a first switching circuit, the multi-level inverter circuit solves the problems of complex structure and high cost of traditional multi-level inverters, achieving the effects of simplifying the topology and reducing hardware costs, while ensuring multi-level output and low loss.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FOXESS CO LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional multilevel inverters require a large number of power switching devices, capacitors, and diodes, resulting in complex circuit topologies, high control difficulty, and high costs, which limits their application.
By combining a series DC source with the first switching circuit, along with a full-bridge circuit and a filter circuit, the number of power switching devices and diodes is reduced. Multi-level output is achieved through bidirectional controllable semiconductor devices, and the current path is isolated when the voltage is zero to suppress leakage current and electromagnetic interference.
It simplifies the inverter circuit topology, reduces hardware costs and control complexity, while achieving multi-level output capability and reducing electromagnetic interference and switching losses.
Smart Images
Figure CN122247228A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power electronics technology, and in particular relates to a multi-level inverter circuit, an energy storage inverter, and a photovoltaic system. Background Technology
[0002] Inverters are an important component of new energy power generation systems such as photovoltaics and energy storage. Compared with traditional two-level inverters, multi-level inverters have advantages such as lower grid-connected current harmonics and smaller filter inductance, and are therefore widely used.
[0003] However, traditional multilevel inverters typically require a large number of power switching devices, capacitors, and diodes, resulting in a complex circuit topology. This not only increases the difficulty and cost of system control but also increases the size and weight, limiting their application in certain situations. Summary of the Invention
[0004] This invention aims to solve at least one of the technical problems existing in the prior art. To this end, this invention proposes a multi-level inverter circuit, an energy storage inverter, and a photovoltaic system, which, while ensuring multi-level output capability, reduces the number of required power switching devices, diodes, and other components, simplifies the main circuit topology, makes its corresponding control logic simpler, and reduces the hardware cost of the inverter circuit.
[0005] In a first aspect, this application provides a multilevel inverter circuit, which includes: A first DC source and a second DC source connected in series; The first switching circuit has a first terminal electrically connected to the connection node of the first DC source and the second DC source, and a second terminal electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source. The second switching circuit is electrically connected between the second terminal of the first switching circuit and the positive terminal of the first DC source, or the second switching circuit is electrically connected between the second terminal of the first switching circuit and the negative terminal of the second DC source. The full-bridge circuit has its positive input terminal on the DC side connected to the positive terminal of the first DC source, and its negative input terminal on the DC side connected to the negative terminal of the second DC source. The filter circuit is electrically connected to the AC side of the full-bridge circuit. The filter circuit is configured to filter the AC output of the full-bridge circuit and provide a freewheeling path for the output current of the multi-level inverter circuit under specific switching states.
[0006] According to the multi-level inverter circuit of this application, by combining a series DC source with a first switching circuit, along with a full-bridge circuit and a filter circuit, the number of required power switching devices, diodes and other components is reduced while ensuring multi-level output capability. This not only simplifies the main circuit topology but also makes its corresponding control logic simpler, thereby reducing the hardware cost of the inverter circuit.
[0007] According to one embodiment of this application, the first switching circuit includes: The bidirectional controllable semiconductor device unit has a first terminal electrically connected to the connection node of a first DC source and a second DC source, and a second terminal electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source. The bidirectional controllable semiconductor device unit is configured to independently turn on or off the bidirectional current path.
[0008] According to one embodiment of this application, the bidirectional controllable semiconductor device includes a first switch and a second switch connected in series; Wherein, the first terminal of the first switching transistor is electrically connected to the connection node of the first DC source and the second DC source, the second terminal of the second switching transistor is electrically connected to the second terminal of the first switching transistor, and the first terminal of the second switching transistor is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source; or The second terminal of the second switch is electrically connected to the connection node of the first DC source and the second DC source, the first terminal of the second switch is electrically connected to the first terminal of the first switch, and the second terminal of the first switch is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source.
[0009] According to one embodiment of this application, the multilevel inverter circuit further includes: Multiple third-party switching circuits; Multiple extended DC sources are connected in series. These multiple extended DC sources, together with the first DC source and the second DC source, constitute a DC source group. In the DC source group, except for the connection node between the first DC source and the second DC source, the connection node between every two adjacent DC sources is electrically connected to the first terminal of a corresponding third switching circuit. The second terminal of each third switching circuit is electrically connected to the DC input terminal of the full-bridge circuit.
[0010] According to one embodiment of this application, the multilevel inverter circuit further includes: Multiple extended DC sources connected in series and multiple bridge arm units are arranged one-to-one with each DC source and are cascaded in sequence. Each bridge arm unit includes a first switching circuit and a second switching circuit. The second terminal of the first switching circuit is electrically connected to the first terminal of the second switching circuit, and together they form the midpoint of the bridge arm of the bridge arm unit. In the first bridge arm unit, the first terminal of the first switching circuit is electrically connected to the connection node between the first DC source and the second DC source, and the second terminal of the second switching circuit is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source. In subsequent bridge arm units, the first terminal of the first switching circuit is electrically connected to the midpoint of the bridge arm of the preceding bridge arm unit, the second terminal of the second switching circuit is electrically connected to the positive or negative terminal of the corresponding extended DC source, and the midpoint of the bridge arm of the last bridge arm unit is electrically connected to the DC input terminal of the full-bridge circuit.
[0011] According to one embodiment of this application, the filter circuit includes a capacitor and at least one inductor.
[0012] According to one embodiment of this application, the full-bridge circuit includes a first bridge arm and a second bridge arm connected in parallel, and the filter circuit includes: The first inductor, the first end of the first inductor is electrically connected to the midpoint of the first bridge arm; The second inductor has its first end electrically connected to the midpoint of the second bridge arm. The filter capacitor has its first terminal electrically connected to the second terminal of the first inductor, and its second terminal electrically connected to the second terminal of the second inductor.
[0013] According to one embodiment of this application, when the multilevel inverter circuit operates in zero-voltage output freewheeling mode, the second switching circuit is in the off state.
[0014] Secondly, this application provides an energy storage inverter that includes the aforementioned multi-level inverter circuit.
[0015] According to the energy storage inverter of this application, the multi-level inverter circuit combines a series DC source with a first switching circuit, along with a full-bridge circuit and a filter circuit. While ensuring multi-level output capability, it reduces the number of required power switching devices, diodes, and other components. This not only simplifies the main circuit topology but also makes its corresponding control logic simpler, thereby reducing the hardware cost of the inverter circuit.
[0016] Thirdly, this application provides a photovoltaic system, which includes a photovoltaic module and the aforementioned energy storage inverter, wherein the photovoltaic module and the energy storage inverter are electrically connected.
[0017] According to the photovoltaic system of this application, the multi-level inverter circuit combines a series DC source with a first switching circuit, along with a full-bridge circuit and a filter circuit. While ensuring multi-level output capability, it reduces the number of required power switching devices, diodes, and other components. This not only simplifies the main circuit topology but also simplifies its corresponding control logic, thereby reducing the hardware cost of the inverter circuit.
[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description
[0019] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a structural block diagram of the multilevel inverter circuit provided in the embodiments of this application; Figure 2 This is one of the circuit topologies of the multilevel inverter circuit provided in the embodiments of this application; Figure 3 This is the second circuit topology diagram of the multilevel inverter circuit provided in the embodiments of this application; Figure 4 This is the third circuit topology diagram of the multilevel inverter circuit provided in the embodiments of this application; Figure 5 This is the fourth circuit topology diagram of the multilevel inverter circuit provided in the embodiments of this application; Figure 6 This is the fifth circuit topology diagram of the multilevel inverter circuit provided in the embodiments of this application; Figure 7 This is the sixth circuit topology diagram of the multilevel inverter circuit provided in the embodiments of this application.
[0020] Figure label: First switching circuit 10, full-bridge circuit 20, filter circuit 30, second switching circuit 40, third switching circuit 50, bridge arm unit 60, first to second DC source Vdc1~Vdc2, extended DC source Vdcn, first to second inductor L1~L2, filter capacitor C1, first to seventh switching transistor Q1~Q7. Detailed Implementation
[0021] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.
[0022] In the following description, a "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "coupled to" or "connected to" another element, or when an element / circuit is said to be "coupled at" or "connected at" two nodes, it can be directly coupled to or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.
[0023] In the description, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such numerical descriptors can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0024] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0025] Figure 1 A structural block diagram of a multilevel inverter circuit provided in an embodiment of this application is shown. (Refer to...) Figure 1One embodiment of this application proposes a multilevel inverter circuit, which includes: a first DC source Vdc1 and a second DC source Vdc2 connected in series, a first switching circuit 10, a full-bridge circuit 20, a filter circuit 30, and a second switching circuit 40. The first terminal of the first switching circuit 10 is electrically connected to the connection node of the first DC source Vdc1 and the second DC source Vdc2, and the second terminal of the first switching circuit 10 is electrically connected to the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2. The second switching circuit 40 is electrically connected between the second terminal of the first switching circuit 10 and the positive terminal of the first DC source Vdc1, or between the second terminal of the first switching circuit 10 and the negative terminal of the second DC source Vdc2. The positive input terminal of the DC side of the full-bridge circuit 20 is connected to the positive terminal of the first DC source Vdc1, and the negative input terminal of the DC side of the full-bridge circuit 20 is connected to the negative terminal of the second DC source Vdc2. The filter circuit 30 is electrically connected to the AC side of the full-bridge circuit 20. The filter circuit 30 is configured to filter the AC output of the full-bridge circuit 20 and provide a freewheeling path for the output current of the multi-level inverter circuit in a specific switching state.
[0026] A DC source refers to a power source capable of providing stable DC power, such as a photovoltaic module or an energy storage battery. In this embodiment, the first DC source Vdc1 and the second DC source Vdc2 are connected in series to form a connection node, thereby providing multiple potential levels to the circuit to achieve multi-level output.
[0027] As an example, if the voltage of the first DC source Vdc1 and the second DC source Vdc2 is both Vdc, then the first DC source Vdc1 and the second DC source Vdc2 connected in series can provide ±2Vdc, ±Vdc and zero voltage. The negative terminal of the first DC source Vdc1 is electrically connected to the positive terminal of the second DC source Vdc2, and the connection node between the negative terminal of the first DC source Vdc1 and the positive terminal of the second DC source Vdc2 is electrically connected to the first terminal of the first switching circuit 10.
[0028] The first switching circuit 10 refers to a power switching unit composed of controllable semiconductor devices. The two ends of the first switching circuit 10 are respectively connected to the intermediate node of a series DC source and the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2. By controlling its conduction state, the potential of the intermediate node can be selectively introduced into the subsequent circuit, thereby expanding the number of voltage levels.
[0029] The full-bridge circuit 20 consists of four switching devices. The DC side of the full-bridge circuit 20 is connected to the positive and negative terminals of the DC source group, and the AC side outputs a pulse width modulation waveform. The full-bridge circuit 20 is responsible for converting DC power to AC power and can output positive, negative, and zero levels through different switching combinations.
[0030] The filter circuit 30 can be a filter network composed of passive components such as inductors and capacitors, connected to the AC side of the full-bridge circuit 20. Its main function is to filter out high-frequency harmonics generated by switching operations, smooth the output current waveform, and provide a freewheeling path for the output current under specific switching states, ensuring continuous current and thus supporting zero-voltage output. For example, when the full-bridge circuit 20 is in freewheeling mode, the energy stored in the inductor in the filter circuit 30 forms a freewheeling path through the capacitor, maintaining continuous current, achieving zero-voltage output, and avoiding voltage spikes and electromagnetic interference caused by sudden current changes.
[0031] The second switching circuit 40 is configured to be in an off state during the freewheeling phase. Specifically, when the multi-level inverter circuit operates in zero-voltage output freewheeling mode, the second switching circuit 40 is turned off by a control signal, thereby physically cutting off the electrical connection between the second terminal of the first switching circuit 10 and the corresponding DC source electrode. This physically isolates the DC side from the AC side, directly blocking the conduction path of leakage current, fundamentally suppressing the generation of common-mode current, and effectively suppressing conducted electromagnetic interference.
[0032] Furthermore, since leakage current and electromagnetic interference can be suppressed, the amount or specifications of peripheral components such as filter capacitor C1 can be reduced accordingly, which helps to further reduce the overall size and lower hardware costs.
[0033] Figure 2 and Figure 3 A circuit topology diagram of a multilevel inverter circuit provided in an embodiment of this application is shown. For example... Figure 2 As shown, the first terminal of the second switching circuit 40 is electrically connected to the second terminal of the first switching circuit 10, and the second terminal of the second switching circuit 40 is electrically connected to the positive terminal of the first DC source Vdc1. Figure 3 As shown, the first terminal of the second switching circuit 40 is electrically connected to the second terminal of the first switching circuit 10, and the second terminal of the second switching circuit 40 is electrically connected to the negative terminal of the second DC source Vdc2. The specific structure of the second switching circuit 40 is not limited here.
[0034] For example, the second switching circuit 40 may include a fifth switching transistor Q5. The fifth switching transistor Q5 and other switching transistors mentioned below may be MOSFETs (Metallic Switches). Oxide Semiconductor Field The application does not limit the specific type and model of the switching device. (Metal-Oxide-Semiconductor Field-Effect Transistor, or IGBT (Insulated Gate Bipolar Transistor)).
[0035] Taking the fifth switch Q5 as a MOSFET as an example, the source of the fifth switch Q5 is electrically connected to the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2, and the drain of the fifth switch Q5 is electrically connected to the second terminal of the first switching circuit 10.
[0036] In some embodiments, the first switching circuit 10 includes a bidirectional controllable semiconductor device unit. The first end of the bidirectional controllable semiconductor device unit is electrically connected to the connection node of the first DC source Vdc1 and the second DC source Vdc2. The second end of the bidirectional controllable semiconductor device unit is electrically connected to the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2. The bidirectional controllable semiconductor device unit is configured to independently turn on or off the bidirectional current path.
[0037] A bidirectional controllable semiconductor device unit can be constructed from two switching transistors (such as MOSFETs, IGBTs, etc.) in a common-source, common-drain, or anti-series configuration, or it can employ an integrated bidirectional switching module (such as a bidirectional thyristor, a four-quadrant switch, etc.). When the device is in the on-state, current can selectively flow in either the forward or reverse direction; when the device is in the off-state, both the forward and reverse current paths are blocked regardless of the applied voltage polarity.
[0038] In this embodiment, the bidirectional controllable semiconductor device unit can simultaneously block both forward and reverse currents in the off state, achieving complete electrical isolation.
[0039] This bidirectional controllable semiconductor device unit is electrically connected between the connection node of the series DC source and the positive (or negative) terminal of the DC bus. By controlling the on and off states of the bidirectional controllable semiconductor device unit, the potential of the connection node can be selectively introduced to the DC bus side, cooperating with the full-bridge circuit 20 to generate multi-level stepped waveforms such as +Vdc and -Vdc. Because the bidirectional controllable semiconductor device unit has bidirectional conduction capability, low-loss power transmission can be achieved regardless of the current flow direction.
[0040] Reference Figure 2 and Figure 3In some embodiments, the bidirectional controllable semiconductor device includes a sixth switch Q6 and a seventh switch Q7 connected in series. The sixth switch Q6 can serve as the aforementioned first switch, and the seventh switch Q7 can serve as the aforementioned second switch. The source of the MOSFET serves as the first terminal of the aforementioned switches, and the drain serves as the second terminal. The source of the sixth switch Q6 is electrically connected to the connection node of the first DC source Vdc1 and the second DC source Vdc2. The drain of the seventh switch Q7 is electrically connected to the drain of the sixth switch Q6, and the source of the seventh switch Q7 is electrically connected to the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2. Alternatively, the drain of the seventh switch Q7 is electrically connected to the connection node of the first DC source Vdc1 and the second DC source Vdc2, the source of the seventh switch Q7 is electrically connected to the source of the sixth switch Q6, and the drain of the seventh switch Q7 is electrically connected to the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2.
[0041] The bidirectional controllable semiconductor device unit is composed of two MOSFETs connected in series. Specifically, based on the polarity connection relationship of the two MOSFETs, it can be divided into common-drain topology and common-source topology.
[0042] In the common-drain topology, the source of the sixth switch Q6 is electrically connected to the connection node of the first DC source Vdc1 and the second DC source Vdc2, and the drain of the seventh switch Q7 is electrically connected to the drain of the sixth switch Q6. They share the same drain node. The source of the seventh switch Q7 is electrically connected to either the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2. The two switches are connected in series back-to-back, with their drains interconnected and their sources facing opposite ends of the circuit.
[0043] When current is required to flow from the connection node to the positive (or negative) terminal of the DC bus, the current flows sequentially through the channel of the sixth switch Q6 (source → drain), the drain interconnection point, and the channel of the seventh switch Q7 (drain → source), finally reaching the target electrode; when current is required to flow in the reverse direction, the current flows sequentially through the channel of the seventh switch Q7 (source → drain), the drain interconnection point, and the channel of the sixth switch Q6 (drain → source), finally reaching the connection node.
[0044] In a common-source topology, the drain of the seventh switch Q7 is electrically connected to the connection node of the first DC source Vdc1 and the second DC source Vdc2. The source of the seventh switch Q7 is electrically connected to the source of the sixth switch Q6, and the two switches share the same source node. The drain of the seventh switch Q7 is electrically connected to the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2. The two switches are connected in series in a "face-to-face" manner, with their sources interconnected and their drains facing opposite ends of the circuit.
[0045] When current is required to flow from the connection node to the positive (or negative) terminal of the DC bus, the current flows sequentially through the channel of the seventh switch Q7 (drain → source), the source interconnection point, and the channel of the sixth switch Q6 (source → drain), finally reaching the target electrode; when current is required to flow in the reverse direction, the current flows sequentially through the channel of the sixth switch Q6 (drain → source), the source interconnection point, and the channel of the seventh switch Q7 (source → drain), finally reaching the connection node.
[0046] In both series topologies described above, the two MOSFETs are connected in reverse series, meaning the current direction when one MOSFET is on is opposite to the current direction when the other is on. When both MOSFETs are on simultaneously, regardless of the applied voltage polarity, one MOSFET will always operate in forward conduction mode, while the other will operate in reverse conduction mode, thus achieving fully active control of the bidirectional current path. When both MOSFETs are off, regardless of the voltage polarity, the body diode is reverse biased, completely cutting off both the forward and reverse current paths, achieving true bidirectional blocking. Both bidirectional currents flow through the low-resistance channel, eliminating the need for freewheeling from the body diode. The forward voltage drop is much lower than that of the diode, reducing switching losses.
[0047] Continue to refer to Figure 2 and Figure 3 The working principle of the multi-level inverter circuit proposed in this embodiment will be further explained below with reference to the specific structure of the full-bridge circuit 20. The full-bridge circuit 20 includes a first bridge arm and a second bridge arm connected in parallel. The first bridge arm includes a first switch Q1 and a third switch Q3 connected in series, and the second bridge arm includes a second switch Q2 and a fourth switch Q4 connected in series. The first terminal of the first switch Q1 and the first terminal of the second switch Q2 are both electrically connected to the positive terminal of the first DC source Vdc1. The second terminal of the first switch Q1 is electrically connected to the first terminal of the third switch Q3. The second terminal of the second switch Q2 is electrically connected to the first terminal of the fourth switch Q4. The second terminals of the third switch Q3 and the fourth switch Q4 are both electrically connected to the negative terminal of the second DC source Vdc2.
[0048] It should be noted that the multi-level inverter circuit proposed in this embodiment can achieve both three-level and five-level outputs. The following is based on... Figure 2 Taking the circuit topology shown as an example, the first switching circuit 10 includes a sixth switch Q6 and a seventh switch Q7 connected in series, and the second switching circuit 40 includes a fifth switch Q5. The output of the multi-level inverter circuit is described with the current flowing from the DC side to the AC side as an example.
[0049] In five-level output mode, the on / off status of each switch is as follows: The first output is +2Vdc when the second switch Q2, the third switch Q3, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the first switch Q1, the fourth switch Q4 and the fifth switch Q5 are all turned on.
[0050] The second output is +Vdc when the second switch Q2, the third switch Q3, and the fifth switch Q5 are all turned off, and the first switch Q1, the fourth switch Q4, and the seventh switch Q7 (or the sixth switch Q6 and the seventh switch Q7) are all turned on.
[0051] The third output: When the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the first switch Q1 is turned on, the current flows through the anti-parallel diode (or body diode) of the first switch Q1 and the second switch Q2 to achieve forward zero-voltage freewheeling.
[0052] The fourth output: When the first switch Q1, the second switch Q2, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the fourth switch Q4 is turned on, the current flows through the anti-parallel diode (or body diode) of the fourth switch Q4 and the third switch Q3 to achieve forward zero-voltage freewheeling.
[0053] The fifth output: When the first switch Q1, the fourth switch Q4, and the seventh switch Q7 (or the sixth switch Q6 and the seventh switch Q7) are all turned off, and the second switch Q2, the third switch Q3, and the fifth switch Q5 are all turned on, the output level is -2Vdc.
[0054] The sixth output: When the first switch Q1, the fourth switch Q4, and the fifth switch Q5 are all turned off, and the second switch Q2, the third switch Q3, and the seventh switch Q7 (or the sixth switch Q6 and the seventh switch Q7) are all turned on, the output level is -Vdc.
[0055] The seventh output: When the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the second switch Q2 is turned on, the current flows through the anti-parallel diode (or body diode) of the second switch Q2 and the first switch Q1 to achieve negative zero-voltage freewheeling.
[0056] The eighth output: When the first switch Q1, the second switch Q2, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the third switch Q3 is turned on, the current flows through the anti-parallel diode (or body diode) of the third switch Q3 and the fourth switch Q4 to achieve negative zero-voltage freewheeling.
[0057] With the above switch combination, the multi-level inverter circuit can smoothly switch between five levels: +2Vdc, +Vdc, 0, -Vdc and -2Vdc, and ensure continuous current when the voltage is zero, thereby reducing switching losses and electromagnetic interference.
[0058] In five-level output mode, the on / off status of each switch is as follows: The first output is +2Vdc when the second switch Q2, the third switch Q3, the sixth switch Q6, and the seventh switch Q7 are all turned off, and the first switch Q1, the fourth switch Q4, and the fifth switch Q5 are all turned on.
[0059] The second output: When the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are turned off at the same time, and the first switch Q1 is turned on, the current passes through the anti-parallel diode (or body diode) of the first switch Q1 and the second switch Q2 and the filter circuit 30 to achieve forward zero-voltage freewheeling.
[0060] The third output: When the first switch Q1, the second switch Q2, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the fourth switch Q4 is turned on, the current flows through the anti-parallel diode (or body diode) of the fourth switch Q4 and the third switch Q3 and the filter circuit 30 to achieve forward zero-voltage freewheeling.
[0061] The fourth output: When the first switch Q1, the fourth switch Q4, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the second switch Q2, the third switch Q3 and the fifth switch Q5 are all turned on, the output level is -2Vdc.
[0062] The fifth output: When the third switch Q3, the fourth switch Q4, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are turned off at the same time, and the second switch Q2 is turned on, the current flows through the anti-parallel diode (or body diode) of the second switch Q2 and the first switch Q1 and the filter circuit 30 to achieve negative zero-voltage freewheeling.
[0063] The sixth output: When the first switch Q1, the second switch Q2, the fifth switch Q5, the sixth switch Q6 and the seventh switch Q7 are all turned off, and the third switch Q3 is turned on, the current flows through the anti-parallel diode (or body diode) of the third switch Q3 and the fourth switch Q4 and the filter circuit 30 to achieve negative zero-voltage freewheeling.
[0064] With the above switch combination, the multi-level inverter circuit can smoothly switch between three levels: +2Vdc, 0, and -2Vdc, and ensure continuous current when the voltage is zero, thereby reducing switching losses and electromagnetic interference.
[0065] Compared with traditional multilevel inverters, this embodiment significantly reduces the number of power switching devices, diodes, and capacitors, requiring only a small number of switching elements to achieve multilevel output, effectively reducing hardware costs and system complexity.
[0066] According to the multi-level inverter circuit of this application, by combining a series DC source with the first switching circuit 10, along with a full-bridge circuit 20 and a filter circuit 30, the number of required power switching devices, diodes and other components is reduced while ensuring multi-level output capability. This not only simplifies the main circuit topology but also makes its corresponding control logic simpler, thereby reducing the hardware cost of the inverter circuit.
[0067] Figure 4 and Figure 5 A circuit topology diagram of a multilevel inverter circuit provided in an embodiment of this application is shown. (Refer to...) Figure 4 and Figure 5 In some embodiments, the multilevel inverter circuit further includes multiple third switching circuits 50 and multiple extended DC sources Vdcn connected in series. The multiple extended DC sources Vdcn, together with the first DC source Vdc1 and the second DC source Vdc2, constitute a DC source group. In the DC source group, except for the connection node between the first DC source Vdc1 and the second DC source Vdc2, the connection node of each pair of adjacent DC sources is electrically connected to the first terminal of a corresponding third switching circuit 50, and the second terminal of each third switching circuit 50 is electrically connected to the DC side input terminal of the full-bridge circuit 20.
[0068] To meet the different requirements of various application scenarios for the number of output levels and voltage levels, the multi-level inverter circuit also includes multiple third switching circuits 50 and multiple extended DC sources Vdcn connected in series.
[0069] Based on the first DC source Vdc1 and the second DC source Vdc2, multiple extended DC sources Vdcn are cascaded sequentially along the positive or negative direction. Each extended DC source Vdcn can have the same voltage level (e.g., the voltage of each branch element is Vdc), or it can have different voltage levels configured as needed, together forming a series DC source group with multiple intermediate taps.
[0070] At each newly added adjacent DC source connection node, an independent third switching circuit 50 is configured. The first end of the third switching circuit 50 is connected to the corresponding node, and the second end is uniformly connected to the positive or negative input terminal of the DC side of the full-bridge circuit 20.
[0071] When the expansion direction is the positive pole side (e.g.) Figure 4 As shown), the second terminal of the third switching circuit 50 is connected to the positive input terminal of the full-bridge circuit 20; when the extension direction is the negative side (as shown in the figure), the second terminal of the third switching circuit 50 is connected to the positive input terminal of the full-bridge circuit 20. Figure 5 As shown), the second end of the third switching circuit 50 is connected to the negative input terminal of the full-bridge circuit 20; when performing bilateral symmetrical expansion, the positive and negative input terminals are respectively connected to multiple third switching circuits 50 on the corresponding sides.
[0072] Through the above extended structure, the number of output levels that the multi-level inverter circuit can achieve can be greatly expanded from the aforementioned five levels to any odd number of levels (such as seven levels, nine levels, eleven levels or even higher). No matter how large the expansion scale is, the connection node between the first DC source Vdc1 and the second DC source Vdc2 always serves as a zero potential reference point, ensuring that the zero-crossing point of the output waveform is symmetrical.
[0073] Each third switching circuit 50 works in coordination with the first switching circuit 10 and the switching transistors of the full-bridge circuit 20. During any switching cycle, at most one third switching circuit 50 is in the on state. The potential of the connection node corresponding to the on third switching circuit 50 is selected to the DC side of the full-bridge circuit 20, and cooperates with the first switching circuit 10 or the DC bus terminal to synthesize the target level.
[0074] When a higher positive level is required, the corresponding third switch circuit 50 near the positive terminal is turned on; when a lower positive level is required, the corresponding third switch circuit 50 near the midpoint is turned on; the same applies to the negative level side. This achieves multi-stage regulation of the DC bus voltage.
[0075] Figure 6 and Figure 7 A circuit topology diagram of a multilevel inverter circuit provided in an embodiment of this application is shown. (Refer to...) Figure 6 and Figure 7In some embodiments, the multilevel inverter circuit also includes multiple extended DC sources Vdcn connected in series and multiple bridge arm units 60. Each bridge arm unit 60 is configured in a one-to-one correspondence with each DC source and is cascaded sequentially. Each bridge arm unit 60 includes a first switching circuit 10 and a second switching circuit 40. The second end of the first switching circuit 10 is electrically connected to the first end of the second switching circuit 40, and together they form the midpoint of the bridge arm of the bridge arm unit 60. In the first bridge arm unit 60, the first end of the first switching circuit 10 is electrically connected to the connection node between the first DC source Vdc1 and the second DC source Vdc2, and the second end of the second switching circuit 40 is electrically connected to the positive terminal of the first DC source Vdc1 or the negative terminal of the second DC source Vdc2. In subsequent bridge arm units 60, the first end of the first switching circuit 10 is electrically connected to the midpoint of the bridge arm of the preceding bridge arm unit 60, and the second end of the second switching circuit 40 is electrically connected to the positive or negative terminal of the corresponding extended DC source Vdcn. The midpoint of the bridge arm of the last bridge arm unit 60 is electrically connected to the DC input terminal of the full-bridge circuit 20.
[0076] Each extended DC source Vdcn is equipped with an independent bridge arm unit 60, which can controllably introduce the voltage of the corresponding DC source into the cascaded link. The bridge arm units 60 are connected in series with the midpoint of the bridge arm to the input terminal of the first switching circuit 10 of the next stage. The midpoint of the bridge arm of the preceding bridge arm unit 60 serves as the power supply node of the following bridge arm unit 60, thereby realizing the automatic superposition of the voltages of each DC source. The midpoint of the bridge arm of the last stage bridge arm unit 60 is connected to the DC side input terminal of the full-bridge circuit 20; the full-bridge circuit 20 only needs to process a single, continuously adjustable DC bus voltage synthesized through cascading.
[0077] The first terminal of the first switching circuit 10 of the first bridge arm unit 60 is connected to the connection node between the first DC source Vdc1 and the second DC source Vdc2, providing a zero potential reference for the entire cascaded circuit.
[0078] like Figure 6 As shown, when the first switching circuit 10 in the first bridge arm unit 60 is turned on and the second switching circuit 40 is turned off, the midpoint potential of its bridge arm is clamped to zero. When the first switching circuit 10 in the first bridge arm unit 60 is turned off and the second switching circuit 40 is turned on, the midpoint potential of its bridge arm rises to the positive potential Vdc of the first DC source Vdc1. This midpoint potential of the bridge arm serves as the reference potential for the input terminal of the first switching circuit 10 of the second bridge arm unit 60. If the second switching circuit 40 of the second bridge arm unit 60 is turned on, the midpoint potential of its bridge arm further rises to +2Vdc. And so on, each bridge arm unit 60 superimposes its corresponding DC source voltage into the link by turning on the second switching circuit 40, and directly transmits the potential of the previous stage by turning on the first switching circuit 10.
[0079] When the first bridge arm unit 60 is configured to connect to the negative terminal of the second DC source Vdc2 (e.g.) Figure 7 As shown in the diagram, a progressively stacked path for negative voltages can be constructed similarly. The midpoint potential of the last bridge arm unit 60 is the algebraic sum of the DC source voltages selected at each stage. This potential is directly supplied to the DC side of the full-bridge circuit 20, where it undergoes inversion processing.
[0080] Regardless of the number of cascaded circuits, the first switching circuit 10 and the second switching circuit 40 in each bridge arm unit 60 only bear the voltage stress of the corresponding single DC source, and the voltage stress is relatively small.
[0081] In some embodiments, the filter circuit 30 includes a capacitor and at least one inductor.
[0082] The filter circuit 30 consists of a capacitor and at least one inductor. On the AC side of the full-bridge circuit 20, the filter inductor is connected in series with the AC output port, and the filter capacitor C1 is connected across the output terminals, forming an LC filter network. The LC filter network utilizes the current smoothing characteristic of the inductor and the voltage clamping characteristic of the capacitor to form a low-pass filter. High-frequency harmonic components are significantly attenuated by the inductor impedance, resulting in a smooth sinusoidal voltage and current at the load end.
[0083] In addition to its filtering function, the inductor in the filter circuit 30 also provides a freewheeling path under specific switching conditions. When the full-bridge circuit 20 enters the zero-voltage output state (i.e., the freewheeling stage), all active switches are turned off, and the load current cannot obtain energy from the DC side. At this time, the magnetic energy stored in the filter inductor maintains the current continuity through the induced electromotive force, forming a complete freewheeling path through the filter capacitor C1, ensuring that zero-voltage output can be achieved.
[0084] In some embodiments, the full-bridge circuit 20 includes a first bridge arm and a second bridge arm connected in parallel, and the filter circuit 30 includes: a first inductor L1, the first end of which is electrically connected to the midpoint of the first bridge arm; a second inductor L2, the first end of which is electrically connected to the midpoint of the second bridge arm; and a filter capacitor C1, the first end of which is electrically connected to the second end of the first inductor L1, and the second end of which is electrically connected to the second end of the second inductor L2.
[0085] The first inductor L1 and the second inductor L2 are respectively connected to the midpoints of the two bridge arms of the full-bridge circuit 20. They are mirror images of each other in the electrical path. The first inductor L1 and the second inductor L2 are usually configured to have the same inductance, the same rated current, the same core material and the same saturation characteristics. The filter capacitor C1 is connected across the output terminals of the first inductor L1 and the second inductor L2 to form a symmetrical LC filter network.
[0086] When a common-mode interference voltage appears at the output of the full-bridge circuit 20, this interference voltage acts simultaneously on the midpoints of the first and second bridge arms with the same polarity and amplitude. Since the parameters of the first inductor L1 and the second inductor L2 are symmetrical, the common-mode currents flowing through the two inductors are equal in magnitude and in the same direction; the common-mode voltage difference across the filter capacitor C1 is zero, therefore the common-mode current cannot form a path through the filter capacitor C1, and its amplitude is significantly attenuated by the high common-mode impedance of the inductor.
[0087] One embodiment of this application provides an energy storage inverter that includes the aforementioned multilevel inverter circuit.
[0088] An energy storage inverter is a power electronic device that converts direct current (DC) power into alternating current (AC) power and enables bidirectional energy flow between a battery energy storage system and the power grid or load. The energy storage inverter described in this embodiment employs the aforementioned multi-level inverter circuit as its main power topology.
[0089] The specific structure and working principle of the multi-level inverter circuit can be referred to the description of the foregoing embodiments, and will not be repeated here.
[0090] According to the energy storage inverter of this application, the multi-level inverter circuit combines a series DC source with the first switching circuit 10, along with a full-bridge circuit 20 and a filter circuit 30. While ensuring multi-level output capability, it reduces the number of required power switching devices, diodes and other components, which not only simplifies the main circuit topology but also makes its corresponding control logic simpler and reduces the hardware cost of the inverter circuit.
[0091] One embodiment of this application proposes a photovoltaic system including a photovoltaic module and the aforementioned energy storage inverter, wherein the photovoltaic module and the energy storage inverter are electrically connected.
[0092] The photovoltaic system described in this embodiment uses photovoltaic modules as the DC power source input and the aforementioned energy storage inverter as the power conversion unit to form a complete energy system integrating photovoltaic power generation, energy storage regulation, and grid-connected / off-grid power supply.
[0093] The energy storage inverter is the multi-level energy storage inverter mentioned in the previous embodiment, whose DC side is connected to both photovoltaic modules and energy storage batteries, and whose AC side is connected to the power grid or AC load.
[0094] According to the photovoltaic system of this application, the multi-level inverter circuit combines a series DC source with the first switching circuit 10, along with a full-bridge circuit 20 and a filter circuit 30. While ensuring multi-level output capability, it reduces the number of required power switching devices, diodes and other components. This not only simplifies the main circuit topology but also makes its corresponding control logic simpler, thereby reducing the hardware cost of the inverter circuit.
[0095] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.
[0096] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
Claims
1. A multi-level inverter circuit, characterized by comprising: include: A first DC source and a second DC source connected in series; A first switching circuit, wherein a first terminal of the first switching circuit is electrically connected to the connection node of the first DC source and the second DC source, and a second terminal of the first switching circuit is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source. The second switching circuit is electrically connected between the second terminal of the first switching circuit and the positive terminal of the first DC source, or the second switching circuit is electrically connected between the second terminal of the first switching circuit and the negative terminal of the second DC source. A full-bridge circuit, wherein the positive input terminal of the DC side of the full-bridge circuit is connected to the positive terminal of the first DC source, and the negative input terminal of the DC side of the full-bridge circuit is connected to the negative terminal of the second DC source; A filter circuit is electrically connected to the AC side of the full-bridge circuit. The filter circuit is configured to filter the AC output of the full-bridge circuit and provide a freewheeling path for the output current of the multi-level inverter circuit in a specific switching state.
2. The multi-level inverter circuit according to claim 1, characterized in that, The first switching circuit includes: A bidirectional controllable semiconductor device unit, wherein a first end of the bidirectional controllable semiconductor device unit is electrically connected to the connection node of the first DC source and the second DC source, and a second end of the bidirectional controllable semiconductor device unit is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source, and the bidirectional controllable semiconductor device unit is configured to independently turn on or off the bidirectional current path.
3. The multi-level inverter circuit according to claim 2, characterized in that, The bidirectional controllable semiconductor device includes a first switch and a second switch connected in series. Wherein, the first terminal of the first switching transistor is electrically connected to the connection node of the first DC source and the second DC source, the second terminal of the second switching transistor is electrically connected to the second terminal of the first switching transistor, and the first terminal of the second switching transistor is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source; or The second terminal of the second switch is electrically connected to the connection node of the first DC source and the second DC source, the first terminal of the second switch is electrically connected to the first terminal of the first switch, and the second terminal of the first switch is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source.
4. The multi-level inverter circuit of claim 2, wherein, The multi-level inverter circuit also includes: Multiple third-party switching circuits; Multiple extended DC sources are connected in series. These multiple extended DC sources, together with the first DC source and the second DC source, constitute a DC source group. In the DC source group, except for the connection node between the first DC source and the second DC source, the connection node of each pair of adjacent DC sources is electrically connected to the first terminal of a corresponding third switching circuit. The second terminal of each third switching circuit is electrically connected to the DC input terminal of the full-bridge circuit.
5. The multi-level inverter circuit according to claim 1, characterized in that, The multi-level inverter circuit also includes: Multiple extended DC sources connected in series and multiple bridge arm units, each bridge arm unit is configured in one-to-one correspondence with each DC source, and are cascaded in sequence; Each of the bridge arm units includes a first switching circuit and a second switching circuit, wherein the second end of the first switching circuit is electrically connected to the first end of the second switching circuit, and together they form the midpoint of the bridge arm of the bridge arm unit. In the first bridge arm unit, the first terminal of the first switching circuit is electrically connected to the connection node between the first DC source and the second DC source, and the second terminal of the second switching circuit is electrically connected to the positive terminal of the first DC source or the negative terminal of the second DC source. In subsequent bridge arm units, the first terminal of the first switching circuit is electrically connected to the midpoint of the bridge arm of the preceding bridge arm unit, the second terminal of the second switching circuit is electrically connected to the positive or negative terminal of the corresponding extended DC source, and the midpoint of the bridge arm of the last bridge arm unit is electrically connected to the DC input terminal of the full bridge circuit.
6. The multilevel inverter circuit according to any one of claims 1-5, characterized in that, The filter circuit includes a capacitor and at least one inductor.
7. The multi-level inverter circuit according to claim 6, characterized in that, The full-bridge circuit includes a first bridge arm and a second bridge arm connected in parallel, and the filter circuit includes: The first inductor, the first end of the first inductor is electrically connected to the midpoint of the first bridge arm; The second inductor, the first end of the second inductor is electrically connected to the midpoint of the bridge arm of the second bridge arm; A filter capacitor, wherein the first end of the filter capacitor is electrically connected to the second end of the first inductor, and the second end of the filter capacitor is electrically connected to the second end of the second inductor.
8. The multilevel inverter circuit according to any one of claims 1-5, characterized in that, When the multi-level inverter circuit operates in zero-voltage output freewheeling mode, the second switching circuit is in the off state.
9. An energy storage inverter, characterized in that, Includes a multilevel inverter circuit according to any one of claims 1-8.
10. A photovoltaic system, characterized in that, It includes a photovoltaic module and an energy storage inverter according to claim 9, wherein the photovoltaic module is electrically connected to the energy storage inverter.