A dither generation circuit and a dither transfer and tolerance measurement circuit

Abstract

This invention provides a jitter generation circuit and a jitter propagation and tolerance measurement circuit, relating to the field of jitter injection and detection technology. The jitter generation circuit includes: an interface circuit for receiving a target code pattern and a target jitter; a sequence calculation module for calculating the injected jitter code pattern based on the target code pattern and the target jitter; a sampler for discretizing the flipped time series to obtain a discretized time series and generating an output sequence; and a clock module for generating a clock signal for the sampler. The jitter propagation and tolerance measurement circuit includes: a transmitter for generating and transmitting a jittered signal; a circuit under test for receiving the jittered signal and generating an output signal; a receiver for calculating the jitter propagation and tolerance; and a clock module for generating a clock signal. The advantages of this invention are that it overcomes the shortcomings of existing jitter injection schemes, such as poor versatility and inflexibility, and also improves the shortcomings of existing index measurement schemes, such as poor economy and lack of integration.

Description

Technical Field

[0001] This invention relates to the field of jitter injection and detection technology, and more specifically, to a jitter generation circuit and a jitter transmission and tolerance measurement circuit. Background Technology

[0002] To measure the jitter tolerance and jitter propagation performance of a receiver chip, a specified amount of jitter needs to be applied to the data stream. This is done by causing the input signal to deviate from its "ideal position," and this deviation is called input jitter, also known as TIE (time interval error).

[0003] Existing jitter injection technologies primarily rely on clock signal frequency / phase modulation methods and high-speed phase difference methods. Clock signal frequency / phase modulation methods are complex to implement, requiring relatively customized designs, and are mainly limited to achieving sinusoidal jitter within a certain frequency and amplitude range. High-speed phase difference methods also require relatively customized circuit structures, making them unsuitable for generalization, and their jitter implementation range is limited by PI stepping and control speed. Regarding the measurement of receiver chip performance indicators such as jitter tolerance and jitter propagation, existing measurement techniques mainly rely on bit error rate (BER) testing. The BER meters or signal analyzers used are expensive, and their large size prevents integration and adaptability to all application scenarios.

[0004] Therefore, it is necessary to improve the jitter injection method and the measurement methods for performance indicators such as jitter tolerance and jitter transmission, so as to improve the shortcomings of the existing jitter injection scheme in terms of poor universality and inflexibility, as well as the shortcomings of the existing indicator measurement scheme in terms of poor economy and inability to be integrated. Summary of the Invention

[0005] The purpose of this invention is to provide a jitter generation circuit and a jitter transmission and tolerance measurement circuit, which can improve the shortcomings of existing jitter injection schemes, such as poor versatility and lack of flexibility in use, as well as the shortcomings of existing index measurement schemes, such as poor economy and inability to be integrated.

[0006] This invention is achieved through the following technical solution:

[0007] A jitter generation circuit includes: Interface circuitry for receiving target code patterns and target jitter; The sequence calculation module is used to calculate the injected jitter-induced code pattern based on the target code pattern and the target jitter. A sampler is used to discretize the flipped time series, obtain a discretized time series, and generate an output sequence; The clock module is used to generate a clock signal for the sampler.

[0008] Preferably, the method for calculating the code pattern after adding jitter is as follows: Based on the target code pattern and the target jitter, the jitter-free flip time series of the target code pattern is obtained respectively. and TIE sequence , The index of the flip edge; The jitter-injected code pattern is obtained based on the jitter-free flip time series and TIE sequence. : .

[0009] Preferably, the method for calculating the TIE sequence based on the target code pattern and target jitter is as follows: Calculate the TIE sequence based on the target jitter. The method involves establishing the TIE sequence based on the jitter type of the target jitter. .

[0010] Preferably, when the jitter type of the target jitter is a sine function, the TIE sequence is established. The method is as follows: ; in, and These represent the amplitude and frequency of the target jitter, respectively.

[0011] Preferably, the method for discretizing the flipped time series is as follows: Discretize the injected jitter-induced code pattern to a time resolution. The discretized time series is obtained. ,in, The unit time interval between the flip edges of the flip time series. This is the oversampling factor, which is the average number of segments in a single original signal period.

[0012] Preferably, the method for generating the output sequence is as follows: The initial state of the output sequence is consistent with the first bit of the target code pattern, and subsequently in each discretized time sequence... The moment is flipped.

[0013] The present invention also provides a jitter propagation and tolerance measurement circuit for measuring the jitter propagation and jitter tolerance of a circuit under test after jitter is injected through a jitter generation circuit as described above, comprising: A transmitter used to generate and transmit signals with jitter; The circuit under test is used to receive jittered signals and generate output signals. The receiver is used to sample the output signal and calculate the propagation and tolerance of jitter based on the sampling results; The clock module is used to generate clock signals for the transmitter and receiver.

[0014] Preferably, the method for calculating the jitter transmission is as follows: ; in, For jitter transmission, and These are output jitter and input jitter, respectively.

[0015] Preferably, jitter of different jitter frequencies is injected and the jitter transmission is calculated. Based on the correspondence between the jitter frequency and the jitter transmission, a functional relationship graph of jitter frequency and jitter transmission is established.

[0016] Preferably, the method for calculating the jitter tolerance at different jitter frequencies is as follows: The jitter is generated with the initial jitter amplitude as the amplitude of the target jitter. Check if the output signal has a bit error. If a bit error occurs, record the jitter tolerance as less than the target jitter amplitude. If no bit error occurs, increase the target jitter amplitude and repeat the current step until a bit error occurs.

[0017] The technical solution of the present invention has at least the following advantages and beneficial effects: The jitter generation circuit proposed in this invention belongs to the data encoding circuit architecture. It can generate arbitrary jitter values ​​through high-speed sampling and frequency division, and has strong versatility and integrability. This invention improves upon the shortcomings of existing modulation and phase difference methods in jitter generation, which suffer from poor versatility and insufficient flexibility in applying jitter, and significantly reduces circuit complexity, resulting in higher cost-effectiveness. This invention eliminates the need for bit error rate testers or signal analyzers in jitter transmission and tolerance measurement, thus overcoming the shortcomings of low economic efficiency and inability to achieve integration in existing technologies. This invention can be implemented based on conventional integrated circuit design and processes, has strong integrability, and does not require high-value measurement equipment, thus reducing measurement costs. The jitter generation, jitter transmission, and jitter tolerance measurement of the present invention are easier to implement and more cost-effective, which helps to achieve more widely applicable chip performance index measurement and facilitates promotion and implementation. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the jitter generation circuit provided in Embodiment 1 of the present invention; Figure 2This is a schematic diagram comparing the ideal data signal and the data signal after jitter injection provided in Embodiment 1 of the present invention; Figure 3 The present invention provides in embodiment 1 the following: Figure 2 A schematic diagram of signal discretization; Figure 4 This is a schematic diagram of the jitter transmission and tolerance measurement circuit provided in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the calculation of jitter transmission measurement provided in Embodiment 1 of the present invention; Figure 6 This is a graph showing the functional relationship between jitter frequency and jitter propagation provided in Embodiment 1 of the present invention; Figure 7 This is a schematic diagram of an example of calculating jitter tolerance provided in Embodiment 1 of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Example 1 The main purpose of this embodiment is to measure the jitter tolerance and jitter propagation of the circuit under test. First, jitter is generated by a jitter generation circuit. After the jitter is injected, it is measured by a jitter propagation and tolerance measurement circuit.

[0021] A schematic diagram of the jitter generation circuit involved in this embodiment is shown in the attached diagram. Figure 1 ,include: The interface circuit is used to receive the target code pattern and the target jitter. The target code pattern is the original code pattern to be output, which can be an encoding rule or a directly input code pattern. The target jitter is the jitter to be injected, which can be based on jitter type and index or a directly input TIE sequence. The sequence calculation module is used to calculate the injected jitter-induced code pattern based on the target code pattern and the target jitter. A sampler is used to discretize the flipped time series, obtain a discretized time series, and generate an output sequence; The clock module is used to generate a clock signal for the sampler.

[0022] First, in the sequence calculation module, the method for calculating the code pattern after adding jitter is as follows: Based on the target code pattern and the target jitter, the jitter-free flip time series of the target code pattern is obtained respectively. and TIE sequence , This is the index of the flip edge.

[0023] On the one hand, jitter-free flipped time series middle, This means the input signal first flips at It happens constantly; for an ideal signal, The value is the unit time interval between the flip edges of the flip time series. Multiples of.

[0024] On the other hand, the method for calculating the TIE sequence based on the target code pattern and target jitter is as follows: Calculate the TIE sequence based on the target jitter. The method involves establishing the TIE sequence based on the jitter type of the target jitter. When the jitter type of the target jitter is a sine function, the TIE sequence is established. The method is as follows: ; in, and These represent the amplitude and frequency of the target jitter, respectively. It should be noted that if there are other types of jitter injection requirements, the cosine function should be replaced with the corresponding function. The jitter-injected code pattern is obtained based on the jitter-free flip time series and TIE sequence. : .

[0025] In the following sampler, the method for discretizing the flipped time series is as follows: Discretize the injected jitter-induced code pattern to a time resolution. The discretized time series is obtained. ,in, The unit time interval between the flip edges of the flip time series. This is the oversampling factor, which is the average number of segments in a single original signal period.

[0026] Then, the method for generating the output sequence is as follows: The initial state of the output sequence is consistent with the first bit of the target code pattern, and subsequently in each discretized time sequence... The moment is flipped.

[0027] The above scheme is implemented in an open-loop manner and only has rate requirements for circuit performance, with no requirements on the jitter sequence. Therefore, it avoids the problems of traditional modulation methods where jitter is only applicable to sinusoidal jitter and its amplitude and frequency are affected by modulator performance, as well as the more complex circuit structure of phase interpolation schemes. A comparison diagram of an ideal data signal at a certain data rate and a data signal injected with jitter can be found in [reference needed]. Figure 2 It can be seen that jitter is the amount by which the actual signal deviates from its ideal position, and the deviation at each data edge constitutes a jitter sequence, i.e., a TIE sequence. For more information on the discretization in the above scheme, please refer to [link to relevant documentation]. Figure 3 ,right Figure 2 Discretizing the two sets of signals yields two different code sequences. It can be seen that sampling with a high-speed clock signal having a data rate N times that of the target data rate DR, and calculating N based on the required TIE sequence... A serial signal with a DR data rate can generate a data signal containing corresponding jitter. The larger the multiple N, the better, as it primarily affects the jitter injection accuracy. For example, to apply 0.1 UI jitter, simply adjust the original high-level signal with a width of 10 "1"s to a high level that maintains 11 "1"s.

[0028] The jitter transmission and tolerance measurement circuit sampled in this embodiment can be found in [reference]. Figure 4 The method is used to measure the jitter propagation and jitter tolerance of the circuit under test after jitter is injected through the jitter generation circuit described above, including: A transmitter used to generate and transmit signals with jitter; The circuit under test is used to receive jittered signals and generate output signals. The receiver is used to sample the output signal and calculate the propagation and tolerance of jitter based on the sampling results; The clock module is used to generate clock signals for the transmitter and receiver.

[0029] In this embodiment, the method for calculating the jitter transmission is as follows: ; in, For jitter transmission, and These are output jitter and input jitter, respectively.

[0030] For example, see Figure 5 The ideal signal's high level lasts for 14 unit time intervals ( Figure 5The interval between the red dashed lines represents one unit time interval. The high level of the additional jitter excitation signal lasts for 18 unit time intervals, and the high level of the output signal of the circuit under test lasts for 16 unit time intervals. Therefore, the input jitter is 18-14=4 unit time intervals, and the output jitter is 16-14=2 unit time intervals. This indicates that the jitter transmission of the circuit under test at this frequency is 20log(2 / 4)=-6dB.

[0031] By injecting jitter at different frequencies and calculating the jitter propagation, a functional relationship graph of jitter frequency versus jitter propagation is established based on the correspondence between the jitter frequency and the jitter propagation. The functional relationship graph of jitter frequency versus jitter propagation can be found in [reference needed]. Figure 6 .

[0032] Meanwhile, the method for calculating the jitter tolerance at different jitter frequencies is as follows: The jitter is generated with the initial jitter amplitude as the target jitter amplitude; the output signal is checked for bit errors. If a bit error occurs, the jitter tolerance is set to be less than the target jitter amplitude. If no bit error occurs, the target jitter amplitude is increased and the current step is repeated until a bit error occurs.

[0033] by Figure 7 For example, when the input jitter is JITIN, the output code changes from the input 00011110… to 00011111…, indicating a bit error. This means that the circuit under test is at the JITIN level. IN It cannot function properly under these conditions; its jitter tolerance is lower than that of JIT. IN .

[0034] The solution is simple in principle, does not require high-value measurement equipment, and is compatible with conventional integrated circuits. It can be implemented based on conventional integrated circuit design and processes, has strong integrability, and does not rely on high-value measurement equipment, thus improving economic efficiency.

[0035] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A jitter generation circuit, characterized in that, include: Interface circuitry for receiving target code patterns and target jitter; The sequence calculation module is used to calculate the injected jitter-induced code pattern based on the target code pattern and the target jitter. A sampler is used to discretize the flipped time series, obtain a discretized time series, and generate an output sequence; The clock module is used to generate a clock signal for the sampler.

2. The jitter generation circuit according to claim 1, characterized in that, The method for calculating the code pattern after adding dithering is as follows: Based on the target code pattern and the target jitter, the jitter-free flip time series of the target code pattern is obtained respectively. and TIE sequence , The index of the flip edge; The jitter-injected code pattern is obtained based on the jitter-free flip time series and TIE sequence. : 。 3. The jitter generation circuit according to claim 2, characterized in that, The method for calculating the TIE sequence based on the target code pattern and target jitter is as follows: Calculate the TIE sequence based on the target jitter. The method involves establishing the TIE sequence based on the jitter type of the target jitter. .

4. The jitter generation circuit according to claim 3, characterized in that, When the jitter type of the target jitter is a sine function, the TIE sequence is established. The method is as follows: ； in, and These represent the amplitude and frequency of the target jitter, respectively.

5. The jitter generation circuit according to claim 1, characterized in that, The method for discretizing the flipped time series is as follows: Discretize the injected jitter-induced code pattern to a time resolution. The discretized time series is obtained. ,in, The unit time interval between the flip edges of the flip time series. This is the oversampling factor, which is the average number of segments in a single original signal period.

6. A jitter generation circuit according to claim 5, characterized in that, The method for generating the output sequence is as follows: The initial state of the output sequence is consistent with the first bit of the target code pattern, and subsequently in each discretized time sequence... The moment is flipped.

7. A jitter propagation and tolerance measurement circuit, used to measure the jitter propagation and jitter tolerance of a circuit under test after jitter is injected through a jitter generation circuit as described in any one of claims 1-6, characterized in that, include: A transmitter used to generate and transmit signals with jitter; The circuit under test is used to receive jittered signals and generate output signals. The receiver is used to sample the output signal and calculate the propagation and tolerance of jitter based on the sampling results; The clock module is used to generate clock signals for the transmitter and receiver.

8. The jitter transmission and tolerance measurement circuit according to claim 7, characterized in that, The method for calculating the jitter transmission is as follows: ; in, For jitter transmission, and These are output jitter and input jitter, respectively.

9. The jitter transmission and tolerance measurement circuit according to claim 8, characterized in that, Inject jitter at different jitter frequencies and calculate the jitter transmission. Based on the correspondence between the jitter frequency and the jitter transmission, establish a functional relationship graph of jitter frequency and jitter transmission.

10. The jitter transmission and tolerance measurement circuit according to claim 7, characterized in that, The method for calculating the jitter tolerance at different jitter frequencies is as follows: The jitter is generated with the initial jitter amplitude as the amplitude of the target jitter. Check if the output signal has a bit error. If a bit error occurs, record the jitter tolerance as less than the target jitter amplitude. If no bit error occurs, increase the target jitter amplitude and repeat the current step until a bit error occurs.

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