A programmable digital delay circuit
The programmable digital delay circuit, which uses a series delay module and a multiplexer, solves the problems of complex delay circuit structure and high power consumption in the prior art. It achieves flexible delay adjustment and low power consumption, is suitable for FPGA and ASIC design, and improves delay resolution and circuit efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- HANGZHOU SDIC MICROELECTRONICS
- Filing Date
- 2025-06-09
- Publication Date
- 2026-06-02
AI Technical Summary
Existing digital circuit delay circuits suffer from problems such as complex structure, poor dynamic adjustment flexibility, narrow delay adjustment range, and high power consumption.
A programmable digital delay circuit consisting of N basic modules connected in series is adopted. Each basic module includes a delay module and a 2-to-1 multiplexer. The delay is dynamically adjusted by enabling the port through control signals. The delay chain consists of a standard unit inverter chain, a NAND gate chain, a NOR gate chain, or a segmented delay line. Logic AND and OR gates are used to shield the input signals of the unenabled delay module.
It achieves simple circuitry, configurable delay, high flexibility, and low power consumption, making it suitable for FPGA and ASIC designs, as well as high-frequency communication and clock synchronization scenarios. The delay resolution reaches the sub-nanosecond level, saving MUX units and reducing power consumption.
Smart Images
Figure CN224319341U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of digital circuit technology, and in particular to a programmable digital delay circuit. Background Technology
[0002] In the field of digital circuits, scenarios requiring signal delay processing are frequently encountered. Traditional delay circuits are mostly implemented using analog circuit technology, requiring passive components such as resistors and capacitors, resulting in complex structures that are not suitable for implementation in digital circuits. Purely digital logic delay circuits are relatively rare, and existing digital delay circuits suffer from poor dynamic adjustment flexibility, narrow delay adjustment range, and high power consumption.
[0003] Therefore, there is an urgent need for a new programmable digital delay circuit to solve the above-mentioned defects. Utility Model Content
[0004] The purpose of this invention is to provide a programmable digital delay circuit to address the shortcomings of existing technologies.
[0005] The objective of this invention is achieved through the following technical solution: a programmable digital delay circuit, composed of N basic modules connected in series. Each basic module includes a delay module and a 2-to-1 multiplexer. Each 2-to-1 multiplexer is configured with two input ports, one output port, and a control signal enable port. In each basic module, the input terminal of the delay module and one input port of the 2-to-1 multiplexer are connected to the input terminal of the current basic module to receive the input signal of the current basic module. The output terminal of the delay module is connected to the other input port of the 2-to-1 multiplexer. The control signal enable port of the 2-to-1 multiplexer receives a control signal to select one input signal from multiple input signals. The output terminal of the 2-to-1 multiplexer outputs the selected input signal and uses it as the input signal for the next basic module.
[0006] Furthermore, the delay module consists of a delay chain;
[0007] Wherein, the delay chain is a delay chain composed of one or more of the following: a standard cell inverter chain, a NAND gate chain, and a NOR gate chain; or,
[0008] The delay chain is a delay chain composed of standard cell buffers; or...
[0009] The delay chain is a delay chain composed of standard unit delay units; or...
[0010] The delay chain is a delay chain composed of segmented delay lines connected in series.
[0011] Furthermore, the basic module also includes an AND gate or an OR gate, the two inputs of which are respectively connected to the input port and the control signal enable port of the basic module, and the output of which is connected to the input of the delay module inside the basic module.
[0012] Furthermore, the delay circuit also includes a multiplexer, which selects one tap at the input node of the first basic module and one tap at the output node of the last basic module, and selects multiple taps at other positions on the cascade chain of basic modules. All selected taps are connected one-to-one to the multiple input terminals of the multiplexer, and the output terminal of the multiplexer is the output of the delay circuit.
[0013] Furthermore, the multiplexer includes a 4-to-1 multiplexer, an 8-to-1 multiplexer, and a 16-to-1 multiplexer.
[0014] Compared with the prior art, the beneficial effects of this utility model are:
[0015] (1) This utility model uses combinational logic to implement the delay. The delay circuit is implemented by pure digital logic circuit. The circuit scheme is simple and only requires combinational logic units. It does not require flip-flops, counters, or high-frequency clock sources, thus avoiding the involvement of analog components (such as capacitors, current sources, etc.). The circuit is easy to port and can be implemented in FPGA and ASIC designs. It is suitable for high-frequency communication, clock synchronization, sensor signal processing and other scenarios, and has outstanding practical application value.
[0016] (2) The present invention can realize the delay of the input signal by configuring the path selection. When the control signal received by the control signal enable terminal of the two-to-one multiplexer of each basic module is updated, the delay circuit can adjust the path in real time. The adjustment time is short and depends on the response speed of the logic gate, and does not depend on the high frequency clock. The delay time of the delay circuit is dynamically configurable and has higher configuration flexibility than the existing delay circuit.
[0017] (3) When the delay time lengths of delay modules 1 to N in this invention are distributed in a power-of-2 multiple relationship, the delay stage of the overall delay circuit can reach 2. N The range is adjustable with a wide adjustment range, offering greater configuration flexibility; compared to common single-chain delay circuits, it achieves 2 N By adjusting the delay length, a significant number of intermediate taps can be saved, thereby saving a large number of MUX units.
[0018] (4) The delay resolution of this utility model depends on the granularity of the delay module. The delay time length of the shortest delay module is taken as the basic granularity. If the delay of a single unit on the delay chain is smaller or the delay chain is shorter, the granularity is smaller, and thus the delay resolution is higher. Furthermore, when the semiconductor process node reaches 45nm, the switching speed and signal transmission speed of the circuit are greatly improved, and the delay resolution can reach the sub-nanosecond level.
[0019] (5) This utility model can effectively reduce the power consumption of the overall delay circuit by gating and shielding the input signal of the unused delay module and stopping the flipping of the node signal inside the delay module. Compared with the existing delay circuit, it has lower power consumption. Attached Figure Description
[0020] Figure 1 This is a schematic diagram of the input / output interface of the programmable digital delay circuit of this utility model;
[0021] Figure 2 This is a schematic diagram of the internal implementation of the programmable digital delay circuit of this utility model;
[0022] Figure 3 This is a timing diagram of the input and output signals of the programmable digital delay circuit of this utility model;
[0023] Figure 4 This is a schematic diagram of the low-power management principle of the programmable digital delay circuit of this utility model;
[0024] Figure 5 This is a schematic diagram of the signal transmission path of the programmable digital delay circuit of this utility model under a specific configuration;
[0025] Figure 6 This is a circuit diagram of a 64-level adjustable delay circuit based on an exponential delay distribution.
[0026] Figure 7 It is an existing circuit diagram of a 64-step adjustable delay circuit based on 64 taps;
[0027] Figure 8 This is an example diagram of the optimized and adjusted delay circuit of this utility model. Detailed Implementation
[0028] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.
[0029] The present invention will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features of the following embodiments and implementation methods can be combined with each other.
[0030] like Figure 2 As shown, the programmable digital delay circuit of this invention consists of N basic modules connected in series. The more basic modules connected in series, i.e., the larger the value of N, the larger the adjustable delay range. Each basic module includes a delay (DELAY, DLY) module and a 2-to-1 multiplexer (MUX). Each 2-to-1 multiplexer is configured with two input ports, one output port, and one control signal enable port. Specifically, in each basic module, the input terminal of the delay module and one input port of the 2-to-1 multiplexer are connected to the input terminal of the current basic module to receive the input signal of the current basic module; the output terminal of the delay module is connected to the other input port of the 2-to-1 multiplexer; the control signal enable port of the 2-to-1 multiplexer receives a control signal to select one input signal from multiple input signals; the output terminal of the 2-to-1 multiplexer outputs the selected input signal and uses it as the input signal for the next basic module.
[0031] It should be understood that a MUX is a basic combinational logic unit in digital circuits, used to select one output from multiple input signals. In ASIC (Field-Programmable Gate Array) and FPGA (Application-Specific Integrated Circuit) designs, the MUX is a core component for implementing key functions such as data path, logic control, and timing optimization.
[0032] like Figure 2As shown, each of the basic modules 1 to N is configured with a control signal enable port. When the control signal DLY_EN received by its internal 2-to-1 multiplexer is valid (e.g., active high), the input signal flows through its internal delay module and finally reaches the output of the basic module, thus achieving signal delay. The signal delay time of the entire delay circuit is equal to the sum of the delay times of all delay modules through which the input signal flows. The circuit structures of basic modules 1 to N are basically the same, with the only difference being the delay time length of each delay module. The 2-to-1 multiplexer is a basic digital circuit logic unit that selects between two input signals through the control signal enable port. For basic modules 1 to N: when DLY_EN is valid, the 2-to-1 multiplexer selects the signal processed by the delay module as the output; when DLY_EN is invalid, the 2-to-1 multiplexer selects the signal that has not been processed by the delay module as the output, meaning the input signal is directly output through the 2-to-1 multiplexer.
[0033] like Figure 1 As shown, the delay circuit has one input signal port, one output signal port, and N control signal enable ports. The input signal is input to the internal delay circuit via the input signal port. By properly configuring the control signal DLY_EN[N:1] to the control signal enable port, the internal delay module is activated, thereby achieving delay processing of the input signal. Figure 3 As shown, the output signal and input signal of the delay circuit are in phase. The output signal is obtained by delaying the input signal, without inverting it.
[0034] Furthermore, regarding the distribution of delay time lengths for each delay module in the basic modules 1 to N, the delay times of each delay module can be the same or different. When the delay times of each delay module are different, the delay time length of each delay module can exhibit an exponential distribution. Specifically, assuming the delay time length of the first delay module is 1x delay (X1), then the delay time lengths of subsequent delay modules are successively 2x delay (X2), 4x delay (X4), 8x delay (X8), ..., 2x delay. N-1 Double delay (X2) N-1 Of course, when the delay times of each delay module are different, assuming that the delay time of a certain delay module is the shortest, then the delay times of the other delay modules can be integer multiples of the shortest delay time of that module, and this multiple can be any integer. The final delay time of the delay circuit is the sum of the delay times of the delay modules that are enabled by the controlled signal.
[0035] Furthermore, the delay module consists of delay chains. The delay chains preferably utilize unit devices whose delay time is minimally affected by PVT (Process, Voltage, Temperature) conditions; otherwise, delay accuracy will be compromised. The delay chain can be composed of one or more of the following: a standard unit inverter chain, a NAND gate chain, or a NOR gate chain. In this delay chain, the number of gates connected in series is even to maintain the input and output signals of the delay module in phase. Alternatively, the delay chain can be composed of standard unit buffers. In this delay chain, the number of gates connected in series can be arbitrary, as long as the input and output signals of the delay module are kept in phase. Alternatively, the delay chain can be composed of standard unit delay cells. In this delay chain, the number of gates connected in series can be arbitrary, as long as the input and output signals of the delay module are kept in phase. Alternatively, the delay chain can be composed of segmented delay lines connected in series; this type of delay chain is suitable for FPGA scenarios.
[0036] Furthermore, the delay resolution of a delay circuit depends on the granularity of the delay modules. Assuming a delay module has the shortest delay time, and using that shortest delay time as the basic granularity, the smaller the delay time of individual units in the delay chain, or the shorter the delay chain, the smaller the granularity, and thus the higher the delay resolution. Smaller granularity results in smaller overall delay granularity for the delay circuit, and vice versa.
[0037] In this embodiment, an external master controller can be used to configure the control signals DLY_EN[N:1] input to the N control signal enable ports of the delay circuit. Based on the configured control signals DLY_EN[N:1], the delay circuit automatically selects the signal path. Different paths traversed by the input signal result in different numbers of delay modules passed through, leading to different cumulative delay times, thus achieving a programmable and configurable delay time. By configuring the control signals DLY_EN[N:1] appropriately, the delay time can be flexibly adjusted.
[0038] like Figure 5 As shown, assuming the delay circuit contains 4 basic modules, and DLY_EN[N:1] is configured as 0101B, the signal flow path from input IN to output OUT is as follows. Figure 5As shown. Specifically, since the high level is active and the configured control signal is 0101B, the control signal DLY_EN[1] = 1 received by the 2-to-1 multiplexer inside the basic module 1, the input signal IN is input to the basic module 2 after passing through the delay module 1 and the 2-to-1 multiplexer inside the basic module 1; while the control signal DLY_EN[2] = 0 received by the 2-to-1 multiplexer inside the basic module 2, the signal input to the basic module 2 is directly output through the 2-to-1 multiplexer and then enters the basic module 3; similarly, the input signal is input to the basic module 4 after passing through the delay module 3 and the 2-to-1 multiplexer inside the basic module 3 in sequence, and the signal input to the basic module 4 is directly output through the 2-to-1 multiplexer, finally realizing the delay of the input signal. The delay time length is the sum of the delay time length of the delay module 1 and the delay time length of the delay module 3.
[0039] It's important to note that the time required from input to output depends on the specific circuit manufacturing process. More advanced process nodes result in shorter latency for logic unit devices, thus reducing the overall path latency. For example, in a 180nm process, the latency of a single logic gate is in the 1-3 nanosecond range; in a 45nm process, the latency of a single logic gate is less than 1 ns.
[0040] exist Figure 6 The delay circuit shown contains six basic modules, namely basic modules 1 to 6. The delay time lengths of the delay modules in these six basic modules are distributed exponentially. Taking the delay time length of the delay module in basic module 1 as the baseline (X1), the delay time lengths of the delay modules in basic modules 2 to 6 are respectively 2 times (X2), 4 times (X4), 8 times (X8), 16 times (X16), and 32 times (X32) of the baseline delay. By configuring DLY_EN[6:1], the overall delay circuit can achieve 2 6 =64 delay levels.
[0041] Commonly available 64-level adjustable delay circuits, such as Figure 7 As shown, 64 taps need to be taken from the delay chain composed of 64 delay modules, and the 64 signals need to be sent to the subsequent 64-to-1 multiplexer to select one signal from the 64 signals for output.
[0042] contrast Figure 6 and Figure 7 To achieve the same number of delay levels, the two delay circuits shown should... Figure 6 It consumed 6 binary MUXs. However, Figure 7 The required multiplexer has as many as 64 inputs. If this 64-to-1 multiplexer is also implemented using a cascaded 2-to-1 MUX, then 63 multiplexers are needed. Figure 6The solution can save 57 dual-choice MUXs. The more selectable options there are, the better. Figure 6 The more MUX options are saved by the scheme shown, the smaller the cumulative delay error caused by the MUX will be.
[0043] In some embodiments, the basic module further includes an AND gate or an OR gate, wherein the two inputs of the AND gate or OR gate are respectively connected to the input port and the control signal enable port of the basic module, and the output of the AND gate or OR gate is connected to the input of the delay module inside the basic module. The control signal controls whether the input signal of the basic module can enter the delay module; that is, the AND gate or OR gate set inside the basic module can shield the input signal of the inactive delay module, thus saving some dynamic power consumption and helping to reduce the power consumption of the delay circuit.
[0044] In such Figure 4 In the delay circuit shown, an AND gate is used to shield the input signals of the disabled delay modules. When an AND gate is used, the control signal DLY_EN is active high; when DLY_EN is low, the input signal is blocked from entering the delay module. Specifically, for a disabled delay module, its corresponding control signal DLY_EN is 0. This control signal DLY_EN is connected to one input of the AND gate, and the output of the AND gate is fixed at 0. Therefore, the input level provided to the delay module is fixed at a low level, and the entire delay chain within the delay module stops level switching. This disables invalid switching actions in the delay module, saving some dynamic power consumption and helping to reduce the overall power consumption of the delay circuit.
[0045] Similarly, an OR gate can be used to shield the input signals of an inactive delay module. When using an OR gate, the control signal DLY_EN is active low; when DLY_EN is high, the input signal is blocked from entering the delay module. Specifically, for an inactive delay module, its corresponding control signal DLY_EN is 1. This control signal DLY_EN is connected to one input of the OR gate, and the output of the OR gate will be fixed at 1. Therefore, the input level provided to the delay module is fixed at a high level, and the entire delay chain within the delay module stops level switching. This disables invalid switching actions in the delay module, saving some dynamic power consumption and helping to reduce the overall power consumption of the delay circuit.
[0046] In some embodiments, the multiplexer itself also experiences path propagation delay during physical implementation. Therefore, when the delay time of the delay module is relatively small, and the delay time of the multiplexer is not negligible relative to the delay time of the delay module, the cumulative error in the total delay time will be significantly larger as the input signal travels through the entire programmable delay circuit to reach the output. This will cause the actual delay time to deviate significantly from the expected value. Optimization adjustments can be made to address this situation. Specifically, in the cascade chain of basic modules, the basic modules with shorter delay times are placed at the beginning. Several taps are appropriately selected in the cascade chain, and a multiplexer is added. One tap is selected at the input node of the first basic module, one tap at the output node of the last basic module, and multiple taps are selected at the remaining positions in the cascade chain. All selected taps are connected to the multiple input terminals of the multiplexer, meaning these selected tap signals are input to the multiple input terminals of the multiplexer. The control signal received by the multiplexer's control signal enable port selects one signal and outputs it through the multiplexer's output terminal. The output terminal of the multiplexer is the output of the delay circuit, and the output signal is the delayed signal.
[0047] Furthermore, multiplexers include 4-to-1 multiplexers, 8-to-1 multiplexers, and 16-to-1 multiplexers, etc.
[0048] The different positions of the taps determine the maximum number of stages the input signal can propagate through in the cascaded chain of basic modules. For example, Figure 8 For the selected tap signal of the four-to-one MUX shown, the path after the tap will be bypassed, thereby shortening the cumulative delay of the two-to-one MUX in the basic module and reducing the overall delay error.
[0049] The shorter the target delay time, the more necessary it is to place taps at the front nodes of the basic module cascade chain. For example, selecting the input node (IN input signal) of basic module 1, the output node of basic module 1, the output node of basic module 2, and the output node of the last basic module, such as... Figure 8 As shown, both long and short delays can be flexibly adapted. The smaller the target delay value, the shorter the path needs to be. The shortest extreme case is where the input signal IN is directly output through a 4-to-1 MUX, with the IN input connected to the 4-to-1 MUX, corresponding to the minimum target delay value. The larger the target delay value, the longer the delay module needs to be used, or multiple delay modules need to be used, with the output of the last basic module connected to the 4-to-1 MUX, corresponding to the maximum target delay value; and different delay lengths can be achieved by adjusting DLY_EN.
[0050] In the digital back-end stage, the actual delay values of each logic unit and wire can be obtained from the timing analysis report. Based on the target delay time value and these timing values, the optimal configuration of the DLY_EN control signal and the 4-to-1 MUX selection control signal can be obtained, thus achieving the optimal delay with minimal error. Specifically, the optimal configuration is considered to be the one where the cumulative delay value of all units along the path the signal traverses from IN to OUT is closest to the target delay value.
[0051] The above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although this utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.
Claims
1. A programmable digital delay circuit, characterized in that, It consists of N basic modules connected in series. Each basic module includes a delay module and a 2-to-1 multiplexer. Each 2-to-1 multiplexer is configured with two input ports, one output port, and a control signal enable port. In each basic module, the input of the delay module and one input port of the 2-to-1 multiplexer are connected to the input of the current basic module to receive the input signal of the current basic module. The output of the delay module is connected to the other input port of the 2-to-1 multiplexer. The control signal enable port of the 2-to-1 multiplexer is used to receive a control signal to select one input signal from multiple input signals. The output of the 2-to-1 multiplexer outputs the selected input signal and uses it as the input signal of the next basic module.
2. The programmable digital delay circuit according to claim 1, characterized in that, The delay module consists of a delay chain; Wherein, the delay chain is a delay chain composed of one or more of the following: a standard cell inverter chain, a NAND gate chain, and a NOR gate chain; or, The delay chain is a delay chain composed of standard cell buffers; or... The delay chain is a delay chain composed of standard unit delay units; or... The delay chain is a delay chain composed of segmented delay lines connected in series.
3. The programmable digital delay circuit according to claim 1, characterized in that, The basic module also includes an AND gate or an OR gate. The two inputs of the AND gate or OR gate are connected to the input port and the control signal enable port of the basic module, respectively. The output of the AND gate or OR gate is connected to the input of the delay module inside the basic module.
4. The programmable digital delay circuit according to claim 1, characterized in that, The delay circuit also includes a multiplexer, which selects one tap at the input node of the first basic module and one tap at the output node of the last basic module, and selects multiple taps at other positions on the cascade chain of basic modules. All selected taps are connected one-to-one to the multiple input terminals of the multiplexer, and the output terminal of the multiplexer is the output of the delay circuit.
5. The programmable digital delay circuit according to claim 4, characterized in that, The multiplexers include 4-to-1 multiplexers, 8-to-1 multiplexers, and 16-to-1 multiplexers.