Bus-based data transmission method, apparatus, device, and storage medium

Abstract

This invention relates to a bus-based data transmission method, apparatus, device, and storage medium. The bus-based data transmission method includes: when a signal edge is detected before the start of a synchronization segment of the next bit time on the bus, acquiring a sampling sequence obtained from multiple samplings, the sampling sequence being used to characterize the quality of the signal edge; determining a target bit synchronization strategy from among several preset bit synchronization strategies based on the sampling sequence, different bit synchronization strategies defining different bit segment adjustment methods; and adjusting a target phase buffer segment of the current bit time for data transmission based on the target bit synchronization strategy, the target phase buffer segment being the interval preceding the synchronization segment. This application evaluates signal quality through the sampling sequence and adopts a corresponding synchronization strategy based on the evaluation result, realizing dynamic adjustment of bit synchronization, effectively reducing synchronization errors caused by noise, and further improving the stability and reliability of data transmission.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a bus-based data transmission method, apparatus, device, and storage medium. Background Technology

[0002] In Controller Area Network (CAN) bus systems, bit synchronization mechanisms primarily rely on accurate detection of signal edges. However, in complex environments, random noise can generate interference signals with steeply falling edges. When such interference signals appear after the end of Phase Buffer Segment 1 (PS1) and before the start of the Synchronization Segment (SS), the receiving node may misinterpret them as valid synchronization edges.

[0003] Currently, the relevant synchronization mechanism cannot distinguish whether the synchronization edge is a genuine synchronization deviation caused by transmission delay or a spurious signal generated by noise interference. It will treat it as a synchronization deviation and trigger a resynchronization process in Phase Buffer Segment 2 (PS2). This false triggering will cause the PS2 segment to be shortened unnecessarily, thereby disrupting the established stable bit timing relationship, causing sampling point offset, and seriously threatening the stability and reliability of data transmission. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of this disclosure provide a bus-based data transmission method, apparatus, device, and storage medium.

[0005] In a first aspect, embodiments of this disclosure provide a bus-based data transmission method, including: When a signal edge is detected before the start of the synchronization segment of the next bit time on the bus, a sampling sequence obtained from multiple samplings is acquired, wherein the sampling sequence is used to characterize the quality of the signal edge. Based on the sampling sequence, the target bit synchronization strategy is determined from a variety of preset bit synchronization strategies, where different bit synchronization strategies define different bit segment adjustment methods; The target phase buffer segment of the current bit time is adjusted based on the target bit synchronization strategy for data transmission. The target phase buffer segment is the interval preceding the synchronization segment.

[0006] Optionally, based on the sampling sequence, a target bit synchronization strategy is determined from a set of preset bit synchronization strategies, including: Analyze the sampled sequence to determine at least one feature related to the signal edge; based on the at least one feature, determine the target bit synchronization strategy among multiple bit synchronization strategies; or... The sampled sequence is compared with multiple preset reference sequences, and the target bit synchronization strategy is determined from multiple bit synchronization strategies based on the comparison results. Different reference sequences correspond to different bit synchronization strategies.

[0007] Optionally, based on the comparison results, a target bit synchronization strategy is determined from multiple bit synchronization strategies, including: If the comparison result shows that the sampling sequence is the first sequence, then the first synchronization strategy is determined as the target bit synchronization strategy. The first sequence is used to indicate that the signal edge is a valid synchronization edge. The first synchronization strategy refers to reducing the duration or bit width of the target phase buffer segment to compensate for the phase error of the signal edge.

[0008] Optionally, based on the comparison results, a target bit synchronization strategy is determined from multiple bit synchronization strategies, including: If the comparison result shows that the sampling sequence is the second sequence, then the second bit synchronization strategy is determined as the target bit synchronization strategy. The second sequence is used to indicate that the signal edge is an edge affected by the first degree of interference. The second bit synchronization strategy refers to adjusting the duration or bit width of the target phase buffer segment based on the first synchronization strategy.

[0009] Optionally, based on the comparison results, a target bit synchronization strategy is determined from multiple bit synchronization strategies, including: If the comparison result shows that the sampling sequence is the third sequence, then the third bit synchronization strategy is determined as the target bit synchronization strategy. The third sequence is used to indicate that the signal edge is an edge affected by the second level of interference. The third bit synchronization strategy means that the duration or bit width of the target phase buffer segment is not adjusted, and the second level of interference is higher than the first level of interference.

[0010] Optionally, after determining the second bit synchronization strategy as the target bit synchronization strategy, the method further includes: Based on the sampling sequence, determine the interference intensity level of the signal edge affected by the first level of interference; Query the preset synchronization adjustment mapping table to obtain the target adjustment amount of the time share or bit segment corresponding to the interference intensity level; the synchronization adjustment mapping table defines the correspondence between different interference intensity levels and different reduction amounts; Update the phase error compensation value in the target bit synchronization strategy to the target adjustment amount.

[0011] Optionally, the target phase buffer segment of the current bit time is adjusted for data transmission based on the target bit synchronization strategy, including: The counting logic of the time segment counter is adjusted according to the phase error compensation value in the target bit synchronization strategy; When the segment synchronization flag indicates that the target phase buffer segment has been entered, the actual count value of the target phase buffer segment is adjusted according to the phase error compensation value to adjust the segment width. When the sampling point trigger signal in the bit segment synchronization flag is valid, sampling is performed at the sampling point position of the target phase buffer segment to complete data transmission.

[0012] Secondly, embodiments of this disclosure provide a bus-based data transmission device, including: The acquisition unit is used to acquire a sampling sequence obtained from multiple samplings when a signal edge is detected before the start of the synchronization segment of the next bit time of the bus. The sampling sequence is used to characterize the quality of the signal edge. The determining unit is used to determine the target bit synchronization strategy from a variety of preset bit synchronization strategies based on the sampling sequence, wherein different bit synchronization strategies define different bit segment adjustment methods; The adjustment unit is used to adjust the target phase buffer segment of the current bit time based on the target bit synchronization strategy for data transmission, wherein the target phase buffer segment is the previous interval of the synchronization segment.

[0013] Thirdly, embodiments of this disclosure provide an electronic device, including: Memory; Processor; and Computer programs; The computer program is stored in memory and configured to be executed by a processor to implement the first aspect of the method described above.

[0014] Fourthly, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0015] The bus-based data transmission method disclosed herein includes: when a signal edge is detected before the start of the synchronization segment of the next bit time on the bus, acquiring a sampling sequence obtained from multiple samplings, wherein the sampling sequence is used to characterize the quality of the signal edge; determining a target bit synchronization strategy from a set of preset bit synchronization strategies based on the sampling sequence, wherein different bit synchronization strategies define different bit segment adjustment methods; and adjusting the target phase buffer segment of the current bit time for data transmission based on the target bit synchronization strategy, wherein the target phase buffer segment is the previous interval of the synchronization segment. This application evaluates signal quality through the sampling sequence and adopts a corresponding synchronization strategy based on the evaluation result, realizing dynamic adjustment of bit synchronization, effectively reducing synchronization errors caused by noise, and further improving the stability and reliability of data transmission. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0017] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a sampling point in a bus provided by an embodiment of the present disclosure; Figure 2 A schematic flowchart illustrating a bus-based data transmission method provided in an embodiment of this disclosure; Figure 3 A schematic diagram of synchronization compensation provided for an embodiment of this disclosure; Figure 4 Another schematic diagram of synchronization compensation provided for an embodiment of this disclosure; Figure 5 Another schematic diagram of synchronization compensation provided for embodiments of this disclosure; Figure 6 A schematic flowchart illustrating a bus-based data transmission method provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the structure of a synchronization compensation module provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of a bus-based data transmission device provided in an embodiment of this disclosure; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0019] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0020] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0021] Specifically, CAN is a bus communication protocol proposed for automotive electronics to address the rapid development of the automotive industry and the significantly increased complexity of automotive electronic systems. Various control units (such as engine management systems, braking systems, and air conditioning control systems) need to achieve data sharing and collaborative operation. In the bit timing synchronization mechanism of the CAN bus, the boundary between phase buffer segment 1 (PS1) and phase buffer segment 2 (PS2) is defined as the ideal sampling point. The sampling method directly affects the accuracy of data reception and is mainly divided into two modes: single sampling and triple sampling. Single sampling only performs signal acquisition once at the ideal sampling point, which is simple but has limited anti-interference capability. Triple sampling, on the other hand, performs signal acquisition at three positions: the time quantum before the ideal sampling point (TQ), the ideal sampling point itself, and the time quantum after the ideal sampling point. It improves sampling stability by using the principle of "majority rule" (i.e., two or more identical sample values ​​are used as the final result). Specifically, as shown below... Figure 1 The diagram shown illustrates three sampling operations between PS1 and PS2.

[0022] In industrial automation scenarios, CAN buses need to maintain stable communication in multi-node, long-distance, and high-noise environments. However, traditional controllers are susceptible to noise interference during data transmission, leading to decreased sampling accuracy. Specifically, during CAN bus data transmission, factors such as transmission delay and noise interference can cause a discrepancy between the falling edge position detected by the receiving node and the actual falling edge position of the sending node, resulting in bit synchronization imbalance. This requires a resynchronization (also known as "soft synchronization") mechanism to correct the deviation and ensure sampling accuracy. However, in high-noise environments, interference signals may simulate the falling edge characteristics of real signals, causing the receiving node to falsely detect a spurious falling edge indicating synchronization. Currently, related technologies cannot distinguish whether this falling edge is a genuine synchronization deviation caused by transmission delay or a spurious signal generated by noise interference. This directly triggers the synchronization process, causing unnecessary bit segment shortening, which disrupts the originally stable bit timing relationship, leading to sampling point offset and threatening the stability and reliability of data transmission.

[0023] To address the aforementioned technical problems, this disclosure provides a bus-based data transmission method that adaptively adjusts the synchronization strategy for the transmission environment to resolve synchronization inaccuracies caused by noise, reduce the impact of noise interference on the CAN bus during data transmission, and ensure the stability and reliability of data transmission. This will be described in detail through one or more of the following embodiments.

[0024] The bus-based data transmission method provided in this disclosure is applicable to bus-based data transmission scenarios. This method can be executed by a bus-based data transmission device, which can be implemented in software and / or hardware and can be integrated into an electronic device. The electronic device can include, but is not limited to, mobile terminals such as smartphones, laptops, digital radio receivers, personal digital assistants (PDAs), tablet computers (Tablet PCs), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable devices, etc., as well as fixed terminals such as digital televisions, desktop computers, smart home devices, etc.

[0025] Figure 2 A flowchart illustrating a bus-based data transmission method provided in this disclosure embodiment specifically includes, as follows: Figure 2 The following steps are shown: S201. When a signal edge is detected before the start of the synchronization segment of the next bit time on the bus, acquire the sampling sequence obtained from multiple samplings.

[0026] The sampling sequence is used to characterize the quality of the signal edges.

[0027] Understandable, such as Figure 1 As shown, the bit time of the bus includes a synchronization segment (SS), phase buffer segment 1 (PS1), and phase buffer segment 2 (PS2). When a signal edge is detected before the start of the synchronization segment of the next bit time, multiple samples are taken at a set sampling point to obtain a sampling sequence. The signal edge can be detected within the interval of phase buffer segment 2 of the current bit time, for example, the interval after the end of phase buffer segment 1 of the current bit time and before the start of the synchronization segment of the next bit time. The signal edge can be understood as a falling edge or a transition edge. Multiple sampling can be three samplings, and the sampling sequence is a sequence composed of the results of the three samplings, such as 000, 010, and 011. The sampling sequence can characterize the quality, reliability, or effectiveness of the signal edge. A high-quality edge should have a clear transition time and a clean and stable level after the transition, which can reliably indicate the bit boundary, that is, the true synchronization deviation caused by the transmission delay. Low-quality edges become blurred, jittery, or distorted due to interference, and may not accurately reflect the true synchronization information, that is, a false synchronization signal caused by interference signals.

[0028] S202. Based on the sampling sequence, determine the target bit synchronization strategy from among the preset multiple bit synchronization strategies.

[0029] Different bit synchronization strategies define different bit segment adjustment methods.

[0030] Understandably, based on the above S201, the sampled sequence is compared with the applicable conditions of each of the preset bit synchronization strategies to determine a target bit synchronization strategy suitable for the transmission scenario. The bit synchronization strategy explicitly specifies the method to be adjusted in the phase buffer segment. For example, the strategy may include parameters such as the adjusted bit segment (e.g., phase buffer segment 1 or 2), the adjustment direction (extending or shortening), and the adjustment amount; that is, the synchronization strategy is dynamically determined. In one embodiment, one strategy is defined as "extending phase buffer segment 1 by 2 TQ", while another strategy may be defined as "shortening phase buffer segment 2 by 1 TQ".

[0031] S203. Adjust the target phase buffer segment of the current bit time based on the target bit synchronization strategy to perform data transmission.

[0032] The target phase buffer segment is the interval preceding the synchronization segment.

[0033] Understandably, based on the above S202, according to the rules defined by the target bit synchronization strategy, the duration or bit segment of the target phase buffer segment in the current bit time is adjusted to optimize or correct the sampling point position of the next bit time. This ensures that the sampling point is always located in a stable and reliable area of ​​the bus level, avoiding falling on signal edges or interference periods, thereby ensuring that the sampled level can be correctly determined. Each correctly determined sampling point (0 or 1) ultimately constitutes a complete and accurate data frame transmission. The target phase buffer segment refers to a specific stage in the current bit time whose length or duration needs to be dynamically changed according to the synchronization strategy; it is the object of the resynchronization operation. For example, shortening phase buffer segment 2 by 2 TQs allows the counting of PS2 to end 2 TQs earlier, thus immediately entering the next bit time and reducing synchronization errors. This method, by dynamically fine-tuning the duration of the target phase buffer segment, compensates in real time for phase errors caused by node deviation, transmission delay, and noise interference, locking the sampling point at the position with the optimal signal quality within each bit time. This significantly improves the accuracy of bit decision-making in complex electromagnetic environments, ensuring the stability and reliability of data transmission in the CAN bus system.

[0034] Optionally, based on the sampling sequence, a target bit synchronization strategy is determined from a set of preset bit synchronization strategies, including: Analyze the sampled sequence to determine at least one feature related to the signal edge; determine a target bit synchronization strategy among multiple bit synchronization strategies based on the at least one feature; or compare the sampled sequence with multiple preset reference sequences and determine the target bit synchronization strategy among multiple bit synchronization strategies based on the comparison results, wherein different reference sequences correspond to different bit synchronization strategies.

[0035] Understandably, real-time signals are objectively evaluated based on feature analysis or pattern comparison to accurately identify specific patterns of signal anomalies and adaptively select the optimal and most targeted synchronization strategy accordingly. Specifically, in one embodiment, the acquired sampling sequence undergoes signal processing to extract feature information that quantifies the characteristics of the edge waveform, such as edge steepness, jitter, and level stability. Subsequently, the feature information is matched with the applicable conditions of each bit synchronization strategy according to a preset decision logic, thereby selecting the target bit synchronization strategy most suitable for the signal condition. The decision logic can be a lookup of a mapping table consisting of feature value ranges and strategy indices, or a calculation function. In another embodiment, the real-time acquired sampling sequence is compared with a reference sequence (e.g., by calculating correlation coefficients, mean square errors, etc.). The reference sequence represents an idealized or representative waveform template of typical signal conditions (e.g., clean edges, slight interference, severe interference, etc.), and each waveform template corresponds to a bit synchronization strategy. Then, the bit synchronization strategy bound to the reference sequence with the highest similarity is selected as the target bit synchronization strategy.

[0036] Optionally, based on the comparison results, a target bit synchronization strategy is determined from multiple bit synchronization strategies, including: If the comparison result shows that the sampling sequence is the first sequence, then the first synchronization strategy is determined as the target bit synchronization strategy. The first sequence is used to indicate that the signal edge is a valid synchronization edge. The first synchronization strategy refers to reducing the duration or bit width of the target phase buffer segment to compensate for the phase error of the signal edge.

[0037] Understandably, the sampled sequence is compared with the reference sequence. If the comparison result is that the sampled sequence is the first sequence, for example, the sampled sequence obtained by three samplings at the transmitting node is 000 or 001, then the first synchronization strategy is determined as the target bit synchronization strategy. The first sequence is used to indicate that the signal edge is a valid synchronization edge, that is, it is a normal synchronization signal generated by the transmission delay. The first synchronization strategy can be the PS2 synchronization strategy. Its core logic is: when the receiving node's synchronization segment is advanced, the timing deviation is corrected by shortening the length of PS2. The maximum shortening of PS2 is limited by the synchronization jump width (SJW). The maximum value of SJW is 4TQ and the minimum value is 1TQ.

[0038] For example, Figure 3 This disclosure provides a synchronization compensation schematic diagram, mainly a 000 or 001 type synchronization compensation schematic diagram. When a transition edge satisfying the synchronization condition is detected (e.g., ... Figure 3 When the arrow in the PS2 bit field of the transmitting node changes from 1 to 0, 000 is collected after 3 samplings. Adjustments are made according to the standard PS2 synchronization rules, combined with SJW limitations, such as... Figure 3 As shown, the current phase error is 5TQ, and SJW is set to 2TQ. In this case, PS2 is shortened by 2TQ to complete PS2 synchronization. In one embodiment, when a transition edge is detected, the data collected at the corresponding acquisition point (the first acquisition point) is recorded as 0, and the data for the subsequent 2TQ (the second and third acquisition points) are collected to obtain the acquisition sequence.

[0039] Optionally, based on the comparison results, a target bit synchronization strategy is determined from multiple bit synchronization strategies, including: If the comparison result shows that the sampling sequence is the second sequence, then the second bit synchronization strategy is determined as the target bit synchronization strategy. The second sequence is used to indicate that the signal edge is an edge affected by the first degree of interference. The second bit synchronization strategy refers to adjusting the duration or bit width of the target phase buffer segment based on the first synchronization strategy.

[0040] Understandably, if the comparison result shows that the sampling sequence is the second sequence, for example, the sampling sequence obtained by three samplings at the transmitting node is 010, then the second bit synchronization strategy is determined as the target bit synchronization strategy. Here, the second sequence is used to indicate that the signal edge is an edge affected by the first degree of interference, that is, a signal edge caused by slight interference. The second bit synchronization strategy refers to adjusting the duration or bit width of the target phase buffer segment based on the first synchronization strategy (conventional PS2 synchronization strategy). For example, if the first synchronization strategy is to shorten by 2TQ, the second bit synchronization strategy will continue to shorten it by 1TQ (a total of 3TQ), or the second bit synchronization strategy will increase it by 1TQ (a total of 1TQ), that is, reduce the shortening amount of the first synchronization strategy. In other words, the second bit synchronization strategy is to redetermine the reduction amount based on the first synchronization strategy.

[0041] For example, Figure 4 Another synchronization compensation diagram provided for this embodiment is mainly a 010 type synchronization compensation diagram. When a falling edge (changing from 1 to 0) that meets the synchronization condition is detected, 010 is acquired after 3 samplings. Based on the normal synchronization of type 000, the PS2 shortening amplitude of 1 TQ is reduced, as shown below. Figure 4 As shown, normally it needs to be shortened by 2TQ, but here it only needs to be shortened by 1TQ.

[0042] Optionally, based on the comparison results, a target bit synchronization strategy is determined from multiple bit synchronization strategies, including: If the comparison result shows that the sampling sequence is the third sequence, then the third bit synchronization strategy is determined as the target bit synchronization strategy. The third sequence is used to indicate that the signal edge is an edge affected by the second level of interference. The third bit synchronization strategy means that the duration or bit width of the target phase buffer segment is not adjusted, and the second level of interference is higher than the first level of interference.

[0043] Understandably, if the comparison result is that the sampling sequence is the third sequence, for example, the sampling sequence obtained by three samplings at the transmitting node is 011, then the third bit synchronization strategy is determined as the target bit synchronization strategy. The third sequence is used to indicate that the signal edge is an edge affected by the second degree of interference, that is, the signal edge generated by severe interference (such as a false synchronization signal generated by noise interference). The third bit synchronization strategy means that the duration or bit width of the target phase buffer segment is not adjusted, and the current timing parameters are maintained. The second degree of interference (severe interference) is higher than the first degree of interference (slight interference).

[0044] For example, Figure 5 Another synchronization compensation diagram provided for the embodiments of this disclosure is mainly a 011 type synchronization compensation diagram. When a falling edge (changing from 1 to 0) that meets the synchronization condition is detected, 011 is collected after 3 samplings, a cancel synchronization command is sent, the PS2 bit segment length is not adjusted, the current bit timing parameters are maintained, and the bit segment synchronization flag remains in its original state.

[0045] Optionally, after determining the second bit synchronization strategy as the target bit synchronization strategy, the method further includes: Based on the sampling sequence, determine the interference intensity level of the signal edge affected by the first level of interference; Query the preset synchronization adjustment mapping table to obtain the target adjustment amount of the time share or bit segment corresponding to the interference intensity level; the synchronization adjustment mapping table defines the correspondence between different interference intensity levels and different reduction amounts; update the phase error compensation value in the target bit synchronization strategy to the target adjustment amount.

[0046] Understandably, for signal edges experiencing first-degree interference (i.e., slight interference), the adjustment amount can be set more finely and dynamically. Specifically, further analysis of the sampling sequence (such as calculating the proportion of unstable sampling points and evaluating the amplitude of level fluctuations near the edges) quantifies the first-degree interference into more refined, discrete interference intensity levels. A pre-built synchronization adjustment mapping table is consulted to determine the target adjustment amount corresponding to the interference intensity level. This mapping table can define different correspondences between interference intensity levels and the number of TQs or the bit segment length. After obtaining the target adjustment amount, it is assigned to the phase error compensation value in the target bit synchronization strategy. This compensation value may initially be a default value or a value calculated according to other rules, and is subsequently dynamically overwritten based on real-time interference intensity analysis. The updated second-bit synchronization strategy then includes the adjustment amount specifically set for the current specific interference scenario. For example, in the synchronization adjustment mapping table, an interference strength level of 1 corresponds to 1 TQ, and an interference strength level of 2 corresponds to 2 TQ. If the first synchronization strategy defines a PS2 reduction of 3 TQ, then for interference strength level 1, PS2 is reduced by 2 TQ (i.e., 3 TQ - 1 TQ), and for interference strength level 2, PS2 is reduced by 1 TQ (i.e., 3 TQ - 2 TQ). This means the TQ to be reduced defined in the first synchronization strategy must be greater than the TQ to be reduced defined in the second synchronization strategy. If the TQ corresponding to the interference strength level is equal to or greater than the TQ to be reduced defined in the first synchronization strategy, then the PS2 bit length is not adjusted. This dynamic setting of the adjustment amount achieves precise matching between the synchronization adjustment amount and the real-time interference strength, avoiding the problems of large adjustments for small interferences or small adjustments for large interferences that may occur with fixed compensation values, making the synchronization adjustment behavior more refined and reasonable.

[0047] Understandably, the phase error compensation value is the amount of correction applied to the bit time phase during the resynchronization process of bit synchronization, and its unit is usually time fraction (TQ). Positive values ​​indicate that the phase buffer needs to be extended to wait for the edge, while negative values ​​(i.e., reduced values) indicate that the phase buffer needs to be shortened to catch up with the edge. It is a direct digital command that the synchronization strategy ultimately applies to the hardware timer.

[0048] Optionally, the target phase buffer segment of the current bit time is adjusted for data transmission based on the target bit synchronization strategy, including: The counting logic of the time quotient counter is adjusted according to the phase error compensation value in the target bit synchronization strategy; when the bit segment synchronization flag indicates entry into the target phase buffer segment, the actual count value of the target phase buffer segment is adjusted according to the phase error compensation value to adjust the bit segment width; when the sampling point trigger signal in the bit segment synchronization flag is valid, sampling is performed at the sampling point position of the target phase buffer segment to complete data transmission.

[0049] Understandably, the phase error compensation value carried in the target bit synchronization strategy is read. This compensation value is usually represented as a signed integer in TQ units. Subsequently, this compensation value is written to the time share counter in the bit timing control unit, dynamically modifying its counting logic. This primarily involves changing the endpoint threshold or offset used in the upcoming bit segment counting process, thus setting preset parameters for subsequent segment length adjustments. The bit timing control unit continuously operates internally, generating bit segment synchronization flags in real time. These flags are a set of high-precision synchronization signals used to indicate the segment currently being executed (such as SS, PS1, PS2, etc.). When this flag indicates that the target phase buffer segment is about to be entered or has already been entered, the previously configured phase error compensation value is immediately invoked to dynamically correct the final count value of that segment. Specifically, the counter, which would normally count to a preset fixed value before ending the segment, ends counting earlier or later based on the compensation value after the counting logic adjustment, thereby adjusting the actual count value of the segment and achieving precise fine-tuning of the bit segment width. If the compensation value is negative (shortening the segment length), the final count value decreases, and the segment width shortens; if it is positive (extending the segment length), the final count value increases, and the segment width extends. The bit timing control unit simultaneously generates a sampling point trigger signal. This signal is a pulse designed to be positioned at a specific location at the end of PS1, representing the only valid moment for the receiving node to read the bus level. In this scenario, since the timing structure of the entire bit has been corrected, the absolute time position of the sampling point trigger signal is also indirectly corrected. When this signal is valid, the receiving circuit immediately performs a deterministic sampling of the bus level and shifts the sampled level value into the receiving shift register, ultimately completing the correct decision for that bit. The accumulation of each bit constitutes a complete data frame, realizing data transmission. By directly mapping the strategy instructions to real-time modifications to the hardware counting logic, dynamic and precise adjustment of the bit segment width is achieved, thereby stably locking the sampling point at the position with optimal signal quality within each bit time.

[0050] This disclosure provides a bus-based data transmission method applied to an automotive CAN controller chip project, adapting to multi-ECU communication scenarios in automotive electronics. By adaptively discriminating the sampling results (e.g., 000 / 010 / 011) of three consecutive TQ bits in the PS2 bit segment, it can accurately distinguish between true synchronization deviations and false falling edges caused by noise interference, and dynamically determine synchronization compensation strategies. For example, synchronization is directly canceled for severe noise signals of type 011, effectively filtering out invalid interference; for slight interference signals of type 010, reduced synchronization is used to avoid over-adjustment, reducing synchronization errors caused by noise at the source, and significantly improving the anti-interference stability of the CAN bus in high electromagnetic noise and long-distance transmission scenarios. Simultaneously, it is compatible with the mainstream CAN2.0 protocol, ensuring stable communication for modules such as engine management and brake control.

[0051] Based on the above embodiments, Figure 6A flowchart illustrating a bus-based data transmission method provided in this embodiment of the disclosure includes the following steps: (1) Start synchronization; (2) Sample at sampling point; (3) TQ count; (4) Synchronization compensation module determines synchronization strategy; (5) Determine bit segment synchronization flag; (6) Adjust bit segment width; (7) Determine actual bit width.

[0052] Understandably, at the start of synchronization, the bit segment synchronization flag is determined through internal BRP counting, TQ counting, and the synchronization compensation module. Based on this flag, corresponding synchronization is then performed to obtain the actual bit width. Specifically, after the synchronization process begins, basic timing counting is first completed using BRP counting (baud rate prescaler counting) and TQ counting (time quantum counting, equivalent to calculating the number of TQs for synchronization). Subsequently, combined with the processing results from the synchronization compensation module, a bit segment synchronization flag is generated. Finally, based on this flag, the corresponding synchronization operation is executed to determine the actual bit width of the data transmission, while simultaneously locating the precise sampling point position to complete the data transmission.

[0053] Based on the above embodiments, Figure 7 This is a schematic diagram of a synchronization compensation module provided in an embodiment of the present disclosure. The synchronization compensation module includes a bit signal, PS2 sampling, TQ counting, and synchronization compensation. Considering the diversity of bit timing synchronization signals, a three-sampling synchronization compensation mechanism is proposed in the synchronization compensation module. When the synchronization condition is met (a falling edge is detected in the PS2 bit segment), each TQ time value is sampled in the PS2 bit segment. When three TQ values ​​are 000, normal PS2 synchronization is performed (reduced by 2 TQ). When three TQ values ​​are 010, PS2 synchronization is reduced by 1 TQ compared to 000 (reduced by 1 TQ). When three TQ values ​​are 011, PS2 synchronization is not performed.

[0054] Figure 8 This is a schematic diagram of a bus-based data transmission device provided in an embodiment of this disclosure. The bus-based data transmission device provided in this embodiment can execute the processing flow provided in the bus-based data transmission method embodiment, such as... Figure 8 As shown, the bus-based data transmission device 800 includes: The acquisition unit 801 is used to acquire a sampling sequence obtained from multiple samplings when a signal edge is detected before the start of the synchronization segment of the next bit time of the bus, wherein the sampling sequence is used to characterize the quality of the signal edge. The determining unit 802 is used to determine the target bit synchronization strategy from a variety of preset bit synchronization strategies based on the sampling sequence, wherein different bit synchronization strategies define different bit segment adjustment methods; The adjustment unit 803 is used to adjust the target phase buffer segment of the current bit time based on the target bit synchronization strategy for data transmission, wherein the target phase buffer segment is the previous interval of the synchronization segment.

[0055] Optionally, the determining unit 802 is used for: Analyze the sampled sequence to determine at least one feature related to the signal edge; based on the at least one feature, determine the target bit synchronization strategy among multiple bit synchronization strategies; or... The sampled sequence is compared with multiple preset reference sequences, and the target bit synchronization strategy is determined from multiple bit synchronization strategies based on the comparison results. Different reference sequences correspond to different bit synchronization strategies.

[0056] Optionally, the determining unit 802 is used for: If the comparison result shows that the sampling sequence is the first sequence, then the first synchronization strategy is determined as the target bit synchronization strategy. The first sequence is used to indicate that the signal edge is a valid synchronization edge. The first synchronization strategy refers to reducing the duration or bit width of the target phase buffer segment to compensate for the phase error of the signal edge.

[0057] Optionally, the determining unit 802 is used for: If the comparison result shows that the sampling sequence is the second sequence, then the second bit synchronization strategy is determined as the target bit synchronization strategy. The second sequence is used to indicate that the signal edge is an edge affected by the first degree of interference. The second bit synchronization strategy refers to adjusting the duration or bit width of the target phase buffer segment based on the first synchronization strategy.

[0058] Optionally, the determining unit 802 is used for: If the comparison result shows that the sampling sequence is the third sequence, then the third bit synchronization strategy is determined as the target bit synchronization strategy. The third sequence is used to indicate that the signal edge is an edge affected by the second level of interference. The third bit synchronization strategy means that the duration or bit width of the target phase buffer segment is not adjusted, and the second level of interference is higher than the first level of interference.

[0059] Optionally, the bus-based data transmission device 800 is used for: Based on the sampling sequence, determine the interference intensity level of the signal edge affected by the first level of interference; Query the preset synchronization adjustment mapping table to obtain the target adjustment amount of the time share or bit segment corresponding to the interference intensity level; the synchronization adjustment mapping table defines the correspondence between different interference intensity levels and different reduction amounts; Update the phase error compensation value in the target bit synchronization strategy to the target adjustment amount.

[0060] Optionally, the adjustment unit 803 is used for: The counting logic of the time segment counter is adjusted according to the phase error compensation value in the target bit synchronization strategy; When the segment synchronization flag indicates that the target phase buffer segment has been entered, the actual count value of the target phase buffer segment is adjusted according to the phase error compensation value to adjust the segment width. When the sampling point trigger signal in the bit segment synchronization flag is valid, sampling is performed at the sampling point position of the target phase buffer segment to complete data transmission.

[0061] Figure 8 The bus-based data transmission device shown in the embodiment can be used to execute the technical solutions of the above method embodiments. Its implementation principle and technical effects are similar, and will not be repeated here.

[0062] Figure 9 This is a schematic diagram of an electronic device provided in an embodiment of the present disclosure. See below for details. Figure 9 The diagram illustrates a structural schematic suitable for implementing the electronic device 900 in the embodiments of this disclosure. The electronic device 900 in the embodiments of this disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, etc., as well as fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 9 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0063] like Figure 9 As shown, the electronic device 900 may include a processing device 901 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 into a random access memory (RAM) 903 to implement the bus-based data transmission method as described in the embodiments of this disclosure. The RAM 903 also stores various programs and data required for the operation of the electronic device 900. The processing device 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0064] Typically, the following devices can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909. Communication device 909 allows electronic device 900 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 9 An electronic device 900 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0065] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts, thereby implementing the bus-based data transmission method as described above. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a storage device 908, or installed from a ROM 902. When the computer program is executed by the processing device 901, it performs the functions defined in the methods of embodiments of this disclosure.

[0066] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0067] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0068] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0069] Optionally, when one or more of the above-described procedures are executed by the electronic device, the electronic device may also perform other steps described in the above embodiments.

[0070] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0071] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0072] The units described in the embodiments of this disclosure can be implemented in software or in hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0073] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0074] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0075] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or gateway that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or gateway. Without further limitations, an element defined by the phrase "comprising a bus-based data transmission" does not exclude the presence of additional identical elements in the process, method, article, or gateway that includes said element.

[0076] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bus-based data transmission method, characterized in that, include: When a signal edge is detected before the start of the synchronization segment of the next bit time of the bus, a sampling sequence obtained from multiple samplings is acquired, wherein the sampling sequence is used to characterize the quality of the signal edge; Based on the sampling sequence, a target bit synchronization strategy is determined from a variety of preset bit synchronization strategies, wherein different bit synchronization strategies define different bit segment adjustment methods; The target phase buffer segment of the current bit time is adjusted based on the target bit synchronization strategy to perform data transmission, wherein the target phase buffer segment is the previous interval of the synchronization segment.

2. The method according to claim 1, characterized in that, The step of determining a target bit synchronization strategy from a set of preset bit synchronization strategies based on the sampling sequence includes: Analyze the sampling sequence to determine at least one feature related to the signal edge; based on the at least one feature, determine a target bit synchronization strategy among multiple bit synchronization strategies; or... The sampled sequence is compared with a variety of preset reference sequences, and the target bit synchronization strategy is determined from a variety of bit synchronization strategies based on the comparison results. Different reference sequences correspond to different bit synchronization strategies.

3. The method according to claim 2, characterized in that, The step of determining the target bit synchronization strategy among multiple bit synchronization strategies based on the comparison results includes: If the comparison result indicates that the sampling sequence is the first sequence, then the first bit synchronization strategy is determined as the target bit synchronization strategy. The first sequence is used to indicate that the signal edge is a valid synchronization edge. The first bit synchronization strategy refers to reducing the duration or bit width of the target phase buffer segment to compensate for the phase error of the signal edge.

4. The method according to claim 3, characterized in that, The step of determining the target bit synchronization strategy among multiple bit synchronization strategies based on the comparison results includes: If the comparison result indicates that the sampling sequence is the second sequence, then the second bit synchronization strategy is determined as the target bit synchronization strategy. The second sequence is used to indicate that the signal edge is an edge subject to a first degree of interference. The second bit synchronization strategy refers to adjusting the duration or bit width of the target phase buffer segment based on the first synchronization strategy.

5. The method according to claim 4, characterized in that, The step of determining the target bit synchronization strategy among multiple bit synchronization strategies based on the comparison results includes: If the comparison result indicates that the sampling sequence is the third sequence, then the third bit synchronization strategy is determined as the target bit synchronization strategy. The third sequence is used to indicate that the signal edge is an edge subject to the second level of interference. The third bit synchronization strategy means not adjusting the duration or bit width of the target phase buffer segment, and the second level of interference is higher than the first level of interference.

6. The method according to claim 4, characterized in that, After determining the second bit synchronization strategy as the target bit synchronization strategy, the method further includes: Based on the sampling sequence, determine the interference intensity level of the signal edge affected by the first level of interference; Query the preset synchronization adjustment mapping table to obtain the target adjustment amount of the time share or bit segment corresponding to the interference intensity level; wherein, the synchronization adjustment mapping table defines the correspondence between different interference intensity levels and different reduction amounts; Update the phase error compensation value in the target bit synchronization strategy to the target adjustment amount.

7. The method according to claim 1, characterized in that, The step of adjusting the target phase buffer segment of the current bit time based on the target bit synchronization strategy for data transmission includes: The counting logic of the time segment counter is adjusted according to the phase error compensation value in the target bit synchronization strategy. When the segment synchronization flag indicates that the target phase buffer segment has been entered, the actual count value of the target phase buffer segment is adjusted according to the phase error compensation value to adjust the segment width. When the sampling point trigger signal in the bit segment synchronization flag is valid, sampling is performed at the sampling point position of the target phase buffer segment to complete data transmission.

8. A bus-based data transmission device, characterized in that, include: An acquisition unit is configured to acquire a sampling sequence obtained from multiple samplings when a signal edge is detected before the start of the synchronization segment of the next bit time of the bus, wherein the sampling sequence is used to characterize the quality of the signal edge; The determining unit is used to determine a target bit synchronization strategy from a variety of preset bit synchronization strategies based on the sampling sequence, wherein different bit synchronization strategies define different bit segment adjustment methods; An adjustment unit is used to adjust the target phase buffer segment of the current bit time based on the target bit synchronization strategy for data transmission, wherein the target phase buffer segment is the previous interval of the synchronization segment.

9. An electronic device, characterized in that, include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and configured to be executed by the processor to implement the bus-based data transmission method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the bus-based data transmission method as described in any one of claims 1 to 7.

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